TECHNICAL NOTE HIGH GRADE Specification HIGH RELIABILITY series Microwire BUS Serial EEPROMs Supply voltage 1.8V~5.5V Operating temperature -40C~+85C type BR93L46-W, BR93L56-W, BR93L66-W, BR93L76-W, BR93L86-W Description BR93L-W series is a serial EEPROM of serial 3-line interface method. Features y y y y y y y y y y y y y y y y 3-line communications of chip select, serial clock, serial data input / output (the case where input and output are shared) Actions available at high speed 2MHz clock (2.5 ~ 5.5V) Speed write available (write time 5 ms max.) Same package and pin layout from 1Kbit to 16Kbit 1.8 ~ 5.5V single power source action Highly reliable connection by Au pad and Au wire Address auto increment function at read action Write mistake prevention function Write prohibition at power on Write prohibition by command code Write mistake prevention function at low voltage Program cycle auto delete and auto end function Program condition display by READY / BUSY Low current consumption At write action (at 5V) : 1.2mA (Typ.) At read action (at 5V) : 0.3mA (Typ.) At standby action (at 5V) : 0.1A (Typ.) (CMOS input) TTL compatible input / output Compact package SOP8, SOP-J8, SSOP-B8, TSSOP-B8, MSOP8, TSSOP-B8J Data retention for 40 years Data rewrite up to 1,000,000 times Data at shipment all addresses FFFFh BR93L Series Type Power source voltage SSOP-B8 Bit format F RF FJ RFJ FV RFV FVT 1Kbit 64 x 16 BR93L46-W 1.8 ~ 5.5V 2Kbit 128 x 16 BR93L56-W 1.8 ~ 5.5V 4Kbit 256 x 16 BR93L66-W 1.8 ~ 5.5V 8Kbit 512 x 16 BR93L76-W 1.8 ~ 5.5V 16Kbit 1K x 16 BR93L86-W 1.8 ~ 5.5V Package type SOP8 SOP-J8 Capacity TSSOP-B8 MSOP8 TSSOP-B8J RFVT RFVM RFVJ Ver.B Oct.2005 Recommended action conditions Absolute Maximum Ratings (Ta=25C) Symbol Parameter VCC Impressed voltage V -0.3 ~ +6.5 SOP8 (F, RF) 450 (*1) SOP-J8 (FJ, RFJ) 450 (*2) SSOP-B8 (FV, RFV) 300 (*3) TSSOP-B8 (FVT, RFVT) 330 (*4) Pd Permissible dissipation Unit Limits MSOP8 (RFVM) 310 (*5) TSSOP-B8J (RFVJ) 310 (*6) Tstg -65 ~ +125 C Action temperature range Topr -40 ~ +85 C -0.3 ~ VCC+0.3 V - Limits Unit Power source voltage VCC 1.8 ~ 5.5 V Input voltage VIN 0 ~ VCC V mW Storage temperature range Terminal voltage Symbol Parameter * When using at Ta = 25C or higher, 4.5mW (*1, *2), 3.0mW (*3), 3.3mW (*4),3.1mW (*5, *6) to be reduced per 1C. Electrical characteristics (Unless otherwise specified, Ta=-40 ~ +85C, Vcc=2.5 ~ 5.5V) Parameter Symbol Min. Typ. "L" input voltage 1 VIL1 -0.3 "L" input voltage 2 VIL2 -0.3 "H" input voltage 1 VIH1 "H" input voltage 2 VIH2 "L" output voltage 1 VOL1 "L" output voltage 2 VOL2 "H" output voltage 1 "H" output voltage 2 Input leak current Output leak current Current consumption at action Standby current Max. Unit Conditions - +0.8 V 4.0VVCC5.5V - 0.2xVCC V VCC4.0V 2.0 - VCC+0.3 V 4.0VVCC5.5V 0.7xVCC - VCC+0.3 V VCC4.0V 0 - 0.4 V IOL=2.1mA, 4.0VVCC5.5V 0 - 0.2 V IOL=100A VOH1 2.4 - VCC V IOH=-0.4mA, 4.0VVCC5.5V VOH2 VCC-0.2 - VCC V IOH=-100A ILI -1 - +1 A VIN=0~VCC ILO -1 - +1 A VOUT=0~VCC, CS=0V ICC1 - - 3.0 mA fSK=2MHz, tE/W=5ms (WRITE) ICC2 - - 1.5 mA fSK=2MHz (READ) ICC3 - - 4.5 mA fSK=2MHz, tE/W=5ms (WRAL,ERAL) ISB - - 2 A CS=0V, DO=OPEN Radiation resistance design is not made. (Unless otherwise specified, Ta=-40 ~ +85C, Vcc=1.8 ~ 2.5V) Parameter Symbol Min. Typ. Max. Unit "L" input voltage VIL -0.3 - 0.2xVCC V "H" input voltage VIH 0.7xVCC - VCC+0.3 V Conditions "L" output voltage VOL 0 - 0.2 V IOL=100A "H" output voltage VOH VCC-0.2 - VCC V IOH=-100A Input leak current ILI -1 - +1 A VIN=0~VCC Output leak current ILO -1 - +1 A VOUT=0~VCC, CS=0V ICC1 - - 1.5 mA fSK=500kHz, tE/W=5ms (WRITE) ICC2 - - 0.5 mA fSK=500kHz (READ) ICC3 - - 2 mA fSK=500kHz (WRAL,ERAL) ISB - - 2 A CS=0V, DO=OPEN Current consumption at action Standby current Radiation resistance design is not made. Memory cell characteristics (Ta=25C, Vcc=1.8 ~ 5.5V) Parameter Min. Typ. Max. Unit Number of data rewrite times *1 1,000,000 - - Times Data hold years - - Years *1 40 *1 Not 100% TESTED 2/16 Action timing characteristics (Ta=-40 ~ +85C, Vcc=2.5 ~ 5.5V) Symbol Min. Typ. Max. Unit SK frequency Parameter fSK - - 2 MHz SK "H" time tSKH 230 - - ns SK "L" time tSKL 230 - - ns CS "L" time tCS 200 - - ns CS setup time tCSS 50 - - ns DI setup time tDIS 100 - - ns CS hold time tCSH 0 - - ns DI hold time tDIH 100 - - ns Data "1" output delay time tPD1 - - 200 ns Data "0" output delay time tPD0 - - 200 ns Time from CS to output establishment tSV - - 150 ns Time from CS to High-Z tDF - - 150 ns Write cycle time tE/W - - 5 ms Symbol Min. Typ. Max. Unit (Ta=-40 ~ +85C, Vcc=1.8 ~ 2.5V) Parameter SK frequency fSK - - 500 kHz SK "H" time tSKH 0.8 - - s SK "L" time tSKL 0.8 - - s CS "L" time tCS 1 - - s CS setup time tCSS 200 - - ns DI setup time tDIS 100 - - ns CS hold time tCSH 0 - - ns DI hold time tDIH 100 - - ns Data "1" output delay time tPD1 - - 0.7 s Data "0" output delay time tPD0 - - 0.7 s Time from CS to output establishment tSV - - 0.7 s Time from CS to High-Z tDF - - 200 ns Write cycle time tE/W - - 5 ms Sync data input / output timing CS tCSS tSKH tSKL tCSH SK tDIS tDIH DI tPD0 tPD1 DO (READ) tDF DO (WRITE) STATUS VALID Fig.1 Sync data input / output timing Data is taken by DI in sync with the rise of SK. At read action, data is output from DO in sync with the rise of SK. The status signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input, at the area DO where CS is "H", and valid until the next command start bit is input. And, while CS is "L", DO becomes High-Z. After completion of each mode execution, set CS "L" once for internal circuit reset, and execute the following action mode. 3/16 6 5 5 4 3 SPEC 2 1 Ta=-40C Ta=25C Ta=85C 0 0 2 1 3 4 5 1 4 3 Ta=85C Ta=25C Ta=-40C 2 1 6 SPEC 0.2 Ta=-40C 3 4 5 0 0 6 0.6 0.4 Ta=25C SPEC Ta=85C 0.2 Fig. 4 H input voltage VIL(CS,SK,DI) 3 2 4 0.8 0.6 SPEC 0.4 Fig. 5 0 0 1 Fig. 6 L output voltage VOL-IOL(VCC=2.5V) SPEC 3 2 4 Ta=25C Ta=85C 2 1 0 0 0.4 1.2 0.8 0 0 5 Ta=-40C 2 1 0 0 Fig. 7 0.4 Fig. 9 H output voltage VOH-IOH(VCC=2.5V) 0.6 0.4 Ta=85C Ta=25C Ta=-40C 1 2 3 4 5 Fig. 11 Output leak current ILO (DO) Ta=85C Ta=25C Ta=-40C 1 Fig. 14 fSK=2MHz DATA=0000h SPEC Ta=85C Ta=25C Ta=-40C 1 1 2 3 4 5 1 2 3 4 5 0.6 0.4 Ta=85C Ta=25C Ta=-40C 0.2 1 Current consumption at WRITE action ICC1(WRITE,fSK=2MHz) 6 SUPPLY VOLTAGE : VCC (V) Consumption current at WRAL action ICC3(WRAL,fSK=2MHz) 4 SPEC 2 Ta=85C Ta=25C Ta=-40C SPEC 1 Fig. 15 2 3 4 5 6 Input leak current ILI (CS,SK,DI) fSK=2MHz DATA=0000h SPEC 1.5 1 Ta=85C Ta=25C Ta=-40C 0.5 1 Fig. 13 2 3 4 5 6 SUPPLY VOLTAGE : VCC (V) Consumption current at READ action ICC2(READ,fSK=2MHz) 2.5 fSK=500kHz DATA=0000h 3 0 0 2 0 0 6 SUPPLY VOLTAGE : VCC (V) CURRENT CONSUMPTION AT READING : ICC2 (READ) (mA) CURRENT CONSUMPTION AT WRITING : ICC1 (WRITE) (mA) SPEC 3 2 0.8 Fig. 10 5 5 fSK=2MHz DATA=0000h SPEC 2.5 2 Fig. 12 1.6 SUPPLY VOLTAGE : VCC (V) H output voltage VOH-IOH(VCC=4.0V) 3 0 0 6 SUPPLY VOLTAGE : VCC (V) 1.2 1 0 0 1.6 CURRENT CONSUMPTION AT READING : ICC2 (READ) (mA) CURRENT CONSUMPTION AT WRITING : ICC1 (WRITE) (mA) 0.8 0 0 1.2 0.8 5 4 0.8 H output voltage VOH-IOH(VCC=1.8V) H OUTPUT CURRENT : IOH (mA) SPEC 4 Ta=25C Ta=85C SPEC 3 1.6 1 0 0 0.4 H OUTPUT CURRENT : IOH (mA) L output voltage VOL-IOL(VCC=4.0V) 4 1.2 0.2 Ta=25C Ta=85C 1.2 H OUTPUT CURRENT : IOH (mA) Fig. 8 Ta=-40C 1 INPUT LEAK CURRENT : ILI (A) H OUTPUT VOLTAGE : VOH (V) Ta=-40C SPEC 5 L output voltage VOL-IOL(VCC=1.8V) 2 5 4 4 3 L OUTPUT CURRENT : IOL (mA) 5 3 4 Ta=-40C L OUTPUT CURRENT : IOL (mA) 3 Ta=25C Ta=85C 0.2 5 2 5 Ta=-40C 1 1 L OUTPUT CURRENT : IOL (mA) H OUTPUT VOLTAGE : VOH (V) L OUTPUT VOLTAGE : VOL (V) L OUTPUT VOLTAGE : VOL (V) Ta=25C 0.4 1 0.8 H OUTPUT VOLTAGE : VOH (V) 2 1 Fig. 3 H input voltage VIH (CS,SK,DI) 0 0 OUTPUT LEAK CURRENT : ILO (A) Ta=85C 0.6 SUPPLY VOLTAGE : VCC (V) 1 CURRENT CONSUMPTION AT OPERATING : ICC3 (WRAL) (mA) 0.8 SPEC 0 0 SUPPLY VOLTAGE : VCC (V) Fig. 2 L OUTPUT VOLTAGE : VOL (V) 6 L INPUT VOLTAGE : VIL (V) H INPUT VOLTAGE : VIH (V) Characteristic data 1 2 3 4 5 6 SUPPLY VOLTAGE : VCC (V) Current consumption at WRITE action ICC1(WRITE,fSK=500kHz) 4/16 2 fSK=500kHz DATA=0000h SPEC 1.5 1 0 0 Fig. 16 Ta=85C Ta=25C Ta=-40C SPEC 0.5 1 2 3 4 5 6 SUPPLY VOLTAGE : VCC (V) Consumption current at READ action ICC2(READ,fSK=500kHz) 2.5 4 SPEC 3 SPEC 2 Ta=85C Ta=25C Ta=-40C 1 0 0 1 Fig. 17 3 2 4 5 2 1.5 1 0.5 Ta=25C Ta=-40C Ta=85C 0 0 6 100 SPEC SK FREQUENCY : fSK (MHz) fSK=500kHz DATA=0000h STAND BY CURRENT : ISB (A) CURRENT CONSUMPTION AT OPERATING : ICC3 (WRAL) (mA) 5 1 3 2 4 5 Ta=-40C 10 Ta=25C 1 0.01 0 6 Consumption current at WRAL action ICC3(WRAL,fSK=500kHz) Fig. 18 1 SPEC SPEC 0.1 SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V) Ta=85C 1 3 2 4 5 6 SUPPLY VOLTAGE : VCC (V) Fig. 19 Consumption current at standby action ISB 1 SK frequency fSK 1.2 SPEC 0.8 L SK TIME : tSKL (s) 0.6 0.4 SPEC 1 0.4 SPEC 0.2 3 2 4 5 0 0 6 SUPPLY VOLTAGE : VCC (V) Fig. 20 Ta=-40C Ta=25C Ta=85C 1 CS SETUP TIME : tCSS (ns) CS HOLD TIME : tCSH (ns) Ta=-40C Ta=85C Ta=25C 1 2 3 4 5 DATA "0" OUTPUT DELAY TIME : tPD0 (s) DI SETUP TIME : tDIS (ns) Ta=-40C Ta=25C 0 Ta=85C 3 4 -100 5 6 SPEC Ta=25C 1 2 3 4 5 0.8 SPEC Ta=85C SPEC Ta=25C Ta=-40C 1 2 3 4 5 TIME BETWEEN CS AND OUTPUT HIGH-Z : tDF (ns) SPEC 0.6 0.4 SPEC 6 1 2 3 4 5 6 SUPPLY VOLTAGE : VCC (V) Fig. 29 Time from CS to output establishment tSV 3 4 5 6 DI hold time tDIH 1 0.8 SPEC 0.6 0.4 Ta=85C SPEC Ta=25C 0.2 Ta=-40C 0 0 1 Fig. 28 Data "0" output delay time tPD0 3 2 4 5 6 Output data "1" delay time tPD1 6 200 SPEC 150 Ta=85C 100 Ta=25C 50 0 0 2 SUPPLY VOLTAGE : VCC (V) Ta=-40C Ta=-40C 1 Fig. 25 0.4 0 0 Ta=85C 0 CS setup time tCSS 0.6 0.2 Ta=-40C Ta=25C SUPPLY VOLTAGE : VCC (V) SPEC 0 0 6 CS low time tCS 50 -50 0 6 250 Ta=85C 5 Ta=85C Ta=-40C Fig. 27 DI setup time tDIS Ta=25C 4 100 SUPPLY VOLTAGE : VCC (V) 1 0.8 3 SPEC 1 SUPPLY VOLTAGE : VCC (V) Fig. 26 2 150 Fig. 24 50 2 1 Fig. 22 SK low time tSKL 0 CS hold time tCSH SPEC 1 SPEC Ta=-40C Ta=25C Ta=85C SUPPLY VOLTAGE : VCC (V) SUPPLY VOLTAGE : VCC (V) 100 0.2 0 0 6 100 -200 0 6 150 TIME BETWEEN CS AND OUTPUT : tSV (s) 5 200 SUPPLY VOLTAGE : VCC (V) Fig. 23 0.4 SPEC -50 -50 0 4 300 SPEC -200 0 3 2 Fig. 21 SK high time tSKH 0 -150 0.6 SUPPLY VOLTAGE : VCC (V) 50 -100 0.8 0.2 DI HOLD TIME : tDIH (ns) 0 0 Ta=-40C Ta=25C Ta=85C 0.6 DATA "1" OUTPUT DELAY TIME : tPD1 (s) 0.2 1 WRITE CYCLE TIME : tE/W (ms) H SK TIME : tSKH (s) 0.8 SPEC L CS TIME : tCS (s) SPEC 1 2 3 4 5 6 SUPPLY VOLTAGE : VCC (V) Fig. 30 Time from CS to High-Z tDF 5/16 SPEC 5 Ta=85C 4 Ta=-40C 3 Ta=25C 2 1 0 0 1 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig. 31 Write cycle time tE/W 6 Block diagram Command decode CS Power source voltage detection Control Clock generation Write prohibition SK Address buffer Command register DI Data register DO High voltage occurrence 6bit 7bit 8bit 9bit 10bit 16bit Address decoder R/W amplifier 6bit 7bit 8bit 9bit 10bit 16bit 1,024 bit 2,048 bit 4,096 bit 8,192 bit 16,384 bit EEPROM VCC NC Dummy bit Fig. 32 Block diagram Pin assignment and function NC GND DO DI VCC CS GND BR93LXXRF-W:SOP8 BR93LXXRFJ-W:SOP-J8 BR93LXXRFV-W:SSOP-B8 BR93LXXRFVT-W:TSSOP-B8 BR93LXXRFVM-W:MSOP8 BR93LXXRFVJ-W:TSSOP-B8J BR93LXXF-W:SOP8 BR93LXXFJ-W:SOP-J8 BR93LXXFV-W:SSOP-B8* BR93LXXFVT-W:TSSOP-B8* NC NC SK CS SK DI DO * BR93L46/56/66-W Fig. 33 Pin assignment diagram Pin name I/O VCC - Power source Function GND - All input / output reference voltage, 0V CS Input Chip select input SK Input Serial clock input DI Input Start bit, ope code, address, and serial data input DO Output NC - Serial data output, READY / BUSY internal condition display output Non connected terminal, Vcc, GND or OPEN 6/16 Description of operations Communications of the Microwire Bus are carried out by SK (serial clock), DI (serial data input), DO (serial data output), and CS (chip select) for device selection. When to connect one EEPROM to a microcontroller, connect it as shown in Fig. 34 (a) or Fig. 34 (b). When to use the input and output common I/O port of the microcontroller, connect DI and DO via a resistor as shown in Fig. 34 (b) (Refer to pages 13/16.), and connection by 3 lines is available. In the case of plural connections, refer to Fig. 34 (c). CS BR93LXX CS SK SK SK DO DI DIO DI DI DO DO Fig. 34-(a) Connection by 4 lines Fig. 34-(b) Connection by 3 lines CS SK DI DO SK Microcontroller CS SK DI DO CS BR93LXX CS CS SK DI DO Microcontroller Microcontroller CS3 CS1 CS0 SK DO DI Device 1 Device 2 Device 3 Fig. 34-(c) Connection example of plural devices Fig. 34 Connection method with microcontroller Communications of the Microwire Bus are started by the first "1" input after the rise of CS. This input is called a start bit. After input of the start bit, input ope code, address and data. Address and data are input all in MSB first manners. "0" input after the rise of CS to the start bit input is all ignored. Therefore, when there is limitation in the bit width of PIO of the microcontroller, input "0" before the start bit input, to control the bit width. Command mode Command Read (READ) Start bit *1 Ope code 1 10 1 00 Write (WRITE) *2 1 01 Write all (WRAL) *2 Write enable (WEN) 1 00 Write disable (WDS) 1 00 Erase (ERASE) 1 11 1 00 Chip erase (ERAL) Address BR93L46-W A5,A4,A3,A2,A1,A0 A5,A4,A3,A2,A1,A0 A5,A4,A3,A2,A1,A0 BR93L56/66-W BR93L76/86-W Data D15 ~ D0 A7,A6,A5,A4,A3,A2,A1,A0 A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 (READ DATA) D15 ~ D0 A7,A6,A5,A4,A3,A2,A1,A0 A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 (WRITE DATA) D15 ~ D0 (WRITE DATA) A7,A6,A5,A4,A3,A2,A1,A0 A9,A8,A7,A6,A5,A4,A3,A2,A1,A0 y Input the address and the data in MSB first manners. y As for , input either VIH or VIL. A7 of BR93L56-W becomes Don't Care. A9 of BR93L76-W becomes Don't Care. * Start bit Acceptance of all the commands of this IC starts at recognition of the start bit. The start bit means the first "1" input after the rise of CS. *1 As for read, by continuous SK clock input after setting the read command, data output of the set address starts, and address data in significant order are sequentially output continuously. (Auto increment function) *2 When the read, and the write all commands are executed, data written in the selected memory cell is automatically deleted, and input data is written. 7/16 Timing chart 1) Read cycle (READ) CS *1 SK 1 2 1 1 4 BR93L46-W : n=25, m=5 n+1 n BR93L56/66-W : n=27, m=7 DI Am 0 A1 A0 BR93L76/86-W : n=29, m=9 *2 DO 0 High-Z D15 D14 D1 D0 D15 D14 *1 Start bit When data "1" is input for the first time after the rise of CS, this is recognized as a start bit. And when "1" is input after plural "0" are input, it is recognized as a start bit, and the following operation is started. This is common to all the commands to described hereafter. Fig. 35 Read cycle When the read command is recognized, input address data (16bit) is output to serial. And at that moment, at taking A0, in sync with the rise of SK, "0" (dummy bit) is output. And, the following data is output in sync with the rise of SK. This IC has address auto increment function valid only at read command. This is the function where after the above read execution, by continuously inputting SK clock, the above address data is read sequentially. And, during the auto increment, keep CS at "H". 2) Write cycle (WRITE) CS tCS 1 SK 2 4 STATUS n BR93L46-W : n=25, m=5 BR93L56/66-W : n=27, m=7 DI 1 0 Am 1 A1 A0 D15 D14 D1 D0 BR93L76/86-W : n=29, m=9 tSV DO BUSY READY High-Z tE/W Fig. 36 Write cycle In this command, input 16bit data (D15 ~ D0) are written to designated addresses (Am ~ A0). The actual write starts by the fall of CS of D0 taken SK clock. When STATUS is not detected, (CS = "L" fixed) Max. 5ms in conformity with tE/W, and when STATUS is detected (CS = "H"), all commands are not accepted for areas where "L" (BUSY) is output from D0, therefore, do not input any command. 3) Write all cycle (WRAL) CS STATUS tCS 1 SK 2 5 n BR93L46-W : n=25 BR93L56/66-W : n=27 DI 1 0 0 0 1 D15 D14 D1 D0 BR93L76/86-W : n=29 tSV DO BUSY READY High-Z tE/W Fig. 37 Write all cycle In this command, input 16bit data is written simultaneously to all addresses. Data is not written continuously per one word but is written in bulk, the write time is only Max. 5ms in conformity with tE/W. 8/16 4) Write enable (WEN) / disable (WDS) cycle CS SK 1 2 3 4 5 6 7 8 BR93L46-W : n=9 n ENABLE = 1 1 DISABLE= 0 0 DI DO 1 0 BR93L56/66-W : n=11 BR93L76/86-W : n=13 0 High-Z Fig. 38 Write enable (WEN) / disable (WDS) cycle At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is necessary to execute the write enable command. And, once this command is executed, it is valid until the write disable command is executed or the power is turned off. However, the read command is valid irrespective of write enable / disable command. Input to SK after 6 clocks of this command is available by either "H" or "L", but be sure to input it. When the write enable command is executed after power on, write enable status gets in. When the write disable command is executed then, the IC gets in write disable status as same as at power on, and then the write command is canceled thereafter in software manner. However, the read command is executable. In write enable status, even when the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the write disable command after completion of write. 5) Erase cycle timing (ERASE) CS tCS SK 1 2 4 STATUS BR93L46-W : n=9, m=5 n BR93L56/66-W : n=11, m=7 DI 1 1 1 Am A3 A2 A1 BR93L76/86-W : n=13, m=9 A0 tSV DO BUSY READY High-Z tE/W Fig. 39 Erase cycle timing In this command, data of the designated address is made into "1". The data of the designated address becomes "FFFFh". Actual ERASE starts at the fall of CS after the fall of A0 taken SK clock. In ERASE, status can be detected in the same manner as in WRITE command. 6) Chip erase cycle timing (ERAL) CS tCS SK 1 2 4 STATUS n BR93L46-W : n=9 BR93L56/66-W : n=11 1 DI 0 0 1 BR93L76/86-W : n=13 0 tSV DO BUSY READY High-Z tE/W Fig. 40 Chip erase cycle timing In this command, data of all addresses is erased. Data of all addresses becomes "FFFFh". Actual ERASE starts at the fall of CS after the fall of the n-th clock from the start bit input. In ERAL, status can be detected in the same manner as in WRITE command. 9/16 Application 1) Method to cancel each command READ Start bit 1 bit Ope code Address 2 bits 6 bits *1 (In the case of BR93L46-W) Data 16 bits Cancel is available in all areas in read mode. y Method to cancel : cancel by CS = "L" *1 Address is 8 bits in BR93L56-W, and BR93L66-W. Address is 10 bits in BR93L76-W, and BR93L86-W. Fig. 41 READ cancel available timing SK WRITE, WRAL *2 y 25 Rise of clock 24 DI 25 D1 D0 Enlarged figure Start bit Ope code 1 bit 2 bits 1 Address * tE/W Data 6 bits a (In the case of BR93L46-W) 16 bits b *2 a : From start bit to 25 clock rise Cancel by CS = "L" *2 b : 25 clock rise and after Cancellation is not available by any means. If Vcc is made OFF in this area, designated address data is not guaranteed, therefore write once again. And when SK clock is input continuously, cancellation is not available. *1 Address is 8 bits in BR93L56-W, and BR93L66-W. Address is 10 bits in BR93L76-W, and BR93L86-W. *2 27 clocks in BR93L56-W, and BR93L66-W 29 clocks in BR93L76-W, and BR93L86-W Fig. 42 WRITE, WRAL cancel available timing ERASE, ERAL y 9 Rise of clock SK DI 8 A1 *3 9 A0 Enlarged figure Start bit Ope code 1 bit 2 bits 1 Address * 1/2 tE/W 6 bits a b *3 *1 Address is 8 bits in BR93L56-W, and BR93L66-W. a : From start bit to 9 clock rise Address is 10 bits in BR93L76-W, and BR93L86-W. Cancel by CS = "L" *2 11 clocks in BR93L56-W, and BR93L66-W *3 13 clocks in BR93L76-W, and BR93L86-W b : 9 clock rise and after Cancellation is not available by any means. If Vcc is made OFF in this area, designated address data is not guaranteed, therefore write once again. And when SK clock is input continuously, cancellation is not available. Fig. 43 ERASE, ERAL cancel available timing 2) At standby Standby current When CS is "L", SK input is "L", DI input is "H", and even with middle electric potential, current does not increase. Timing As shown in Fig. 44, when SK at standby is "H", if CS is started, DI status may be read at the rise edge. At standby and at power ON/OFF, when to start CS, set SK input or DI input to "L" status. (Refer to Fig. 45.) CS = SK = DI = "H" Wrong recognition as a start but CS If CS is started when SK = "L" or DI = "L", a start bit is recognized correctly. CS Start bit input SK SK DI DI Start bit input Fig. 45 Normal action timing Fig. 44 Wrong action timing 10/16 3) Equivalent circuit Output circuit Input circuit RESETint. DO CSint. CS OEint. Fig. 46 Output circuit (DO) Input circuit Fig. 47 Input circuit (CS) Input circuit CSint. CSint. SK DI Fig. 48 Input circuit (DI) Fig. 49 Input circuit (SK) 4) I/O peripheral circuit 4-1) Pull down CS. By making CS = "L" at power ON/OFF, mistake in operation and mistake write are prevented. Pull down resistance Rpd of CS pin To prevent mistake in operation and mistake write at power ON/OFF, CS pull down resistance is necessary. Select an appropriate value to this resistance value from microcontroller VOH, IOH, and VIL characteristics of this IC. Microcontroller Rpd VOHM VOHM . . . IOHM VIHE . . . EEPROM Example) When Vcc = 5V, VIHE = 2V, VOHM = 2.4V, IOHM = 2mA, from the equation , VIHE VOHM IOHM "H" output Rpd "L" input Rpd Rpd 2.4 2x10-3 1.2 (K ) With the value of Rpd to satisfy the above equation, VOHM becomes 2.4V or higher, and with VIHE (= 2.0V), the equation is also satisfied. Fig. 50 CS pull down resistance y VIHE : EEPROM VIH specifications y VOHM : Microcontroller VOH specifications y IOHM : Microcontroller IOH specifications 4-2) DO is available in both pull up and pull down. DO output become "High-Z" in other READY / BUSY output timing than after data output at read command and write command. When malfunction occurs at "High-Z" input of the microcontroller port connected to DO, it is necessary to pull down and pull up DO. When there is no influence upon the microcontroller actions, DO may be OPEN. If DO is OPEN, and at timing to output status READY, at timing of CS = "H", SK = "H", DI = "H", EEPROM recognizes this as a start bit, resets READY output, and DO = "High-Z", therefore, READY signal cannot be detected. To avoid such output, pull up DO pin for improvement. CS CS SK "H" SK Enlarged DI DO D0 DI High-Z READY DO High-Z BUSY BUSY CS = SK = DI = "H" When DO = OPEN Improvement by DO pull up Fig. 51 READY output timing at DO = OPEN 11/16 DO BUSY READY CS = SK = DI = "H" When DO = pull up Pull up resistance Rpu and pull down resistance Rpd of DO pin As for pull up and pull down resistance value, select an appropriate value to this resistance value from microcontroller VIH, VIL, and VOH, IOH, VOL, IOL characteristics of this IC. VCC-VOLE Rpu Microcontroller VOLE Rpu VILM VOLE "L" input Rpu "L" output 2.2 (K ) With the value of Rpu to satisfy the above equation, VOLE becomes 0.4V or below, and with VILM (= 0.8V), the equation is also satisfied. y VOLE : EEPROM VOL specifications y IOLE : EEPROM IOL specifications y VILM : Microcontroller VIL specifications Fig. 52 DO pull up resistance VOHE Rpd EEPROM VIHM . . . . . . Example) When Vcc = 5V, VOHE = Vcc - 0.2V, IOHE = 0.1mA, VIHM = Vcc x 0.7V from the equation , VIHM VOHE Rpd "H" output Rpd IOHE VOHE Microcontroller "H" input . . . Example) When Vcc = 5V, VOLE = 0.4V, IOLE = 2.1mA, VILM = 0.8V, from the equation , 5-0.4 Rpu 2.1x10-3 IOLE IOHE . . . IOLE VILM EEPROM Rpd 5-0.2 0.1x10-3 48 (K ) With the value of Rpd to satisfy the above equation, VOHE becomes 2.4V or below, and with VIHM (= 3.5V), the equation is also satisfied. Fig. 53 DO pull down resistance y VOHE : EEPROM VOH specifications y IOHE : EEPROM IOH specifications y VIHM : Microcontroller VIH specifications 5) READY / BUSY status display (DO terminal) (common to BR93L46-W, BR93L56-W, BR93L66-W, BR93L76-W, BR93L86-W) This display outputs the internal status signal. When CS is started after tCS (Min. 200ns) from CS fall after write command input, "H" or "L" is output. R/B display = "L" (BUSY) = write under execution After the timer circuit in the IC works and creates the period of tE/W, this time circuit completes automatically. And write to the memory cell is made in the period of tE/W, and during this period, other command is not accepted. (D0 status) R/B display = "H" (READY) = command wait status (D0 status) Even after tE/W (Max. 5ms) from write of the memory cell, the following command is accepted. Therefore, CS = "H" in the period of tE/W, and when input is in SK, DI, malfunction may occur, therefore, DI = "L" in the area CS = "H". (Especially, in the case of shared input port, attention is required.) * Do not input any command while status signal is output. Command input in BUSY area is cancelled, but command input in READY area is accepted. Therefore, status READY output is cancelled, and malfunction and mistake write may be made. CS STATUS SK CLOCK DI WRITE INSTRUCTION tSV DO High-Z READY BUSY Fig. 54 R/B status output timing chart 12/16 6) When to directly connect DI and DO This IC has independent input terminal DI and output terminal DO, and separate signals are handled on timing chart, meanwhile, by inserting a resistance R between these DI and DO terminals, it is possible to carry out control by 1 control line. EEPROM Microcontroller DI / O PORT DI R DO Fig. 55 DI, DO control line common connection Data collision of microcontroller DI/O output and DO output and feedback of DO output to DI input Drive from the microcontroller DI/O output to DI input on I/O timing, and signal output from DO output occur at the same time in the following points. (1) 1 clock cycle to take in A0 address data at read command Dummy bit "0" is output to DO terminal. When address data A0 = "1" input, through current route occurs. "H" EEPROM CS input EEPROM SK input A0 A1 EEPROM DI input Collision of DI input and DO output EEPROM DO output Microcontroller DI/O port D15 D14 D13 0 High-Z A0 A1 High-Z Microcontroller input Microcontroller output Fig. 56 Collision timing at read data output at DI, DO direct connection (1) Timing of CS = "H" after write command. DO terminal in READY / BUSY function output. When the next start bit input is recognized, "HIGH-Z" gets in. Especially, at command input after write, when CS input is started with microcontroller DI/O output "L", READY output "H" is output from DO terminal, and through current route occurs. Feedback input at timing of these (1) and (2) does not cause disorder in basic operations, if resistance R is inserted. EEPROM CS input Write command EEPROM SK input Write command EEPROM DI input Write command EEPROM DO output Write command READY Microcontroller DI/O port READY Collision of DI input and DO output READY Write command Microcontroller output High-Z BUSY BUSY Microcontroller output Microcontroller input Fig. 57 Collision timing at DI, DO direct connection Note) As for the case (2), attention must be paid to the following. When status READY is output, DO and DO are shared, DI = "H" and the microcontroller DI/O = "High-Z" or the microcontroller DI/O = "H", if SK clock is input, DO output is input to DI and is recognized as a start bit, and malfunction may occur. As a method to avoid malfunction, at status READY output, set SK = "L", or start CS within 4 clocks after "H" of READY signal is output. Start bit CS SK Because DI = "H", set SK = "L" at CS rise. DI DO READY High-Z Fig. 58 Start bit input timing at DI, DO direct connection 13/16 Selection of resistance value R The resistance R becomes through current limit resistance at data collision. When through current flows, noises of power source line and instantaneous stop of power source may occur. When allowable through current is defined as I, the following relation should be satisfied. Determine allowable current amount in consideration of impedance and so forth of power source line in set. And insert resistance R, and set the value R to satisfy EEPROM input level VIH/VIL even under influence of voltage decline owing to leak current and so forth. Insertion of R will not cause any influence upon basic operations. (1) Address data A0 = "1" input, dummy bit "0" output timing (When microcontroller DI/O output is "H", EEPROM DO outputs "L", and "H" is input to DI) y Make the through current to EEPROM 10mA or below. y See to it that the input level VIH of EEPROM should satisfy the following. Conditions Microcontroller EEPROM DI/O PORT VOHM VOHM DI VIHE IOHM x R + VOLE At this moment, if VOLE = 0V, "H" output VOHM IOHM VOHM R R DO y y y y VOLE "L" output IOHM x R VOHM . . . IOHM VIHE : EEPROM VIH specifications VOLE : EEPROM VOL specifications VOHM : Microcontroller VOH specifications IOHM : Microcontroller IOH specifications Fig. 59 Circuit at DI, DO direct connection (Microcontroller DI/O "H" output, EEPROM "L" output) (2) DO status READY output timing (When the microcontroller DI/O is "L", EEPROM DO outputs "H", and "L" is input to DI) y Set the EEPROM input level VIL so as to satisfy the following. Conditions Microcontroller "L" output EEPROM DI/O PORT DI VOLM VOLM VILE VOLM VOHE - IOLM x R At this moment, VOHE=VCC, IOHM R VOLM R DO VOHE "H" output y y y y VILE VOHE VOLM IOLM VCC - IOLM x R VCC - VOLM IOLM : EEPROM VIL specifications : EEPROM VOH specifications : Microcontroller VOL specifications : Microcontroller IOL specifications Fig. 60 Circuit at DI, DO direct connection (Microcontroller DI/O "L" output, EEPROM "H" output) Example) When Vcc = 5V, VOHM = 5V, IOHM = 0.4mA, VOLM = 5V, IOLM = 0.4mA, From the equation From the equation , , VCC - VOLM IOLM R VOHM IOHM R R 5 0.4x10-3 R R 12.5 [k ] R 2.2 [k ] . . . 5 - 0.4 2.1x10-3 . . . Therefore, from the equations R 14/16 . . . 12.5 [k ] and , 7) Notes on power ON/OFF y At power ON/OFF, set CS "L". When CS is "H", this IC gets in input accept status (active). If power is turned on in this status, noises and the likes may cause malfunction, mistake write or so. To prevent these, at power ON, set CS "L". (When CS is in "L" status, all inputs are cancelled.) And at power decline, owing to power line capacity and so forth, low power status may continue long. At this case too, owing to the same reason, malfunction, mistake write may occur, therefore, at power OFF too, set CS "L". VCC VCC GND VCC CS GND Good example Bad example Fig. 61 Timing at power ON/OFF (Good example) It is "L" at power ON/OFF. (Bad example) CS pin is pulled up to Vcc. In this case, CS becomes "H" (active status), and EEPROM may have malfunction, mistake write owing to noises and the likes. Even when CS input is High-Z, the status becomes like this case, which please note. Set 10ms or higher to recharge at power OFF. When power is turned on without observing this condition, IC internal circuit may not be reset, which please note. POR circuit This IC has a POR (Power On Reset) circuit as mistake write countermeasure. After POR action, it gets in write disable status. The POR circuit is valid only when power is ON, and does not work when power is OFF. However, if CS is "H" at power ON/OFF, it may become write enable status owing to noises and the likes. For secure actions, observe the following conditions. 1 Set CS = "L". 2 Turn on power so as to satisfy the recommended conditions of tR, tOFF, Vbot for POR circuit action. tR VCC Recommended conditions of tR, tOFF, Vbot tR tOFF tOFF Vbot 10ms or below 10ms or higher 0.3V or below Vbot 100ms or below 10ms or higher 0.2V or below 0 Fig. 62 Rise waveform diagram LVCC circuit LVCC (Vcc - Lockout) circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. = 1.2V) or below, it prevent data rewrite. 8) Noise countermeasures Vcc noise (bypass capacitor) When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a by pass capacitor (0.1F) between IC Vcc and GND, At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND. SK noise When the rise time (tR) of SK is long, and a certain degree or more of noise exists, malfunction may occur owing to clock bit displacement. To avoid this, a Schmitt trigger circuit is built in SK input. the hysteresis width of this circuit is set about 0.2V, if noises exist at SK input, set the noise amplitude 0.2Vp-p or below. And it is recommended to set the rise time (tR) of SK 100ns or below. In the case when the rise time is 100ns or higher, take sufficient noise countermeasures. Make the clock rise, fall time as small as possible. Cautions on use (1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute Maximum Ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is not lower than that of GND terminal in consideration of transition status. (5) Heat design In consideration of allowable loss in actual use condition, carry out heat design with sufficient margin. (6) Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. 15/16 Selection of order type BR ROHM type name 93 L BUS type 46 Operating temperature 93 : Microwire F Capacity W Package type Microwire BUS 46=1K 56=2K 66=4K 76=8K 86=16K -4085 A -40105 H -40125 - Double cell F : SOP8 FJ : SOP-J8 RF : SOP8 RFJ : SOP-J8 FV : SSOP-B8 RFV : SSOP-B8 FVT : TSSOP-B8 RFVT : TSSOP-B8 RFVM : MSOP8 RFVJ : TSSOP-B8J Package specifications E2 Taping type name E2 : reel shape emboss taping TR : reel shape emboss taping (MSOP8 package only) SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J <Package specifications> <External appearance> +0.05 0.65 4 0.450.15 0.950.2 4.90.2 3.00.1 0.10.05 1.00.1 0.08 S 0.245 -0.04 0.850.05 4.40.1 6.40.2 0.3Min. 4.40.2 6.40.3 6.00.3 0.3Min. 0.45Min. 1.150.1 0.1 0.65 1 +0.05 0.145 -0.03 +0.05 0.145 -0.03 0.08 S 0.32 1234 0.220.1 (0.52) 4 1234 0.420.1 0.1 1234 0.1 1.27 1 0.150.1 Package direction E2 (When the reel is gripped by the left hand, and the tape is pulled out by the right hand, No.1 pin of the product is at the left top.) 1234 0.11 4 0.20.1 3.00.1 8 5 1234 1.50.1 1 3.00.1 8 5 1234 0.1 5 Package type Emboss taping Package quantity 2500pcs 1234 1.27 0.420.1 1 2 3 4 +0.1 -0.05 8 * TSSOP-B8J 1234 0.17 3.90.2 4 8 7 6 5 1.3750.1 0.175 1 6.20.3 4.40.2 5 * TSSOP-B8 3.00.2 4.90.2 5.00.2 8 * SSOP-B8 0.50.15 1.00.2 * SOP-J8 0.10.05 * SOP8 +0.05 -0.04 0.65 Pin No.1 Reel (Unit : mm) Pulling side * For ordering, specify a number of multiples of the package quantity. MSOP8 <External appearance> <Package specifications> Package type Package quantity 5 0.9Max. 0.75 0.05 0.08 0.05 0.475 1 4 0.145+0.05 -0.03 0.22+0.05 -0.04 0.65 Emboss taping 3000pcs Package direction TR (When the reel is gripped by the left hand, and the tape is pulled out by the right hand, No.1 pin of the product is at the right top.) 0.29 0.15 0.6 0.2 8 2.8 0.1 4.0 0.2 2.9 0.1 0.08 M 0.08 S Pin No.1 Pulling side Reel (Unit : mm) * For ordering, specify a number of multiples of the package quantity. The contents described herein are correct as of October, 2005 The contents described herein are subject to change without notice. For updates of the latest information, please contact and confirm with ROHM CO.,LTD. Any part of this application note must not be duplicated or copied without our permission. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams and information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. The products described herein utilize silicon as the main material. The products described herein are not designed to be X ray proof. Published by Application Engineering Group Catalog No. 05T816Ae '05.10 (c) 2000 ROHMTSU Appendix Notes No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. Products listed in this document are no antiradiation design. The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the NOTES specified in this catalog. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright (c) 2007 ROHM CO.,LTD. THE AMERICAS / EUPOPE / ASIA / JAPAN Contact us : webmaster@ rohm.co. jp 21, Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix1-Rev2.0