TPS75103YFFT - NATIONAL SEMICONDUCTOR

TP3054-X, TP3057-X

OBSOLETE

October 24, 2011

Extended Temperature Serial Interface CODEC/Filter

COMBO® Family

General Description

The TP3054, TP3057 family consists of μ-law and A-law

monolithic PCM CODEC/filters utilizing the A/D and D/A con-

version architecture shown in Figure 1, and a serial PCM

interface. The devices are fabricated using National's ad-

vanced double-poly CMOS process (microCMOS).

The encode portion of each device consists of an input gain

adjust amplifier, an active RC pre-filter which eliminates very

high frequency noise prior to entering a switched-capacitor

band-pass filter that rejects signals below 200 Hz and above

3400 Hz. Also included are auto-zero circuitry and a com-

panding coder which samples the filtered signal and encodes

it in the companded μ-law or A-law PCM format. The decode

portion of each device consists of an expanding decoder,

which reconstructs the analog signal from the companded μ-

law or A-law code, a low-pass filter which corrects for the sin

x/x response of the decoder output and rejects signals above

3400 Hz followed by a single-ended power amplifier capable

of driving low impedance loads. The devices require two

1.536 MHz, 1.544 MHz or 2.048 MHz transmit and receive

master clocks, which may be asynchronous; transmit and re-

ceive bit clocks, which may vary from 64 kHz to 2.048 MHz;

and transmit and receive frame sync pulses. The timing of the

frame sync pulses and PCM data is compatible with both in-

dustry standard formats.

Features

■−40°C to +85°C operation

■Complete CODEC and filtering system (COMBO)

including:

—Transmit high-pass and low-pass filtering

—Receive low-pass filter with sin x/x correction

—Active RC noise filters

—μ-law or A-law compatible COder and DECoder

—Internal precision voltage reference

—Serial I/O interface

—Internal auto-zero circuitry

■μ-law, 16-pin—TP3054

■A-law, 16-pin—TP3057

■Designed for D3/D4 and CCITT applications

■±5V operation

■Low operating power—typically 50 mW

■Power-down standby mode—typically 3 mW

■Automatic power-down

■TTL or CMOS compatible digital interfaces

■Maximizes line interface card circuit density

■Dual-In-Line or PCC surface mount packages

■See also AN-370, “Techniques for Designing with

CODEC/Filter COMBO Circuits”

Connection Diagrams

Plastic Chip Carriers

867408

Top View

Order Number TP3057V-X

NS Package Number V20A

Dual-In-Line Package

867401

Top View

Order Number TP3054N-X

NS Package Number N16E

Order Number TP3054WM-X

NS Package Number M16B

COMBO® is a registered trademark of National Semiconductor.

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

8674 Version 3 Revision 4 Print Date/Time: 2011/10/24 15:43:24

TP3054-X, TP3057-X Extended Temperature Serial Interface CODEC/Filter COMBO Family

Block Diagram

867402

FIGURE 1.

Pin Descriptions

Symbol Function

VBB Negative power supply pin.

VBB = −5V ±5%.

GNDA Analog ground. All signals are referenced

to this pin.

VFRO Analog output of the receive power

amplifier.

VCC Positive power supply pin.

VCC = +5V ±5%.

FSRReceive frame sync pulse which enables

BCLKR to shift PCM data into DR. FSR is

an 8 kHz pulse train. See Figure 2 and

Figure 3 for timing details.

DRReceive data input. PCM data is shifted

into DR following the FSR leading edge.

Symbol Function

BCLKR/CLKSEL The bit clock which shifts data into DR

after the FSR leading edge. May vary from

64 kHz to 2.048 MHz. Alternatively, may

be a logic input which selects either 1.536

MHz/1.544 MHz or 2.048 MHz for master

clock in synchronous mode and BCLKX is

used for both transmit and receive

directions (see Table 1).

MCLKR/PDN Receive master clock. Must be 1.536

MHz, 1.544 MHz or 2.048 MHz. May be

asynchronous with MCLKX, but should be

synchronous with MCLKX for best

performance. When MCLKR is connected

continuously low, MCLKX is selected for

all internal timing. When MCLKR is

connected continuously high, the device

is powered down.

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TP3054-X, TP3057-X

Symbol Function

MCLKXTransmit master clock. Must be 1.536

MHz, 1.544 MHz or 2.048 MHz. May be

asynchronous with MCLKR. Best

performance is realized from

synchronous operation.

FSXTransmit frame sync pulse input which

enables BCLKX to shift out the PCM data

on DX. FSX is an 8 kHz pulse train, see

Figure 2 and Figure 3 for timing details.

BCLKXThe bit clock which shifts out the PCM

data on DX. May vary from 64 kHz to 2.048

MHz, but must be synchronous with

MCLKX.

DXThe TRI-STATE® PCM data output which

is enabled by FSX.

TSXOpen drain output which pulses low

during the encoder time slot.

GSXAnalog output of the transmit input

amplifier. Used to externally set gain.

VFXI−Inverting input of the transmit input

amplifier.

VFXI+Non-inverting input of the transmit input

amplifier.

Functional Description

POWER-UP

When power is first applied, power-on reset circuitry initializes

the COMBO and places it into a power-down state. All non-

essential circuits are deactivated and the DX and VFRO out-

puts are put in high impedance states. To power-up the

device, a logical low level or clock must be applied to the

MCLKR/PDN pin and FSX and/or FSR pulses must be present.

Thus, 2 power-down control modes are available. The first is

to pull the MCLKR/PDN pin high; the alternative is to hold both

FSX and FSR inputs continuously low—the device will power-

down approximately 1 ms after the last FSX or FSR pulse.

Power-up will occur on the first FSX or FSR pulse. The TRI-

STATE PCM data output, DX, will remain in the high

impedance state until the second FSX pulse.

SYNCHRONOUS OPERATION

For synchronous operation, the same master clock and bit

clock should be used for both the transmit and receive direc-

tions. In this mode, a clock must be applied to MCLKX and the

MCLKR/PDN pin can be used as a power-down control. A low

level on MCLKR/PDN powers up the device and a high level

powers down the device. In either case, MCLKX will be se-

lected as the master clock for both the transmit and receive

circuits. A bit clock must also be applied to BCLKX and the

BCLKR/CLKSEL can be used to select the proper internal di-

vider for a master clock of 1.536 MHz, 1.544 MHz or 2.048

MHz. For 1.544 MHz operation, the device automatically com-

pensates for the 193rd clock pulse each frame.

With a fixed level on the BCLKR/CLKSEL pin, BCLKX will be

selected as the bit clock for both the transmit and receive di-

rections. Table 1 indicates the frequencies of operation which

can be selected, depending on the state of BCLKR/CLKSEL.

In this synchronous mode, the bit clock, BCLKX, may be from

64 kHz to 2.048 MHz, but must be synchronous with

MCLKX.

Each FSX pulse begins the encoding cycle and the PCM data

from the previous encode cycle is shifted out of the enabled

DX output on the positive edge of BCLKX. After 8 bit clock

periods, the TRI-STATE DX output is returned to a high

impedance state. With an FSR pulse, PCM data is latched via

the DR input on the negative edge of BCLKX (or BCLKR if run-

ning). FSX and FSR must be synchronous with MCLKX/R.

TABLE 1. Selection of Master Clock Frequencies

BCLKR/CLKSEL

Master Clock

Frequency Selected

TP3057 TP3054

Clocked 2.048 MHz 1.536 MHz or

1.544 MHz

0 1.536 MHz or 2.048 MHz

1.544 MHz

1 2.048 MHz 1.536 MHz or

1.544 MHz

ASYNCHRONOUS OPERATION

For asynchronous operation, separate transmit and receive

clocks may be applied. MCLKX and MCLKR must be

2.048 MHz for the TP3057, or 1.536 MHz, 1.544 MHz for the

TP3054, and need not be synchronous. For best transmission

performance, however, MCLKR should be synchronous with

MCLKX, which is easily achieved by applying only static logic

levels to the MCLKR/PDN pin. This will automatically connect

MCLKX to all internal MCLKR functions (see Pin Description).

For 1.544 MHz operation, the device automatically compen-

sates for the 193rd clock pulse each frame. FSX starts each

encoding cycle and must be synchronous with MCLKX and

BCLKX. FSR starts each decoding cycle and must be syn-

chronous with BCLKR. BCLKR must be a clock, the logic levels

shown in Table 1 are not valid in asynchronous mode.

BCLKX and BCLKR may operate from 64 kHz to 2.048 MHz.

SHORT FRAME SYNC OPERATION

The COMBO can utilize either a short frame sync pulse or a

long frame sync pulse. Upon power initialization, the device

assumes a short frame mode. In this mode, both frame sync

pulses, FSX and FSR, must be one bit clock period long, with

timing relationships specified in Figure 2. With FSX high dur-

ing a falling edge of BCLKX, the next rising edge of BCLKX

enables the DX TRI-STATE output buffer, which will output

the sign bit. The following seven rising edges clock out the

remaining seven bits, and the next falling edge disables the

DX output. With FSR high during a falling edge of BCLKR

(BCLKX in synchronous mode), the next falling edge of

BCLKR latches in the sign bit. The following seven falling

edges latch in the seven remaining bits. All four devices may

utilize the short frame sync pulse in synchronous or asyn-

chronous operating mode.

LONG FRAME SYNC OPERATION

To use the long frame mode, both the frame sync pulses,

FSX and FSR, must be three or more bit clock periods long,

with timing relationships specified in Figure 3. Based on the

transmit frame sync, FSX, the COMBO will sense whether

short or long frame sync pulses are being used. For 64 kHz

operation, the frame sync pulse must be kept low for a mini-

mum of 160 ns. The DX TRI-STATE output buffer is enabled

with the rising edge of FSX or the rising edge of BCLKX,

whichever comes later, and the first bit clocked out is the sign

bit. The following seven BCLKX rising edges clock out the re-

maining seven bits. The DX output is disabled by the falling

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BCLKX edge following the eighth rising edge, or by FSX going

low, whichever comes later. A rising edge on the receive

frame sync pulse, FSR, will cause the PCM data at DR to be

latched in on the next eight falling edges of BCLKR (BCLKX in

synchronous mode). All four devices may utilize the long

frame sync pulse in synchronous or asynchronous mode.

In applications where the LSB bit is used for signalling, with

FSR two bit clock periods long, the decoder will interpret the

lost LSB as “½” to minimize noise and distortion.

TRANSMIT SECTION

The transmit section input is an operational amplifier with pro-

vision for gain adjustment using two external resistors, see

Figure 4. The low noise and wide bandwidth allow gains in

excess of 20 dB across the audio passband to be realized.

The op amp drives a unity-gain filter consisting of RC active

pre-filter, followed by an eighth order switched-capacitor

bandpass filter clocked at 256 kHz. The output of this filter

directly drives the encoder sample-and-hold circuit. The A/D

is of companding type according to μ-law (TP3054) or A-law

(TP3057) coding conventions. A precision voltage reference

is trimmed in manufacturing to provide an input overload

(tMAX) of nominally 2.5V peak (see table of Transmission

Characteristics). The FSX frame sync pulse controls the sam-

pling of the filter output, and then the successive-approxima-

tion encoding cycle begins. The 8-bit code is then loaded into

a buffer and shifted out through DX at the next FSX pulse. The

total encoding delay will be approximately 165 μs (due to the

transmit filter) plus 125 μs (due to encoding delay), which to-

tals 290 μs. Any offset voltage due to the filters or comparator

is cancelled by sign bit integration.

RECEIVE SECTION

The receive section consists of an expanding DAC which

drives a fifth order switched-capacitor low pass filter clocked

at 256 kHz. The decoder is A-law (TP3057) or μ-law (TP3054)

and the 5th order low pass filter corrects for the sin x/x atten-

uation due to the 8 kHz sample/hold. The filter is then followed

by a 2nd order RC active post-filter/power amplifier capable

of driving a 600Ω load to a level of 7.2 dBm. The receive sec-

tion is unity-gain. Upon the occurrence of FSR, the data at the

DR input is clocked in on the falling edge of the next eight

BCLKR (BCLKX) periods. At the end of the decoder time slot,

the decoding cycle begins, and 10 μs later the decoder DAC

output is updated. The total decoder delay is ∼10 μs (decoder

update) plus 110 μs (filter delay) plus 62.5 μs (½ frame), which

gives approximately 180 μs.

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TP3054-X, TP3057-X

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

VCC to GNDA 7V

VBB to GNDA −7V

Voltage at any Analog Input

or Output VCC+0.3V to VBB−0.3V

Voltage at any Digital Input or

Output VCC+0.3V to GNDA−0.3V

Operating Temperature Range −55°C to + 125°C

Storage Temperature Range −65°C to +150°C

Lead Temperature

(Soldering, 10 sec.) 300°C

Electrical Characteristics

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C to

+85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other production tests

and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC = +5.0V, VBB = −5.0V, TA

= 25°C.

Symbol Parameter Conditions Min Typ Max Units

DIGITAL INTERFACE

VIL Input Low Voltage 0.6 V

VIH Input High Voltage 2.2 V

VOL Output Low Voltage DX, IL=3.2 mA 0.4 V

SIGR, IL=1.0 mA 0.4 V

TSX, IL=3.2 mA, Open Drain 0.4 V

VOH Output High Voltage DX, IH=−3.2 mA 2.4 V

SIGR, IH=−1.0 mA 2.4 V

IIL Input Low Current GNDA≤VIN≤VIL, All Digital Inputs −10 10 μA

IIH Input High Current VIH≤VIN≤VCC −10 10 μA

IOZ Output Current in High Impedance State

(TRI-STATE)

DX, GNDA≤VO≤VCC −10 10 μA

ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)

IIXA Input Leakage Current −2.5V≤V≤+2.5V, VFXI+ or VFXI−−200 200 nA

RIXA Input Resistance −2.5V≤V≤+2.5V, VFXI+ or VFXI−10 MΩ

ROXA Output Resistance Closed Loop, Unity Gain 1 3 Ω

RLXA Load Resistance GSX10 kΩ

CLXA Load Capacitance GSX 50 pF

VOXA Output Dynamic Range GSX, RL ≥ 10 kΩ−2.8 2.8 V

AVXA Voltage Gain VFXI+ to GSX5000 V/V

FUXA Unity Gain Bandwidth 1 2 MHz

VOSXA Offset Voltage −20 20 mV

VCMXA Common-Mode Voltage CMRRXA > 60 dB −2.5 2.5 V

CMRRXA Common-Mode Rejection Ratio DC Test 60 dB

PSRRXA Power Supply Rejection Ratio DC Test 60 dB

ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)

RORF Output Resistance Pin VFRO 1 3 Ω

RLRF Load Resistance VFRO=±2.5V 600 Ω

CLRF Load Capacitance 500 pF

VOSRO Output DC Offset Voltage −200 200 mV

POWER DISSIPATION (ALL DEVICES)

ICC0 Power-Down Current No Load (Note 2) 0.65 2.0 mA

IBB0 Power-Down Current No Load (Note 2) 0.01 0.33 mA

ICC1 Power-Up (Active) Current No Load( –40°C to 85°C) 5.0 11.0 mA

IBB1 Power-Up (Active) Current No Load ( –40°C to 85°C) 5.0 11.0 mA

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TP3054-X, TP3057-X

Timing Specifications

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C to

+85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other production tests

and/or product design and characterization. All signals referenced to GNDA. Typicals specified at VCC = +5.0V, VBB = –5.0V, TA =

25°C. All timing parameters are assured at VOH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test

methods information.

Symbol Parameter Conditions Min Typ Max Units

1/tPM Frequency of Master Clocks Depends on the Device Used and the 1.536 MHz

BCLKR/CLKSEL Pin. 1.544 MHz

MCLKX and MCLKR 2.048 MHz

tRM Rise Time of Master Clock MCLKX and MCLKR 50 ns

tFM Fall Time of Master Clock MCLKX and MCLKR 50 ns

tPB Period of Bit Clock 485 488 15725 ns

tRB Rise Time of Bit Clock BCLKX and BCLKR 50 ns

tFB Fall Time of Bit Clock BCLKX and BCLKR 50 ns

tWMH Width of Master Clock High MCLKX and MCLKR160 ns

tWML Width of Master Clock Low MCLKX and MCLKR160 ns

tSBFM Set-Up Time from BCLKX High First Bit Clock after Short Frame 100 ns

to MCLKX Falling Edge the Leading Edge

of FSX Long Frame 125

tSFFM Setup Time from FSX High to MCLKX

Falling Edge

Long Frame Only 100 ns

tWBH Width of Bit Clock High VIH=2.2V 160 ns

tWBL Width of Bit Clock Low VIL=0.6V 160 ns

tHBFL Holding Time from Bit Clock

Low to Frame Sync

Long Frame Only 0 ns

tHBFS Holding Time from Bit Clock

High to Frame Sync

Short Frame Only 0 ns

tSFB Set-Up Time from Frame Sync

to Bit Clock Low

Long Frame Only 115 ns

tDBD Delay Time from BCLKX High

to Data Valid

Load=150 pF plus 2 LSTTL Loads 0 140 ns

tDBTS Delay Time to TSX Low Load=150 pF plus 2 LSTTL Loads 140 ns

tDZC Delay Time from BCLKX Low to

Data Output Disabled

CL=0 pF to 150 pF 50 165 ns

tDZF Delay Time to Valid Data from

FSX or BCLKX, Whichever Comes

Later

CL=0 pF to 150 pF 20 165 ns

tSDB Set-Up Time from DR Valid to

BCLKR/X Low

50 ns

tHBD Hold Time from BCLKR/X Low to

DR Invalid

50 ns

tSF Set-Up Time from FSX/R to

BCLKX/R Low

Short Frame Sync Pulse (1 Bit Clock Period

Long)

50 ns

tHF Hold Time from BCLKX/R Low

to FSX/R Low

Short Frame Sync Pulse (1 Bit Clock Period

Long)

100 ns

tHBFl Hold Time from 3rd Period of

Bit Clock Low to Frame Sync

(FSX or FSR)

Long Frame Sync Pulse (from 3 to 8 Bit

Clock Periods Long)

100 ns

tWFL Minimum Width of the Frame

Sync Pulse (Low Level)

64k Bit/s Operating Mode 160 ns

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TP3054-X, TP3057-X

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device

is functional, but do not guarantee specific performance limits.

Note 2: ICC0 and IBB0 are measured after first achieving a power-up state.

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Timing Diagrams

867403

FIGURE 2. Short Frame Sync Timing

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TP3054-X, TP3057-X

867409

FIGURE 3. Long Frame Sync Timing

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TP3054-X, TP3057-X

Transmission Characteristics

Unless otherwise noted, limits printed in BOLD characters are guaranteed for VCC = +5.0V ±5%, VBB = −5.0V ±5%; TA = −40°C to

+85°C by correlation with 100% electrical testing at TA = 25°C. All other limits are assured by correlation with other production tests

and/or product design and characterization. GNDA = 0V, f = 1.02 kHz, VIN = 0 dBm0, transmit input amplifier connected for unity

gain non inverting. Typicals are specified at VCC = +5.0V, VBB = −5.0V, TA = 25°C.

Symbol Parameter Conditions Min Typ Max Units

AMPLITUDE RESPONSE

Absolute Levels Nominal 0 dBm0 Level is 4 dBm

(Definition of nominal gain) (600Ω)

0 dBm0 1.2276 Vrms

tMAX Max Overload Level

TP3054 (3.17 dBm0) 2.501 VPK

TP3057 (3.14 dBm0) 2.492 VPK

GXA Transmit Gain, Absolute TA=25°C, VCC=5V, VBB=−5V

Input at GSx=0 dBm0 at 1020 Hz −0.15 0.15 dB

GXR Transmit Gain, Relative to GXA f=16 Hz −40 dB

f=50 Hz −30 dB

f=60 Hz −26 dB

f=200 Hz −1.8 −0.1 dB

f=300 Hz–3000 Hz −0.15 0.15 dB

f=3152 Hz −0.15 0.20 dB

f=3300 Hz −0.35 0.1 dB

f=3400 Hz −0.7 0dB

f=4000 Hz −14 dB

f=4600 Hz and Up, Measure −32 dB

Response from 0 Hz to 4000 Hz

GXAT Absolute Transmit Gain Variation Relative to GXA −0.15 0.15 dB

with Temperature

GXAV Absolute Transmit Gain Variation Relative to GXA −0.05 0.05 dB

with Supply Voltage

GXRL Transmit Gain Variations with Sinusoidal Test Method

Level Reference Level=−10 dBm0

VFXI+=−40 dBm0 to +3 dBm0 −0.2 0.2 dB

VFXI+=−50 dBm0 to −40 dBm0 −0.4 0.4 dB

VFXI+=−55 dBm0 to −50 dBm0 −1.2 1.2 dB

GRA Receive Gain, Absolute TA=25°C, VCC=5V, VBB=−5V

Input=Digital Code Sequence

for 0 dBm0 Signal at 1020 Hz −0.20 0.20 dB

GRR Receive Gain, Relative to GRA f=0 Hz to 3000 Hz −0.15 0.15 dB

f=3300 Hz −0.35 0.1 dB

f=3400 Hz −0.7 0dB

f=4000 Hz −14 dB

GRAT Absolute Receive Gain Variation Relative to GRA −0.15 0.15 dB

with Temperature

GRAV Absolute Receive Gain Variation Relative to GRA −0.05 0.05 dB

with Supply Voltage

GRRL Receive Gain Variations with Sinusoidal Test Method; Reference

Level Input PCM Code Corresponds to an

Ideally Encoded

PCM Level =−40 dBm0 to +3 dBm0 −0.2 0.2 dB

PCM Level =−50 dBm0 to −40 dBm0 −0.4 0.4 dB

PCM Level =−55 dBm0 to −50 dBm0 −1.2 1.2 dB

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Symbol Parameter Conditions Min Typ Max Units

VRO Receive Output Drive Level RL=600Ω −2.5 2.5 V

ENVELOPE DELAY DISTORTION WITH FREQUENCY

DXA Transmit Delay, Absolute f=1600 Hz 290 315 μs

DXR Transmit Delay, Relative to DXA f=500 Hz−600 Hz 195 220 μs

f=600 Hz−800 Hz 120 145 μs

f=800 Hz−1000 Hz 50 75 μs

f=1000 Hz−1600 Hz 20 40 μs

f=1600 Hz−2600 Hz 55 75 μs

f=2600 Hz−2800 Hz 80 105 μs

f=2800 Hz−3000 Hz 130 155 μs

DRA Receive Delay, Absolute f=1600 Hz 180 200 μs

DRR Receive Delay, Relative to DRA f=500 Hz−1000 Hz −40 −25 μs

f=1000 Hz−1600 Hz −30 −20 μs

f=1600 Hz−2600 Hz 70 90 μs

f=2600 Hz−2800 Hz 100 125 μs

f=2800 Hz−3000 Hz 145 175 μs

NOISE

NXC Transmit Noise, C Message TP3054 12 16 dBrnC0

Weighted (Note 3)

NXP Transmit Noise, P Message TP3057 −74 −67 dBm0p

Weighted (Note 3)

NRC Receive Noise, C Message PCM Code is Alternating

Weighted Positive and Negative Zero — TP3054 8 11 dBrnC0

NRP Receive Noise, P Message TP3057 PCM Code Equals Positive

Weighted Zero — −82 −79 dBm0p

NRS Noise, Single Frequency f=0 kHz to 100 kHz, Loop Around −53 dBm0

Measurement, VFXI+=0 Vrms

PPSRXPositive Power Supply Rejection, VCC=5.0 VDC+100 mVrms

Transmit f=0 kHz−50 kHz (Note 4)40 dBC

NPSRXNegative Power Supply Rejection, VBB=−5.0 VDC+ 100 mVrms

Transmit f=0 kHz−50 kHz (Note 4)40 dBC

PPSRRPositive Power Supply Rejection, PCM Code Equals Positive Zero

Receive VCC=5.0 VDC+100 mVrms

Measure VFR0

f=0 Hz−4000 Hz 38 dBC

f=4 kHz−25 kHz 38 dB

f=25 kHz−50 kHz 35 dB

NPSRRNegative Power Supply Rejection, PCM Code Equals Positive Zero

Receive VBB=−5.0 VDC+100 mVrms

Measure VFR0

f=0 Hz−4000 Hz 38 dBC

f=4 kHz−25 kHz 38 dB

f=25 kHz−50 kHz 35 dB

SOS Spurious Out-of-Band Signals Loop Around Measurement, 0 dBm0, −30 dB

at the Channel Output 300 Hz to 3400 Hz Input PCM Code

Applied at DR.

4600 Hz–7600 Hz −30 dB

7600 Hz–8400 Hz −40 dB

8400 Hz–100,000 Hz −30 dB

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Symbol Parameter Conditions Min Typ Max Units

DISTORTION

STDX, Signal to Total Distortion Sinusoidal Test Method (Note 6)

STDRTransmit or Receive Level=3.0 dBm0 33 dBC

Half-Channel =0 dBm0 to −30 dBm0 36 dBC

=−40 dBm0 XMT 28 dBC

RCV 29 dBC

=−55 dBm0 XMT 13 dBC

RCV 14 dBC

SFDXSingle Frequency Distortion, −43 dB

Transmit

SFDRSingle Frequency Distortion, −43 dB

Receive

IMD Intermodulation Distortion Loop Around Measurement, −41 dB

VFXI+=−4 dBm0 to −21 dBm0, Two

Frequencies in the Range

300 Hz−3400 Hz

CROSSTALK

CTX-R Transmit to Receive Crosstalk, f=300 Hz−3400 Hz −90 −70 dB

0 dBm0 Transmit Level DR=Quiet PCM Code (Note 6)

CTR-X Receive to Transmit Crosstalk, f=300 Hz−3400 Hz, VFXI=Multitone −90 −70 dB

0 dBm0 Receive Level (Note 4)

Encoding Format at DX Output

TP3054 TP3057

μ-Law A-Law

(Includes Even Bit Inversion)

VIN (at GSX)=+Full-Scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0

VIN (at GSX)=0V 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1

0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1

VIN (at GSX)=−Full-Scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0

Note 3: Measured by extrapolation from the distortion test result at −50 dBm0.

Note 4: PPSRX, NPSRX, and CTR–X are measured with a −50 dBm0 activation signal applied to VFXI+.

Note 5: TP3054/57 are measured using C message weighted filter for μ-law and psophometric weighted filter for A-law.

Note 6: CTX–R @ 1.544 MHz MCLKX freq. is −70 dB max. 50% ±5% BCLKX duty cycle.

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Applications Information

POWER SUPPLIES

While the pins of the TP3050 family are well protected against

electrical misuse, it is recommended that the standard CMOS

practice be followed, ensuring that ground is connected to the

device before any other connections are made. In applica-

tions where the printed circuit board may be plugged into a

“hot” socket with power and clocks already present, an extra

long ground pin in the connector should be used.

All ground connections to each device should meet at a com-

mon point as close as possible to the GNDA pin. This mini-

mizes the interaction of ground return currents flowing

through a common bus impedance. 0.1 μF supply decoupling

capacitors should be connected from this common ground

point to VCC and VBB, as close to device pins as possible.

For best performance, the ground point of each CODEC/FIL-

TER on a card should be connected to a common card ground

in star formation, rather than via a ground bus.

This common ground point should be decoupled to VCC and

VBB with 10 μF capacitors.

RECEIVE GAIN ADJUSTMENT

For applications where a TP3050 family CODEC/filter receive

output must drive a 600Ω load, but a peak swing lower than

±2.5V is required, the receive gain can be easily adjusted by

inserting a matched T-pad or π-pad at the output. Table 2 lists

the required resistor values for 600Ω terminations. As these

are generally non-standard values, the equations can be used

to compute the attenuation of the closest practical set of re-

sistors. It may be necessary to use unequal values for the R1

or R4 arms of the attenuators to achieve a precise attenua-

tion. Generally it is tolerable to allow a small deviation of the

input impedance from nominal while still maintaining a good

return loss. For example a 30 dB return loss against 600Ω is

obtained if the output impedance of the attenuator is in the

range 282Ω to 319Ω (assuming a perfect transformer).

T-Pad Attenuator

867411

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π-Pad Attenuator

867412

Note: See Application Note 370 for further details.

TABLE 2. Attentuator Tables for Z1=Z2=300Ω

(All Values in Ω)

dB R1 R2 R3 R4

0.1 1.7 26k 3.5 52k

0.2 3.5 13k 6.9 26k

0.3 5.2 8.7k 10.4 17.4k

0.4 6.9 6.5k 13.8 13k

0.5 8.5 5.2k 17.3 10.5k

0.6 10.4 4.4k 21.3 8.7k

0.7 12.1 3.7k 24.2 7.5k

0.8 13.8 3.3k 27.7 6.5k

0.9 15.5 2.9k 31.1 5.8k

1.0 17.3 2.6l 34.6 5.2k

2 34.4 1.3k 70 2.6k

3 51.3 850 107 1.8k

4 68 650 144 1.3k

5 84 494 183 1.1k

6 100 402 224 900

7 115 380 269 785

8 379 284 317 698

9 143 244 370 630

10 156 211 427 527

11 168 184 490 535

12 180 161 550 500

13 190 142 635 473

14 200 125 720 450

15 210 110 816 430

16 218 98 924 413

18 233 77 1.17k 386

20 246 61 1.5k 366

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Typical Synchronous Application

867406

FIGURE 4.

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TP3054-X, TP3057-X

Physical Dimensions inches (millimeters) unless otherwise noted

Dual-In-Line Package (M)

Order Number TP3054WM-X

NS Package Number M16B

Molded Dual-In-Line Package (N)

Order Number TP3054N-X

NS Package Number N16E

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TP3054-X, TP3057-X

Cavity Dual-In-Line Package (V)

Order Number TP3057V-X

NS Package Number V20A

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TP3054-X, TP3057-X

Notes

TP3054-X, TP3057-X Extended Temperature Serial Interface CODEC/Filter COMBO Family

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