9FGV1001, 9FGV1002, and 9FGV1004 PhiClockTM PCIe Evaluation Board User Guide Introduction The evaluation board is designed to help the customer evaluate the 9FGV1001, 9FGV1002, and 9FGV1004 devices. When the board is connected to a PC running IDT Timing CommanderTM software through USB, the device can be configured and programmed to generate different combinations of frequencies. Board Overview Use Figure 1 and Table 1 to identify: power supply jacks, USB connector, input and output frequency SMA connectors. Figure 1. Evaluation Board Overview 8 9 10 10 7 11 6 12 13 1 (c)2018 Integrated Device Technology, Inc. 2 1 3 4 5 March 1, 2018 9FGV1001, 9FGV1002, and 9FGV1004 PhiClockTM PCIe Evaluation Board User Guide Table 1. Evaluation Board Pins and Functions Label Number Name On-board Connector Label 1 I2C Interface Connector J2 Function Alternative I2C interface connector for Aardvark. IDT Timing Commander can also use Aardvark. 2 USB Connector J6 Connect this USB to your PC to run IDT Timing Commander. The board can be powered from the USB port. 3 Output Power Supply Jack J3 Connect to 1.8V, 2.5V or 3.3V for the output voltage of the device. 4 Core Power Supply Jack J4 Connect to 1.8V, 2.5V or 3.3V for the core voltage of the device. 5 Ground Jack J5 Connect to ground of power supply. 6 Differential Output 1 S7 and S10 Can be a differential pair, or two single-ended outputs. Available logic types: LVCMOS, LVDS and LP-HCSL. 7 Differential Output 2 S6 and S9 Can be a differential pair, or two single-ended outputs. Available logic types: LVCMOS, LVDS and LP-HCSL. 8 Differential Output 3 S5 and S8 9 Reference Output 0 S1 10 Power Supply Voltage Selector E1, E2, E3, E4, E5, E6 11 Reference Output 1 S2 12 Differential Output 0 S3 and S4 Can be a differential pair, or two single-ended outputs. Available logic types: LVCMOS, LVDS and LP-HCSL. 13 DIP Switch U2 Used to control certain pins like OEA, OEB, SEL0, SEL1 and I2C versus Hardware Select mode. Can be a differential pair, or two single-ended outputs. Available logic types: LVCMOS, LVDS and LP-HCSL. Reference or buffered output from the crystal. VDD_REFP1, VDDO_0, VDDO_1, four-way headers used to select a power supply voltage. Connect the center pin to one of the 4 surrounding pins to select a voltage or a source. Reference or buffered output from the crystal. Board Power Supply The evaluation board uses jumpers E1-E6 to set the power supply voltages for various VDD pins. The 4-way jumpers can select 3 different voltages from regulators that use power from the USB port. Selection #2 is the jack for connecting a bench power supply. E1: Power supply for the REF outputs. The E1 voltage also determines the LVCMOS output levels of the REF0 and REF1 outputs. E2: Power supply for the OUT0 output driver. E3: Power supply for the OUT1 output driver. E4: Power supply for the analog (VDDA) and digital (VDDD) core VDD pins. E5: Power supply for the OUT2 output driver. E6: Power supply for the OUT3 output driver. See 9FGV100x Evaluation Board Schematics (Figure 5-Figure 8) for detailed information. (c)2018 Integrated Device Technology, Inc. 2 March 1, 2018 9FGV1001, 9FGV1002, and 9FGV1004 PhiClockTM PCIe Evaluation Board User Guide DIP Switch (U2) Refer to Figure 2 and Table 2 for the DIP switch settings and functions. Figure 2. DIP Switch (U2) Table 2. DIP Switch Settings Switch Number 1 = OEA 2 = OEB 3 = SEL0 4 = SEL1 Function See datasheet. Select 1 of 4 pre-programmed configurations when in Hardware Select mode. Also see switch 8. 5 Not used. 6 Not used. 7 Not used. 8 = Mode Selects operating mode at power-up. "-" or "O" selects I2C mode. "+" selects Hardware Select mode. Interfacing with a Computer to Run Timing Commander As shown in Figure 3, jumpers JP1 and JP2 are installed to use the FTDI chip U6 for connecting to the computer with the USB port J6. The U6 chip translates USB to I2C. When using Aardvark, remove jumpers JP1 and JP2 and connect the Aardvark to connector J2. Default I2C device address for the 9FGV100x is 0x68. Miscellaneous interfaces can connect to J2 pin 1 for the Serial Clock and to J2 pin 3 for the Serial Data signal. J2 pin 2 can be used as ground, but any other ground pin will also work. When OTP in the 9FGV100x devices is burned with multiple configurations, JP1 and JP2 can be applied in JP3 position respectively to connect the SEL0 and SEL1 switches in U2. Move switch 8 to "+" and power-up the 9FGV100x in Hardware Select mode. This enables changing between 4 configurations with SEL0/1. (c)2018 Integrated Device Technology, Inc. 3 March 1, 2018 9FGV1001, 9FGV1002, and 9FGV1004 PhiClockTM PCIe Evaluation Board User Guide Figure 3. Connecting to a Computer via USB Port J6 On-board Crystal A 25MHz crystal is installed on the board and is used as the reference frequency. The board can also be modified to insert an external reference clock into the XIN pin using SMA connector S11. When using an external reference clock, additional components need to be assembled and the crystal needs to be removed. Output Terminations Each differential output has a pair of SMA connectors to connect to a 50 coax. It is recommended to combine the two signals using a balun or splitter/combiner device when measuring jitter or phase noise. The circuit at the SMA connectors is shown in Figure 4. Figure 4. SMA Connectors Circuit (c)2018 Integrated Device Technology, Inc. 4 March 1, 2018 9FGV1001, 9FGV1002, and 9FGV1004 PhiClockTM PCIe Evaluation Board User Guide The circuit is designed for maximum flexibility when testing all possible logic types. Default assembly uses a 0.1F capacitor in place of R14 and R16, and the short across R14 and R16 is cut. No other devices are assembled. This simple AC-coupled configuration allows for testing phase noise and jitter of all possible logic types. The circuit can be modified for custom tests. TP3 is a position to place a differential FET probe. Operating Instructions 1. Set all jumpers for power supply choices (E1-E6), interface choices (JP1 and JP2), and set the U2 switches. 2. Connect an interface: USB or I2C. 3. In the case of an I2C interface, also connect external power supply to jacks J3, J4 and J5. 4. Start Timing Commander for either USB or Aardvark. a. Start new configuration or load TCS file for existing configuration. b. Choose PhiClock personality. c. For Aardvark, click to select Aardvark "Connection Interface". d. For a new configuration, prepare all settings. e. Click f. Click to connect to the 9FGV100x device. Top right should turn green. to write all settings to the 9FGV100x device. g. It should now be possible to measure clocks on outputs. h. While connected, each change to the settings will be written to the 9FGV100x immediately and can be observed at the clock outputs. (c)2018 Integrated Device Technology, Inc. 5 March 1, 2018 A B C OUT3T 5 OUT3C SE Trace 12 inches/50ohm SE Trace 12 inches/50ohm 2 1 2 2pF_NP C8 1 1 CM3 50_NP R61 2 R60 50_NP 2pF_NP C5 OE_B {2} GND O3C_S 1 R23 0 _NP S8 1 50_NP GND 3 4 5 4 2 TP6 U1 OEB OEA SEL1/SDA SEL0/SCL OTP_VPP vREF0_SEL_I2CB REF1 XO XIN/CLKIN 4 VDDO0p12 2R5 OUT0 OUT0B 2 R6 VDDO1p15 OUT1 R82 OUT1B R92 VDDO2p18 1 OUT2 R10 1 OUT2B R11 VDDO3p21 1 OUT3 R12 1 OUT3B R13 12 11 10 15 14 13 18 17 16 21 20 19 02 02 02 02 01 01 01 01 VDDREFp OUT3T OUT3C OUT2T OUT2C OUT1T OUT1C OUT0T OUT0C VDDDp VDDAp VDDO3 VDDO2 SE Trace 12 inches/50ohm 2 1 1 2 2pF_NP C9 1 CM2 50_NP R59 2 R58 50_NP 2pF_NP C6 2 1 GND 3 O2C_S 1 R24 0 _NP S9 50_NP R20 S6 0 _NP O2T_S 1 R18 GND GND 3 4 5 5 4 3 4 2 OUT0C OUT2C IO4 GND3 IO2 GND1 OUT2T TP5 SE Trace 12 inches/50ohm GND 3 1 2 2 1 1 2 1 Date: Size B Title C10 2 2pF_NP 1 1 1 2 GND GND Tuesday, August 16, 2016 Document Number 9FGS9091 EVB revB O1C_S 1 R25 0 _NP S10 R22 1 50_NP GND GND 3 4 5 5 4 3 GND IO GND 1 1 2 IO GND 3 4 5 5 4 3 4 2 OUT0T 4 2 1 Sheet OUT1C IO4 GND3 IO2 GND1 GND 2 1 GND 3 1 GND 3 1 GND OUT1T TP4 OUT0C IO4 GND3 IO2 GND1 TP3 REF1 TP2 3 4 5 REF0 TP1 REF0_S 1 R1 0 _NP S1 cut-able trace REF1_S 1 R7 0 _NP S2 S7 0 _NP O1T_S 1 R19 S4 O0C_S 1 S3 1 C2 5pF_NP GND 2 2 1 5pF_NP C1 1 50_NP R16 0 _NP CM1 50_NP R57 2 R56 50_NP 2 1 0 _NP O0T_S R14 2 R15 2pF_NP C7 2 2pF_NP C4 1 CM0 50_NP OUT1C SE Trace 12 inches/50ohm OUT1T SE Trace 12 inches/50ohm SE Trace 12 inches/50ohm R55 2 R54 50_NP C3 2pF_NP SE Trace 12 inches/50ohm REF1 Support LVCMOS/PCIEX/LVDS OUT0T VDDO1 VDDO0 vREF0_SEL_I2CB_SW 1 R2 10K 2 SE Trace 12 inches/50ohm {2} vREF0_SEL_I2CB_SW vREF0_SEL_I2CB 1 2 2 3 cut-able trace option: 1) Use SMA: don't cut; no load cap 2) No SMA: cut SE Trace 12 inches/50ohm OUT2T OUT2C VDDREFp24 VDDDp7 VDDAp22 24 7 22 9FGS9091_24NBG VDDO3 OUT3 OUT3B VDDO2 OUT2 OUT2B VDDO1 OUT1 OUT1B VDDO0 OUT0 OUT0B VDDREFp VDDDp VDDAp Support LVCMOS/PCIEX/LVDS GND 3 1 GND IO4 GND3 IO2 GND1 8 OEB 5 4 3 6 GND 5 4 OEA 9 SEL1_SDA SEL0_SCL S5 O3T_S1 OE_A SEL1_SDA SEL0_SCL 3 2 1 1 R4 33 2 REF0p23 23 XOp2 XIN_CLKINp1 R3 1 33 2 REF1p3 OTP_VPP {2} 0 _NP R17 2 R21 {2} {2} vREF0_SEL_I2CB REF1 {2} XO {2} XIN_CLKIN EPAD1 EPAD2 EPAD3 EPAD4 EPAD5 EPAD6 EPAD7 EPAD8 EPAD9 25 26 27 28 29 30 31 32 33 J1 HEADER 2 1 1 VDDDp 2 2 2 D 2 2 1 1 1 2 9FGS9091/9FGV1001/9FGV1004 2 2 2 2 2 4 1 1 2 2 1 1 2 2 2 2 6 2 2 1 2 (c)2018 Integrated Device Technology, Inc. 1 2 1 1 2 1 2 5 of 3 4 5 4 Rev 1 A B C D 9FGV1001, 9FGV1002, and 9FGV1004 PhiClockTM PCIe Evaluation Board User Guide Schematics Figure 5. 9FGV100x Evaluation Board Schematic - page 1 March 1, 2018 A B C D 1 3 4 5 S11 GND GND 4 1 5 XINRCONN TP21 1 cut-able XIN_CLKIN_X1 1 TP22 XIN_CLKIN R29 1 XO 50_NP 2 {1} XIN_CLKIN_X1 {1} 4 3 LABEL: OEA OEB SEL0 SEL1 SEL[1:0]/I2C (Float) Unpopulate C23 when Crystal is used as input reference Overlap C23 XIN_CLKIN with C21 XIN_CLKIN 100pF _NP C13 2 1 ESR resistor test 25MHz GND X1 GND XO_X2 R26 0_NP 3 XO_R 1 SMA STRAIGHT_NP C12 6.8pF_NP GND cut-able trace 2 GND 1 2 2 1 C11 6.8pF_NP 2 2 3 GND VDDDp 8 VEE VCC DIP_SW8 U2 1 16 15 14 13 12 11 10 9 1K R33 LD1 Green s1 s2 s3 s4 s5 s6 s7 s8 1 2 R30_LED SDA 1K R32 VDDDp SELR0 SELR1 1 2 4 2 {2,4} 2 1 R27 1 R28 7 Date: Size B Title JP1 HEADER 3 HW SEL SEL1_SDA SDA_AADVAR SCL_AADVAR Tuesday, August 16, 2016 Document Number 9FGS9091 EVB revB JP2 HEADER 3 I2C I2C {1} vREF0_SEL_I2CB_SW AADVARK {1} {1} {1,2} {1,2} OE_A OE_B SEL0 SEL1 OEA OEB SEL0 SEL1 SCL {2,4} 0 2 1 R31 2 0 R30 1 2 10K 2 10K 1 2 3 (c)2018 Integrated Device Technology, Inc. 1 2 3 5 1 Sheet 2 {1} {1,2} SEL1 {1} {1,2} SEL1_SDA HW SEL SEL0_SCL SEL0 1 3 5 7 9 J2 2 4 6 8 10 of GND AARDVARK HEADER 5X2 1 4 Rev 1 A B C D 9FGV1001, 9FGV1002, and 9FGV1004 PhiClockTM PCIe Evaluation Board User Guide Figure 6. 9FGV100x Evaluation Board Schematic - page 2 March 1, 2018 A B C D GND C38 10uF USB_5V USB_5V Power Jack Black J5 Power Jack Red 1 2 GND 0.1uF C46 5 C47 10uF USB_5V 0.01uF C37 1 2 3 6 5 REG_CP3 4 USB_5V GND_J GND GND GND(CP) EN CP IN IN IN(CP) U3 LP38789 {3,4} GND1 GND2 10uF 0.1uF OUT OUT C21 0.1uF GND FB SET OUT(FB) GND C20 C19 GND VDD_J 1 2 1 2 EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD 2 1 2 3 6 5 GND(CP) EN CP IN IN IN(CP) U5 LP38789 R36 21K_1% REG_CP5 4 GND 1 13 14 15 16 17 18 19 20 21 7 8 9 10 12 11 GND FB SET OUT(FB) OUT OUT GND R40 1 2 2 1 4 R34 1 R63 1K_NP 23.2K_1% R39 2 GND 4 R66 10uF C39 0.1uF C40 R67 1K_NP REG_D5 2 GND REG_CP4 10uF C48 0.01uF C41 10uF VDDO_3.3V GND 2 600 ohm 500mA C25 1 FB3 0.1uF USB_5V VDDA_VDDD FB2 600 ohm 500mA C22 2.2 2 R31_C31 1 VDDO_2.5V VDDA_p REG_D3 REG_SET5 13.3K_1% 7 8 9 10 12 11 10.5K_1% R35 REG_SET3 R62 E4 VDDO_1.8V VDDO_3.3V 5 2 VDDO_1.8V3 2 1 HEADER 2 J7 POT_25K_NP VDD_J 1 2 1 2 3 1 2 1 1 2 1 2 J4 R36_C56 1 2 GND 0.1uF C27 VDDDp GND 0.1uF C24 GND(CP) EN CP IN IN IN(CP) U4 LP38789 GND FB SET OUT(FB) OUT OUT Locate near DUT power pin GND 6 5 4 1 2 3 10uF C26 10uF C23 VDDAp 1 2 1 2 EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD 2 15K_1% R38 7 8 9 10 12 11 1 13 14 15 16 17 18 19 20 21 J3 3 VDDO_J 16.2K_1% R37 REG_SET4 R65 1K_NP REG_D4 GND 10uF C42 C14 0.1uF C15 10uF E3 2 3 VDDO_3.3V 5 VDDO_J 2 2 E6 1 VDDO_1.8V 4 VDDO_J 2 E5 VDDO_3.3V 5 VDDO_1.8V 3 VDDO_3.3V 5 VDDO_J 1 1 VDDO_1.8V 3 4 2 VDDO_3.3V 5 VDDO_J VDDO_1.8V3 4 1 VDDO_3.3V 4 5 E2 E1 2 VDDO_1.8V 3 VDDO_J 2 Header Alignment: Single pin header above and below the center pin of 3-pin header so that center pin can be jumped with the surrounding 4 pins, shown as left 2 R64 GND VDDO_2.5V Power Jack Red 3 1 4 R33_C48 1 Date: Size B Title 1 4 C16 0.1uF 2 FB7 2 Tuesday, August 16, 2016 Document Number 9FGS9091 EVB REVB C43 0.1uF 600 ohm 500mA VDDO_3 1 GND FB6 C34 0.1uF VDDO_4 2 600 ohm 500mA VDDO_2 1 GND FB5 C31 0.1uF VDDO_3 2 600 ohm 500mA VDDO_1 1 GND FB4 C28 0.1uF VDDO_2 GND 2 600 ohm 500mA VDDO_0 1 VDDO_1 GND FB1 600 ohm 500mA VDD_REFp 1 VDD_REFP1 VDDO_2.5V VDDO_2.5V VDDO_2.5V VDDO_2.5V VDDO_2.5V GND GND GND GND GND 1 Sheet 3 of VDDREFp VDDO2 4 C45 0.1uF Rev 1 VDDO3 C36 0.1uF C33 0.1uF VDDO1 C30 0.1uF VDDO0 C18 0.1uF Locate near DUT power pin C44 10uF C35 10uF C32 10uF C29 10uF C17 10uF LABEL ON EACH RESPECTIVE PIN OF HEADERS: 1.8V, 2.5V, 3.3V 1 2 VDDAP_VDDDP1 POT_25K_NP R32_C45 EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD EPAD 13 14 15 16 17 18 19 20 21 1 2 3 1 2 1 1 2 POT_25K_NP 2 3 1 2 1 1 2 1 1 2 1 2 1 2 1 2 2 1 2 1 2 8 1 (c)2018 Integrated Device Technology, Inc. 2 5 A B C D 9FGV1001, 9FGV1002, and 9FGV1004 PhiClockTM PCIe Evaluation Board User Guide Figure 7. 9FGV100x Evaluation Board Schematic - page 3 March 1, 2018 A B C TP24 GND USB_5V 1 GND 2 D {3} FB8 5 2 C52 GND 27 R45 GND R48 1.5K USB_3 33pF 4 GND VCC2232 GND 10K USB_8 47 2 1 48 4 R50 44 VCC2232 43 5 7 8 6 TEST EEDATA EESK EECS RESET# XTOUT XTIN RSTOUT# USBDP USBDM 3V3OUT U6 0.1uF C56 470 USB_15 FB9 600 ohm 500mA R43 XTOUT 0.1uF 3V3_USB C57 VCC2232_3V USB_2 XTIN C59 LD2 Green GND Y1 6MHz 2 4 USB_13 R42 1K USB_1 0.1uF 2 10uF USB_11 C55 1 33pF C58 1 R44 27 USB_6 3 USB_7 USB_5 1 2 4 FB10 300ohm 2A USB_42 1 USB_14 USB PORT GND D+ D- VBUS J6 C53 47uF C805A R41 1 0 mod1: connect C55 p1 to C52 p1 1USB_12 300ohm 2A 2 1 2 1 2 1 1 2 TP23: Label TP23 / 5V INPUT R41: provide USB 5 V to Regulators 2 2 1 1 2 1 2 TP23 1 2 1 2 1 2 3 42 VCC VCC GND C54 C51 C50 1 1 C49 1 14 31 GND 41 26 30 29 28 27 40 39 38 37 36 35 33 32 10 15 13 12 11 24 23 22 21 20 19 17 16 3 3V3_USB1 1 3V3_USB0 1 10K R51 10K R49 2 2 3V3_USB 1 USB_10 R47 R46 1 USB_9 2 3 2 On Layout, make EPAD to easy connect to GND FT2232_LQFP48 PWREN# SI/WUB UNUSED8 UNUSED9 UNUSED10 UNUSED11 UNUSED0 UNUSED1 UNUSED2 UNUSED3 UNUSED4 UNUSED5 UNUSED6 UNUSED7 SI/WUA GPIOH0 GPIOH1 GPIOH2 GPIOH3 TCK/SK TDI/DO TDO/DI TMS/CS GPIOL0 GPIOL1 GPIOL2 GPIOL3 3V3_USB 10uF 0.1uF 0.1uF 2 2 10nF 2 VCCIOA VCCIOB 46 AVCC AGND GND GND GND GND 45 9 18 25 34 9 EPAD1 EPAD2 EPAD3 EPAD4 (c)2018 Integrated Device Technology, Inc. 49 50 51 52 5 0 0 2 2 Date: Size B Title Tuesday, August 16, 2016 Document Number IDT_9FGS9091 EVM_BOARD_REV1 SDA {2} SCL {2} 1 Sheet 1 4 of 4 Rev 1 A B C D 9FGV1001, 9FGV1002, and 9FGV1004 PhiClockTM PCIe Evaluation Board User Guide Figure 8. 9FGV100x Evaluation Board Schematic - page 4 March 1, 2018 9FGV1001, 9FGV1002, and 9FGV1004 PhiClockTM PCIe Evaluation Board User Guide Ordering Information Orderable Part Number Description EVK9FGV1001 EVK9FGV1002 Evaluation board with all differential outputs AC coupled. EVK9FGV1004 Revision History Revision Date March 1, 2018 Description of Change Initial release. Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as "IDT") reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. 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