MSC23436B-xxBS10/DS10 (98.11.16) OKi semiconductor MSC23436B-xxBS10/DS10 4,194,304 Word By 36-Bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE GENERAL DESCRIPTION The Oki MSG23436B-xxBS10/DS10 is a fully decoded, 4,194,304 word X 36 bit CMOS dynamic random access : memory composed of eight 16MbDRAMs (4Mx4) in SOU and two 8Mb DRAMs(4Mx2) in SOJ. The mounting o DRAMs together with decoupling capacitors on a 72-pin glass epoxy Single-in-Line Package supports any application where high density and large capacity of storage memory are required. aftan ao FEATURES 4,194,304 word x 36 bit Parity organization 72-Pin Socket Insertable Module MSC23436B-xxBS10 : Gold tab MSC23436B-xxDS10 : Solder tab Single +5V supply + 10% tolerance Input =: TTL compatible Output : TTL compatible,tristate,noniach Refresh : 2048 cycles/32 ms CAS before BAS refresh, TAS before RAS hidden refresh, RAS only refresh capability PRODUCT FAMILY FAMILY MOOT) cycle Power Dissipation trac | taa | tcac | (MAX) | Operating | Standby (MAX) (Max) MSC23436B-60BS10/D810 | 60ns | 30ns | 18ns.{ 110ns | 5720mW 55mW MSC23436B-708810/0810 | 7Ons| 35ns | 20ns | 130ns | 5226mWMSC23436B-xxBS10/DS 10 ~ 107.9540.2 3.3840.2 | |. 101.19TYP _ 1 mo @3.18 th . / o 25,440.2 Nhd to bd te bd tt bgt bd? * . * i We Jo I YP TYPTHH e o o o e o 2 o o o y 10.169 6.35 l RU | Le nn i i 2.03TYP 6:35 LoaTyP 6.35TYP 93.25 > *] The common size difference of the board width 12.5mm of its height is specified as 40.2. The value above 12.5mm is specified as 10.5. 3.28MAK we al = a 3.7MIN t +0.1 1.27 9.08.FUNCTIONAL BLOCK DIAGRAM MSC23436B-xxBS$10/DS10 CAS DQ [-DQ29 WE DQ -po30 OE vec vss | _ DQ34 AQ-A10 pa RAS pa | Da32 CAS pa [-Da33 WE ba FpDaes4 OE vec vss A0-A10 RASO RAS2 cAsO -" cAs2 - WE +# Ad-A10 paf Dad RAS pak bat e- CAS DQF D2 ? WE Daf Das vec vss | 7 aA0-aio pai DGa4 RAS par Das CAS bpaf DaQ ? WE DQT DQ7 OE vec vss | @4 A0-A10 po fr Das RAS po F DQi7 CASI CAS2. _ WE OE vec vss | @1 AC-A10 pafe Das o ae DQ t bDaQIN L % aoe Da F Dail WE le ? OE DQT2 yvcc vss | l AD-A10 pah ba13 RAS par Dat4 e_ CAS Dar bai5 we Dar pate OE vec VSS cAsi CAS3 vec t Ci Tr veo aS we c10 -MSC23436B-xxBS10/DS10 (98.11.16) PIN CONFIGURATION MSC23436B-xxBS10/DS10 PinNo. Pinname | PinNo. Pinname | PinNo. Pinname | Pin No. Pin name 1 Vss 19 A10 37 DQt7 55 Dai2 2 pao 20 Da4 38 DQ35 56 DAZ 3 DQI18 a1- Da22 39 Vss 57 DQa13 4 DO1 22 DQs 40 TASO 58 DaQsa1 5 Dai9 23 Da23 41 TAS2 59 Voc 6 Daz 24 DQG 42 CASS 60 DQs2 7 DaQz0 25 DQ24 43 TAST 61 DQi4 8 Das 26 DQ7 44 FASO 62 DQ33 9 Dae21 27 DQ25 45 NG 63 DQi5 10 Voc 26 AT 46 NC 64 pas4 11 NC 29 - NC 47 WE 65 DQI6 12 AO 30 Voc 48 NC 66 NC 13 At 31 AS 49 pag 67 PD1 14 A2 32 Ag 50 0Q27 68 PD2 15 A3 33 NG 51 DQ10 69 PDS 16 A4 34 RAS. 52 bazs 70 PD4 17 A5 35 DQ26 53 0Q11 71 NC 18 AG 36 pas 54 paezg 72 VssMSC23436B-xxBS10/DS10 (98.11.16) ELECTRICAL CHARACTERISTICS ABSOLUTE_MAXIMUM RATINGS Rating Symbot Value Unit Voltage on any pin relative to Vss Vin Vout 1,0 ~+7.0 Vv Voltage Vcc supply relative to Vss Voc - 1.0 ~4+7.0 V Short circuit output current: los 50 mA Power dissipation Pp 10 WwW _ Operating temperature Topr -0 ~ +70 ae: Storage temperature Tst@ - 40 ~+ 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted within the limits as specified in this data sheet. Exposure to absolute maximum rating conditions for extended period may affect device rellabity. RECOMMENDED OPERATING CONDITIONS Parameter Symbol MIN TYPE MAX UNIT [Operating . temperature Supply Voltage Veo. 4.5 5.0 5.5 v Vgs 0 0 0 Vo Joc~+70C Input high voltage Vin 2.4 - 6.5 V Input low voltage Vit -1.0 - 0.8 v CAPACITANCE Parameter NOTE: AQ-A10 Capacitance maaciirar Measureg with Boonton Meter.DC CHARACTERISTICS (Vcc = 5V + 10%, Ta = 0~+70C) MSC23436B-xxBS10/DS10 (98.11.16) with the output open. 2, Address can be changed once or less while RAS = Vj, 3. Address canbe changed once or lass while TAS = ViH tae MSC23436B- MSC23436B- . Parameter Symbol Condition 60BS19/Ds10 | 70BS10/DS10 Unit | Note Min Max Min Max input Leakage Current OVSVins6.5V: hu All other pins not -100 | 100 | -100 | 100 | #A under tast = 0V Output Leakage Current ILo Data out is disabie 10 10 10 10 WA OVSV 5 1S5.5V Output High Voltage Vou. | on=-5.0mA 2.4 | Veco 2.4 Vee Vv Output Low Voltage Voi lo. =4.2mA 0.4 - 0.4 Vv Average power supply current ' | RAS cycling, : (Operating) oct | cK cycling - | ioao} - | 950 | mA} 1,2 tac =min RAS Power supply current lece =ViH TTL - 20 20 | mA (Standby) CAS . 10 . to | ma =Vin = | Mos Average power supply current RAS cycling, : (RAS only refresh) ccs | cas =VIH, ee . 950 | mA | 1,2 tac=min Average power supply current trcamin (CAS before RAS refresh ) loce 1040 . 960 | MA|1 Avarana anwar cunnh: currant RAS=Ve Average power supply current RAS = Vit (Fast page) . 'cor CAS cycling 920 . 830 | MA] 1.3 : tec =min NOTE: 1. locisdependent on output loading and cycles rates. Spacified values are obtainedAC CHARACTERISTIC | (Voc = 5V10%, Ta=0 ~70 C) MSC23436B-xxBS10/DS10 (98.11.16) NOTE 1,2,3,9,10 MSC23436B- MSC23436B- Parameter Symbol 60BS10/D$10 70BS10/DS10 UNIT | NOTE MIN MAX MIN MAX Random read or write cycle time tac 110 - 130 - ns Fast page mode cycle time IPC 40 - 45 - ns Access time from RAS tRAC - 60 - 70 ns 14,5 Access time from TAS: tcAc - 15 - 20 ns 14,5 Access time from column address | TAA - 30 35 ns | 4,6 Access time from TAS precharge ICPA 35 - 40 ns 4 TAS to output in Low-Z ~ | terz 0 . 0 - | ons f4 Output buffer turn-off delay , tOFF oO 15 0 20 ns |7 Transition time IT 3 50 3 50 ns |3 Refresh period 'REF 32 - 32 ms RAS precharge time tRP 40 - 50 - ns RAS pulse width iRAS 60 10K 70 10K ns FAS pulse width (Fast page mode} | 'RASP 60 | 100K! 79 | 100K 1 ns _ RAS hold time IRSH 15 - 20 - ns TAS precharge time tcP 10 - 10 - ns TAS pulse width {CAS 15 10K 20 10K ns TAS hold time tCSH 60 - 70 - ns TAS to BAS precharge time tCRP 5 - 5 - ns |5 BAS to column address delay time | tRAD 15 30 15 35 ns 16 Row address set-up time tasR 0) - 0 ns Row address hold time tRAH 10 10 - ns Column address set-up time tASC 0 - 0 - ns Column address hold time iCAH 15 . 15 - ns Column address to RAS lead time =| tRAL 30 35 - nsAC CHARACTERISTICS (Continued) (Voc = 5V+10%, Ta=0~70 C) MSC23436B-xxBS10/DS10 (98.11.16) MSC23436B- MSC23436B- Parameter Symbol | 60BS10/DS10 | 7OBS10/OS10 | UNIT | NOTE MIN | MAX MIN MAX Read command set-up time tACS 0 - 0 - ns Read command hold time tRCH O- - 0 - ns |8 Read command hold time reference | tary o - ns |8 to RAS Write command set-up time twes 0 . 0 - ns Write command hold time tWCH 10 - 13 - ns Write command pulse width twPe 10 10 - 7 ons Write command to RAS read time _| tRWL, is | - | 20] - ns . Write command to CAS read time tCWL 15 20 ns Data-in set-up time ips 0 - 0 - ns Data-in hold time DH i0 - 15 - ns TAS active delay time from BAS tRPC 5 - 5 - ns precharge . RAS to CAS set-up time tcSR 10 - 10 - ns (CAS before RAS) TAS hold time (CAS before RAS) =| CHR 10 : 10 : ns WE to BAS precharge time tWRP 10 - 10 - ns (CAS before RAS} WE hold time from RAS tWRH 10 - 10 - ns (CAS before RAS) FAS to WE Set-up tim (test mode) | WTS 10 : 1o-| - ns FAS to WE hold time (test mode) | WTH 10 - 10 - nsNOTES: 1. 3) > oO 10. MSC23436B-xxBS10/DS10 (98.11.16) Astart-up delay of 200 1s is required after power-up followed by aminimum of 8 initialisation cycles (AAS only refresh or TAS before RAS refresh) before proper device operation is achieved, , Wher using the intemal refrash counter, aminimum of 8 CAS before RAS initialization cycles is required. AC measurement assume tT = 5 ns. VIH (min.) and VIL (max.) are reference levels for measuring input signals. Transition times are measured between VjH and ViL. Measured with aioad circuit eqivaient io 2 TTL ioads and 100 pF. Operation within the tacp (max} ima ensures that tRac (max) can be met. taco(max) is specified as areference point only. if trop is greater than the specified tacp(max) limit, then access time is controlled by tcac. Operation within the tRap (max limit ensures that trac (max) can be met. tRAD(max) is specified as areference point only. I tRADis greater than the specified tRAD (max} limit, then access time is controlled by ta a. torrdefines the time at which time the output achieves an open circuit condition and is not referenced to output voltage levels. tRCH or RAH must be satisfied for a read cycie. The test mode is initiated by performing aWE and before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheets is an 8-bil parallel test function. CA10, CA1 and CAO are not used. In aread cycle, if all intemal bits are equal, the DQ pin will indicate afigh level. if any intemal bits are not equal, ie DO pin will indicate alow fevel. The test mode is cleared and the memory device returned to its normal operating state by performing aFAS only refresh cycle or aCAS before RAS refresh cycle. In atest mode read cycle, the access time parameters are delayed by 5ns. The test mode parameters ara obtained by adding 5 ns to the normal read cycle values.