INCH-POUND MIL-M-38510/208D 15 February 2006 SUPERSEDING MIL-M-38510/208C 31 January 1984 MILITARY SPECIFICATION MICROCIRCUIT, DIGITAL, 4096-BIT SCHOTTKY, BIPOLAR, PROGRAMMABLE READ-ONLY MEMORY (PROM), MONOLITHIC SILICON Inactive for new design after 24 July 1995 This specification is approved for use by all Departments and Agencies of the Department of Defense. The requirements for acquiring the product herein shall consist of this specification sheet and MIL-PRF 38535. 1. SCOPE 1.1 Scope. This specification covers the detail requirements for monolithic silicon, programmable read-only memory (PROM) microcircuits which employ thin film nichrome resistors or titanium-tungsten as the fusible link or programming element. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M-38510 have been superseded by MIL-PRF-38535, (see 6.4). 1.2 Part or Identifying Number (PIN). The PIN is in accordance with MIL-PRF-38535, and as specified herein. 1.2.1 Device types. The device types are as follows: Device type 01 02 03 04 05 Circuit 512 word/8 bits per word PROM with uncommitted collector 512 word/8 bits per word PROM with active pull-up and a choice third high-impedance state output 512 word/8 bits per word PROM with active pull-up and a third high-impedance state output 512 word/8 bits per word PROM with uncommitted collector 512 word/8 bits per word PROM with active pull-up and a third high-impedance state output 1.2.2 Device class. The device class is the product assurance level as defined in MIL-PRF-38535. 1.2.3 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter J K X Y Z Descriptive designator GDIP1-T24 or CDIP2-T24 GDFP2-F24 or CDFP3-F24 See figure 1 See figure 2 CQCC1-N24 Terminals 24 24 24 20 24 Package style Dual-in-line Flat pack Flat pack Dual-in-line Square leadless chip carrier Comments, suggestions, or questions on this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC-VAS, P. O. Box 3990, Columbus, OH 43218-3990, or emailed to mailto:memory@dscc.dla.mil. Since contact information can change, you may want to verify the currency of this address information using the ASSIST Online database at http://assist.daps.dla.mil AMSC N/A FSC 5962 MIL-M-38510/208D 1.3 Absolute maximum ratings. Supply voltage range ............................................................................. Input voltage range ................................................................................ Storage temperature range .................................................................... Lead temperature (soldering, 10 seconds).............................................. Thermal resistance, junction to case (JC) 1/: Cases J, K, and Y ............................................................................. Case X and Z ................................................................................... Output voltage applied ............................................................................ Output sink current............................................................................ Maximum power dissipation (PD) 2/ ........................................................ Maximum,unction temperature (TJ) ......................................................... -0.5 V dc to +7.0 V dc -1.5 V dc at -10 mA to +5.5 V dc -65 to +150C +300C 30C/W 36 C/W -0.5 V dc dc to +VCC 100 mA 1.02 W +175C 1.4 Recommended operating conditions. Supply voltage ....................................................................................... +4.5 V dc minimum to +5.5 V dc maximum Minimum high-level input voltage .......................................................... 2.0 V dc Maximum low-level input voltage .......................................................... 0.8 V dc Normalized fanout (each output) .......................................................... 8 mA 3/ Case operating temperature range (TC) .................................................. -55 C to +125 C 2. APPLICABLE DOCUMENTS 2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This section does not include documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this specification, whether or not they are listed. 2.2 Government documents. 2.2.1 Specifications and Standards. The following specifications and standards form a part of this specification to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF-38535 - Integrated Circuits (Microcircuits) Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard for Microelectronics. Interface Standard Electronic Component Case Outline ______ 1/ Heat sinking is recommended to reduce the junction temperature. 2/ Must withstand the added PD due to short circuit test (e.g. IOS). 3/ 16 mA for circuit F devices. 2 MIL-M-38510/208D (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.3 Order of precedence. In the event of a conflict between the text of this specification and the references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Qualification. Microcircuits furnished under this specification shall be products that are manufactured by a manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturers list before contract award (see 4.3 and 6.3). 3.2 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.3 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein. 3.3.1 Terminal connections. The terminal connections shall be as specified on figures 3. 3.3.2 Truth table 3.3.2.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered itme drawing shall be as specified on figure 4. When required in groups A, B, or C (see 4.4), the devices shall be programmed by the manufacturer prior to test in a checkerboard pattern (a minimum of 50 percent of the total number of bits programmed) or to any altered item drawing pattern which includes at least 25 percent of the total number of bits programmed. 3.3.2.2 Programmed devices. The truth table for programmed devices shall be as specified by the altered item drawing. 3.3.3 Logic diagram. The logic diagram shall be as specified on figure 5. 3.3.4 Case outlines. The case outlines shall be as specified in 1.2.3. 3.4 Lead material and finish. The lead material and finish shall be in accordance with MIL-PRF-38535 (see 6.6). 3.5 Electrical performance characteristics. The electrical performance characteristics are as specified in table I, and apply over the full recommended case operating temperature range, unless otherwise specified. 3.6 Electrical test requirements. The electrical test requirements shall be as specified in table II, and where applicable, the altered item drawing. The electrical tests for each subgroup are described in table III. 3.7 Marking. Marking shall be in accordance with MIL-PRF-38535. 3 MIL-M-38510/208D TABLE I. Electrical performance characteristics. Test Symbol High-level output voltage VOH Low-level output voltage VOL Input clamp voltage VIC Maximum collector cut-off current High-impedance (off-state) output high current High-impedance (off-state) output low current High-level input current ICEX IOHZ IOLZ IIH1 IIH2 Low-level input current IIL1 IIL2 Short circuit output current Supply current IOS Propagation delay time, high-to-low level logic, address to output Propagation delay time, low-to-high level logic, address to output Propagation delay time, high-to-low level logic, enable to output Propagation delay time, low-to-high level logic, enable to output tPHL1 ICC tPLH1 tPHL2 tPLH2 Conditions 1/ 2/ VCC = 4.5 V, IOH = -2 mA VCC = 4.5 V, IOL = 8 mA 3/ VCC = 4.5 V, IIN = -10 mA, TC = 25C VCC = 5.5 V, VO = 5.2 V VCC = 5.5 V VO = 5.2 V VCC = 5.5 V, VO = 0.5 V VCC = 5.5 V, VIN = 5.5 V VCC = 5.5 V, VIN = 4.5 V, special programming pin VCC = 5.5 V, VIN = 0.5 V VCC = 5.5 V, VIN = 0.5 V, for CE3 and CE4 VCC = 5.5 V, VO = 0.0 V 4/ VCC = 5.5 V, VIN = 0, outputs = open VCC = 4.5 V and 5.5 V, CL = 30 pF (see figure 6) VCC = 4.5 V and 5.5 V, CL = 30 pF (see figure 6) Device type 02,03,05 Limits Min Max 2.4 --- V All --- 0.5 V All --- -1.5 V 01,04 --- 100 A 02,03,05 --- 100 A -100 A 02,03,05 All --- 50 A All --- 100 A All -1.0 -250 A 01,02 -1.0 -1000 A 02,03,05 -10 -100 mA 01,02,03 04,05 ----- 185 155 mA mA 01,02,03 04,05 ----- 90 80 ns ns 01,02,03 04,05 ----- 90 80 ns ns 01,02,03 04,05 ----- 50 40 ns ns 01,02,03 04,05 --- 50 40 ns ns 1/ Complete terminal conditions shall be as specified on table III. 2/ For device type 03, the fusing pins FE1 and FE2 may be grounded or floating during operation. 3/ IOL = 16 mA for circuit F devices. 4/ Not more than one output shall be grounded at one time. Output shall be at high logic level prior to test. 4 Unit MIL-M-38510/208D TABLE II. Electrical test requirements. Subgroups (see table III) 1/, 2/, 3/ Class S Class B devices devices 1 1 MIL-PRF-38535 test requirements Interim electrical parameters Final electrical test parameters for unprogrammed devices Final electrical test parameters for programmed devices Group A test requirements Group B end-point electrical parameters when using the method 5005 QCI option Group C end-point electrical parameters Group D test requirements 1*, 2, 3, 7*, 8 1*, 2, 3, 7* 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8 1*, 2, 3, 7*, 8 1*, 2, 3, 7*, 8, 9, 1, 2, 3, 7, 8 9, 10, 11 N/A 1, 2, 3, 7, 8 1, 2, 3, 7, 8 1/ * indicates PDA applies to subgroups 1 and 7. 2/ Any or all subgroups may be combined when using high-speed testers. 3/ Subgroups 7 and 8 shall consist of verifying the pattern specified. 3.8 Processing options. Since the PROM is an unprogrammed memory capable of being programmed by either the manufacturer or the user to result in a wide variety of configurations, two processing options are provided for selection in the contract, using an altered item drawing. 3.8.1 Unprogrammed PROM delivered to the user. All testing shall be verified through group A testing as defined in 3.3.2.1, table II, and table III. It is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.8.2 Maunufacturer-programmed PROM delivered to the user. All testing requirements and quality assurance provisions herein, including the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery. 3.9 Microcircuit group assignment. The devices covered by this specification shall be in microcircuit group number 14 (see Appendix A MIL-PRF-38535.) 5 MIL-M-38510/208D 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not effect the form, fit, or function as described herein. 4.2 Screening. Screening shall be in accordance with MIL-PRF-38535 and shall be conducted on all devices prior to qualification and quality conformance inspection. The following additional criteria shall apply: a. The burn-in test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD883. b. Interim and final electrical test parameters shall be as specified in table II, except interim electrical parameters test prior to burn-in is optional at the discretion of the manufacturer. c. Additional screening for space level product shall be as specified in MIL-PRF-38535, appendix B. d. Class B devices processed to an altered item drawing may be programmed either before or after burn-in at the manufacturer's discretion. The required electrical testing shall include, as a minimum, the final electrical tests for programmed devices as specified in table II herein. Class S devices processed by the manufacturer to an altered item drawing shall be programmed prior to burnin. 4.3 Qualification inspection. Qualification inspection shall be in accordance with MIL-PRF-38535. 4.4 Technology Conformance inspection (TCI). Technology conformance inspection shall be in accordance with MIL-PRF-38535 and as specified herein for groups A, B, C, and D inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. Group A inspection shall be in accordance with table III of MIL-PRF-38535 and as follows: a. Electrical test requirements shall be as specified in table II herein. b. Subgroups 4, 5, and 6 shall be omitted. c. For unprogrammed devices, a sample shall be be selected to satisfy programmability requirements prior to performing subgroups 9, 10, and 11. Twelve devices shall be submitted to programming (see 3.3.2.1). If more than 2 devices fail to program, the lot shall be rejected, At the manufacturer's option, the sample may be increased to 24 total devices with no more than 4 total device failures allowed. d. For unprogrammed devices, 10 devices from the programmability sample shall be submitted to the requirements of group A, subgroups 9, 10, and 11. If more than two total devices fail in all three subgroups, the lot shall be rejected. At the manufacturer's option, the sample may be increased to 20 total devices with no more that 4 total device failures allowed. 6 MIL-M-38510/208D 4.4.2 Group B inspection. Group B inspection shall be in accordance with table II MIL-PRF-38535. 4.4.3 Group C inspection. Group C inspection shall be in accordance with table IV of MIL-PRF-38535 and as follows: a. End-point electrical parameters shall be as specified in table II herein. b. The steady-state life test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burnin test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MILSTD-883. c. For qualification, at least 25 percent of the sample selected for life testing shall be programmed (see 3.3.2). For quality conformance inspection, the programmability sample (see 4.4.1c) shall be included in the life test. 4.4.4 Group D inspection. Group D inspection shall be in accordance with table V of MIL-PRF-38535 and as follows: a. End-point electrical tests shall be as specified in table II herein. b. Subgroup 2 shall be omitted for devices in package Z. c. For moisture resistance and salt atmosphere of subgroups 3 and 5, omit initial conditioning for devices in package Z. 4.5 Methods of inspection. Methods of inspection shall be as specified and as follows: 4.5.1 Voltage and current. All voltages given are referenced to the microcircuit ground terminal. Currents given are conventional and positive when flowing into the referenced terminal. 4.6 Programming procedure identification. The programming procedure to be utilized shall be identified by the manufacturer's circuit designator. 7 MIL-M-38510/208D Symbol A b c D E E1 E2 E3 e k L Q S1 S2 Inches Min Max .045 .090 .015 .019 .003 .006 ---.400 .340 .385 ---.400 .125 ---.030 ---.050 BSC .008 .015 .250 .370 .010 .040 .005 ---.005 --30 90 Dimension Millimeters Min Max 1.14 2.29 .38 .48 .08 .15 ---10.16 8.64 9.78 ---10.16 3.18 ---.76 ---1.27 BSC .20 .38 6.35 9.40 .25 1.02 .13 ---.13 ---30 90 Notes 5 5 3 3 14 4, 6 10 2 7, 8 11 12, 13 FIGURE 1. Case outline X. 8 MIL-M-38510/208D NOTES: 1. Index area; a notch or a pin one identification mark shall be located adjacent to pin one and shall be within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. Dimension Q shall be measured at the point of exit of the lead from the body. 3. Ths dimension allows for off-center lid, meniscus and glass overrun. 4. The basic pin spacing is .050 (1.25 mm) between centerlines. Each pin centerline shall be located within .005 (0.13 mm) of its exact longitudinal position relative to pins relative to pins 1 and 24. 5. All leads - increase maximum limit by .003 ( 0.08mm) measured at the center of the flat, when lead finish A is applied. 6. Twenty-two spaces. 7. Applies to all four corners (leads number 3, 10, 15, and 22). 8. Dimension S1 may be .000 (0.00 mm) if leads number 3, 10, 15, and 22 bend toward the cavity of the package within one lead width from the point of entry of the lead, into the body or if the leads are brazed to the metallized ceramic body (see MIL-STD-1835) . 9. Optional configuration; if this configuration is used, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 10. Optional, see note 1. If a pin one identification mark is used in addition to this tab, the minimum limit of dimension k does not apply. 11. Applies to leads number 2, 11, 14, and 23. 12. Lead configuration is optional within dimension E except dimensions b and c apply (see MIL-STD-1835). 13. Applies to lead numbers 1, 2, 11, 12, 13, 14, 23, and 24. 14. Applies to all edges. FIGURE 1. Case outline X - Continued. 9 MIL-M-38510/208D Symbol A b b1 C D E E1 e L L1 Q S S1 S2 Inches Min Max ---.175 .016 .020 .040 .060 .008 .012 .970 1.010 .280 .300 .290 .320 .090 .110 .125 .180 .150 ---.020 .060 ---.098 .005 ---.005 ---0 15 Dimension Millimeters Min Max ---4.44 .41 .51 1.02 1.52 .20 .30 24.64 25.65 7.11 7.62 7.37 8.13 2.29 2.79 3.18 4.58 3.81 ---.51 1.52 ---2.49 .13 ---.13 ---0 15 Notes 11, 8 8, 2 11, 8 4 4 7 5, 9 3 6 6 8 FIGURE 2. Case outline Y. 10 MIL-M-38510/208D NOTES: 1. Index area; a notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The minimum limit for dimension b1 may be .020 (.51 mm) for leads number 1, 10, 11, and 20 only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54 mm) between centerlines. Each pin centerline shall be located within .010 (.25 mm) of its exact longitudinal position relative to pins 1 and 20. 6. Applies to all four corners (leads number 1, 10, 11, and 20) (see MIL-STD-1835). 7. Lead center when is 0. E1 shall be measured at the centerline of leads (see MIL-STD-1835). 8. All leads - Increase maximum limit by .003 (.08 mm) measured at the center of the flat, when lead finish A is applied. 9. Eighteen spaces. 10. No organic or polymeric materials shall be molded to the bottom of the package. 11. Applies to all leads. FIGURE 2. Case outline Y - Continued. 11 MIL-M-38510/208D Device type Case outline Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 01 and 02 J, K, X, and Z A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 GND O4 O5 O6 03 J, K, and X Terminal symbol A3 A4 A5 A6 A7 A8 O1 O2 O3 O4 FE2 GND FE1 O5 O6 16 17 18 19 20 O7 O8 CE4 CE3 O7 O8 STROBE CE2 CE 2 CE 1 A0 21 22 23 24 CE 1 NC A8 VCC A1 A2 VCC NOTE: Case Z; option A with active terminals on plane 1. FIGURE 3. Terminal connections. 12 04 and 05 Y A0 A1 A2 A3 A4 O1 O2 O3 O4 GND O5 O6 O7 O8 CE 1 A5 A6 A7 A8 VCC ------------- MIL-M-38510/208D Device types 01 and 02 WORD NO. NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA CE 1 L H L H L H L H L H L H L H L H ENABLE CE3 CE4 CE ADDRESS A8 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 DATA O4 O5 O6 O7 O8 L L H H L L H H L L H H L L H H X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X OC OC OC OC OC OC OC OC OC OC OC OC 4/ OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC 4/ OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC 4/ OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC 4/ OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC 4/ OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC 4/ OC OC OC 2 L L L L H H H H L L L L H H H H L L L L L L L L H H H H H H H H X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X OC OC OC OC OC OC OC OC OC OC OC OC 4/ OC OC OC OC OC OC OC OC OC OC OC OC OC OC OC 4/ OC OC OC Device type 03 WORD NO. NA NA NA NA NA CE 1 L H L H L CE2 STROBE L L H H H H H H H L A8 A7 A6 ADDRESS A5 A4 A3 A2 A1 A0 O1 O2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X OC OC 4/ OC OC OC OC OC OC OC OC OC 4/ 4/ 4/ 4/ OC OC OC OC Last data is latched X X X X X X X X X X X X X X X O3 DATA O4 O5 O6 O7 O8 OC OC 4/ OC OC OC 4/ OC OC OC 4/ OC Device types 04 and 05 WORD NO. NA NA ENABLE CE 1 H L A8 A7 A6 A5 X X X X X X X X ADDRESS A4 A3 X X X X A2 A1 A0 O1 O2 O3 DATA O4 O5 O6 O7 O8 X X X X X X OC 4/ OC 4/ OC 4/ OC 4/ OC 4/ OC 4/ OC 4/ OC 4/ NOTES: 1. NA = Not applicable. 2. X = Input may be high level, low level, or open circuit. 3. OC = Open circuit (high resistance output). 4. The outputs for an unprogrammed device shall be high for circuits A, B, D, and F, and low for circuit C and G. FIGURE 4. Truth table (unprogrammed). 13 MIL-M-38510/208D LOGIC CIRCUIT A (Device types 01 and 02) FIGURE 5. Logic diagrams. 14 MIL-M-38510/208D LOGIC CIRCUIT B (Device types 01, 02, 04, & 05) and LOGIC CIRCUIT F (Device type 05) FIGURE 5. Logic diagrams - Continued. 15 MIL-M-38510/208D LOGIC CIRCUIT C (Device types 01 and 02) FIGURE 5. Logic diagrams - Continued. 16 MIL-M-38510/208D LOGIC CIRCUIT C (Device type 03) FIGURE 5. Logic diagrams - Continued. 17 MIL-M-38510/208D LOGIC CIRCUIT D (Device types 01 and 02) FIGURE 5. Logic diagrams - Continued 18 MIL-M-38510/208D LOGIC CIRCUIT G (Device type 01) FIGURE 5. Logic diagrams - Continued. 19 MIL-M-38510/208D LOGIC CIRCUIT G (Device type 02) FIGURE 5. Logic diagrams - Continued. 20 MIL-M-38510/208D LOGIC CIRCUIT G (Device types 04 and 05) FIGURE 5. Logic diagrams - Continued. 21 MIL-M-38510/208D Device types 01 and 02 NOTES: 1. Test table for devices programmed in accordance with an altered item drawing may be replaced by the equivalent tests which apply to the specific program configuration for the resulting read-only memory 2. CL = 30 pF minimum, including jig and probe capacitance, R1 =330 25%, and R2 = 680 20%. 3. Outputs may be under load simultaneously. FIGURE 6. Switching time test circuit. 22 MIL-M-38510/208D Device type 03 NOTES: 1. Test table for devices programmed in accordance with an altered item drawing may be replaced by the equivalent tests which apply to the specific program configuration for the resulting read-only memory 2. CL = 30 pF minimum, including jig and probe capacitance, R1 =330 25%, and R2 = 680 20%. 3. Outputs may be under load simultaneously. FIGURE 6. Switching time test circuit - Continued. 23 MIL-M-38510/208D Device types 04 and 05 NOTES: 1. Test table for devices programmed in accordance with an altered item drawing may be replaced by the equivalent tests which apply to the specific program configuration for the resulting read-only memory 2. CL = 30 pF minimum, including jig and probe capacitance, R1 =330 25%, and R2 = 680 20%. 3. Outputs may be under load simultaneously. FIGURE 6. Switching time test circuit - Continued. 24 MIL-M-38510/208D NOTES: 1. Disregard for devices with no chip enable inputs. 2. All other waveforms characteristics shall be as specified in table IVA. FIGURE 7a. Programming voltage waveforms during programming for circuit A. 25 MIL-M-38510/208D NOTES: 1. Output load is 0.2 mA and 12 mA during 7.0 V and 4.0 V check, respectively. 2. All other waveform characteristics shall be as specified in table IVB. 3. CE1 is the programming pin for device types 04 and 05. FIGURE 7b. Programming voltage waveforms during programming for circuit B. 26 MIL-M-38510/208D Device types 01 and 02 Device type 03 NOTE: All other waveform characteristics shall be as specified in table IVC. NOTE: All other waveform characteristics shall be as specified in table IVC. FIGURE 7c. Programming voltage waveforms during programming for circuit C. 27 MIL-M-38510/208D NOTE: All other waveform characteristics shall be as specified in table IVD. FIGURE 7d Programming voltage waveforms during programming for circuit D. NOTES: 1. Output load is 0.2 mA and 12 mA during 7.0 V and 4.0 V check, respecitively. 2. All other waveform characteristics shall be as specified in table IVF. FIGURE 7f. Programming voltage waveforms during programming for circuit F. 28 MIL-M-38510/208D FIGURE 7g. Programming voltage waveforms during programming for circuit G. 29 TABLE III. Group A inspection for device type 01. Terminal conditions: Outputs not designated are open or resistive coupled to GND or voltage; input not designated are high 2.0 V, low 0.8 V, or open. Subgroup Symbol 1 TC=25C VIC VOL 30 IIL2 IIH1 IIH2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 GND O4 O5 O6 O7 O8 CE4 CE3 -10mA -10mA -10mA -10mA -10mA -10mA -10mA 1/ 3/ " " " " " " 13/ 14/ 1/ " " " " " " 13/ 14/ 1/ " " " " " " 13/ 14/ 1/ " " " " " " 13/ 14/ 1/ " " " " " " 13/ 14/ 1/ " " " " " " 13/ 14/ 1/ 2/ " " " " " " 13/ 14/ 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 5.5V See footnotes at end of table. 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 8 mA 8 mA 8 mA GND " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 20 CE 21 2 CE 22 23 24 NC A8 VCC 1 -10mA -10mA -10mA -10mA 8 mA 8 mA 8 mA 8 mA 8 mA 2.4V " " " " " " " 2.4V " " " " " " " 0.5V " " " " " " " 0.5V " " " " " " " -10mA 1/2/4/ " " " " " " 13/14/ 0.5V 0.5V 0.5V 0.5V 0.5V 5.5V 5.5V 5.5V 5.5V 4.5V 4.5V " " " " " " " " " " " " " " " " " " " " 5.5V " " " " " " " " " " " " " " " " " " " " " " " " " Measured terminal Test limits Min A7 A6 A5 A4 A3 A2 A1 A0 CE4 CE3 CE2 CE1 A8 O1 O2 O3 O4 O5 O6 O7 O8 A7 A6 A5 A4 A3 A2 A1 A0 CE2 CE1 A8 CE4 CE3 A7 A6 A5 A4 A3 A2 A1 A0 CE4 CE3 CE1 A8 CE -1.0 " " " " " " " " " " " " 2 Unit Max -1.5 " " " " " " " " " " " " 0.5 " " " " " " " -250 " " " " " " " " " " -1000 -1000 50 " " " " " " " " " " " 100 V " " " " " " " " " " " " " " " " " " " " A " " " " " " " " " " " " " " " " " " " " " " " " MIL-M-38510/208D IIL1 MIL- Cases 1 STDJ,K, 883 X,Z method Test A7 no. 1 -10mA 2 3 4 5 6 7 8 9 10 11 12 13 3007 14 1/ 2/ " " 15 " 16 " " " 17 " 18 " " 19 " " 20 " " 21 13/ 14/ 3009 22 0.5V " 23 " 24 " 25 " 26 " 27 " 28 " 29 " 30 " 31 " 32 " 33 " 34 3010 35 5.5V " 36 " 37 " 38 " 39 " 40 " 41 " 42 " 43 " 44 " 45 " 46 " 47 TABLE III. Group A inspection for device type 01 - Continued. Terminal conditions: Outputs not designated are open or resistive coupled to GND or voltage; input not designated are high 2.0 V, low 0.8 V, or open. Subgroup Symbol See footnotes at end of table. 12 13 14 15 16 17 18 19 GND O4 O5 O6 O7 O8 CE4 CE3 GND " " " " " " " " 20 CE 21 2 CE 22 NC 23 24 Measured terminal A8 VCC 5.5V " " " " " " " " O1 O2 O3 O4 O5 O6 O7 O8 VCC 100 " " " " " " " 185 6/ 1 Min 5/ 5/ GND GND 15/ 1/ " " " " " " GND 6/ 6/ Outputs 5.2V 5.2V 5.2V 5.2V 5.2V Test limits Unit Max A " " " " " " " mA GND 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ GND 9/ 9/ 9/ 9/ 9/ 5.5V 5.5V GND GND 7/ 7/ Outputs 90 ns " " " " " " 5.5V 5.5V GND GND 7/ 7/ " 90 " " " " " " " 8/ 8/ 8/ 8/ 8/ 8/ " 50 " " " " " " " 8/ 8/ 8/ 8/ 8/ 8/ " 50 " MIL-M-38510/208D 31 MILCases 1 2 3 4 5 6 7 8 9 10 11 STDJ,K, 883 X,Z method Test A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 no. 1 ICEX 48 15/ 15/ 15/ 15/ 15/ 15/ 15/ 5.2V 15/ 49 1/ 1/ 1/ 1/ 1/ 1/ 1/ 1/ 5.2V TC=+25C " " " " " " " " 50 5.2V " " " " " " " " 51 " " " " " " " " 52 " " " " " " " " 53 " " " " " " " " 54 " " " " " " " " 55 3005 56 GND GND GND GND GND GND GND GND ICC 2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125C and VIC tests are omitted. 3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55C and VIC tests are omitted. Func3014 57 6/ 7 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ TC=25C tional test 8 Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125C. tPLH1 GALPAT 9 7/ 7/ 7/ 7/ 7/ 7/ 7/ 9/ 9/ 9/ 58 7/ Fig. 6 TC=25C tPHL1 GALPAT 7/ 7/ 7/ 7/ 7/ 7/ 7/ 7/ " " " 59 Fig. 6 tPLH2 Sequen8/ 8/ 8/ 8/ 8/ 8/ 8/ 8/ " " " 60 tial Fig. 6 tPHL2 Sequen8/ 8/ 8/ 8/ 8/ 8/ 8/ 8/ " " " 61 tial Fig. 6 10 Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125C. 11 Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55C. MIL-M-38510/206D TABLE III. Group A inspection for device type 02. Terminal conditions: Outputs not designated are open or resistive coupled to GND or voltage; input not designated are high 2.0 V, low 0.8 V, or open. Subgroup Symbol 1 TC=25C VIC VOL 32 IIL1 IIL2 24/ IIH1 IIH2 23/ 1 2 3 4 5 6 7 8 9 10 11 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 -10mA -10mA -10mA -10mA -10mA -10mA -10mA -10mA 1/ 2/ " " " 16/ " " 13/ " " " " " " " 17/ 0.5V 1/ 3/ " " " 16/ " " 13/ 1/ 10/ " " " " " " 17/ 1/ " " " 16/ " " 13/ 1/ " " " " " " 17/ 1/ " " " 16/ " " 13/ 1/ " " " " " " 17/ 1/ " " " 16/ " " 13/ 1/ " " " " " " 17/ 1/ " " " 16/ " " 13/ 1/ " " " " " " 17/ 1/ " " " 16/ " " 13/ 1/ " " " " " " 17/ 1/ 2/ " " " 16/ " " 13/ 1/ " " " " " " 17/ 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 5.5V 5.5V See footnotes at end of table. 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 8 mA 8 mA 8 mA -2mA -2mA -2mA 12 13 14 15 16 17 18 19 GND O4 O5 O6 O7 O8 CE4 CE3 GND " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 20 CE 21 2 CE 22 23 NC A8 1 -10mA -10mA -10mA -10mA 8 mA 8 mA 8 mA 8 mA 8 mA -2mA -2mA -2mA -2mA -2mA 2.4V " " " " " " " " " " " " " " " 2.4V " " " " " " " " " " " " " " " 0.5V " " " " " " " " " " " " " " " 0.5V " " " " " " " " " " " " " " " -10mA 1/ 4/ " " " 16/ " " 13/ 1/ 10/ " " " " " " 17/ 0.5V 0.5V 0.5V 0.5V 0.5V 5.5V 5.5V 5.5V 5.5V 4.5V 24 Measured terminal VCC 4.5V " " " " " " " " " " " " " " " " " " " " " " " " " " " " 5.5V " " " " " " " " " " " " " " " " " " " " " " " " " Test limits Min A7 A6 A5 A4 A3 A2 A1 A0 CE4 CE3 CE2 CE1 A8 O1 O2 O3 O4 O5 O6 O7 O8 O1 O2 O3 O4 O5 O6 O7 O8 A7 A6 A5 A4 A3 A2 A1 A0 CE2 CE1 A8 CE4 CE3 A7 A6 A5 A4 A3 A2 A1 A0 CE4 CE3 CE1 A8 CE 2 Max -1.5 " " " " " " " " " " " " 0.5 " " " " " " " 2.4 " " " " " " " -1.0 " " " " " " " " " " " " Unit -250 " " " " " " " " " " -1000 -1000 50 " " " " " " " " " " " 100 V " " " " " " " " " " " " " " " " " " " " " " " " " " " " A " " " " " " " " " " " " " " " " " " " " " " " " " MIL-M-38510/208D VOH MIL- Cases STDJ,K, 883 X,Z method Test no. 1 2 3 4 5 6 7 8 9 10 11 12 13 3007 14 " 15 " 16 " 17 " 18 " 19 " 20 " 21 3006 22 " 23 " 24 " 25 " 26 " 27 " 28 " 29 3009 30 " 31 " 32 " 33 " 34 " 35 " 36 " 37 " 38 " 39 " 40 " 41 " 42 3010 43 " 44 " 45 " 46 " 47 " 48 " 49 " 50 " 51 " 52 " 53 " 54 " 55 TABLE III. Group A inspection for device type 02 - Continued. Terminal conditions: Outputs not designated are open or resistive coupled to GND or voltage; input not designated are high 2.0 V, low 0.8 V, or open. Subgroup Symbol See footnotes at end of table. 10 11 12 13 14 15 16 17 18 19 O2 O3 GND O4 O5 O6 O7 O8 CE4 CE3 GND GND " " " " " " " " " " " " " " " 5/ 5.5V " " " " " " " GND " " " " " " " " " " " " " " " 5/ 5.5V " " " " " " " 5.5V " " " " " " " " " " " " " " " GND " " " " " " " " 5.2V 5.2V 0.5V 0.5V GND GND GND " " " " " " " " " " " " " " " " " " " " " " " " 5.2V 5.2V 5.2V 5.2V 5.2V 0.5V 0.5V 0.5V 0.5V 0.5V GND GND GND GND 20 CE 21 2 22 23 24 NC A8 VCC 5.5V " " " " " " " " " " " " " " " GND " " " " " " " " GND 1/ 10/ " " " " " " 18/ 5.5V " " " " " " " " " " " " " " " " " " " " " " " " O1 O2 O3 O4 O5 O6 O7 O8 O1 O2 O3 O4 O5 O6 O7 O8 VCC O1 O2 O3 O4 O5 O6 O7 O8 CE 1 Measured terminal Test limits Unit Min Max -10 " " " " " " " 100 " " " " " " " -100 " " " " " " " 185 -100 " " " " " " " A " " " " " " " " " " " " " " " mA " " " " " " " " 6/ 6/ GND 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ Outputs 6/ ns 9/ 9/ GND 9/ 9/ 9/ 9/ 9/ 5.5V 5.5V GND GND 7/ 7/ Outputs 90 ns " " " " " " " " 5.5V 5.5V GND GND 7/ 7/ " 90 " " " " " " " " " 8/ 8/ 8/ 8/ 8/ 8/ " 50 " " " " " " " " " 8/ 8/ 8/ 8/ 8/ 8/ " 50 " MIL-M-38510/208D 33 MILCases 1 2 3 4 5 6 7 8 9 STDJ,K, 883 X,Z method Test A7 A6 A5 A4 A3 A2 A1 A0 O1 no. 1 IOHZ 56 5.2V 57 TC=25C 58 59 60 61 62 63 IOLZ 64 0.5V 65 66 67 68 69 70 71 3005 72 GND GND GND GND GND GND GND GND ICC IOS 3011 1/ 10/ 1/ 1/ 1/ 1/ 1/ 1/ GND 73 1/ " " " " " " " " " 74 " " " " " " " " " 75 " " " " " " " " " 76 " " " " " " " " " 77 " " " " " " " " " 78 " " " " " " " " " 79 " 18/ 18/ 18/ 18/ 18/ 18/ 18/ 18/ 80 2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125C and VIC tests are omitted. 3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55C and VIC tests are omitted. Func3014 81 6/ 7 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ TC=25C tional test 8 Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125C and TC = -55C. 9 GALPAT Fig. 6 7/ 7/ 7/ 7/ 7/ 7/ 7/ 9/ 82 7/ TC=25C tPLH1 GALPAT tPHL1 7/ 7/ 7/ 7/ 7/ 7/ 7/ 7/ " Fig. 6 83 SequentPLH2 8/ 8/ 8/ 8/ 8/ 8/ 8/ 8/ " tial 84 Fig. 6 tPHL2 Sequen8/ 8/ 8/ 8/ 8/ 8/ 8/ 8/ " 85 tial Fig. 6 10 Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125C. 11 Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55C. TABLE III. Group A inspection for device type 03. Terminal conditions: Outputs not designated are open or resistive coupled to GND or voltage; inputs not designated are high 2.0 V, low 0.8 V, or open. Subgroup Symbol 1 TC=25C VIC VOL 34 IIL1 IIH1 See footnotes at end of table. 8 9 10 11 12 13 14 15 16 17 18 O2 O3 O4 FE2 GND FE1 O5 O6 O7 O8 Strobe -10mA 8mA 8mA 8mA -2mA -2mA -2mA GND " " " " " " " " " " " " " " " 0.5V GND " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 19 CE 20 2 CE 21 22 23 24 A0 A1 A2 VCC 1 -10mA -10mA -10mA -10mA -10mA -10mA GND " " " " " " `' " " " " " " " " 8mA 8mA 8mA 8mA -2mA -2mA -2mA -2mA 2.4V " " " " " " " " " " " " " " " 2.4V " " " " " " " " " " " " " " " 0.5V " " " " " " " " " " " " " " " 1/ " " " " " " " " " " " " " " " 1/ " " " " " " " -10mA 1/ " " " " " " " " " " " " " " " 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 0.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 4.5V " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 5.5V " " " " " " " " " " " " " " " " " " " " " " " " " Measured terminal Test limits Min A3 A4 A5 A6 A7 A8 FE2 FE1 Strobe CE2 CE1 A0 A1 A2 O1 O2 O3 O4 O5 O6 O7 O8 O1 O2 O3 O4 O5 O6 O7 O8 A3 A4 A5 A6 A7 A8 FE2 FE1 Strobe CE2 CE1 A0 A1 A2 A3 A4 A5 A6 A7 A8 Strobe CE2 CE1 A0 A1 A2 -1.5 " " " " " " " " " " " " " 0.5 " " " " " " " 2.4 " " " " " " " -1.0 " " " " " -1.0 " " " " " Unit Max -100 " " " " " 1.0 1.0 -100 " " " " " 50 " " " " " " " " " " " V " " " " " " " " " " " " " " " " " " " " " " " " " " " " " A " " " " " mA mA A " " " " " " " " " " " " " " " " " MIL-M-38510/208D VOH MIL- Cases 1 2 3 4 5 6 7 STD- J,K,X 883 Test A3 A4 A5 A6 A7 A8 O1 method no. 1 -10mA 2 -10mA 3 -10mA 4 -10mA 5 -10mA 6 -10mA 7 8 9 10 11 12 13 14 3007 15 1/ 1/ 1/ 1/ 1/ 8mA 1/ ` " " " " " " 16 " 17 " " " " " " " 18 " " " " " " " 19 " " " " " " " 20 " " " " " " " 21 " " " " " " " " " " " " " 22 3006 23 " " " " " 1/ 10/ -2mA " " 24 " " " " " " " 25 " " " " " " " 26 " " " " " " " 27 " " " " " " " 28 " " " " " " " 29 " " " " " " " 30 " " " " " 3009 31 0.5V " 32 0.5V " 33 0.5V " 34 0.5V " 35 0.5V " 36 0.5V " 37 " 38 " 39 " 40 " 41 " 42 " 43 " 44 3010 45 5.5V " 46 5.5V " 47 5.5V " 48 5.5V " 49 5.5V " 50 5.5V " 51 " 52 " 53 " 54 " 55 " 56 TABLE III. Group A inspection for device type 03 - Continued. Terminal conditions: Outputs not designated are open or resistive coupled to GND or voltage; input not designated are high 2.0 V, low 0.8 V, or open. Subgroup Symbol See footnotes at end of table. 10 11 12 13 14 15 16 17 18 O4 FE2 GND FE1 O5 O6 O7 O8 Strobe 5.2V 0.5V GND GND GND " " " " " " " " " " " " " " " " " " " " " " " " 19 CE 20 2 CE 21 22 23 A0 A1 A2 VCC 1/ " " " " " " " 5.5V " " " " " " " " " " " " " " " " " " " " " " " " O1 O2 O3 O4 O5 O6 O7 O8 O1 O2 O3 O4 O5 O6 O7 O8 VCC O1 O2 O3 O4 O5 O6 O7 O8 6/ 6/ Outputs 6/ 1 GND 0.5V " " " " " " " " " " " " " " " GND " " " " " " " " 2.4V " " " " " " " " " " " " " " " GND 5.5V " " " " " " " 0.5V " " " " " " " " " " " " " " " GND " " " " " " " " 1/ " " " " " " " 6/ 5.2V 5.2V 5.2V 5.2V 0.5V 0.5V 0.5V 0.5V GND GND GND GND 1/ 10/ " " " " " " " 24 Measured terminal Test limits Min Max -10 " " " " " " " 100 " " " " " " " -100 " " " " " " " 185 -100 " " " " " " " Unit A " " " " " " " " " " " " " " " mA " " " " " " " " 6/ 6/ GND 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ 9/ GND GND GND 9/ 9/ 9/ 9/ GND 5.5V GND 7/ 7/ 7/ 7/ Outputs 90 ns " " " " " " " " " " " 7/ 7/ 7/ 7/ " 90 " " " " " " " " " " " " 8/ 8/ 8/ 8/ " 50 " " " " " " " " " " " " 8/ 8/ 8/ 8/ " 50 " MIL-M-38510/208D 35 MILCases 1 2 3 4 5 6 7 8 9 STDJ,K,X 883 Test A3 A4 A5 A6 A7 A8 O1 O2 O3 method no. 1 IOHZ 57 5.2V 58 5.2V TC=25C 59 5.2V 60 61 62 63 64 IOLZ 65 0.5V 66 0.5V 67 0.5V 68 69 70 71 72 3005 73 GND GND GND GND GND GND ICC IOS 3011 74 1/ 1/ 1/ 1/ 1/ 10/ GND 1/ " " " " " " " 75 GND " " " " " " " 76 GND " " " " " " " 77 " " " " " " " 78 " " " " " " " 79 " " " " " " " 80 " " " " " " " 81 2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125C and VIC tests are omitted. 3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55C and VIC tests are omitted. Func3014 82 6/ 7 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ TC=25C tional test 8 Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125C and TC = -55C. 9 GALPAT Fig. 6 7/ 7/ 7/ 7/ 7/ 9/ 9/ 9/ 83 7/ TC=25C tPLH1 GALPAT tPHL1 7/ 7/ 7/ 7/ 7/ 7/ " " " Fig. 6 84 SequentPLH2 8/ 8/ 8/ 8/ 8/ 8/ " " " tial 85 Fig. 6 tPHL2 Sequen8/ 8/ 8/ 8/ 8/ 8/ " " " 86 tial Fig. 6 10 Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125C. 11 Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55C. TABLE III. Group A inspection for device type 04. Terminal conditions: Outputs not designated are open or resistive coupled to GND or voltage; input not designated are high 2.0 V, low 0.8 V, or open. Subgroup Symbol 1 TC=25C VIC VOL 36 IIH1 IIH2 ICEX ICC 3005 39 40 41 42 43 44 45 46 47 6 O1 7 O2 8 O3 9 O4 8mA 8mA 8mA 8mA 5.2V 5.2V 5.2V 5.2V GND See footnotes at end of table. GND GND GND GND 10 GND GND " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 11 O5 12 O6 13 O7 14 O8 20 VCC Measured terminal A0 A1 A2 A3 A4 CE1 A5 A6 A7 A8 O1 O2 O3 O4 O5 O6 O7 O8 A0 A1 A2 A3 A4 CE1 A5 A6 A7 A8 A0 A1 A2 A3 A4 A5 A6 A7 A8 4.5V 4.5V " " " " " " " " " " " " " " " " 19/ 5.5V " " " " " " " " " " " " " " " " " " " 5.5V " " " " " " " GND " " " " " " " " " 15 CE 1 16 A5 17 A6 18 A7 19 A8 -10mA -10mA -10mA -10mA 8mA 8mA 8mA 8mA 0.5V " " " " " " 19/ 1/ " " " " " " 19/ 1/ " " " " " " 19/ 1/ " " " " " " 19/ -10mA 1/ " " " " " " 19/ 0.5V 0.5V 0.5V 0.5V 0.5V 5.5V 5.5V 5.5V 5.5V 5.2V 5.2V 5.2V 5.2V GND GND GND GND CE 1 O1 O2 O3 O4 O5 O6 O7 O8 VCC Test limits Min Max Unit -1.5 " " " " " " " " " 0.5 " " " " " " " -250 " " " " " " " " " 50 " " " " " " " " 100 V " " " " " " " " " " " " " " " " " A " " " " " " " " " " " " " " " " " " " " " " " " " " " 155 " " " " " " " " mA -1.0 " " " " " " " " " MIL-M-38510/208D IIL MIL- Case Y 1 2 3 4 5 STDTest A0 A1 A2 A3 A4 883 no. method 1 -10mA 2 -10mA 3 -10mA 4 -10mA 5 -10mA 6 7 8 9 10 1/ 3/ 1/ 1/ 1/ 3007 11 2.4V " 12 " " " " " " 13 " " " " " " 14 " " " " " " 15 " " " " " " 16 " " " " " " 17 " " " " " " 18 19/ 19/ 19/ 19/ 19/ 3009 19 0.5V " 20 0.5V " 21 0.5V " 22 0.5V " 23 0.5V " 24 " 25 " 26 " 27 " 28 3010 29 5.5V " 30 5.5V " 31 5.5V " 32 5.5V " 33 5.5V " 34 " 35 " 36 " 37 " 38 TABLE III. Group A inspection for device type 04 - Continued. Terminal conditions: Outputs not designated are open or resistive coupled to GND or voltage; input not designated are high 2.0 V, low 0.8 V, or open. Subgroup Symbol MIL-STD- Case Y 1 2 3 4 5 6 7 8 9 10 883 Test A0 A1 A2 A3 A4 O1 O2 O3 O4 GND method no. 2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125C and VIC tests are omitted. 3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55C and VIC tests are omitted. 7 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ GND Func3014 48 6/ TC=25C tional test 8 Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125C and TC = -55C. 9 GALPAT Fig. 6 7/ 7/ 7/ 7/ 9/ 9/ 9/ 9/ GND 49 7/ TC=25C tPLH1 GALPAT tPHL1 Fig. 6 50 7/ 7/ 7/ 7/ 7/ " " " " " Sequential " " " " " tPLH2 Fig. 6 51 8/ 8/ 8/ 8/ 8/ Sequential tPHL2 Fig. 6 8/ 8/ 8/ 8/ 8/ " " " " " 52 10 Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125C. 11 Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55C. 12 O6 13 O7 14 O8 6/ 6/ 6/ 6/ 9/ 9/ 9/ " " " " " " 15 16 A5 17 A6 18 A7 19 A8 20 VCC Measured terminal 6/ 6/ 6/ 6/ 6/ 6/ Outputs 6/ 9/ GND 7/ 7/ 7/ 7/ 7/ Outputs 80 ns " " GND 7/ 7/ 7/ 7/ 7/ " 80 " " " 8/ 8/ 8/ 8/ 8/ 8/ " 50 " " " 8/ 8/ 8/ 8/ 8/ 8/ " 50 " CE 1 Test limits Min Max Unit 37 MIL-M-38510/208D See footnotes at end of table. 11 O5 TABLE III. Group A inspection for device type 05. Terminal conditions: Outputs not designated are open or resistive coupled to GND or voltage; input not designated are high 2.0 V, low 0.8 V, or open. Subgroup Symbol 1 TC=25C VIC VOL 38 IIL IIH1 IIH2 See footnotes at end of table. 6 O1 7 O2 8 O3 9 O4 12/ 12/ 12/ 12/ -2mA -2mA -2mA -2mA 10 GND GND " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 11 O5 12 O6 13 O7 14 O8 15 CE 1 16 A5 17 A6 18 A7 19 A8 -10mA -10mA -10mA -10mA 12/ 12/ 12/ 12/ -2mA -2mA -2mA -2mA 0.5V " " " " " " " " " " " " " " " 1/ " " " " " " 20/ 1/ " " " " " " 21/ 1/ " " " " " " 20/ 1/ " " " " " " 21/ 1/ " " " " " " 20/ 1/ " " " " " " 21/ -10mA 1/ " " " " " " 20/ 1/ " " " " " " 21/ 0.5V 0.5V 0.5V 0.5V 0.5V 5.5V 5.5V 5.5V 5.5V 4.5V 20 VCC Measured terminal 4.5V " " " " " " " " " " " " " " " " " " " " " " " " " 5.5V " " " " " " " " " " " " " " " " " " " A0 A1 A2 A3 A4 CE1 A5 A6 A7 A8 O1 O2 O3 O4 O5 O6 O7 O8 O1 O2 O3 O4 O5 O6 O7 O8 A0 A1 A2 A3 A4 CE1 A5 A6 A7 A8 A0 A1 A2 A3 A4 A5 A6 A7 A8 CE 1 Test limits Min Max Unit -1.5 " " " " " " " " " 0.5 " " " " " " " V " " " " " " " " " " " " " " " " " " " " " " " " " A " " " " " " " " " " " " " " " " " " " 2.4 " " " " " " " -1.0 " " " " " " " " " -250 " " " " " " " " " 50 " " " " " " " " 100 MIL-M-38510/208D VOH MIL- Case Y 1 2 3 4 5 STDTest A0 A1 A2 A3 A4 883 no. method 1 -10mA 2 -10mA 3 -10mA 4 -10mA 5 -10mA 6 7 8 9 10 1/ 3/ 1/ 11/ 1/ 11/ 1/ 11/ 3007 11 2.4V " 12 " " " " " " 13 " " " " " " 14 " " " " " " 15 " " " " " " 16 " " " " " " 17 " " " " " " 18 20/ 20/ 20/ 20/ 20/ 3006 19 1/ 1/ 1/ 1/ 1/ " " " " " " 20 " 21 " " " " " " " " " " " 22 " 23 " " " " " " 24 " " " " " " 25 " " " " " " 26 21/ 21/ 21/ 21/ 21/ 3009 27 0.5V " 28 0.5V " 29 0.5V " 30 0.5V " 31 0.5V " 32 " 33 " 34 " 35 " 36 3010 37 5.5V " 38 5.5V " 39 5.5V " 40 5.5V " 41 5.5V " 42 " 43 " 44 " 45 " 46 TABLE III. Group A inspection for device type 05 - Continued. Terminal conditions: Outputs not designated are open or resistive coupled to GND or voltage; input not designated are high 2.0 V, low 0.8 V, or open. See footnotes at end of table. 11 O5 12 O6 13 O7 14 O8 15 CE 1 16 A5 17 A6 18 A7 19 A8 20 VCC Measured terminal O1 O2 O3 O4 O5 O6 O7 O8 O1 O2 O3 O4 O5 O6 O7 O8 VCC O1 O2 O3 O4 O5 O6 O7 O8 GND 5.5V " " " " " " " " " " " " " " " GND 0.5V " " " " " " " GND 1/ " " " " " " 22/ GND 1/ " " " " " " 22/ GND 1/ " " " " " " 22/ GND 1/ " " " " " " 22/ 5.5V " " " " " " " " " " " " " " " " " " " " " " " " 6/ 6/ 6/ Outputs 5.2V 5.2V 5.2V 5.2V 0.5V 0.5V 0.5V 0.5V GND GND GND Test limits Min Max Unit 100 " " " " " " " -100 " " " " " " " -100 " " " " " " " " A " " " " " " " " " " " " " " " mA " " " " " " " " -10 " " " " " " " " 6/ 6/ 6/ 6/ GND 6/ 6/ 6/ 9/ 9/ 9/ 9/ GND 7/ 7/ 7/ 7/ 7/ Outputs 80 ns " " " " GND 7/ 7/ 7/ 7/ 7/ " 80 " " " " " 8/ 8/ 8/ 8/ 8/ 8/ " 40 " " " " " 8/ 8/ 8/ 8/ 8/ 8/ " 40 " MIL-M-38510/208D 39 Subgroup Symbol MIL-STD- Case Y 1 2 3 4 5 6 7 8 9 10 883 Test A0 A1 A2 A3 A4 O1 O2 O3 O4 GND method no. 1 IOHZ 47 5.2V GND 48 5.2V " TC=25C 49 5.2V " 50 5.2V " 51 " 52 " 53 " 54 " IOLZ 55 0.5V " 56 0.5V " 57 0.5V " 58 0.5V " 59 " 60 " 61 " 62 " ICC 3005 63 GND GND GND GND GND " IOS 3011 64 1/ 1/ 1/ 1/ 1/ GND " " 65 " " " " " GND " " 66 " " " " " GND " " 67 " " " " " GND " " 68 " " " " " " " 69 " " " " " " " 70 " " " " " " " 71 22/ 22/ 22/ 22/ 22/ " 2 Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125C and VIC tests are omitted. 3 Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55C and VIC tests are omitted. 7 Func3014 72 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ GND TC=25C tional test 8 Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125C and TC = -55C. 9 tPLH1 9/ 9/ 9/ GND GALPAT 73 7/ 7/ 7/ 7/ 7/ 9/ Fig. 6 TC=25C tPHL1 GALPAT 74 7/ 7/ 7/ 7/ 7/ " " " " " Fig. 6 tPLH2 Sequential 75 8/ 8/ 8/ 8/ 8/ " " " " " Fig. 6 tPHL2 Sequential 76 8/ 8/ 8/ 8/ 8/ " " " " " Fig. 6 10 Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125C. 11 Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55C. MIL-M-38510/208D 1/ For unprogrammed devices, select an appropriate address to acquire the desired output state. 2/ For unprogrammed devices (circuit D), apply 12.0 V on pin 8 (A0) and pin 1 (A7). 3/ For unprogrammed device types 01 and 02 (circuit B), apply 12.0 V on pin 2 (A6); for unprogrammed device types 04 and 05 (circuit B), apply 12.0 V on pin 2 (A1). 4/ For unprogrammed devices (circuit A), apply 11.0 V on pin 23 (A8). 5/ CE4 and CE3 may be "GND" or "2.4 V". 6/ The functional test shall verify that no fuses are blown for unprogrammed devices or that the altered item drawing pattern exists for programmed devices (see table II and 3.3.2.2). All bits shall be tested. The functional tests shall be performed with VCC = 4.5 V and VCC = 5.5 V. Terminal conditions shall be as follows: a. Inputs: H = 3.0 V, L = 0.0 V. b. Outputs: Output voltage shall be either: (1) H = 2.4 V minimum and L = 0.5 V maximum when using a high-speed checker double comparator, or (2) H 1.0 V and L < 1.0 V when using a high-speed checker single comparator. 7/ GALPAT (PROGRAMMED PROM). This program will test all bits in the array, the addressing and interaction between bits for ac performance, tPLH1 and tPHL1. Each bit in the pattern is fixed by being programmed with an "H" or "L". The GALPAT tests shall be performed with VCC = 4.5 V and 5.5 V. Description: Step 1. Word 0 is read. Step 2. Word 1 is read. Step 3. Word 0 is read. Step 4. Word 2 is read. Step 5. Word 0 is read. Step 6. The reading procedure continues back and forth between word 0 and the next higher numbered word until word 511 is reached, then increments to the next word and reads back and forth as in step 1 through step 6 and shall include all words. Step 7. Pass execution time = (n2 + n) x cycle time. n = 512. 8/ SEQUENTIAL (PROGRAMMED PROM). This program will test all bits in the array for tPLH2 and tPHL2. The SEQUENTIAL tests shall be performed with VCC = 4.5 V and 5.5 V. Description: Step 1. Each word in the pattern is tested from the enable lines to the output lines for recovery. Step 2. Word 0 is addressed. Enable line is pulled high to low and low to high. tPHL2 and tPLH2 are Step 3. Word 1 is addressed. Same enable sequence as above. Step 4. The reading procedure continues until word 511 is reached. Step 5. Pass execution time = 512 x cycle time. 9/ The outputs are loaded per figure 6. 10/ For uprogrammed device types 01 and 02 (circuit C), apply 10.0 V on pin 23 (A8); 0.5 V on pin 2 (A6); and 5.0 V on all other address pins. For unprogrammed device type 03 (circuit C), apply 10.0 V on pin 6 (A8); 0.5 V on pin 22 (A1); and 5.0 V on all other address pins. 11/ For unprogrammed devices (circuit F), apply 12.0 V on pin 3 (A2) and 0.0 V on pin 4 (A3). 12/ IOL = 8 mA for circuit B devices; IOL = 16 mA for circuit F devices. 40 MIL-M-38510/208D 13/ For unprogrammed device types 01, 02, 04, and 05 (circuit G) select an appropriate address to obtain the desired output state. 14/ For programmed device type 02 (circuit G) apply 4.5 V to pin 24; 10.5 V to pin 1; 3.0 V to pins 23, 19, 18, 8, 7, 6, 4, 3, and 2; and 0.0 V to pins 21, 20, 12, and 5. 15/ For unprogrammed device type 01 (circuit G) apply 10.5 V to pins 6 and 1; 5.5 V to pin 24; 3.0 V to pins 23, 19, 18, 8, 7, 6, 4, 3, and 2; 0.0 V to pins 21, 20, 12, and 5. 16/ For programmed device type 02 (circuit G) apply 10.5 V to pin 1; 4.5 V to pin 24; 3.0 V to pins 23, 19, 18, 8, 7, 6, 4, 3, and 2; and 0.0 V to pins 21, 20, 5, and 12. 17/ For unprogrammed device type 02 (circuit G) apply 10.5 V to pins 6 and 1; 4.5 V to pin 24; 3.0 V to pins 23, 19, 18, 8, 7, 4, and 2; 2.0 V to pin 3; 0.0 V to pins 21, 20, 12, and 5. 18/ For unprogrammed device type 02 (circuit G) apply 10.5 V to pins 1 and 6; 5.5 V to pin 24; 3.0 V to pins 23, 19, 18, 8, 7, 4, 3 and 2; 0.0 V to pins 5, 12, 20, and 21. 19/ For programmed device type 04 (circuit G) apply 10.5 V to pin 16; 4.5 V to pin 20; 3.0 V to pins 1, 2, 3, 4, 5, 18, and 19; 0.0 V to pins 10 and 15. 20/ For programmed device type 05 (circuit G) apply 10.5 V to pin 16; 4.5 V to pin 20; 3.0 V to pins 1, 2, 3, 4, 5, 18, and 19; 0.0 V to pins 10 and 15. 21/ For unprogrammed device type 05 (circuit G) apply 10.5 V to pins 17 and 3; 4.5 V to pin 20; 3.0 V to pins 2, 4, 5, 16, 18, and 19; 0.0 V to pins 1, 10, and 15. 22/ For unprogrammed device type 05 (circuit G) apply 10.5 V to pins 3 and 17; 5.5 V to pin 20; 3.0 V to pins 2, 4, 5, 16, 18, and 19; 0.0 V to pins 1, 10, and 15. 23/ At the manufacturer's option, this may be prepared with VIH = 5.5 and test limits of 50 A maximum. 24/ At the manufacturer's option, this may be performed with VIO = 0.5 V and test limits of -1 A minimum to -250 A maximum. 41 MIL-M-38510/208D 4.7 Programming procedure for circuit A. The waveforms on figure 7a, the programming characteristics in table IVA and the following procedures shall apply: a. Connect the device in the electrical configuration for programming. b. Address the PROM with the binary address of the selected word to be programmed. Address inputs are TTL compatible. c. Disable the chip by applying VIH to the CE 1 and CE 2 inputs and VIL to the CE3 and CE4 inputs. The CE inputs are TTL compatible. d. Disable the programming circuitry by applying a voltage of VOPD to the outputs of the PROM. e. Raise VCC to VPH as specified on the waveforms on figure 7a. f. After a delay of tD, apply only one VOPE pulse with duration of tp to the output selected for programming. Note that the PROM is supplied with fuses generating a high-level logic output. Programming a fuse will cause the output to go to a low-level logic in the verify mode. g. Other bits in the same word may be programmed sequentially while the VCC input is at the VPH level by applying VOPE pulses to each output to be programmed allowing a delay of tD between pulses as shown on figure 7a. h. Repeat steps 4.7b through 4.7g for all other bits to be programmed. i. Lower VCC to 4.5 volts following a delay of tD from the last programming pulse applied to an output. j. Enable the chip by applying VIL to the CE 1 and CE 2 inputs and VIH to the CE3 and CE4 inputs and verify the program. k. For class S and B devices, if any bit does not verify as programmed, it shall be considered a programming reject. 42 MIL-M-38510/208D TABLE IVA. Programming characteristics for circuit A. Parameter Address input voltage 2/ VCC required during programming Programming input low current Programming voltage transition time Programming delay Programming pulse width Programming duty cycle Output voltage Enable 3/ Disable 4/ Output voltage enable current Symbol Unit Limits 1/ Min Recommended Max VIH VIL VPH VPL 2.4 0.0 12.0 4.5 5.0 0.4 12.0 4.5 5.0 0.8 12.5 5.5 V V V V IILP ---- -300 -600 A tTLH tTHL tD 1 1 10 1 1 10 10 10 100 s s s tP D.C. 90 ---- 100 50 110 90 s % VOPE VOPD IOPE 10.5 4.5 ---- 10.5 5.0 ---- 11.0 5.5 10 V V mA 1/ TA = +25C. 2/ Address and chip enable shall not be left open for VIH. 3/ VOPE supply shall be capable of sourcing 10 mA. 4/ Disable condition can be met with output open circuit. 43 MIL-M-38510/208D 4.8 Programming procedure for circuit B. The waveforms on figure 7b, the programming characteristics of table IVB, and the following procedures shall apply: a. Connect the device in the electrical configuration for programming. b. Raise VCC to 5.5 volts. c. Address the PROM with the binary address of the selected word to be programmed. Address inputs are TTL compatible. d. Disable the chip by applying VIH to the CE 1 and CE 2 and VIL to the CE3 and CE4 inputs (device types 01 and 02) or VIH to the CE input (device types 04 and 05). The CE input is TTL compatible. e. Apply the VPP pulse to the programming pin CE 2 (device types 01 and 02) or CE (device types 04 and 05). In order to insure that the output transistor is off before increasing the voltage on the output pin, the programming pin's voltage pulse shall precede the output pin's programming pulse by TD1 and leave after the output pin's programming pulse by TD2 (see figure 7b). f. Apply only one VOUT pulse with duration of tP to the output selected for programming. The outputs shall be programmed one output at a time, since internal decoding circuitry is capable of sinking only one unit of programming current at a time. Note that the PROM is supplied with fuses generating a high-level logic output. Programming a fuse will cause the output to go to a low-level logic in the verify mode. g. Other bits in the same word may be programmed sequentially by applying VPP pulses to each output to be programmed. h. Repeat 4.8c through 4.8g for all other bits to be programmed. i. Enable the chip by applying VIL to the CE 1 and CE 2 and VIH to the CE3 and CE4 inputs (device types 01 and 02) or VIL to the CE inputs (device types 04 and 05) and verify the program. Verification may check for a low output by requiring the device to sink 12 mA at VCC = 4.0 V and 0.2 mA at VCC = 7.0 V at TA = 25C. j. For class S and B devices, if any bit does not verify as programmed, it shall be considered a programming reject. . 44 MIL-M-38510/208D TABLE IVB. Programming characteristics for circuit B. Parameter VCC required during programming Rise time of programming pulse to data out or programming pin Programming voltage on programming pin Output programming voltage Programming pin pulse width ( CE 2) 2/ Pulse width of programming voltage Required current limit of power supply feeding programming pin and output during programming Required time delay between disabling memory output and application of output programming pulse Required time delay between removal of programming pulse and enabling memory output Output current during verification Symbol Maximum duty cycle during automatic programming of program pin and output pin Unit Min Recommended Max VCCP 5.4 5.5 5.6 V tTLH 0.34 0.40 0.46 V/s VPP 32.5 33 33.5 V VOUT 25.6 26 26.5 V 100 180 ns 40 s tPP Chip disabled, VCC = 5.5 V tP Chip disabled, VCC = 5.5 V VPP = 33 V, VOUT = 26 V, VCC = 5.5 V IL 1 240 mA Measured at 10% levels 70 TD2 Measured at 10% levels 100 IOLV1 Chip enabled, VCC = 4.0 V Chip enabled, VCC = 7.0 V 11 12 13 mA 0.19 0.2 0.21 mA VIH 2.4 5.0 5.5 V VIL 0.0 0.4 0.8 V ---- ---- 25 % D.C. tP/ tC 1/ TA = +25C. 2/ CE 1 is the programming pin for device types 04 and 05. 45 80 90 s TD1 IOLV2 Address input voltage Limits 1/ Conditions ns MIL-M-38510/208D 4.9 Programming procedures for circuit C. The waveforms on figure 7c, the programming characteristics in table IVC, and the following procedures shall be used for programming the device: 4.9.1 Device types 01 and 02. a. Connect the device in the electrical configuration for programming. b. Terminate all device outputs with a 10 k resistor to VCC. Apply CE 1 = VIH, CE 2 = VIL, CE3 = VIH, and CE4 = VIH. c. Address the PROM with the binary address of the selected word to be programmed. Raise VCC to VCCP. d. After a tD delay (10s), apply only one VOUT pulse to the output to be programmed. Program one output at a time. e. After a tD delay (10s), pulse CE1 input to logic "0" for a duration of tP. f. After a tD delay (10s), remove the VOUT pulse from the programmed output. Programming a fuse will cause the output to go to a high-level logic in the verify mode. g. Other bits in the same word may be programmed sequentially while the VCC input is at the VCCP level by applying VOUT pulses to each output to be programmed allowing a delay of tD between pulses as shown on figure 7c. h. Repeat 4.9.1c through 4.9.1g for all other bits to be programmed. i. To verify programming, after tD (10 s) delay, lower VCC to VCCH and apply a logic "0" level to both CE 1 and CE 2 inputs. The programmed output should remain in the "1" state. Again, lower VCC to VCCL and verify that the programmed output remains in the "1" state. j. For class S and B devices, if any bit does not veify as programmed it shall be considered a programming reject. 4.9.2 Device type 03. a. Connect the device in the electrical configuration for programming. b. Terminate all device outputs with a 10 k resistor to VCC. Apply CE 1 = VIL, CE 2 = VIH, and strobe = VIH. c. Address the PROM with the binary address of the selected word to be programmed. Raise VCC to VCCP. d. After a tD delay (10s), apply to FE1 (pin 13) a voltage source of +5.0 0.5 V, with 10 mA sourcing current capability. e. After a tD delay (10s), apply only one VOUT pulse to the output to be programmed. Program one output at a time. f. After a tD delay (10s), raise FE2 (pin 11) from GND to +5.0 0.5 V for 1 ms, and return to GND. g. After a tD delay (10 s), remove the VOUT pulse from the programmed output. 46 MIL-M-38510/208D h. Programming a fuse will cause the output to go to a high level logic in the verify mode. Other bits in the same word may be programmed sequentially while the VCC input is at the VCCP level by applying VOUT pulses to each output to be programmed allowing a delay to tD between pulses as shown on figure 7c. i. Repeat 4.9.2c through 4.9.2h for all other bits to be programmed. j. To verify programming after a tD (10 s) delay, return FE1 to GND. Raise VCC to VCCH. The programmed output should remain in the high state. Again lower VCC to VCCL and verify that the programmed output remains in the high state. k. For class S and B devices, if any bit does not veify as programmed it shall be considered a programming reject. TABLE IVC. Programming characteristics for circuit C. Parameter Programming voltage to VCC Verificaiton upper limit Verificaiton lower limit Verify threshold Programming supply current Input voltage, high level "1" Input voltage, low level "0" Input current Input current Output programming voltage Output programming current Programming voltage transition time Symbol Limits Conditions Unit Min Recommended Max 8.5 8.75 9.0 V VCCH 5.3 5.5 5.7 V VCCL VS 2/ 4.3 1.4 4.5 1.5 4.7 1.6 V V 300 450 mA VIH 2.4 5.5 V VIL 0 0.4 0.8 V 16 17 50 -500 18 A A V 180 200 220 mA 50 s 500 s VCCP 1/ ICCP IIH IIL VOUT 3/ IOUT ICCP = 375 75 mA Transient or steady-state VCCP = 8.75 0.25 V VIH = 5.5 V VIL = 0.4 V IOUT = 200 20 mA Transient or steady-state VOUT = 17 1 V tTLH 10 CE programming pulse width tP 300 Pulse sequence delay tD 10 400 1/ Bypass VCC to GND with a 0.01 F capacitor to reduce voltage spikes. 2/ VS is the sensing threshold of the PROM output voltage for a programmed bit. It normally constitutes the reference voltage applied to a comparator circuit to verify a successful fusing attempt. 3/ Care should be taken to insure the 17 1 V output voltage is maintained during the entire fusing cycle. The recommended supply is a constant current source clamped at the specified voltage limit. 47 s MIL-M-38510/208D 4.10 Programming procedure for circuit D. The waveforms on figure 7d, the programming characteristics of table IVD, and the following procedures shall apply: a. Connect the device in the electrical configuration for programming. b. Address the PROM with the binary address of the selected word to be programmed. Address inputs are TTL compatible. c. Disable the chip by applying VIH to the CE 1 and CE 2 inputs and VIL to the CE3 and CE4 inputs. The chip enable input is TTL compatible. d. After a delay of tD, apply only one VOUT pulse with a duration of tp to the ouput selected for programming. The other outputs may be left open or tied to VIH. The outputs shall be programmed one output at a time. Note that the PROM is supplied with fuses generating a high-level logic output. Programming a fuse will cause the output to go to a low-level logic in the verify mode. e. Other bits in the same word may be programmed sequentially by applying VOUT pulses to each output to be programmed. f. Repeat 4.10b through 4.10e for all other bits to be programmed. g. Enable the chip by applying VIL to the CE 1 and CE 2 inputs and VIH to the CE3 and CE4 inputs and verify the program. h. For class S and B devices, if any bit does not verify as programmed, it shall be considered a programming reject. 48 MIL-M-38510/208D TABLE IVD. Programming characteristics for circuit D. Parameter VCC required during programming Verification VCC read Input voltage, high level "1" Input voltage, low level "0" Output programming voltage Output programming current Programming voltage transition time Programming pulse width Programming duty cycle Required delay between disabling memory output and application of output programming pulse Symbol Limits Conditions 1/ VCCP Unit Min Recommended Max 4.75 5.0 5.25 V VCCL Programming read verify 4.2 4.4 5.0 V VIH Do not leave inputs open Do not leave inputs open 2.4 5.0 5.0 V 0 0 0.4 V Applied to ouput to be programmed If pulse generator is used, set current limit to the max value 20 20.5 21 V 100 mA VIL VOUT IOUT tTLH 0.5 1.0 3.0 s tP 50 100 180 s 20 20 % D. C. Maximum duty cycle to maintain TA < +85C tD 30 ns 1/ Recommended TA = +25C; maximum TA = +85C. 4.11 Programming procedure for circuit F. The waveforms on figure 7f, the programming characteristics on table IVF, and the following procedures shall apply: a. Connect the device in the electrical configuration for programming. b. Raise VCC to 5.5 Volts. c. Address the PROM with the binary address of the selected word to be programmed. Address inputs are TTL compatible. d. Disable the chip by applying VIH to the CE inputs and VIL to the CE inputs. The chip enable inputs are TTL compatible. e. Apply the VPP pulse to the programming pin CE 2. In order to insure that the output transistor is off before increasing voltage on the output pin, the programming pin's voltage pulse shall precede the output pin's programming pulse by TD1 and leave after the programming pin's programming pulse by TD2 (see figure 7f). f. Apply only one VOUT pulse with duration of tP to the output selected for programming. The outputs shall be programmed one output at a time, since internal decoding circuitry is capable of sinking only one unit of programming current at a time. Note that the PROM is supplied with fuses generating a high-level logic output. Programming a fuse will cause the output to go to a low-level logic in the verify mode. 49 MIL-M-38510/208D g. Other bits in the same word may be programmed sequentially by applying VOUT pulses to each output to be programmed. h. Repeat steps 4.11c through 4.11g for all other bits to be programmed. i. Enable the chip by applying VIL to the CE inputs and VIH to the CE inputs, and verify the program. Verification may check for a low output by requiring the device to sink 12 mA at VCC = 4.0 V and 0.2 mA at VCC = 7.0 V at TA = 25C. j. For class S and B devices, if any bit does not verify as programmed, it shall be considered a programming reject. TABLE IVF. Programming characteristics for circuit F - Continued. Parameter VCC required during programming Rise time of programming pulse data out or programming pin Programming voltage on programming pin Output programming voltage Programming pin pulse width ( CE ) Pulse width of programming voltage Required current limit of power supply feeding programming pin and output during programming Required time delay between disabling memory output and application of output programming pulse Required time delay between removal of programming pulse and enabling memory output Output current during verification Symbol Min Recommended Max VCCP 5.4 5.5 5.6 V tTLH 0.34 0.40 0.46 V/s VPP 32.5 33 33.5 V VOUT 25.5 26 26.5 V 100 180 ns 40 s tPP Chip disabled, VCC = 5.5 V tP Chip disabled, VCC = 5.5 V VPP = 33 V, VOUT = 26 V, VCC = 5.5 V IL Maximum duty cycle during automatic programming of program pin and output pin 1 240 mA TD1 Measured at 10% levels 70 80 90 s TD2 Measured at 10% levels 100 ---- ---- ns IOLV1 Chip enabled, VCC = 4.0 V Chip enabled, VCC = 7.0 V 11 12 13 mA 0.19 0.2 0.21 mA VIH 2.4 5.0 5.5 V VIL 0.0 0.4 0.8 V ---- ---- 25 % IOLV2 Address input voltage Unit Limits 1/ Conditions D. C. tP/ tC 1/ TA = +25C. 50 MIL-M-38510/208D 4.12 Programming procedure for circuit G. The programming characteristics on table IVG and the following procedures shall be used for programming: a. Connect the device in the electrical configuration for programming. The waveforms on figure 7g and the programming characteristics of table IVG shall apply to these procedures. b. Select the desired word by applying high or low levels to the appropriate address inputs. Disable the device by applying a high level to one or more `active low' chip Enable inputs. NOTE: Address and enable inputs must be driven with TTL logic levels during programming and verification. c. Increase VCC from nominal to VCCP (10.5 0.5 V) with a slew rate limit of IRR (1.0 to 10.0 V/s). Since VCC is the source of the current required to program the fuse as well as the ICC for the device at the programming voltage, it must be capable of supplying 750 mA at 11.0 volts. d. Select the output where a logical high is desired by raising that output voltage to VOP (10.5 0.5 V). Limit the slew rate to IRR (1.0 to 10.0 V/s). This voltage change may occur simultaneously with the VCC increase to VCCP, but must not preced it. It is critical that only one output at a time be programmed since the internal circuits can only supply programming current to one bit at a time. Outputs not being programmed must be left open or connected to a high impedance source of 20 k minimum (rememeber that the outputs of the device are disabled at this time) . e. Enable the device by taking the chip Enable(s) to a low level. This is done with a pulse PWE for 10 s. The 10 s duration refers to the time that the circuit (device) is enabled. Normal input levels are used and rise and fall times are not critical. f. Verify that the bit has been programmed by first removing the programming voltage from the output and then reducing VCC to 5.0 (0.25 V). The device must be Enabled to sense the state of the outputs. During verification, the loading of the output must be within specified IOL and IOH limits. g. If the device is not to be tested for VOH over the entire operating range subsequent to programming, the verification of Step f. is to be performed at a VCC level of 4.0 volts (0.2 V). VOH, during the 4 volt verification, must be at least 2.0 volts. The 4 volt VCC verification assures minimum VOH levels over the entire operating range. h. Repeat steps 4.12b through 4.12f for each bit to be programmed to a high level. If the procedure is performed on an automatic programmer, the duty cycle of VCC at the programming voltage must be limited to a maximum of 25 percent. This is necessary to minimize device junction temperatures. After all selected bits are programmed, the entire contents of the memory should be verified. i. For class S and B devices, if any bit does not verify as programmed, it shall be considered a programming reject. 51 MIL-M-38510/208D TABLE IVG. Programming characteristics for circuit G. Parameter Symbol Required VCC during programming ICC during programming VCCP Required output voltage for programming Output current while programming Rate of voltage change of VCC or output Programming pulse width (Enabled) Required VCC for verification Maximum duty cycle for VCC at VCCP Address set-up time VCCP set-up time VOP VCCP hold time VOP set-up time VOP hold time ICCP IOP Limits 1/ Conditions Unit Min Recommended Max 10.0 10.5 11.0 V 750 mA 11.0 V 20 mA 10.0 V/s VCC = 11 V 10.0 10.5 VOUT = 11 V IRR 1.0 PWE 9 10 11 s VCCV 3.8 4.0 4.2 V 25 25 % MDC t1 t2 2/ t5 t3 t4 100 5 ns s 100 100 100 ns ns ns 1/ TA = +25C. 2/ VCCP set-up time may be greater than 0 if VCCP rises at the same rate or faster than VOP. 5. PACKAGING 5.1 Packaging requirements. For acquisition purposes, the packaging requirements shall be as specified in the contract or order (see 6.2). When packaging of materiel is to be performed by DoD or in-house contractor personnel, these personnel need to contact the responsible packaging activity to ascertain packaging requirements. Packaging requirements are maintained by the Inventory Control Point's packaging activity within the Military Service or Defense Agency, or within the military service's system command. Packaging data retrieval is available from the managing Military Department's or Defense Agency's automated packaging files, CD-ROM products, or by contacting the responsible packaging activity. 6. NOTES (This section contains information of a general or explanatory nature which may be helpful, but is not mandatory.) 6.1 Intended use. Microcircuits conforming to this specification are intended for logistic support of existing equipment. 52 MIL-M-38510/208D 6.2 Acquisition requirements. Acquisition documents should specify the following: a. Title, number, and date of the specification. b. PIN and compliance identifier, if applicable (see 1.2). c. Requirements for delivery of one copy of the conformance inspection data pertinent to the device inspection lot to be supplied with each shipment by the device manufacturer, if applicable. d. Requirements for certificate of compliance, if applicable. e. Requirements for notification of change of product or process to contracting activity in addition to notification to the qualifying activity, if applicable. f. Requirements for failure analysis (including required test condition of method 5003 of MIL-STD-883), corrective action, and reporting of results, if applicable. g. Requirements for product assurance options. h. Requirements for special lead lengths, or lead forming, if applicable. Unless otherwise specified, these requirements will not apply to direct purchase by or direct shipment to the Government. i. Requirement for programming the device, including processing option. The device may be programmed pre- or post-burn-in, if applicable. j. Requirements for "JAN" marking. k. Packaging Requirements (see 5.1) 6.3 Qualification. With respect to products requiring qualification, awards will be made only for products which are, at the time of award of contract, qualified for inclusion in Qualified Manufacturers List QML-38535 whether or not such products have actually been so listed by that date. The attention of the contractors is called to these requirements, and manufacturers are urged to arrange to have the products that they propose to offer to the Federal Government tested for qualification in order that they may be eligible to be awarded contracts or purchase orders for the products covered by this specification. Information pertaining to qualification of products may be obtained from DSCC-VQ, 3990 E. Broad Street, Columbus, Ohio 43218-3990. 6.4 Superseding information. The requirements of MIL-M-38510 have been superseded to take advantage of the available Qualified Manufacturer Listing (QML) system provided by MIL-PRF-38535. Previous references to MIL-M38510 in this document have been replaced by appropriate references to MIL-PRF-38535. All technical requirements now consist of this specification and MIL-PRF-38535. The MIL-M-38510 specification sheet number and PIN have been retained to avoid adversely impacting existing government logistics systems and contractor's parts lists. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535, MIL-HDBK-1331, and as follows: GND ............................................ VIN ............................................... VIC ................................................ IIN ................................................. Ground zero voltage potential. Voltage level at an input terminal Input clamp voltage Current flowing into an input terminal 6.6 Logistic support. Lead materials and finishes (see 3.4) are interchangeable. Unless otherwise specified, microcircuits acquired for Government logistic support will be acquired to device class B (see 1.2.2), lead material and finish C (see 3.4). Longer length leads and lead forming should not affect the part number. It is intended that spare devices for logistic support be acquired in the unprogrammed condition (see 3.8.1) and programmed by the maintenance activity, except where use quantities for devices with a specific program or pattern justify stocking of preprogrammed devices. 53 MIL-M-38510/208D 6.7 Substitutability. The cross-reference information below is presented for the convenience of users. Microcircuits covered by this specification will functionally replace the listed generic-industry type. Generic-industry microcircuit types may not have equivalent operational performance characteristics across military temperature ranges or reliability factors equivalent to MIL-M-38510 device types and may have slight physical variations in relation to case size. The presence of this information should not be deemed as permitting substitution of generic-industry types for MIL-M-38510 types or as a waiver of any of the provisions of MIL-PRF-38535. Military device type 01 01 01 01 01 02 02 02 02 02 03 04 04 05 05 05 Generic-industry Type 7640/Harris Corporation 5340-1/Monolithic Memories, Inc. 82S140/Signetics Corporation 93438/Fairchild Corporation 54S475/National Semiconductor 7641/Harris Corporation 5341-1/Monolithic Memories, Inc. 82S141/Signetics Corporation 93448/Fairchild Corporation 54S474/National Semiconductor 82S115/Signetics Corporation 5348-1/Monolithic Memories, Inc. 54S473/National Semiconductor 5349-1/Monolithic Memories, Inc. 29621/Raytheon Company 54S472/National Semiconductor Circuit Designator A B C D G A B C D G C B G B F G Fusible Links NiCr NiCr NiCr NiCr TiW NiCr NiCr NiCr NiCr TiW NiCr NiCr TiW NiCr NiCr TiW Symbol/ FSCM no. CDWO/34371 CECD/50364 CDKB/18324 CFJ/07263 CCXP/27014 ---------------------------CRP/07933 ---- 6.8 Change from previous issue. Marginal notations are not used in this revision to identify changes with respect to the previous issue, due to the extensiveness of the changes. Custodians: Army - CR Navy - EC Air Force - 11 DLA - CC Preparing activity: DLA - CC Review activities: Army - SM, MI Navy - AS, CG, MC, SH TD Air Force - 03, 19, 99 (Project 5962-2005-055) NOTE: The activities listed above were interested in this document as of the date of this document. Since organization and responsibilities can change, you should verify the currency of the information above using the ASSIST Online database at http://assist.daps.dla.mil. 54