TP82C55A - Intel - Datasheet.Live

October 1995 Order Number: 231256-004

82C55A

CHMOS PROGRAMMABLE PERIPHERAL INTERFACE

YCompatible with all Intel and Most

Other Microprocessors

YHigh Speed, ‘‘Zero Wait State’’

Operation with 8 MHz 8086/88 and

80186/188

Y24 Programmable I/O Pins

YLow Power CHMOS

YCompletely TTL Compatible

YControl Word Read-Back Capability

YDirect Bit Set/Reset Capability

Y2.5 mA DC Drive Capability on all I/O

Port Outputs

YAvailable in 40-Pin DIP and 44-Pin PLCC

YAvailable in EXPRESS

Ð Standard Temperature Range

Ð Extended Temperature Range

The Intel 82C55A is a high-performance, CHMOS version of the industry standard 8255A general purpose

programmable I/O device which is designed for use with all Intel and most other microprocessors. It provides

24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation.

The 82C55A is pin compatible with the NMOS 8255A and 8255A-5.

In MODE 0, each group of 12 I/O pins may be programmed in sets of 4 and 8 to be inputs or outputs. In

MODE 1, each group may be programmed to have 8 lines of input or output. 3 of the remaining 4 pins are used

for handshaking and interrupt control signals. MODE 2 is a strobed bi-directional bus configuration.

The 82C55A is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption

with performance equal to or greater than the equivalent NMOS product. The 82C55A is available in 40-pin

DIP and 44-pin plastic leaded chip carrier (PLCC) packages.

231256–1

Figure 1. 82C55A Block Diagram

231256–31

231256–2

Figure 2. 82C55A Pinout

Diagrams are for pin reference only. Package

sizes are not to scale.

82C55A

Table 1. Pin Description

Symbol Pin Number Type Name and Function

Dip PLCC

PA3–0 1–4 2–5 I/O PORT A, PINS 0– 3: Lower nibble of an 8-bit data output latch/

buffer and an 8-bit data input latch.

RD 56IREAD CONTROL: This input is low during CPU read operations.

CS 67ICHIP SELECT: A low on this input enables the 82C55A to

respond to RD and WR signals. RD and WR are ignored

otherwise.

GND 7 8 System Ground

A1–0 8–9 9–10 I ADDRESS: These input signals, in conjunction RD and WR,

control the selection of one of the three ports or the control

word registers.

A1A0RD WR CS Input Operation (Read)

00010 Port A - Data Bus

01010 Port B - Data Bus

10010 Port C - Data Bus

11010Control Word - Data Bus

Output Operation (Write)

00100 Data Bus - Port A

01100 Data Bus - Port B

10100 Data Bus - Port C

11100 Data Bus - Control

Disable Function

XXXX1 Data Bus-3-State

X X 1 1 0 Data Bus-3-State

PC7–4 10– 13 11,13– 15 I/O PORT C, PINS 4– 7: Upper nibble of an 8-bit data output latch/

buffer and an 8-bit data input buffer (no latch for input). This port

can be divided into two 4-bit ports under the mode control. Each

4-bit port contains a 4-bit latch and it can be used for the control

signal outputs and status signal inputs in conjunction with ports

A and B.

PC0–3 14–17 16–19 I/O PORT C, PINS 0– 3: Lower nibble of Port C.

PB0-7 18– 25 20 –22, I/O PORT B, PINS 0–7: An 8-bit data output latch/buffer and an 8-

24– 28 bit data input buffer.

VCC 26 29 SYSTEM POWER: a5V Power Supply.

D7–0 27– 34 30 –33, I/O DATA BUS: Bi-directional, tri-state data bus lines, connected to

35– 38 system data bus.

RESET 35 39 I RESET: A high on this input clears the control register and all

ports are set to the input mode.

WR 36 40 I WRITE CONTROL: This input is low during CPU write

operations.

PA7–4 37–40 41–44 I/O PORT A, PINS 4– 7: Upper nibble of an 8-bit data output latch/

buffer and an 8-bit data input latch.

NC 1, 12, No Connect

23, 34

82C55A

82C55A FUNCTIONAL DESCRIPTION

General

The 82C55A is a programmable peripheral interface

device designed for use in Intel microcomputer sys-

tems. Its function is that of a general purpose I/O

component to interface peripheral equipment to the

microcomputer system bus. The functional configu-

ration of the 82C55A is programmed by the system

software so that normally no external logic is neces-

sary to interface peripheral devices or structures.

Data Bus Buffer

This 3-state bidirectional 8-bit buffer is used to inter-

face the 82C55A to the system data bus. Data is

transmitted or received by the buffer upon execution

of input or output instructions by the CPU. Control

words and status information are also transferred

through the data bus buffer.

Read/Write and Control Logic

The function of this block is to manage all of the

internal and external transfers of both Data and

Control or Status words. It accepts inputs from the

CPU Address and Control busses and in turn, issues

commands to both of the Control Groups.

Group A and Group B Controls

The functional configuration of each port is pro-

grammed by the systems software. In essence, the

CPU ‘‘outputs’’ a control word to the 82C55A. The

control word contains information such as ‘‘mode’’,

‘‘bit set’’, ‘‘bit reset’’, etc., that initializes the func-

tional configuration of the 82C55A.

Each of the Control blocks (Group A and Group B)

accepts ‘‘commands’’ from the Read/Write Control

Logic, receives ‘‘control words’’ from the internal

data bus and issues the proper commands to its as-

sociated ports.

Control Group A - Port A and Port C upper (C7–C4)

Control Group B - Port B and Port C lower (C3– C0)

The control word register can be both written and

read as shown in the address decode table in the

pin descriptions. Figure 6 shows the control word

format for both Read and Write operations. When

the control word is read, bit D7 will always be a logic

‘‘1’’, as this implies control word mode information.

Ports A, B, and C

The 82C55A contains three 8-bit ports (A, B, and C).

All can be configured in a wide variety of functional

characteristics by the system software but each has

its own special features or ‘‘personality’’ to further

enhance the power and flexibility of the 82C55A.

Port A. One 8-bit data output latch/buffer and one

8-bit input latch buffer. Both ‘‘pull-up’’ and ‘‘pull-

down’’ bus hold devices are present on Port A.

Port B. One 8-bit data input/output latch/buffer.

Only ‘‘pull-up’’ bus hold devices are present on Port

Port C. One 8-bit data output latch/buffer and one

8-bit data input buffer (no latch for input). This port

can be divided into two 4-bit ports under the mode

control. Each 4-bit port contains a 4-bit latch and it

can be used for the control signal outputs and status

signal inputs in conjunction with ports A and B. Only

‘‘pull-up’’ bus hold devices are present on Port C.

See Figure 4 for the bus-hold circuit configuration for

Port A, B, and C.

82C55A

231256–3

Figure 3. 82C55A Block Diagram Showing Data Bus Buffer and Read/Write Control Logic Functions

*NOTE: 231256–4

Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following a hardware reset.

Figure 4. Port A, B, C, Bus-hold Configuration

82C55A

82C55A OPERATIONAL DESCRIPTION

Mode Selection

There are three basic modes of operation that can

be selected by the system software:

Mode 0 Ð Basic input/output

Mode 1 Ð Strobed Input/output

Mode 2 Ð Bi-directional Bus

When the reset input goes ‘‘high’’ all ports will be set

to the input mode with all 24 port lines held at a logic

‘‘one’’ level by the internal bus hold devices (see

Figure 4 Note). After the reset is removed the

82C55A can remain in the input mode with no addi-

tional initialization required. This eliminates the need

for pullup or pulldown devices in ‘‘all CMOS’’ de-

signs. During the execution of the system program,

any of the other modes may be selected by using a

single output instruction. This allows a single

82C55A to service a variety of peripheral devices

with a simple software maintenance routine.

The modes for Port A and Port B can be separately

defined, while Port C is divided into two portions as

required by the Port A and Port B definitions. All of

the output registers, including the status flip-flops,

will be reset whenever the mode is changed. Modes

may be combined so that their functional definition

can be ‘‘tailored’’ to almost any I/O structure. For

instance; Group B can be programmed in Mode 0 to

monitor simple switch closings or display computa-

tional results, Group A could be programmed in

Mode 1 to monitor a keyboard or tape reader on an

interrupt-driven basis.

231256–5

Figure 5. Basic Mode Definitions and Bus

Interface

231256–6

Figure 6. Mode Definition Format

The mode definitions and possible mode combina-

tions may seem confusing at first but after a cursory

review of the complete device operation a simple,

logical I/O approach will surface. The design of the

82C55A has taken into account things such as effi-

cient PC board layout, control signal definition vs PC

layout and complete functional flexibility to support

almost any peripheral device with no external logic.

Such design represents the maximum use of the

available pins.

Single Bit Set/Reset Feature

Any of the eight bits of Port C can be Set or Reset

using a single OUTput instruction. This feature re-

duces software requirements in Control-based appli-

cations.

When Port C is being used as status/control for Port

A or B, these bits can be set or reset by using the Bit

Set/Reset operation just as if they were data output

ports.

82C55A

231256–7

Figure 7. Bit Set/Reset Format

Interrupt Control Functions

When the 82C55A is programmed to operate in

mode 1 or mode 2, control signals are provided that

can be used as interrupt request inputs to the CPU.

The interrupt request signals, generated from port C,

can be inhibited or enabled by setting or resetting

the associated INTE flip-flop, using the bit set/reset

function of port C.

This function allows the Programmer to disallow or

allow a specific I/O device to interrupt the CPU with-

out affecting any other device in the interrupt struc-

ture.

INTE flip-flop definition:

(BIT-SET)ÐINTE is SETÐInterrupt enable

(BIT-RESET)ÐINTE is RESETÐInterrupt disable

Note:

All Mask flip-flops are automatically reset during

mode selection and device Reset.

82C55A

Operating Modes

Mode 0 (Basic Input/Output). This functional con-

figuration provides simple input and output opera-

tions for each of the three ports. No ‘‘handshaking’’

is required, data is simply written to or read from a

specified port.

Mode 0 Basic Functional Definitions:

#Two 8-bit ports and two 4-bit ports.

#Any port can be input or output.

#Outputs are latched.

#Inputs are not latched.

#16 different Input/Output configurations are pos-

sible in this Mode.

MODE 0 (BASIC INPUT)

231256–8

MODE 0 (BASIC OUTPUT)

231256–9

82C55A

MODE 0 Port Definition

A B GROUP A GROUP B

D4D3D1D0PORT A PORT C ÝPORT B PORT C

(UPPER) (LOWER)

0 0 0 0 OUTPUT OUTPUT 0 OUTPUT OUTPUT

0 0 0 1 OUTPUT OUTPUT 1 OUTPUT INPUT

0 0 1 0 OUTPUT OUTPUT 2 INPUT OUTPUT

0 0 1 1 OUTPUT OUTPUT 3 INPUT INPUT

0 1 0 0 OUTPUT INPUT 4 OUTPUT OUTPUT

0 1 0 1 OUTPUT INPUT 5 OUTPUT INPUT

0 1 1 0 OUTPUT INPUT 6 INPUT OUTPUT

0 1 1 1 OUTPUT INPUT 7 INPUT INPUT

1 0 0 0 INPUT OUTPUT 8 OUTPUT OUTPUT

1 0 0 1 INPUT OUTPUT 9 OUTPUT INPUT

1 0 1 0 INPUT OUTPUT 10 INPUT OUTPUT

1 0 1 1 INPUT OUTPUT 11 INPUT INPUT

1 1 0 0 INPUT INPUT 12 OUTPUT OUTPUT

1 1 0 1 INPUT INPUT 13 OUTPUT INPUT

1 1 1 0 INPUT INPUT 14 INPUT OUTPUT

1 1 1 1 INPUT INPUT 15 INPUT INPUT

MODE 0 Configurations

231256–10

82C55A

MODE 0 Configurations (Continued)

231256–11

82C55A

MODE 0 Configurations (Continued)

231256–12

Operating Modes

MODE 1 (Strobed Input/Output). This functional

configuration provides a means for transferring I/O

data to or from a specified port in conjunction with

strobes or ‘‘handshaking’’ signals. In mode 1, Port A

and Port B use the lines on Port C to generate or

accept these ‘‘handshaking’’ signals.

Mode 1 Basic functional Definitions:

#Two Groups (Group A and Group B).

#Each group contains one 8-bit data port and one

4-bit control/data port.

#The 8-bit data port can be either input or output

Both inputs and outputs are latched.

#The 4-bit port is used for control and status of the

8-bit data port.

82C55A

Input Control Signal Definition

STB (Strobe Input). A ‘‘low’’ on this input loads

data into the input latch.

IBF (Input Buffer Full F/F)

A ‘‘high’’ on this output indicates that the data has

been loaded into the input latch; in essence, an ac-

knowledgement. IBF is set by STB input being low

and is reset by the rising edge of the RD input.

INTR (Interrupt Request)

A ‘‘high’’ on this output can be used to interrupt the

CPU when an input device is requesting service.

INTR is set by the STB is a ‘‘one’’, IBF is a ‘‘one’’

and INTE is a ‘‘one’’. It is reset by the falling edge of

RD. This procedure allows an input device to re-

quest service from the CPU by simply strobing its

data into the port.

INTE A

Controlled by bit set/reset of PC4.

INTE B

Controlled by bit set/reset of PC2.

231256–13

Figure 8. MODE 1 Input

231256–14

Figure 9. MODE 1 (Strobed Input)

82C55A

Output Control Signal Definition

OBF (Output Buffer Full F/F). The OBF output will

go ‘‘low’’ to indicate that the CPU has written data

out to the specified port. The OBF F/F will be set by

the rising edge of the WR input and reset by ACK

Input being low.

ACK (Acknowledge Input). A ‘‘low’’ on this input

informs the 82C55A that the data from Port A or Port

B has been accepted. In essence, a response from

the peripheral device indicating that it has received

the data output by the CPU.

INTR (Interrupt Request). A ‘‘high’’ on this output

can be used to interrupt the CPU when an output

device has accepted data transmitted by the CPU.

INTR is set when ACK is a ‘‘one’’, OBF is a ‘‘one’’

and INTE is a ‘‘one’’. It is reset by the falling edge of

WR.

INTE A

Controlled by bit set/reset of PC6.

INTE B

Controlled by bit set/reset of PC2.

231256–15

Figure 10. MODE 1 Output

231256–16

Figure 11. MODE 1 (Strobed Output)

82C55A

Combinations of MODE 1

Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed

I/O applications.

231256–17

Figure 12. Combinations of MODE 1

Operating Modes

MODE 2 (Strobed Bidirectional Bus I/O).This

functional configuration provides a means for com-

municating with a peripheral device or structure on a

single 8-bit bus for both transmitting and receiving

data (bidirectional bus I/O). ‘‘Handshaking’’ signals

are provided to maintain proper bus flow discipline in

a similar manner to MODE 1. Interrupt generation

and enable/disable functions are also available.

MODE 2 Basic Functional Definitions:

#Used in Group A only.

#One 8-bit, bi-directional bus port (Port A) and a 5-

bit control port (Port C).

#Both inputs and outputs are latched.

#The 5-bit control port (Port C) is used for control

and status for the 8-bit, bi-directional bus port

(Port A).

Bidirectional Bus I/O Control Signal Definition

INTR (Interrupt Request). A high on this output can

be used to interrupt the CPU for input or output oper-

ations.

Output Operations

OBF (Output Buffer Full). The OBF output will go

‘‘low’’ to indicate that the CPU has written data out

to port A.

ACK (Acknowledge). A ‘‘low’’ on this input enables

the tri-state output buffer of Port A to send out the

data. Otherwise, the output buffer will be in the high

impedance state.

INTE 1 (The INTE Flip-Flop Associated with

OBF). Controlled by bit set/reset of PC6.

Input Operations

STB (Strobe Input). A ‘‘low’’ on this input loads

data into the input latch.

IBF (Input Buffer Full F/F). A ‘‘high’’ on this output

indicates that data has been loaded into the input

latch.

INTE 2 (The INTE Flip-Flop Associated with IBF).

Controlled by bit set/reset of PC4.

82C55A

231256–18

Figure 13. MODE Control Word

231256–19

Figure 14. MODE 2

231256–20

Figure 15. MODE 2 (Bidirectional)

NOTE:

Any sequence where WR occurs before ACK, and STB occurs before RD is permissible.

(INTR eIBF #MASK #STB #RD aOBF #MASK #ACK #WR)

82C55A

231256–21

Figure 16. MODE (/4 Combinations

82C55A

Mode Definition Summary

MODE 0 MODE 1 MODE 2

IN OUT IN OUT GROUP A ONLY

PA0IN OUT IN OUT

PA1IN OUT IN OUT

PA2IN OUT IN OUT

PA3IN OUT IN OUT

PA4IN OUT IN OUT

PA5IN OUT IN OUT

PA6IN OUT IN OUT

PA7IN OUT IN OUT

PB0IN OUT IN OUT Ð

PB1IN OUT IN OUT Ð

PB2IN OUT IN OUT Ð

PB3IN OUT IN OUT Ð MODE 0

PB4IN OUT IN OUT Ð OR MODE 1

PB5IN OUT IN OUT Ð ONLY

PB6IN OUT IN OUT Ð

PB7IN OUT IN OUT Ð

PC0IN OUT INTRBINTRBI/O

PC1IN OUT IBFBOBFBI/O

PC2IN OUT STBBACKBI/O

PC3IN OUT INTRAINTRAINTRA

PC4IN OUT STBAI/O STBA

PC5IN OUT IBFAI/O IBFA

PC6IN OUT I/O ACKAACKA

PC7IN OUT I/O OBFAOBFA

Special Mode Combination Considerations

There are several combinations of modes possible.

For any combination, some or all of the Port C lines

are used for control or status. The remaining bits are

either inputs or outputs as defined by a ‘‘Set Mode’’

command.

During a read of Port C, the state of all the Port C

lines, except the ACK and STB lines, will be placed

on the data bus. In place of the ACK and STB line

states, flag status will appear on the data bus in the

PC2, PC4, and PC6 bit positions as illustrated by

Figure 18.

Through a ‘‘Write Port C’’ command, only the Port C

pins programmed as outputs in a Mode 0 group can

be written. No other pins can be affected by a ‘‘Write

Port C’’ command, nor can the interrupt enable flags

be accessed. To write to any Port C output pro-

grammed as an output in a Mode 1 group or to

change an interrupt enable flag, the ‘‘Set/Reset Port

C Bit’’ command must be used.

With a ‘‘Set/Reset Port C Bit’’ command, any Port C

line programmed as an output (including INTR, IBF

and OBF) can be written, or an interrupt enable flag

can be either set or reset. Port C lines programmed

as inputs, including ACK and STB lines, associated

with Port C are not affected by a ‘‘Set/Reset Port C

Bit’’ command. Writing to the corresponding Port C

bit positions of the ACK and STB lines with the

‘‘Set/Reset Port C Bit’’ command will affect the

Group A and Group B interrupt enable flags, as illus-

trated in Figure 18.

Current Drive Capability

Any output on Port A, B or C can sink or source 2.5

mA. This feature allows the 82C55A to directly drive

Darlington type drivers and high-voltage displays

that require such sink or source current.

82C55A

Reading Port C Status

In Mode 0, Port C transfers data to or from the pe-

ripheral device. When the 82C55A is programmed to

function in Modes 1 or 2, Port C generates or ac-

cepts ‘‘hand-shaking’’ signals with the peripheral de-

vice. Reading the contents of Port C allows the pro-

grammer to test or verify the ‘‘status’’ of each pe-

ripheral device and change the program flow ac-

cordingly.

There is no special instruction to read the status in-

formation from Port C. A normal read operation of

Port C is executed to perform this function.

INPUT CONFIGURATION

D7D6D5D4D3D2D1D0

I/O I/O IBFAINTEAINTRAINTEBIBFBINTRB

GROUP A GROUP B

OUTPUT CONFIGURATIONS

D7D6D5D4D3D2D1D0

OBFAINTEAI/O I/O INTRAINTEBOBFBINTRB

GROUP A GROUP B

Figure 17a. MODE 1 Status Word Format

D7D6D5D4D3D2D1D0

OBFAINTE1IBFAINTE2INTRA

GROUP A GROUP B

(Defined By Mode 0 or Mode 1 Selection)

Figure 17b. MODE 2 Status Word Format

Interrupt Enable Flag Position Alternate Port C Pin Signal (Mode)

INTE B PC2 ACKB(Output Mode 1) or STBB(Input Mode 1)

INTE A2 PC4 STBA(Input Mode 1 or Mode 2)

INTE A1 PC6 ACKA(Output Mode 1 or Mode 2

Figure 18. Interrupt Enable Flags in Modes 1 and 2

82C55A

ABSOLUTE MAXIMUM RATINGS*

Ambient Temperature Under BiasÀÀÀÀ0§Ctoa70§C

Storage Temperature ÀÀÀÀÀÀÀÀÀb65§Ctoa150§C

Supply Voltage ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀb0.5 to a8.0V

Operating Voltage ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀa4V to a7V

Voltage on any InputÀÀÀÀÀÀÀÀÀÀGNDb2V to a6.5V

Voltage on any Output ÀÀGNDb0.5V to VCC a0.5V

Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1 Watt

NOTICE: This is a production data sheet. The specifi-

cations are subject to change without notice.

WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

D.C. CHARACTERISTICS

TAe0§Cto70

C, VCC ea

5V g10%, GND e0V (TAeb

40§Ctoa

85§C for Extended Temperture)

Symbol Parameter Min Max Units Test Conditions

VIL Input Low Voltage b0.5 0.8 V

VIH Input High Voltage 2.0 VCC V

VOL Output Low Voltage 0.4 V IOL e2.5 mA

VOH Output High Voltage 3.0 V IOH eb

2.5 mA

VCC b0.4 V IOH eb

100 mA

IIL Input Leakage Current g1mAV

IN eVCC to 0V

(Note 1)

IOFL Output Float Leakage Current g10 mAV

IN eVCC to 0V

(Note 2)

IDAR Darlington Drive Current g2.5 (Note 4) mA Ports A, B, C

Rext e500X

Vext e1.7V

IPHL Port Hold Low Leakage Current a50 a300 mAV

OUT e1.0V

Port A only

IPHH Port Hold High Leakage Current b50 b300 mAV

OUT e3.0V

Ports A, B, C

IPHLO Port Hold Low Overdrive Current b350 mAV

OUT e0.8V

IPHHO Port Hold High Overdrive Current a350 mAV

OUT e3.0V

ICC VCC Supply Current 10 mA (Note 3)

ICCSB VCC Supply Current-Standby 10 mAV

CC e5.5V

VIN eVCC or GND

Port Conditions

If I/P eOpen/High

O/P eOpen Only

With Data Bus e

High/Low

CS eHigh

Reset eLow

Pure Inputs e

Low/High

NOTES:

1. Pins A1,A

,CS,WR,RD, Reset.

2. Data Bus; Ports B, C.

3. Outputs open.

4. Limit output current to 4.0 mA.

82C55A

CAPACITANCE

TAe25§C, VCC eGND e0V

Symbol Parameter Min Max Units Test Conditions

CIN Input Capacitance 10 pF Unmeasured plns

returned to GND

CI/O I/O Capacitance 20 pF fce1 MHz(5)

NOTE:

5. Sampled not 100% tested.

A.C. CHARACTERISTICS

TAe0§to 70§C, VCC ea

5V g10%, GND e0V

TAeb

40§Ctoa

85§C for Extended Temperature

BUS PARAMETERS

READ CYCLE

Symbol Parameter 82C55A-2 Units Test

Min Max Conditions

tAR Address Stable Before RD

0ns

RA Address Hold Time After RD

0ns

RR RD Pulse Width 150 ns

tRD Data Delay from RD

120 ns

tDF RD

to Data Floating 10 75 ns

tRV Recovery Time between RD/WR 200 ns

WRITE CYCLE

Symbol Parameter 82C55A-2 Units Test

Min Max Conditions

tAW Address Stable Before WR

0ns

WA Address Hold Time After WR

20 ns PortsA&B

20 ns Port C

tWW WR Pulse Width 100 ns

tDW Data Setup Time Before WR

100 ns

tWD Data Hold Time After WR

30 ns PortsA&B

30 ns Port C

82C55A

OTHER TIMINGS

Symbol Parameter 82C55A-2 Units Test

Min Max Conditions

tWB WR e1 to Output 350 ns

tlR Peripheral Data Before RD 0ns

HR Peripheral Data After RD 0ns

AK ACK Pulse Width 200 ns

tST STB Pulse Width 100 ns

tPS Per. Data Before STB High 20 ns

tPH Per. Data After STB High 50 ns

tAD ACK e0 to Output 175 ns

tKD ACK e1 to Output Float 20 250 ns

tWOB WR e1toOBFe0 150 ns

tAOB ACK e0toOBFe1 150 ns

tSIB STB e0toIBFe1 150 ns

tRIB RD e1toIBFe0 150 ns

tRIT RD e0 to INTR e0 200 ns

tSIT STB e1 to INTR e1 150 ns

tAIT ACK e1 to INTR e1 150 ns

tWIT WR e0 to INTR e0 200 ns see note 1

tRES Reset Pulse Width 500 ns see note 2

NOTE:

1. INTR

may occur as early as WR

2. Pulse width of initial Reset pulse after power on must be at least 50 mSec. Subsequent Reset pulses may be 500 ns

minimum. The output Ports A, B, or C may glitch low during the reset pulse but all port pins will be held at a logic ‘‘one’’ level

after the reset pulse.

82C55A

WAVEFORMS

MODE 0 (BASIC INPUT)

231256–22

MODE 0 (BASIC OUTPUT)

231256–23

82C55A

WAVEFORMS (Continued)

MODE 1 (STROBED INPUT)

231256–24

MODE 1 (STROBED OUTPUT)

231256–25

82C55A

WAVEFORMS (Continued)

MODE 2 (BIDIRECTIONAL)

231256–26

Note:

Any sequence where WR occurs before ACK AND STB occurs before RD is permissible.

(INTR eIBF #MASK #STB #RD aOBF #MASK #ACK #WR)

WRITE TIMING

231256–27

READ TIMING

231256–28

A.C. TESTING INPUT, OUTPUT WAVEFORM

231256–29

A.C. Testing Inputs Are Driven At 2.4V For A Logic 1 And 0.45V

For A Logic 0 Timing Measurements Are Made At 2.0V For A

Logic 1 And 0.8 For A Logic 0.

A.C. TESTING LOAD CIRCUIT

231256–30

*VEXT Is Set At Various Voltages During Testing To Guarantee

The Specification. CLIncludes Jig Capacitance.