Device Engineering Incorporated 385 East Alamo Drive Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com DEI1041 ARINC 429 LINE RECEIVER FEATURES * * * * * * * ARINC 429 to TTL/CMOS logic line receiver Operates from single +5V 10% or 3.3V 10% power supply ARINC inputs internally protected to lightning requirements of DO-160D Level A3 Operates in high noise environment o Input Common Voltage Range: 20V o 2V minimum Input hysteresis Logic level TEST inputs bypass analog inputs. 8 Lead SOIC. Replacement for HI-8588 and HI-8588-10 TERMINAL DESCRIPTION Table 1 Terminal Description NAME (c)2009 Device Engineering Inc. DESCRIPTION INA 429 INPUT. ARINC 429 format serial digital data "A" input. INB 429 INPUT. ARINC 429 format serial digital data "B" input. TESTA LOGIC INPUT. Test input A. TESTB LOGIC INPUT. Test input B. OUTA LOGIC OUTPUT. CMOS/TTL format serial digital data "A" output. OUTB LOGIC OUTPUT. CMOS/TTL format serial digital data "B" output. VDD POWER INPUT. 5 VDC OR 3.3VDC. GND POWER INPUT. Ground. Page 1 of 8 DS-MW-01041-01 Rev H 10/28/2008 FUNCTIONAL DESCRIPTION The DEI1041 is a BICMOS device which contains one ARINC 429 differential line receiver. It translates incoming ARINC 429 data bus signals (tri-level RZ bipolar differential modulation) to a pair of TTL/CMOS logic outputs. It meets the requirements of the ARINC 429 Digital Information Transfer Standard. Refer to Figure 1 " DEI1041 Block Diagram and Truth Table". The device is designed to operate in a high noise environment. Inputs are accepted over a +/- 20V common mode voltage range and the receivers provide over 2 Volts of hysteresis. Circuit speed is optimized to reject high frequency transients. All ARINC input pins are designed with internal protection from damage due to transients meeting the lightning induced transient requirements of DO-160D Level A3. The ARINC inputs may optionally be connected to ARINC bus through external 10k ohm series resistors. These resistors may be added in combination with transient voltage suppressors to achieve lighting protection beyond the Level A3 limits due to high input impedance. The DEI1041 device provides logic level TEST inputs for built in system test. They force the receiver outputs to the specified ZERO, ONE or NULL state. The ARINC inputs are ignored when the device is in test mode. DEI1041 Block Diagram Typical Channel DEI1041 Truth Table INPUTS TEST INPUTS (TTL/CMOS) INA OUTA INB TEST A TEST B AIN - BIN V RESISTOR NETWORK AND LIGHTNING PROTECTION OUTPUT AND TEST LOGIC OUTB Comparators TESTA TESTB ARINC INPUTS IINPUT BUFFERS OUTPUTS TTL/CMOS OUT A OUT B Logic 0 0 >6.5v 1 0 ONE 0 0 <-6.5V 0 1 ZERO 0 0 -2.5 to +2.5 0 0 NULL 0 1 X 0 1 ZERO 1 0 X 1 0 ONE 1 1 X 0 0 NULL Figure 1 DEI1041 Block Diagram and Truth Table ELECTRICAL DESCRIPTION Table 2 Recommended Operating Conditions PARAMETER Supply Voltage Logic Input Levels Operating Temperature -SES -SMS (c)2009 Device Engineering Inc. SYMBOL CONDITIONS Vdd +5V 10% +3.3V 10% VTESTA,B 0 to Vdd Ta -55 to +85C -55 to +125C Page 2 of 8 DS-MW-01041-01 Rev H 10/28/2008 Table 3 Absolute Maximum Rating MIN MAX UNITS Supply Voltage (with respect to VSS) PARAMETER -0.3 7.0 V Storage Temperature -65 +150 C Input Voltage, continuous (ARINC Inputs) -40 +40 V VSS - 0.3 VDD+0.3 V 500 mW 145 C Input Voltage (Test Inputs) Power Dissipation @ 85 C Junction Temperature: Tjmax, (limited by molding compound Tg) Peak Body Temperature, Non-G Package - G Package Lightning Protection (ARINC 429 Channel Inputs and TESTA/TESTB Inputs) Waveform 3* Waveform 4 and 5* *Per DO160D level 3A. See Figures 4-6. - 240 260 -600 -300 +600 +300 V V 2000 V ESD per JEDEC A114-A Human Body Model o C Stresses above these limits can cause permanent damage. Table 4 Electrical Characteristics Conditions: Temperature: -55C to +85C (SES) : -55C to +125C (SMS); VDD = +5V 10% or 3.3V 10% PARAMETER TEST CONDITION VA - VB = Logic +1 OUTA = 1 VA - VB = Logic -1 VA - VB = Logic Null SYMBOL MIN NOM MAX UNITS V+1 6.5 10 13 V OUTB = 1 V-1 -6.5 -10 -13 V OUTA = 0 OUTB = 0 VNULL -2.5 0 2.5 V VHY 2.0 4.0 V ARINC INPUTS Input Hysteresis VA - VB = Null to +1 transition OUTA = 01 VT+1+ 5.5 6.5 V VA - VB = +1 to Null transition OUTA = 10 VT+1- 2.5 3.5 V VA - VB = Null to -1 transition OUTB = 01 VT-1+ -6.5 -5.5 V VA - VB = -1 to Null transition OUTB = 10 VT-1- -3.5 -2.5 V Logic +1, Null, Logic -1 VCM -20 +20 V RIN 140k 390K RS 140k 390K Input Common Mode Voltage Range Input Resistance INA to INB Input Resistance INA or INB to VSS Input Capacitance INA to INB Input Capacitance INA or INB to VSS (c)2009 Device Engineering Inc. VDD open, Shorted to VSS or +5V VDD open, Shorted to VSS or +5V VDD open, Shorted to VSS or +5V (1) VDD open, Shorted to VSS or +5V (1) Page 3 of 8 CIN 10 pF CS 10 pF DS-MW-01041-01 Rev H 10/28/2008 Conditions: Temperature: -55C to +85C (SES) : -55C to +125C (SMS); VDD = +5V 10% or 3.3V 10% PARAMETER TEST CONDITION SYMBOL MIN NOM MAX UNITS 0.8 V TEST INPUTS Logic 0 Voltage VIL Logic 1 Voltage VIH Logic 0 Current Logic 1 Current OUT A or OUT B OUT A or OUT B OUT A or OUT B OUT A or OUT B VDD Current VIL = 0.8 2.0 V IIL VIH = 2.0 IIH LOGIC OUTPUTS IOH = 5mA (5V Vdd) VOH IOH = 1.5mA (3.3V Vdd) TTL Compatible IOL = 5mA (5V Vdd) VOL IOL = 1.5mA (3.3V Vdd) TTL Compatible IOH = 100A VOH CMOS Compatible IOL = 100A VOH CMOS Compatible SUPPLY CURRENT Data Rate = 0MHz, A/BIN =open, IDD A/BOUT=open, Vdd = 5.5V or 3.63V 20 A 20 A 2.4 V 0.5 0.4 V VDD - 50mV V VSS + 50mV V 5 mA 2.5 Notes: 1. Guaranteed by design, not production tested. 2. Current flowing into device is positive. Current flowing out of device is negative. All voltages are with respect to Ground unless otherwise noted. Table 5 Switching Characteristics PARAMETER TEST CONDITION SYMBOL MAX MAX UNITS Vdd 3.3V Vdd 5V INA/B to OUT A/B Prop Delay INA/B to OUT A/B Prop Delay TESTA = TESTB = 0 CL = 50pF TESTA = TESTB = 0 CL = 50pF tLH 1000 900 ns tHL 1000 900 ns Dtp 500 25 25 ns OUT A/B rise time 10% to 90%, CL = 50pF tr OUT A/B fall time TESTA/B to OUTA/B Prop delay TESTA/B to OUTA/B Prop delay 10% to 90%, CL = 50pF tf 500 50 50 CL = 50pF tTOH 100 60 ns CL = 50pF tTOL 100 60 ns Matching of tLH and tHL (c)2009 Device Engineering Inc. Page 4 of 8 ns ns DS-MW-01041-01 Rev H 10/28/2008 V/I INA 25% to 75% of Largest Peak Largest Peak Vdif = 6.5V Vdif = 2.5V 50% INB t 0 tHL tLH OUTA 1.5V OUTB 1.5V Figure 2 ARINC 429 Input to Logic Output Switching Waveform Figure 4 DO160D Lightning Induced Transient Voltage Waveform #3. Voc = 600V, Isc = 24A, Frequency =1MHz +-20% V Peak T1 = 6.4 us +-20% T2 = 70us +-20% TESTA OR B 1.5V tTOH tTOL 50% OUTA OR B 1.5V 0 Figure 3 TEST Input to Logic Output Switching Waveform T1 t T2 Figure 5 DO160D Lightning Induced Transient Voltage Waveform #4. Voc = 300V, Isc = 60A V/I LIGHTNING TRANSIENT NOTES: 1. Voc = Peak Open Circuit Voltage available at the calibration point. 2. Isc = Peak Short Circuit Current available at the calibration point. 3. Amplitude tolerances: +10%, -0%. 4. The ratio of Voc to Isc is the generator source impedance to be used for generating the waveforms. Peak 5A: T1 = 40us +-20% T2 = 120us +-20% 5B: T1 = 50us +-20% T2 = 500us +-20% 50% Figure 6 DO160D Lightning Induced Transient t Voltage Waveform #5. T1 T2 Voc = 300V, Isc = 300A 0 (c)2009 Device Engineering Inc. Page 5 of 8 DS-MW-01041-01 Rev H 10/28/2008 PACKAGE DESCRIPTION 8 Lead NB SOIC Table 6 - 8 Lead NB SOIC Package Characteristics Table 6: Package Characteristics Table 16 Lead SOIC Narrow Body PACKAGE TYPE REFERENCE 16 Lead SOIC Narrow Body, Green 8L NB SOIC 8L NB SOIC G 55 C/W 55 C/W 24 C/W 24 C/W MSL 1 / 240C MSL 1 / 260C SnPb NiPdAu e4 Pb-Free DESIGNATION Not Pb-free RoHS Compliant JEDEC REFERENCE MS-012-AC MS-012-AC THERMAL RESISTANCE: JA (4 layer PCB with Power Planes) JC JEDEC MOISTURE SENSITIVITY LEVEL (MSL) LEAD FINISH MATERIAL / JEDEC Pb-free CODE Figure 7 Mechanical Outline, 8L NB SOIC - Non - Green Package (c)2009 Device Engineering Inc. Page 6 of 8 DS-MW-01041-01 Rev H 10/28/2008 Figure 8 Mechanical Outline, 8L NB SOIC G - Green Package (c)2009 Device Engineering Inc. Page 7 of 8 DS-MW-01041-01 Rev H 10/28/2008 PROCESS FLOW Table 7 Process Flow PROCESS STEP PLASTIC STANDARD PRE-BURN-IN Electrical Test BURN IN (1) FINAL ELECTRICAL TEST, Room Temperature FINAL ELECTRICAL TEST, High Temperature FINAL ELECTRICAL TEST, Low Temperature PLASTIC BURN-IN N/A YES N/A 96hrs @ +125 C 100% 100% @ +85 or +125C 0.65% AQL @ -55C 100% 100% @ +85 or +125C 0.65% AQL @ -55C NOTES: 1. Burn-in conditions: 125C, 96 hrs, Vcc = 5.0V Inputs = 0V, Outputs open. ORDERING INFORMATION Table 8 Ordering Information DEI PN DEI1041-SES DEI1041-SES - G DEI1041-SMS DEI1041-SMS-G DEI1041-SMB PART MARKING DEI1041 DEI1041 E4 DE1041M DE1041M E4 DE1041B TEMPERATURE RANGE -55/+85 C -55/+85 C BURN-IN NO NO PACKAGE TYPE 8L NB SOIC 8L NB SOIC G -55/+125 C -55/+125 C NO NO 8L NB SOIC 8L NB SOIC G -55/+125 C YES 8L NB SOIC NOTES: 1. All packages marked with Lot Code and Date Code. "E4" after Date Code denotes Pb Free category. DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose. (c)2009 Device Engineering Inc. Page 8 of 8 DS-MW-01041-01 Rev H 10/28/2008