©2009 Device Engineering Inc. Page 1 of 8 DS-MW-01041-01 Rev H
10/28/2008
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
FEATURES
• ARINC 429 to TTL/CMOS logic line receiver
• Operates from single +5V ± 10% or 3.3V ± 10% power supply
• ARINC inputs internally protected to lightning requirements of DO-160D Level A3
• Operates in high noise environment
o Input Common Voltage Range: ± 20V
o 2V minimum Input hysteresis
• Logic level TEST inputs bypass analog inputs.
• 8 Lead SOIC.
• Replacement for HI-8588 and HI-8588-10
TERMINAL DESCRIPTION
Table 1 Terminal Description
Device
Engineering
Incorporated DEI1041
ARINC 429 LINE RECEIVER
NAME DESCRIPTION
INA 429 INPUT. ARINC 429 format serial digital data
“A” input.
INB 429 INPUT. ARINC 429 format serial digital data
“B” input.
TESTA LOGIC INPUT. Test input A.
TESTB LOGIC INPUT. Test input B.
OUTA LOGIC OUTPUT. CMOS/TTL format serial digital
data “A” output.
OUTB LOGIC OUTPUT. CMOS/TTL format serial digital
data “B” output.
VDD POWER INPUT. 5 VDC OR 3.3VDC.
GND POWER INPUT. Ground.
©2009 Device Engineering Inc. Page 2 of 8 DS-MW-01041-01 Rev H
10/28/2008
FUNCTIONAL DESCRIPTION
The DEI1041 is a BICMOS device which contains one ARINC 429 differential line receiver. It translates incoming ARINC
429 data bus signals (tri-level RZ bipolar differential modulation) to a pair of TTL/CMOS logic outputs. It meets the
requirements of the ARINC 429 Digital Information Transfer Standard. Refer to Figure 1 “ DEI1041 Block Diagram and
Truth Table”.
The device is designed to operate in a high noise environment. Inputs are accepted over a +/- 20V common mode voltage
range and the receivers provide over 2 Volts of hysteresis. Circuit speed is optimized to reject high frequency transients.
All ARINC input pins are designed with internal protection from damage due to transients meeting the lightning induced
transient requirements of DO-160D Level A3. The ARINC inputs may optionally be connected to ARINC bus through
external 10k ohm series resistors. These resistors may be added in combination with transient voltage suppressors to achieve
lighting protection beyond the Level A3 limits due to high input impedance.
The DEI1041 device provides logic level TEST inputs for built in system test. They force the receiver outputs to the specified
ZERO, ONE or NULL state. The ARINC inputs are ignored when the device is in test mode.
DEI1041 Block Diagram Typical Channel
INB
RESISTOR
NETWOR
K
A
ND
LIGHTNING
PROTECTION OUTPUT
AND
TEST
LOGIC
INA
Comparators
OUTA
OUTB
TESTA
TESTB IINPUT
BUFFERS
INPUTS OUTPUTS
TEST INPUTS
(TTL/CMOS)
A
RINC
INPUTS
TTL/CMOS
TEST A TEST B
A
IN – B
IN
V
OUT A
OUT B
0
0
0
0
1
1
0
0
0
1
0
1
>6.5v
<-6.5V
-2.5 to +2.5
X
X
X
1
0
0
0
1
0
0
1
0
1
0
0
DEI1041 Truth Table
Logic
ONE
ZERO
NULL
ZERO
ONE
NULL
Figure 1 DEI1041 Block Diagram and Truth Table
ELECTRICAL DESCRIPTION
Table 2 Recommended Operating Conditions
PARAMETER SYMBOL CONDITIONS
Supply Voltage Vdd +5V ± 10%
+3.3V ± 10%
Logic Input Levels VTESTA,B 0 to Vdd
Operating Temperature
-SES
-SMS
Ta
-55 to +85°C
-55 to +125°C
©2009 Device Engineering Inc. Page 3 of 8 DS-MW-01041-01 Rev H
10/28/2008
Table 3 Absolute Maximum Rating
PARAMETER MIN MAX UNITS
Supply Voltage (with respect to VSS) -0.3 7.0 V
Storage Temperature -65 +150 °C
Input Voltage, continuous (ARINC Inputs) -40 +40 V
Input Voltage (Test Inputs) VSS – 0.3 VDD+0.3 V
Power Dissipation @ 85 °C 500 mW
Junction Temperature:
Tjmax, (limited by molding compound Tg)
145
°C
Peak Body Temperature,
Non-G Package
- G Package
-
240
260
o C
Lightning Protection (ARINC 429 Channel Inputs and TESTA/TESTB Inputs)
Waveform 3*
Waveform 4 and 5*
*Per DO160D level 3A. See Figures 4-6.
-600
-300
+600
+300
V
V
ESD per JEDEC A114-A Human Body Model 2000 V
Stresses above these limits can cause permanent damage.
Table 4 Electrical Characteristics
Conditions: Temperature: -55°C to +85°C (SES) : -55°C to +125°C (SMS); VDD = +5V ± 10% or 3.3V ± 10%
PARAMETER TEST CONDITION SYMBOL MIN NOM MAX UNITS
ARINC INPUTS
VA – VB = Logic +1 OUTA = 1 V+1 6.5 10 13 V
VA – VB = Logic -1 OUTB = 1 V-1 -6.5 -10 -13 V
VA – VB = Logic Null OUTA = 0
OUTB = 0 VNULL -2.5 0 2.5 V
Input Hysteresis VHY 2.0 4.0
V
VA – VB = Null to +1 transition OUTA = 0→1 VT+1+ 5.5 6.5 V
VA – VB = +1 to Null transition OUTA = 1→0 VT+1- 2.5 3.5 V
VA – VB = Null to -1 transition OUTB = 0→1 VT-1+ -6.5 -5.5 V
VA – VB = -1 to Null transition OUTB = 1→0 VT-1- -3.5 -2.5 V
Input Common Mode
Voltage Range Logic +1, Null, Logic -1 VCM -20 +20
V
Input Resistance
INA to INB
VDD open,
Shorted to VSS or +5V RIN 140k 390K Ω
Input Resistance
INA or INB to VSS
VDD open,
Shorted to VSS or +5V RS 140k 390K Ω
Input Capacitance
INA to INB
VDD open,
Shorted to VSS or +5V (1) CIN
10 pF
Input Capacitance
INA or INB to VSS
VDD open,
Shorted to VSS or +5V (1) CS
10 pF
©2009 Device Engineering Inc. Page 4 of 8 DS-MW-01041-01 Rev H
10/28/2008
Conditions: Temperature: -55°C to +85°C (SES) : -55°C to +125°C (SMS); VDD = +5V ± 10% or 3.3V ± 10%
PARAMETER TEST CONDITION SYMBOL MIN NOM MAX UNITS
TEST INPUTS
Logic 0 Voltage VIL
0.8 V
Logic 1 Voltage VIH 2.0
V
Logic 0 Current VIL = 0.8 IIL
20 µA
Logic 1 Current VIH = 2.0 IIH
20 µA
LOGIC OUTPUTS
OUT A or OUT B
IOH = 5mA (5V Vdd)
IOH = 1.5mA (3.3V Vdd)
TTL Compatible
VOH 2.4
V
IOL = 5mA (5V Vdd)
0.5
IOL = 1.5mA (3.3V Vdd)
0.4
OUT A or OUT B
TTL Compatible
VOL
V
OUT A or OUT B IOH = 100µA
CMOS Compatible VOH VDD –
50mV
V
OUT A or OUT B IOL = 100µA
CMOS Compatible VOH
VSS +
50mV V
SUPPLY CURRENT
VDD Current
Data Rate = 0MHz,
A/BIN =open,
A/BOUT=open,
Vdd = 5.5V or 3.63V
IDD 2.5 5 mA
Notes:
1. Guaranteed by design, not production tested.
2. Current flowing into device is positive. Current flowing out of device is negative. All voltages are with respect to
Ground unless otherwise noted.
Table 5 Switching Characteristics
PARAMETER TEST CONDITION SYMBOL MAX MAX UNITS
Vdd 3.3V Vdd 5V
INA/B to OUT A/B Prop Delay TESTA = TESTB = 0
CL = 50pF tLH 1000 900 ns
INA/B to OUT A/B Prop Delay TESTA = TESTB = 0
CL = 50pF tHL 1000 900 ns
Matching of tLH and tHL Dtp
500 500 ns
OUT A/B rise time 10% to 90%, CL = 50pF tr 50 25 ns
OUT A/B fall time 10% to 90%, CL = 50pF tf 50 25 ns
TESTA/B to OUTA/B Prop
delay CL = 50pF tTOH 100 60 ns
TESTA/B to OUTA/B Prop
delay CL = 50pF tTOL 100 60 ns
©2009 Device Engineering Inc. Page 5 of 8 DS-MW-01041-01 Rev H
10/28/2008
INA
INB
OUTA
OUTB
1.5V
1.5V
tLH
Vdif = 6.5V
tHL
Vdif = 2.5V
0t
V/I
25% to 75%
of Largest Peak
50%
Largest
Peak
t
0
50%
Peak
T1 T2
V
t
0
50%
Peak
T1 T2
V/I
tTOH tTOL
1.5V
1.5V
TESTA OR B
OUTA OR B
Figure 2 ARINC 429 Input to Logic Output Switching
Waveform
Figure 3 TEST Input to Logic Output Switching
Waveform
Figure 4 DO160D Lightning Induced Transient
Voltage Waveform #3.
Voc = 600V, Isc = 24A, Frequency =1MHz +-20%
Figure 5 DO160D Lightning Induced Transient
Voltage Waveform #4.
Voc = 300V, Isc = 60A
Figure 6 DO160D Lightning Induced Transient
Voltage Waveform #5.
Voc = 300V, Isc = 300A
T1 = 6.4 us +-20%
T2 = 70us +-20%
5A: T1 = 40us +-20%
T2 = 120us +-20%
5B: T1 = 50us +-20%
T2 = 500us +-20%
LIGHTNING TRANSIENT NOTES:
1. Voc = Peak Open Circuit Voltage available at the
calibration point.
2. Isc = Peak Short Circuit Current available at the
calibration point.
3. Amplitude tolerances: +10%, -0%.
4. The ratio of Voc to Isc is the generator source
impedance to be used for generating the
waveforms.
©2009 Device Engineering Inc. Page 6 of 8 DS-MW-01041-01 Rev H
10/28/2008
PACKAGE DESCRIPTION
8 Lead NB SOIC
Table 6 - 8 Lead NB SOIC Package Characteristics
Table 6: Package Characteristics Table
PACKAGE TYPE
16 Lead SOIC
Narrow Body
16 Lead SOIC
Narrow Body, Green
REFERENCE 8L NB SOIC 8L NB SOIC G
THERMAL RESISTANCE:
θJA (4 layer PCB with Power Planes) 55 °C/W 55 °C/W
θJC 24 °C/W 24 °C/W
JEDEC MOISTURE
SENSITIVITY LEVEL (MSL) MSL 1 / 240°C MSL 1 / 260°C
LEAD FINISH MATERIAL /
JEDEC Pb-free CODE SnPb NiPdAu
e4
Pb-Free DESIGNATION Not Pb-free RoHS Compliant
JEDEC REFERENCE MS-012-AC MS-012-AC
Figure 7 Mechanical Outline, 8L NB SOIC – Non - Green Package
©2009 Device Engineering Inc. Page 7 of 8 DS-MW-01041-01 Rev H
10/28/2008
Figure 8 Mechanical Outline, 8L NB SOIC G – Green Package
©2009 Device Engineering Inc. Page 8 of 8 DS-MW-01041-01 Rev H
10/28/2008
PROCESS FLOW
Table 7 Process Flow
PROCESS
STEP
PLASTIC
STANDARD
PLASTIC
BURN-IN
PRE-BURN-IN Electrical Test N/A YES
BURN IN (1)
N/A
96hrs @ +125 °C
FINAL ELECTRICAL TEST,
Room Temperature 100% 100%
FINAL ELECTRICAL TEST,
High Temperature
100% @
+85 or +125°C
100% @
+85 or +125°C
FINAL ELECTRICAL TEST,
Low Temperature
0.65% AQL
@ -55°C
0.65% AQL
@ -55°C
NOTES:
1. Burn-in conditions: 125°C, 96 hrs, Vcc = 5.0V Inputs = 0V, Outputs open.
ORDERING INFORMATION
Table 8 Ordering Information
DEI PN PART MARKING TEMPERATURE RANGE BURN-IN PACKAGE TYPE
DEI1041-SES DEI1041 -55/+85 ºC NO 8L NB SOIC
DEI1041-SES - G DEI1041
E4
-55/+85 ºC NO 8L NB SOIC G
DEI1041-SMS DE1041M -55/+125 ºC NO 8L NB SOIC
DEI1041-SMS-G DE1041M
E4
-55/+125 ºC NO 8L NB SOIC G
DEI1041-SMB DE1041B -55/+125 ºC YES 8L NB SOIC
NOTES:
1. All packages marked with Lot Code and Date Code. “E4” after Date Code denotes Pb Free category.
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or
guarantee regarding suitability of its products for any particular purpose.
