Features
•
Fast Access Time: 30/45 ns
•
Wide Temperature Range: -55°C to +125°C
•
Separate Upper Byte and Lower Byte Control for Multiplexed Bus Compatibility
•
Expandable Data Bus to 32 bits or More Using Master/Slave Chip Select When Using
More Than One Device
•
On-chip Arbitration Logic
•
Versatile Pin Select for Master or Slave:
– M/S = H for Busy Output Flag On Master
– M/S = L for Busy Input Flag On Slave
•
INT Flag for Port to Port Communication
•
Full Hardware Support of Semaphore Signaling Between Ports
•
Fully Asynchronous Operation From Either Port
•
Battery Back-up Operation: 2V Data Retention
•
TTL Compatible
•
Single 5V + 10% Power Supply
•
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm
2
•
Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019
•
Quality grades: QML Q and V with SMD 5962-91617 and ESCC with 9301/050
Introduction
The M67025E is a very low power CMOS dual port static RAM organized as 8192 bit
× 16. The product is designed to be used as a stand-alone 16-bit dual port RAM or as
a combination MASTER/SLAVE dual port for 32-bit or more width systems. The Atmel
MASTER/SLAVE dual port approach in memory system applications results in full
speed, error free operation without the need of an additional discrete logic.
Master and slave devices provide two independent ports with separate control,
address and I/O pins that permit independent, asynchronous access for reads and
writes to any location in the memory. An automatic power down feature controlled by
CS permits the on-chip circuitry of each port in order to enter a very low stand by
power mode.
Using an array of eight transistors (8T) memory cell, the M67025E combines an
extremely low standby supply current (typ = 1.0 µA) with a fast access time at 30 ns
over the full temperature range. All versions offer battery backup data retention capa-
bility with a typical power consumption at less than 5 µW.
For military/space applications that demand superior levels of performance and reli-
ability the M67025E is processed according to the methods of the latest revision of the
MIL PRF 38635 (Q and V) and/or ESCC 9000.
4146N–AERO–04/07
Rad. Tolerant
High Speed
8 Kb x 16
Dual Port RAM
M67025E
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4146N–AERO–04/07
M67025E
Block Diagram
Notes: 1. (MASTER): BUSY is output. (SLAVE): BUSY is input.
2. LB = Lower Byte UB = Upper Byte
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4146N–AERO–04/07
M67025E
Pin Configuration
Pin Description
Left Port Right Port Names
CS
L
CS
R
Chip select
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L –
12L
A
0R – 12R
Address
I/O
0L – 15L
I/O
0R – 15R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable
UB
L
UB
R
Upper Byte Select
LB
L
LB
R
Lower Byte Select
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/S Master or Slave Select
Vcc Power
GND Ground
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4146N–AERO–04/07
M67025E
Functional
Description
The M67025E has two ports with separate control, address and I/O pins that permit independent
read/write access to any memory location. These devices have an automatic power-down fea-
ture controlled by CS. CS controls on-chip power-down circuitry which causes the port
concerned to go into stand-by mode when not selected (CS high). When a port is selected
access to the full memory array is permitted. Each port has its own Output Enable control (OE).
In read mode, the port’s OE turns the Output drivers on when set LOW. Non-conflicting
READ/WRITE conditions are illustrated in Table 1.
The interrupt flag (INT) allows communication between ports or systems. If the user chooses to
use the interrupt function, a memory location (mail box or message center) is assigned to each
port. The left port interrupt flag (INT
L
) is set when the right port writes to memory location 1FFE
(HEX). The left port clears the interrupt by reading address location 1FFE. Similarly, the right
port interrupt flag (INT
R
) is set when the left port writes to memory location 1FFF (HEX), and the
right port must read memory location 1FFF in order to clear the interrupt flag (INT
R
). The 16-bit
message at 1FFE or 1FFF is user-defined. If the interrupt function is not used, address locations
1FFE and 1FFF are not reserved for mail boxes but become part of the RAM. See Table 3 for
the interrupt function.
Arbitration Logic
The arbitration logic will resolve an address match or a chip select match down to a minimum of
5 ns determine which port has access. In all cases, an active BUSY flag will be set for the inhib-
ited port.
The BUSY flags are required when both ports attempt to access the same location simulta-
neously. Should this conflict arise, on-chip arbitration logic will determine which port has access
and set the BUSY flag for the inhibited port. BUSY is set at speeds that allow the processor to
hold the operation with its associated address and data. It should be noted that the operation is
invalid for the port for which BUSY is set LOW. The inhibited port will be given access when
BUSY goes inactive.
A conflict will occur when both left and right ports are active and the two addresses coincide.
The on-chip arbitration determines access in these circumstances. Two modes of arbitration are
provided: (1) if the addresses match and are valid before CS on-chip control logic arbitrates
between CS
L
and CS
R
for access; or (2) if the CS are low before an address match, on-chip con-
trol logic arbitrates between the left and right addresses for access (refer to Table 4). The
inhibited port’s BUSY flag is set and will reset when the port granted access completes its oper-
ation in both arbitration modes.
Data Bus Width
Expansion
Expanding the data bus width to 32 or more bits in a dual-port RAM system means that several
chips may be active simultaneously. If every chips has a hardware arbitrator, and the addresses
for each arrive at the same time one chip may activate in L BUSY signal while another activates
its R BUSY signal. Both sides are now busy and the CPUs will wait indefinitely for their port to
become free.
To overcome this “Busy Lock-Out’ problem, Atmel has developed a MASTER/SLAVE system
which uses a single hardware arbitrator located on the MASTER. The SLAVE has BUSY inputs
which allow direct interface to the MASTER with no external components, giving a speed advantage
over other systems.
When dual-port RAMs are expanded in width, the SLAVE RAMs must be prevented from writing
until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a con-
flict situation. Conversely, the write pulse must extend a hold time beyond BUSY to ensure that a write
cycle occurs once the conflict is resolved. This timing is inherent in all dual-port memory systems where
more than one chip is active at the same time.
5
4146N–AERO–04/07
M67025E
The write pulse to the SLAVE must be inhibited by the MASTER’s maximum arbitration time. If a
conflict then occurs, the write to the SLAVE will be inhibited because of the MASTER’s BUSY
signal.
Semaphore Logic
The M67025E is an extremely fast dual-port 4 Kb × 16 CMOS static RAM with an additional loca-
tions dedicated to binary semaphore flags. These flags allow either of the processors on the left or right
side of the dual-port RAM to claim priority over the other for functions defined by the system software.
For example, the semaphore flag can be used by one processor to inhibit the other from accessing a
portion of the dual-port RAM or any other shared resource.
The dual-port RAM has a fast access time, and the two ports are completely independent of
each another. This means that the activity on the left port cannot slow the access time of the
right port. The ports are identical in function to standard CMOS static RAMs and can be read
from, or written to, at the same time with the only possible conflict arising from simultaneous writ-
ing to, or a simultaneous READ/WRITE operation on, a non-semaphore location. Semaphores
are protected against such ambiguous situations and may be used by the system program to
prevent conflicts in the non-semaphore segment of the dual-port RAM. The devices have an
automatic power-down feature controlled by CS, the dual-port RAM select and SEM, the semaphore
enable. The CS and SEM pins control on-chip-power-down circuitry that permits the port concerned to
go into stand-by mode when not selected. This conditions is shown in Table 1 where CS and SEM are
both high.
Systems best able to exploit the M67025E are based around multiple processors or controllers
and are typically very high-speed, software controlled or software-intensive systems. These sys-
tems can benefit from the performance enhancement offered by the M67025 hardware
semaphores, which provide a lock-out mechanism without the need for complex programming.
Software handshaking between processors offers the maximum level of system flexibility by per-
mitting shared resources to be allocated in varying configurations. The M67025E does not use
its semaphore flags to control any resources through hardware, thus allowing the system
designer total flexibility in system architecture.
An advantage of using semaphores rather than the more usual methods of hardware arbitration
is that neither processor ever incurs wait states. This can prove to be a considerable advantage
in very high speed systems.
How The
Semaphore Flags
Work
The semaphore logic is a set of eight latches independent of the dual-port RAM. These latches
can be used to pass a flag or token, from one port to the other to indicate that a shared resource
is in use. The semaphore provides the hardware context for the “Token Passing Allocation’
method of use assignment. This method uses the state of a semaphore latch as a token indicat-
ing that a shared resource is in use. If the left processor needs to use a resource, it requests the
token by setting the latch. The processor then verifies that the latch has been set by reading it. If
the latch has been set the processor assumes control over the shared resource. If the latch has
not been set, the left processor has established that the right processor had set the latch first,
has the token and is using the shared resource. The left processor may then either repeatedly
query the status of the semaphore, or abandon its request for the token and perform another
operation whilst occasionally attempting to gain control of the token through a set and test oper-
ation. Once the right side has relinquished the token the left side will be able to take control of
the shared resource.
The semaphore flags are active low. A token is requested by writing a zero to a semaphore
latch, and is relinquished again when the same side writes a one to the latch.
The eight semaphore flags are located in a separate memory space from the dual-port RAM in
the M67025E. The address space is accessed by placing a low input on the SEM pin (which acts
as a chip select for the semaphore flags) and using the other control pins (address, OE and R/W) as nor-
6
4146N–AERO–04/07
M67025E
mally used in accessing a standard static RAM. Each of the flags has a unique address accessed by
either side through address pins A0-A2. None of the other address pins has any effect when accessing
the semaphores. Only data pin D
0
is used when writing to a semaphore. If a low level is written to an
unused semaphore location, the flag will be set to zero on that side and to one on the other side (see
Table 5). The semaphore can now only be modified by the side showing the zero. Once a one is written
to this location from the same side, the flag will be set to one for both sides (unless a request is pending
from the other side) and the semaphore can then be written to by either side.
The effect the side writing a zero to a semaphore location has of locking out the other side is the
reason for the use of semaphore logic in interprocessor communication. (A thorough discussion
of the use of this feature follows below). A zero written to the semaphore location from the
locked-out side will be stored in the semaphore request latch for that side until the semaphore is
relinquished by the side having control. When a semaphore flag is read its value is distributed to
all data bits so that a flag set at one reads as one in all data bits and a flag set at zero reads as
all zeros. The read value is latched into the output register of one side when its semaphore
select (SEM) and output enable (OE)
signals
go active. This prevents the semaphore changing state in
the middle of a read cycle as a result of a write issued by the other side. Because of this latch, a repeated
read of a semaphore flag in a test loop must cause either signal (SEM or OE) to go inactive, otherwise
the output will never change.
The semaphore must use a WRITE/READ sequence in order to ensure that no system level
conflict will occur. A processor requests access to shared resources by attempting to write a
zero to a semaphore location. If the semaphore is already in use, the semaphore request latch
will contain a zero, yet the semaphore flag will appear as a one, and the processor will detect
this status in the subsequent read (see Table 5). For example, assume a processor writes a zero
to the left port at a free semaphore location. On a subsequent read, the processor will verify that
it has written successfully to that location and will assume control over the resource concerned.
If a processor on the right side then attempts to write a zero to the same semaphore flag it will
fail, as will be verified by a subsequent read returning a one from the semaphore location on the
right side has a READ/WRITE sequence been used instead, system conflict problems could
have occurred during the interval between the read and write cycles.
It must be noted that a failed semaphore request needs to be followed by either repeated reads
or by writing a one to the same location. The simple logic diagram for the semaphore flag in Fig-
ure 2 illustrates the reason for this quite clearly. Two semaphore request latches feed into a
semaphore flag. The first latch to send a zero to the semaphore flag will force its side of the
semaphore flag low and other side high. This status will be maintained until a one is written to
the same semaphore request latch. Should a zero be written to the other side’s semaphore
request latch in the meantime, the semaphore flag will flip over to this second side as soon as a
one is written to the first side’s request latch. The second side’s flag will now stay low until its
semaphore request latch is changed to a one. Thus, clearly, if a semaphore flag is requested
and the processor requesting it no longer requires access to the resource, the entire system can
hang up until a one is written to the semaphore request latch concerned.
Semaphore timing becomes critical when both sides request the same token by attempting to
write a zero to it at the same time. Semaphore logic is specially conceived to resolve this prob-
lem. The logic ensures that only one side will receive the token if simultaneous requests are
made. The first side to make a request will receive the token where request do not arrive at the
same time. Where they do arrive at the same time, the logic will assign the token arbitrarily to
one of the ports. It should be noted, however, that semaphores alone do not guarantee that
access to a resource is secure. As with any powerful programming technique, errors can be
introduced if semaphores are misused or misinterpreted. Code integrity is of the utmost perfor-
mance when semaphores are being used instead of slower, more restrictive hardware-intensive
systems.
7
4146N–AERO–04/07
M67025E
Semaphore initialization is not automatic and must therefore be incorporated in the power up ini-
tialization procedures. Since any semaphore flag containing a zero must be reset to one,
initialization should write a one to all request flags from both sides to ensure that they will be
available when required.
Using
Semaphores –
Some Examples
Perhaps the simplest application of semaphores is their use as resource markers for the
M67025E’s dual-port RAM. If it is necessary to split the 8 Kb × 16 RAM into two 4 Kb × 16 blocks
which are to be dedicated to serving either the left or right port at any one time. Semaphore 0 can be
used to indicate which side is controlling the lower segment of memory and semaphore 1 can be defined
as indicating the upper segment of memory.
To take control of a resource, in this case the lower 4 Kb of a dual-port RAM, the left port proces-
sor would then write a zero into semaphore flag 0 and then read it back. If successful in taking
the token (reading back a zero rather than a one), the left processor could then take control of
the lower 4 Kb of RAM. If the right processor attempts to perform the same function to take con-
trol of the resource after the left processor has already done so, it will read back a one in
response to the attempted write of a zero into semaphore 0. At this point the software may
choose to attempt to gain control of the second 4 Kb segment of RAM by writing and then read-
ing a zero in semaphore 1. If successful, it will lock out the left processor.
Once the left side has completed its task it will write a one to semaphore 0 and may then attempt
to access semaphore 1. If semaphore 1 is still occupied by the right side, the left side may aban-
don its semaphore request and perform other operations until it is able to write and then read a
zero in semaphore 1. If the right processor performs the same operation with semaphore 0, this
protocol would then allow the two processes to swap
4 Kb blocks of dual-port RAM between one another.
The blocks do not have to be any particular size, and may even be of variable size depending on
the complexity of the software using the semaphore flags. All eight semaphores could be used
to divide the dual-port RAM or other shared resources into eight parts. Semaphores can even be
assigned different meanings on each side, rather than having a common meaning as is
described in the above example.
Semaphores are a useful form of arbitration in systems such as disk interfaces where the CPU
must be locked out of a segment of memory during a data transfer operation, and the I/0 device
cannot tolerate any wait states. If semaphores are used, both the CPU and the I/0 device can
access assigned memory segments, without the need for wait states, once the two devices have
determined which memory area is barred to the CPU.
Semaphores are also useful in applications where no memory WAIT state is available on one or
both sides. On a semaphore handshake has been performed, both processors can access their
assigned RAM segments at full speed.
Another application is in complex data structures. Block arbitration is very important in this case,
since one processor may be responsible for building and updating a data structure whilst the
other processor reads and interprets it. A major error condition may be created if the interpreting
processor reads an incomplete data structure. Some sort of arbitration between the two different
processors is therefore necessary. The building processor requests access to the block, locks it
and is then able to enter the block to update the data structure. Once the update is completed
the data structure may be released.
This allows the interpreting processor, to return to read the complete data structure, thus ensur-
ing a consistent data structure.
8
4146N–AERO–04/07
M67025E
Truth Table
Note: 1. A
OL
- A
12
≠ A
OR
n- A
12R
Note: 1. Inputs Signals are for Semaphore Flags set and test (Write and Read) operations.
Table 1. Non Contention Read/Write Control
Note: Inputs
(1)
Outputs
ModeCS R/W OE UB LB SEM IO
8
- IO
15
I/O
0
- I/O
7
H X X X X H Hi-Z Hi-Z Deselected: Power Down
X X X H H H Hi-Z Hi-Z Deselected: Power Down
L L X L H H DATA
IN
Hi-Z Write to Upper Byte Only
L L X H L H Hi-Z DATA
IN
Write to Lower Byte Only
L L X L L H DATA
IN
DATA
IN
Write to Both Bytes
L H L L H H DATA
OUT
Hi-Z Read Upper Byte Only
L H L H L H Hi-Z DATA
OUT
Read Lower Byte Only
L H L L L H DATA
OUT
DATA
OUT
Read Both Bytes
X X H X X X Hi-Z Hi-Z Outputs Disabled
H H L X X L DATA
OUT
DATA
OUT
Read Data in Sema. Flag
X H L H H L DATA
OUT
DATA
OUT
Read Data in Sema. Flag
H X X X L DATA
IN
DATA
IN
Write D
IN0
into Sema. Flag
X X H H L DATA
IN
DATA
IN
Write D
IN0
into Sema. Flag
L X X L X L – – Not Allowed
L X X X L L – – Not Allowed
Table 2. Arbitration Options
Options
Inputs Outputs
CS UB LB M/S SEM BUSY INT
Busy Logic Master
L X L H H Output –
L L X H H Signal
Busy Logic Slave
L X L L H Input –
L L X L H Signal –
Interrupt Logic
L X L X H – Output
L L X X H Signal
Semaphore Logic
(1)
H X X H L H –
H X X L L Hi-Z
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4146N–AERO–04/07
M67025E
Notes: 1. Assumes BUSY
L
= BUSY
R
= H.
2. If BUSY
L
= L, then NC.
3. If BUSY
R
= L, then NC.
4. H = HIGH, L = LOW, X = DON’T CARE, NC = NO CHANGE.
Notes: 1. INT Flags Don’t Care.
2. X = DON’T CARE, L = LOW, H = HIGH.
LV5R = Left Address Valid ≥ 5 ns before right address.
RV5L = Right Address Valid ≥ 5 ns before left address
Same = Left and Right Addresses match within 5 ns of each other.
LL5R = Left CS = LOW ≥ 5 ns before Right CS.
RL5L = Right CS = LOW ≥ 5 ns before left CS.
LW5R = Left and Right CS = LOW within 5 ns of each other.
Table 3. Interrupt Flag
(1) (4)
Left Port Right Port
FunctionR/W
L
CS
L
OE
L
A
OL
-A
12L
INT
L
R/W
R
CS
R
OE
R
A
OR
-A
12R
INT
R
L L X 1FFF X X X X X L
(2)
Set Right INT
R
Flag
X X X X X X L L 1FFF H
(3)
Reset Right INT
R
Flag
X X X X L
(3)
L L X 1FFE X Set Left INT
L
Flag
X L L 1FFE H
(2)
X X X X X Reset Left INT
L
Flag
Table 4. Arbitration
(2)
Left Port Right Port Flags
(1)
FunctionCS
L
A
0L
– A
12L
CS
R
A
0R
– A
12R
BUSY
L
BUSY
R
H X H X H H No Contention
L Any H X H H No Contention
H X L Any H H No Contention
L≠ A
0R
– A
12R
L≠ A
0L
– A
12L
H H No Contention
Address Arbitration With CS Low Before Address Match
L LV5R L LV5R H L L-Port Wins
L RV5L L RV5L L H R-Port Wins
L Same L Same H L Arbitration Resolved
L Same L Same L H Arbitration Resolved
CS Arbitration With Address Match Before CS
LL5R = A
0R
– A
12R
LL5R = A
0L
– A
12L
H L L-Port Wins
RL5L = A
0R
– A
12R
RL5L = A
0L – A12L
L H R-Port Wins
LW5R = A
0R – A12R
LW5R = A
0L
– A
12L
H L Arbitration Resolved
LW5R = A
0R
– A
12R
LW5R = A
0L
– A
12L
L H Arbitration Resolved
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4146N–AERO–04/07
M67025E
Note: 1. This table denotes a sequence of events for only one of the 8 semaphores on the M67025E.
Figure 1. Semaphore Logic
Table 5. Example Semaphore Procurement Sequence
Function D
0
- D
15
Left D
0
- D
15
Right Status
No Action 1 1 Semaphore free
Left Port Writes ’0’ to Semaphore 0 1 Left Port has semaphore token
Right Port Writes ’0’ to Semaphore 0 1 No change. Right side has no write
access to semaphore
Left Port Writes ’1’ to Semaphore 1 0 Right port obtains semaphore token
Left Port Writes ’0’ to Semaphore 1 0 No change. Left port has no write
access to semaphore
Right Port Writes ’1’ to Semaphore 0 1 Left port obtains semaphore token
Left Port Writes ’1’ to Semaphore 1 1 Semaphore free
Right Port Writes ’0’ to Semaphore 1 0 Right port has semaphore token
Right Port Writes ’1’ to Semaphore 1 1 Semaphore free
Left Port Writes ’0’ to Semaphore 0 1 Left Port has semaphore token
Left Port Writes ’1’ to Semaphore 1 1 Semaphore free
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4146N–AERO–04/07
M67025E
Electrical Characteristics
Absolute Maximum Ratings
DC Parameters
Notes: 1. CS
L
= CS
R
> 2.2V.
2. CS
L
= CS
R
> VCC - 0.2V.
3. Both ports active - Maximum frequency - Outputs open - OE = VIH.
4. One port active (f = fMAX) - Output open - One port stand-by TTL or CMOS Level Inputs - CS
L
= CS
R
= VIH
Supply voltage (VCC-GND): ............................... -0.5V to 7.0V
Input or output voltage applied: (GND - 0.5V) to (VCC + 0.5V)
Storage temperature:..................................... -65°C to +150°C
*NOTE:
Stresses greater than those listed under Absolute Max-
imum Ratings may cause permanent damage to the
device.This is a stress rating only and functional opera-
tion of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
Table 6. DC Test Conditions
TA = -55°C to + 125°C; Vss = 0V; Vcc = 4.5V to 5.5V
Parameter Description 67025-30 67025-45 Unit Value
I
CCSB(1)
Standby supply current (Both ports TTL level inputs) 10 10 mA Max
I
CCSB1(2)
Standby supply current (Both ports CMOS level
inputs) 500 500 µA Max
I
CCOP(3)
Operating supply current (Both ports active) 320 260 mA Max
I
CCOP1(4)
Operating supply current (One port active - One
port standby) 200 180 mA Max
Parameter Description 67025E Unit Value
IL I/O
(1)
1. Vcc = 5.5V, Vin = Gnd to Vcc, CS = VIH, Vout = 0 to Vcc.
Input/Output leakage current ± 5 µA Max
VIL
(2)
2. VIH max = Vcc + 0.5V, VIL min = -0.5V or -1V pulse width 50 ns.
Input low voltage 0.8 V Max
VIH
(2)
Input high voltage 2.2 V Min.
VOL
(3)
3. Vcc Min., IOL = 4 mA, IOH = -4 mA.
Output low voltage (I/O
0
- I/O
15
) 0.4 V Max
VOH
(3)
Output high voltage 2.4 V Min.
C IN Input capacitance 5 pF Max
C OUT Output capacitance 7 pF Max
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4146N–AERO–04/07
M67025E
Data-retention
Mode
Atmel CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply
current are guaranteed over temperature. The following rules ensure data retention:
1. Chip select (CS
L
, CS
R
) must be held high during data retention; within VCC to VCC -
0.2V.
2. CS
L
, CS
R
must be kept between VCC - 0.2V and 70% of VCC during the power up and
power down transitions.
3. The RAM can begin operation > tRC after VCC reaches the minimum operating voltage
(4.5 volts).
Timing
Parameter Description Minimum Maximum Unit
VDR Data Retention
Voltage 2.0 – V
T
CDR
Chip deselect to
data retention time 0 – ns
T
R
Operation recovery
time TAVAV
(1)
1. TAVAV = Read cycle time.
– ns
ICCDR1
(2)
2. V
IN
(CS
L/R
) = Vcc
Vcc = 2V
V
IL
= 0V
V
IH
= Vcc
Data retention
current – 400 µA
13
4146N–AERO–04/07
M67025E
AC Parameters
AC Test Conditions
Note: 1. Including scope and jig.
AC Read Characteristics
Notes: 1. Transition is measured +500 mV from low or high impedance voltage with load (Figure 2 and Figure 3).
2. This parameter is guaranteed but not tested.
3. To access RAM CS = VIL, UB or LB = VIL, SEM = VIH. To access semaphore CS = VIH, SEM = VIL. Refer to Table 1.
4. STD symbol.
5. ALT symbol.
Input Pulse Levels: GND to 3.0V Output Reference Levels: 1.5V
Input Rise/Fall Times: 5 ns Output Load: See Figures 2, 3
Input Timing Reference Levels: 1.5V
Table 7. Over the Full Operating Temperature and Supply Voltage Range
Read Cycle
Parameter
M
67025-30
M
67025-45
UnitSymbol
(4)
Symbol
(5)
Min. Max. Min. Max.
TAVAVR t
RC
Read cycle time 30 – 45 – ns
TAVQV t
AA
Address access time – 30 – 45 ns
TELQV t
ACS
Chip Select access time
(3)
– 30 – 45 ns
TBLQV t
ABE
Byte enable access time
(3)
– 30 – 45 ns
TGLQV t
AOE
Output enable access time – 15 – 25 ns
TAVQX t
OH
Output hold from address change 3 – 3 – ns
TELQX t
LZ
Output low Z time
(1) (2)
3 – 5 – ns
TEHQZ t
HZ
Output high Z time
(1) (2)
– 15 – 20 ns
TPU t
PU
Chip Select to power up time
(2)
0 – 0 – ns
TPD t
PD
Chip disable to power down time
(2)
– 50 – 50 ns
TSOP t
SOP
SEM flag update pulse (OE or SEM) 15 – 15 – ns
TSLQV t
ACS
Semaphore Access time
(3)
– 30 – 45 ns
Figure 2. Output Load Figure 3. Output Load (for t
HZ
, t
LZ
, t
WZ
, and t
OW
)
1
1
(1)
(1)
14
4146N–AERO–04/07
M67025E
Timing Waveform of Read Cycle number 1, Either Side
(1) (2)(4)
Timing Waveform of Read Cycle number 2, Either Side
(1) (3) (4) (5)
Timing Waveform of Read Cycle number 3, Either Side
(1)(3)(4)(5)
1. R/W is high for read cycles.
2. Device is continuously enabled, CS=V
IL
, UB or LB V
IL
. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition low.
4. OE = V
IL
5. To access RAM, CS=V
IL
, UB or LB = V
IL
, SEM = V
IH
. To access semaphore, CS = V
IH
, SEM = V
IL
. Refer to Table 1.
O
15
4146N–AERO–04/07
M67025E
AC Write Characteristics
Table 8. AC Electrical Characteristics
Over the Full Operating Temperature and Supply Voltage Range
Write Cycle
Parameter
M
67025-30
M
67025-45 Unit
Symbol
(1)
Symbol
(2)
Min. Max. Min. Max.
TAVAVW t
WC
Write cycle time 30 – 45 – ns
TELWH t
SW
Chip select to end of write
(3)
25 – 40 – ns
TAVWH t
AW
Address valid to end of write 25 – 40 – ns
TAVWL t
AS
Address Set-up Time 0 – 0 – ns
TWLWH t
WP
Write Pulse Width 25 – 35 – ns
TWHAX t
WR
Write Recovery Time 0 – 0 – ns
TDVWH t
DW
Data Valid to end of write 20 – 25 – ns
TGHQZ t
HZ
Output high Z time
(4)
(5)
– 15 – 20 ns
TWHDX t
DH
Data hold time
(6)
0 – 0 – ns
TWLQZ t
WZ
Write enable to output in high Z
(4)
(5)
– 15 – 20 ns
TWHQX t
OW
Output active from end of write
(4) (5) (6)
0 – 0 – ns
TSWRD t
SWRD
SEM flag write to read time 10 – 10 – ns
TSPS t
SPS
SEM flag contention window 10 – 10 – ns
1. STD symbol.
2. ALT symbol.
3. To access RAM CS = V
IL
, UB or LB = V
IL
, SEM = V
IH
. To access semaphore CS = V
IH
, SEM = V
IL
. This condition must be valid
for entire t
SW
time.
4. Transition is measured ± 500 mV from low or high impedance voltage with load (Figure 2 and Figure 3).
5. The parameters is guaranteed but not tested.
6. The specification fot t
DH
must be met by the device supplying write data to the RAM under all operating conditions. Although t
DH
and t
OW
values will vary over voltage and temperature, the actual t
DH
will always be smaller than the actual t
OW
.
16
4146N–AERO–04/07
M67025E
Timing Waveform of Write Cycle number 1, R/W Controlled Timing
(1) (3) (5) (8)
Timing Waveform of Write Cycle number 2, CS Controlled Timing
(1) (3) (5) (8)
Notes: 1. R/WC or CS must be high during all address transitions.
2. A write occurs during the overlap (t
SW
or t
WP
) of a low CS or SEM and a low R/W.
3. t
WR
is measured from the earlier of CS or R/W (or SEM or R/W) going high to the end of write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CS or SEM low transition occurs simultaneously with or after the R/W low transition, the outputs remain in the high
impedance state.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signla is de-assertted first.
8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O
drivers to turn off and data to be placed on the bus for the required t
DW
. If OE is high during an R/W controlled write cycle,
this requirement does not apply and the write pulse can be as short as the specified t
WP
.
t
WC
t
HZ
t
AW
t
AS
(6)
t
WP
(2)
t
WR
(7)
t
WZ
t
OW
t
DW
t
DH
t
WC
t
AW
t
AS
(6)
t
SW
(2)
t
WR
(7)
t
DW
t
DH
17
4146N–AERO–04/07
M67025E
AC Busy
Characteristics
Table 9. AC Electrical Characteristics
Over the Full Operating Temperature and Supply Voltage Range
Write Cycle Parameter
M
67025-30
M
67025-45
UnitMin. Max. Min. Max.
Busy Timing (For Master 67025 only)
t
BAA
BUSY Access time from
address matched – 30 – 35 ns
t
BDA
BUSY Disable time from
address not matched – 25 – 30 ns
t
BAC
BUSY Access time
to Chip Select – 25 – 30 ns
t
BDC
BUSY Disable time
to Chip Select – 20 – 25 ns
t
WDD
Write Pulse to data Delay
(1)
– 55 – 70 ns
t
DDD
Write data valid to read data delay
(1)
– 40 – 55 ns
t
APS
Arbitration priority set-up time
(2)
5 – 5 – ns
t
BDD
BUSY disable to valid data –
(3)
–
(3)
ns
t
WB
Write to BUSY input
(4)
0 – 0 – ns
t
WH
Write hold after BUSY
(5)
20 – 25 – ns
t
WDD
Write pulse to data delay
(6)
– 55 – 70 ns
t
DDD
Write data valid to read data delay
(6)
– 40 – 55 ns
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Read with BUSY (For Mas-
ter 67025 only)’.
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
- t
WP
(actual) to t
DDD
- t
DW
(actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveforms of Read with Port-to-port
delay (For Slave, 67025 only)’.
18
4146N–AERO–04/07
M67025E
Timing Waveform of Read with BUSY
(2) (3) (4)
(For Master 67025)
Notes: 1. To ensure that the earlier of the two port wins.
2. Write cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enabled for both ports.
4. OE = L for the reading port.
Timing Waveform of Write with Port-to-Port
(1) (2) (3)
(For Slave 67025 Only)
Notes: 1. Assume BUSY = H for the writing port, and OE = L for the reading port.
2. Write cycle parameters should be adhered to, to ensure proper writing.
3. Device is continuously enabled for both ports.
19
4146N–AERO–04/07
M67025E
Timing Waveform of Write with BUSY (For Slave 67025)
Timing Waveform of Contention Cycle number 1, CS Arbitration (For Master 67025 only)
Timing Waveform of Contention Cycle number 2, Address Valid Arbitration (For Master 67025 only)
(1)
Left Address Valid First:
20
4146N–AERO–04/07
M67025E
Right Address Valid First:
Note: 1. CS
L
= CS
R
= V
IL
21
4146N–AERO–04/07
M67025E
AC Interrupt Characteristics
Waveform of Interrupt Timing
(1)
Notes: 1. All timing is the same for left and right ports. Port “A’ may be either the left or right port. Port “B’ is the port opposite from “A’.
2. See interrupt truth table.
3. Timing depends on which enable signal is asserted last.
4. Timing depends on which enable signal is de-asserted first.
Interrupt
Timing
Parameter
67025-30 67025-45
UnitSymbol Min. Max. Min. Max.
t
AS
Address set-up time 0 – 0 – ns
t
WR
Write recovery time 0 – 0 – ns
t
INS
Interrupt set time – 25 – 35 ns
t
INR
Interrupt reset time – 25 – 35 ns
22
4146N–AERO–04/07
M67025E
32-bit Master/Slave Dual-port Memory Systems
Note: 1. No arbitration in M67025E (SLAVE). BUSY-IN inhibits write in M67025E SLAVE.
Timing Waveform of Semaphore Read after Write Timing, Either Side
(1)
Note: 1. CS = V
IH
for the duration of the above timing (both write and read cycle).
23
4146N–AERO–04/07
M67025E
Timing Waveform of Semaphore Contention
(1) (3) (4)
Notes: 1. D
OR
= D
OL
V
IL
, CS
R
= CS
L
= V
IH
, semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. Either side “A’ = left and side “B’ = right, or side “A’ = right and side “B’ = left.
3. This parameter is measured from the point where R/W
A
or SEM
A
goes high until R/W
B
or SEM
B
goes high.
4. IF t
SPS
is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain
the flag.
24
4146N–AERO–04/07
M67025E
Ordering
Information
Note: 1. Contact Atmel for availability.
Part Number
Temperature
Range Speed Package Quality Flow
MMK2-67025EV-30-E 25°C 30 ns MQFPF84 Engineering Samples
930105001 -55 to +125°C 30 ns MQFPF84 ESCC
930105002 -55 to +125°C 45 ns MQFPF84 ESCC
5962-9161709QZC -55 to +125°C 30 ns MQFPF84 QML Q
5962-9161706QZC -55 to +125°C 45 ns MQFPF84 QML Q
5962-9161709VZC -55 to +125°C 30 ns MQFPF84 QML V
5962-9161706VZC -55 to +125°C 45 ns MQFPF84 QML V
MM0-67025EV-30-E
(1)
25°C 30 ns Die Engineering Samples
5962-9161709V9A
(1)
-55 to +125°C 30 ns Die QML V
25
4146N–AERO–04/07
M67025E
Package Drawings
84 lead MQFPF (1.15 inch square)
Printed on recycled paper.
4146N–AERO–04/07
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