INTE ORATED CIRCUITS INTEGRATED CIRCUITS DATA Slrlleler 74LV595 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) Product specification 1998 Apr 20 IC24 Data Handbook Philips SemiconductorsPhilips Semiconductors 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) FEATURES Optimized for Low Voltage applications: 1.0V to 3.6V Accepts TTL input levels between Voc = 2.7V and Voc = 3.6V @ Typical Vo,_p (output ground bounce) < 0.8V at Vcc = 3.3V, Tamb = 25C Typical Voyy (output Vox undershoot) > 2V at Voc = 3.3V, Tamb = 25C @ 8-bit serial input 8-bit serial or parallel output Storage register with 3-State outputs Shift register with direct clear Output capability: parallel outputs; bus driver ~ serial output; standard loc category: MSI Product specification 74LV595 APPLICATIONS Serial-to-paraflel data conversion Remote control holding register DESCRIPTION The 74LV595 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT595. The74LV595 is an 8-stage serial shift register with a storage register and 3-State outputs. The shift register and storage register have separate clocks. Data is shifted on the positive-going transitions of the SHp input. The data in each register is transferred to the storage register on a positive-going transition of the STcp input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (Ds) and a serial standard output (Q;) all for cascading. It is also provided with asynchronous reset {active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-State bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. QUICK REFERENCE DATA GND = OV; Tamp = 25C; t, = = 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay CL = 15pF SHep to Q7 = 3.3V 16 teHufteLy ST, cr to Oo ve 16 ns to Q7 14 fax Maximum clock frequency SHop, STcp 77 MHz C; Input capacitance 3.5 pF Crp Power dissipation capacitance per gate Nog ey 2 115 pF NOTES: . Cpp is used to determine the dynamic Power dissipation (Pp in pW) Pp = Cpp X Voo* xf +5 (CL X Voc* x fo) where: {| = input frequency in MHz; C, = output load capacitance in pF; fp = output frequency in MHz; Vcc = supply voltage in V; 5 (Cy X Veco? x fy) = sum of the outputs. 2. The condition is Vj = GND to Voc. ORDERING AND PACKAGE INFORMATION PACKAGES TEMPERATURE RANGE | OUTSIDE NORTH AMERICA | NORTH AMERICA PKG. DWG. # 16-Pin Plastic DIL 40C to +125C 7T4LV595 N 74LV595 N SOT38-4 16-Pin Plastic SO 40C to +125C 74LV595 D 74LV595 D SOT109-1 16-Pin Plastic SSOP Type It 40C to +425C 74LV595 DB 74LV595 DB SOT338-1 16-Pin Plastic TSSOP Type | 40C to +126C 74LV595 PW 74LV595PW DH SOT403-1 1998 Apr 20 2 853-1987 19255Philips Semiconductors . . Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 74LV595 PIN DESCRIPTION PIN CONFIGURATION PIN |SYMBOL FUNCTION NUMBER 15, 1, 2,3, 45.6.7 Qo to Q7 | Parallel data output a, [7 L/S 8] Voc 8 GND =] Ground (0V) Qe [2 HS] Qo 9 Q, | Serial data output Os [3] 14] Ds 10 MR | Master reset (active LOW) Os [4] 13] OF 11 SHcp _ | Shift register clock input 2s [5 2] Stor - Qe (8] 3] SHop 12 STop Storage register clock input oF Fa) a, [7 7 13 OE Output enable input (active LOW) oxo [6 rs} a 14 Ds Serial data input 16 Vec Positive supply voltage Sv00720 FUNCTION TABLE INPUTS OUTPUTS FUN N SHep | STcp BE MR Ds Qy Qn x xX L L Xx L NC A LOW level on MR only affects the shift registers x t L L xX L L Empty shift register loaded into storage register x x H L x L Shift register clear. Parallel outputs in high-impedance OFF-states Logic high level shifted into shift register stage 0. Contents of all shift ' Xx L H H Qs NC register stages shifted through, .g. previous state of stage 6 (intemal Qe) appears on the serial output (G7) x ' L H x NC Qa, Contents of shift register stages (internal Qn) are transferred to the n storage register and parallel output stages Contents of shift register shifted through. Previous contents of the shift ' L H x Qe Oy register are transferred to the storage register and the parallel output stages H = HIGH voltage level L = LOW voltage level X =Don'tcare Z = High impedance OFF-state NC= No change * = LOW-to-HIGH clock transition 4 =HIGH-to-LOW transition 1998 Apr 20 3Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register 7ALV595 with output latches (3-State) LOGIC SYMBOL FUNCTIONAL DIAGRAM 1" 2 StHicp STop Ds a, Ls 14 1 SHce 8-STAGE SHIFT Q@ P 15 _ REGISTER 10 |___-q Q, -1 Q7 9 Q Le2 Stop &-BIT STORAGE 14 | Ds QO, -3 i REGISTER G_ -4 Q,. p-5 a [6 139 | 4 3-STATE OUTPUTS Q, -7 Qo FQ; [Qe | Og [Qe | Q5 [Qs | OQ, WR OE 15 1 2 a 4 5 6 7 10 13 sveore9 svoo725 LOGIC SYMBOL (IEEE/EC) SV00724 1998 Apr 20 4Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register 7A4LV595 with output latches (3-State) LOGIC DIAGRAM STAGE 0 STAGES 1106 STAGE 7 os +> Da D Q Da f>+- or FFO FF7 cp cP Ls Le SHep +> anne URmnmnan Samm AEE iiieeinndiinetnetneeiad eee wa +f>o}+_ + ++ - - ------------- L bd a L Da roel | uscul | cP cp Stop +> | Tot em te I vE +o ptt - errr cere ee Ly Qo Q, Qa Qs OQ, Qs Q; svoo72i TIMING DIAGRAM se TULL Ds Td T 1 | || Ii 1 Tn DE ee LT} bee p-__ oI Ti Te. oo | co | ee | ry Fy : | ea LL vo] _ SV00726 1998 Apr 20 Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register FALV595 with output latches (3-State) RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT Veco DC supply voltage See Note1 1.0 3.3 3.6 v Vi input voltage 0 - Voc Vv Vo Output voltage 0 - Voc V Tamb Operating ambient temperature range in free See DC and AC ~40 +85 C air characteristics ~40 +125 Vec = 1.0V to 2.0V ~ - 500 ty, Input rise and fall times Voc =2.0V to 2.7V - ~ 200 nsi Veco = 2.7V to 3.6V ~ - 100 NOTE: 1. The LV is guaranteed to function down to Voc = 1.0V (input levels GND or Vcc); DC characteristics are guaranteed from Voc = 1.2V to Vor =3.6V. ABSOLUTE MAXIMUM RATINGS! 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = OV) SYMBOL PARAMETER CONDITIONS RATING UNIT Vee DC supply voitage 6.5 to +4.6 Vv the DC input diode current Vi, <-0.5 of Vi > Voc + 6.5V 20 mA Hox DC output diode current Vo < -0.5 OF Vg > Vee + 0.5V 50 mA DC output source or sink current tlo ~ standard outputs ~0.5V < Vo < Vec + 0.5V 25 mA ~ bus driver outputs 35 DC Voc or GND current for types with tlenp> standard outputs 50 mA tlee bus driver outputs 70 Tstg Storage temperature range -5 to +150 C Power dissipation per package | for tamiperature range: -40 to +125C P. ~plastic DIL | above +70C derate linearly with 12mW/K 750 mW TOT | -plastic mini-pack (SO) above +70C derate linearly with. 8 mW/K 500 ~plastic shrink mini-pack (SSOP and TSSOP) above +60C derate linearly with 5.5 mW/K 400 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = OV) LIMITS SYMBOL PARAMETER TEST CONDITIONS ~40C to +85C 40C to +125C UNIT MIN TYP! MAX MIN MAX Voc = 1.2V 0.9 0.9 Vin volage Input Wee =2.0V 4 14 Vv Veo =27 to 3.6V 2.0 2.0 Veo = 1.2 0.3 03 Viv voltage Input Woo = 2.0V 06 06 Vv Voc = 2.7 to 3.6V 0.8 0.8 Voc =.1.2V; Vi = Vin or Vit: lo = 100pA 1.2 Vv HIGH level output | Voc = 2.0V; Vi = Viy oF Vie. lo = 100pA 1.8 2.0 1.8 Vv OH | voltage; all outputs [Vg =2.7V; Vj = Viq oF Vi_. ip = 100HA 2.5 2.7 2.5 Veo = 3.0V; Vj = Vin oF Vi, lo = 100pA 28 3.0 28 HIGH ievel output voltage; . Aye = 2 Vv Von | STANDARD Vec = 3.0V:V; = Vig oF Vy lo = 6MA 240 | 2.82 2.20 outputs 4998 Apr 20Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register 741.595 with output latches (3-State) DC CHARACTERISTICS (Continued) Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS ' -40C to +85C -40C to +125C UNIT HIGH level output Vou voltage; BUS driver | Voc = 3.0V;V) = Vin OF Vip- lo = 8A 2.40 2.82 2.20 Vv outputs Veco = 1.2V; Vy = Vin or Vip: to = 100nA 0 Vv LOW level output Voc = 2.0V; Vi = Vin or Vit; lo = 100RA 0 0.2 0.2 OL . Vv voltage; all outputs. [Veo = 2.7V; V; = Viz or Vic. io = TOOpA 0 0.2 0.2 Voc = 3.0V;V; = Vin or Viz. lp = 100pA 0 0.2 0.2 LOW level output voltage; . Vo. | STANDARD Voc = 3.0V;\y = Vin oF Vit: lo = 6MA 0.25 0.40 0.50 v outputs LOW level output Vor voltage; BUS driver | Voc = 3.0V;V; = Vin Or Vit lo = 8MA 0.20 0.40 0.50 Vv outputs | nputleakage Voc = 3.6V; Vj = Voc or GND 1.0 1.0 pA 3-State output Voc = 3.6V; Vi = Vin or Vin. loz | OF F-state current | Vo = Voc or GND 5 10 pA lec calescont guppy Voc = 3.6V; Vi = Vec or GND; Io = 0 20.0 160 | pA Additional Alec quiescent supply Voc = 2.7V to 3.6V; Vi = Voc -0.8V 500 850 pA current per input NOTE: 1. All typical values are measured at Tamp = 25C. AC CHARACTERISTICS GND = OV; t, = & < 2.5ns; C, = 50pF; Ry = 1KQ SYMBOL teHuteLy 'PHLAPLH 1998 Apr 20 PARAMETER Propagation delay SHep to Q7 Propagation delay STep to Q, Propagation delay MR to Q7' 3-State output enable time OE to Q, 3-State output disable time OE to Q, CONDITION WAVEFORM Figure 1 Figure 2 Figure 5 Figure 3 ~40 to +425 C LIMITS UNITPhilips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 74LV595 AC CHARACTERISTICS (Continued) GND = OV; t, = << 2.5ns; C, = 50pF; Ry = 1KQ CONDITION SYMBOL | PARAMETER WAVEFORM ~40 to +85 C -40 to +125C | unr Shift clock pulse width HIGH or Low | Figure 1 Storage clock pulse , width HIGH or Low | Figure 2 Master reset pulse width LOW Figure 5 Set-up time Ds to SHcp Figure 4 Set-up time SHcp to STop Figure 2 Hold time Dg to SHep Figure 4 Removal time MR to SHcp Maximum clock fax pulse frequency Figure 1,2 SHep or STop NOTES: 1. Uniess otherwise stated, all typical values are at Tamp = 25C. 2. Typical value measured at Voc = 3.3V. 1998 Apr 20 8Philips Semiconductors . Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 74LVS95 AC WAVEFORMS Vue = 1.5V at Voc 2 2.7V Vm = 0.5 * Voc at Veg < 2.7V Mone Voy, and Voy are the typical output voltage drop that occur with the OE INPUT output load. Vx = VoL + 0.3V at Veco 2 2.7V GND Vx = Vor + 0.1Vec at Vor < 2.7V Vy = Vou 0.3V at Veco = 2.7V Voc Vy = Vou - 0.1Vec at Voc < 2.7V ose OFF-to-LOW Vo Vrocce / Vou CP INPUT Ve . OUTPUT ] HIGH-t0-OFF OFF-to-HIGH VM GND GND -------- outputs. > outputs enabled enabled Vor Q, OUTPUT svoo3sa Vou Figure 3. 3-State enable and disable times for input OE. SV00718 Figure 1. Clock (SHcp) te output (Q)), propagation delays, the shift clock pulse width and the maximum shift clock frequency. Vy SHcp INPUT Vers SHcp INPUT GND VI STop INPUT GND Vou Q, OUTPUT 800722 Figure 4. Data set-up and hold times for the data input (Ds). Vor Svoq727 Figure 2. Storage clock (ST cp) to output (Q,) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time. 1998 Apr 20 9Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 74LV595 AC WAVEFORMS (Continued) TEST CIRCUIT Vu = 1.5V at Vcc 2.2.7V Vu = 0.5 * Veco at Voc < 2.7V Vor and Vox are the typical output voltage drop that occur with the output load. Vy = Voy + 0.3V at Veco 2 2.7V Vx = Voi + 0.1Vec at Veco < 2.7V I Vy = Von - 0.3V at Voc = 2.7V PULSE Vy = VoH- 0-1Vco at Voc < 2.7V GENERATOR Rr Test Circuit for switching times vi DEFINITIONS Ri, = Load resistor GC, = Load capacitance includes jig and probe capacitance Ry = Termination rasistance should be equal to Zour of pulse generators. MF INPUT GND - - SWITCH POSITION Vie- dee eee eee TEST Sy Vec vi SHcp INPUT teuvter. Open <2.7V Veo t . end PLZAPZL 2+ Voc 2.7-3.6V 2N Vou tprztezy GND SV0G895 Figure 6. Load circuitry for switching times. Qy' OUTPUT SV00728 Figure 5. Master reset (MR) puise width, the master reset to output (Q7-) propagation delay and the master reset to shift clock (SHcp) removal time. 1998 Apr 20 10Philips Semiconductors 8-bit serial-in/serial or parallel-out shift register Product specification with output latches (3-State) DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 2 5 a 2 3 3 i i | | . 1 1 8 0 5 10mm Nenana dopant etaneeel scale DIMENSIONS (inch dimensions are derived trom the original mm dimensions) A A A : () UNIT | ee | min. | max | | | be | | OM] eM) e |e, | b | Me | My | wf Ze 1.73 | 053 | 1.25 | 0.36 | 19.50 | 6.48 3.60 | 8.25 | 10.0 mm | 42 | 051 | 32 | i369 | 0.38 | 085 | 0.23 | 1855 | 620 | 254 | 762 | 305 | 7e0 | 23 | 9254] 0-76 ; 0.068 | 0.021 | 0.049 | 0.014 | 0.77 | 0.26 0.14 |-0392 | 0.39 inches | 0.17 | 0.020 | 0.13 | 9551 | 0.015 | 0.033 | 0.009 | 073 | 0.24 | 1 | 930 | 42 | a1 | oa | 0-01 | 9-090 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION lec JEDEC EIAJ PROJECTION SHE SOT38-4 =} 95-01-14 1998 Apr 20 "1Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register 7ALV595 with output latches (3-State) $016: plastic small outline package; 16 leads; body width 3.9 mm $OT109-1 Ly THEA G pin 1 index | | He HH HH $ 6 PeCSEIC) dai bp 0 2.5 5mm bn Eel hieebipnbnsenZaientet scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT | ax | At | Az | As | Bp ec | DG] eM] e He L Lp | @ w y | 2) 6 0.25 | 1.45 0.49 | 025 | 100] 40 62 19 | o7 07 mm 1 175 1 oo | 1.25 | 975] o26 | 019] 98 | sa | 2? | 5a fF] o4 | o6 | O78] 975) Ot | og | ge . 0.0098} 0.057 0.019 |0.0098|. 0:39-] 0.16 0.24 0.039 | 0.028 0.028; 9 inches | 0.0691) agsql 0.049 | 9! | o.014 0.00751 0.98 | 0.15 | ?) 0.23 141 5 o16| 0.0201 998 | O01 | 0.004) | G15 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION lec JEDEC EIAJ PROJECTION = SOT 109-1 o76E07S MS-012AC =} ereras 1998 Apr 20 12Philips Semiconductors 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm Product specification 74LV595 SOT338-1 angina P ] 4. 4.4 Oo 1 index I TEEN ix bp o 2.5 5mm Ldap inn lienieednionndenl scale DIMENSIONS (mm are the original dimensions) A UNT | a | Ar | Ae | Ao | bp | | OM] eM) e | He | LE [| a v w y | 2M] 6 6.21 | 1.80 0.38 | 020 6.4 5.4 7.9 1.03 0.9 1.00 8 mm 1 2.0 | oos | 165 | 975 | 025 | 009 | 60 | 52 | ] 76 | 175] 063 | o7 | %2 191 | 1 | oss] oe Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION 1EC JEDEC EIAJ PROJECTION 94-04-44 SOT338-1 MO-150AC E4@ 95-02-04 1998 Apr 20 13Philips Semiconductors Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 74LV595 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 <->) -______- Cy] ee ree Oo L 3| He | J > ey 4 f 47 Oo 1 we Hl _ cam) ~ 0 25 5mm re DIMENSIONS (mm are the original dimensions) UNIT rae Ar | Ao | As | bp e | pM!) EM] oe | He L Lp | @ w y | 21 6 wm | sao | 998 | 988 [ oz | 889] oF | $3 | $5 [owe | ES | 0 [928] 98 | 02 [ors | on | 299] g Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interiead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN SOT403-1 MO-183 =} 95-04-04 ISSUE DATE 1998 Apr 20 14Philips Semiconductors . Product specification 8-bit serial-in/serial or parallel-out shift register with output latches (3-State) 74LV595 NOTES 1998 Apr 20 15Philips Semiconductors - Product specification 8-bit serial-in/serial or parallel-out shift register 74.595 with output latches (3-State) DEFINITIONS Data Sheet Identification Product Status Definition Dolective Spectfieation Forthative' or i Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Preliminary Specification Preproduction Product Semiconductors reserves the right to make changes at any tima without natice in orderto improve design and supply the bast possibla product. This datasheet contains Final Specifications. Philips Semiconductors reserves the rignt to make changes Product Specification Full Production at any time without natice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained. herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liabllity for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, orsystems where matfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in.a personal injury. Philips Semiconductors. and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors Copyright Philips Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved. Printed in U.S.A. P.O. Box 3409 Sunnyvale, California 94088-3409 print code Date of release: 05-96 7 elephone 800-234-7381 Document order number: 9397-750-04455 Philips Semiconductors