19-6381; Rev 0; 6/12 EVALUATION KIT AVAILABLE MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC General Description Benefits and Features The MAX19794 dual general-purpose analog voltage variable attenuator (VVA) is designed to interface with 50I systems operating in the 10MHz to 500MHz frequency range. This device includes a patented control circuit that provides 22.4dB of attenuation range (per attenuator) with a typical linear control slope of 8dB/V. S Wide Band Coverage RF Frequency Range from 10MHz to 500MHz Both attenuators share a common analog control. They can be cascaded together to yield 44.7dB of total attenuation range with a typical combined linear control slope of 16dB/V (5V operation). Alternatively, the on-chip, 4-wire SPI-controlled 10-bit DAC can be used to control both attenuators. In addition, a step-up/down feature allows user-programmable attenuator stepping through command pulses without re-programming the SPI interface. S Integrates Two Analog Attenuators in One Monolithic Device The MAX19794 is a monolithic device designed using one of Maxim's proprietary SiGe BiCMOS processes. The part operates from a single +5V supply or alternatively operates from a single +3.3V supply. It is available in a compact 36-pin TQFN package (6mm x 6mm x 0.8mm) with an exposed pad. Electrical performance is guaranteed over the -40NC to +100NC extended temperature range. Applications Broadband System Applications, Including Wireless Infrastructure Digital and SpreadSpectrum Communication Systems WCDMA/LTE, TD-SCDMA/TD-LTE, WiMAX(R), cdma2000(R), GSM/EDGE and MMDS Base Stations S High Linearity Greater than +34.4dBm IIP3 over the Full Attenuation Range +21.8dBm Input P1dB S Two Convenient Control Options Single Analog Voltage On-Chip, SPI-Controlled 10-Bit DAC S Step-Up/Down Pulse Command Inputs S Flexible Attenuation Control Ranges 22.4dB (per Attenuator) 44.7dB (both Attenuators Cascaded) S Linear dB/V Analog Control Response Curve Simplifies Automatic Leveling Control and Gain Trim Algorithms S Excellent Attenuation Flatness over Wide Frequency Ranges and Attenuation Settings S On-Chip Comparator (for Successive Approximation Measurement of Attenuator Control Voltage) S Low 13mA Supply Current S Single +5V or 3.3V Supply Voltage S Pin Similar with MAX19791, MAX19792, and MAX19793 S Lead-Free Package VSAT/Satellite Modems Military Systems Microwave Point to Point Systems Lineup Gain Trim Temperature Compensation Circuits Automatic Level Control (ALC) Transmitter Gain Control Receiver Gain Control General Test Equipment WiMAX is a registered certification mark and regisitered service mark of WiMAX Forum. cdma2000 is a registered trademark of Telecommunications Industry Association. Ordering Information appears at end of data sheet. For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX19794.related. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC ABSOLUTE MAXIMUM RATINGS VCC........................................................................-0.3V to +5.5V REF_IN...............................-0.3V to Minimum (VCC + 0.3V, 3.6V) REF_SEL,DAC_LOGIC,MODE, DWN, UP, DIN, CLK, CS.................-0.3V to Minimum (VCC + 0.3V, 3.6V) COMP_OUT, DOUT...............................................-0.3V to +3.6V IN_A, OUT_A, IN_B, OUT_B........................ -0.3V to VCC + 0.3V CTRL (except for test mode)........................ -0.3V to VCC + 0.3V Maximum CTRL Pin Load Current (CTRL configured as an output).....................................0.3mA RF Input Power at IN_A, IN_B, OUT_A, OUT_B............ +20dBm Continuous Power Dissipation (Note 1)...............................2.8W Operating Case Temperature Range (Note 2)....-40NC to +100NC Maximum Junction Temperature........................................ 150NC Storage Temperature........................................ -65NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Note 1: Based on junction temperature TJ = TC + (BJC x VCC x ICC). This formula can be used when the temperature of the exposed pad is known while the device is soldered down to a PCB. See the Application Information section for details. The junction temperature must not exceed +150NC. Note 2: TC is the temperature on the exposed pad of the package. TA is the ambient temperature of the device and PCB. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS TQFN Junction-to-Case Thermal Resistance (qJC) (Notes 1, 4)........................................................... +10C/W Junction-to-Ambient Thermal Resistance (qJA) (Notes 3, 4)........................................................... +36C/W Note 3: Junction temperature TJ = TA + (BJA x VCC x ICC). This formula can be used when the ambient temperature of the PCB is known. The junction temperature must not exceed +150NC. Note 4: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. 3.3V DC ELECTRICAL CHARACTERISTICS (VCC = 3.15V to 3.45V, VCTRL = 1V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, no RF signals applied, all input and output ports terminated with 50I through DC blocks, TC = -40NC to +100NC, unless otherwise noted. Typical values are at VCC = 3.3V, VCTRL = 1.0V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, TC = +25NC, unless otherwise noted.) (Note 5) PARAMETER SYMBOL Supply Voltage VCC Supply Current ICC CONDITIONS MIN TYP MAX UNITS 3.15 3.3 3.45 V 9.5 14 mA Control Voltage Range VCTRL CTRL Input Resistance RCTRL 1.0 2.5 Input CurrentLogic-High IIH -1.0 +1.0 FA Input Current Logic-Low IIL -1.0 +1.0 FA 1.0 V MI REF_IN Voltage 1.4 V REF_IN Input Resistance 1.0 MI DAC Number of Bits Monotonic Input Voltage Logic-High VIH Input Voltage Logic-Low VIL 10 2.0 bits V 0.8 V COMP_OUT Logic-High RDBK_EN (D9, REG3) = Logic 1, RLOAD = 47k 3.3 V COMP_OUT Logic-Low RDBK_EN (D9, REG3) = Logic 1, RLOAD = 47k 0 V 2 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC 5V DC ELECTRICAL CHARACTERISTICS (VCC = 4.75V to 5.25V, VCTRL = 1.0V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, no RF signals applied, all input and output ports terminated with 50I through DC blocks, TC = -40NC to +100NC, unless otherwise noted. Typical values are at VCC = 5.0V, VCTRL = 1.0V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, TC = +25NC, unless otherwise noted.) (Note 5) PARAMETER SYMBOL Supply Voltage VCC Supply Current ICC Control Voltage Range VCTRL CTRL Input Resistance RCTRL CONDITIONS MIN TYP MAX 4.75 5.0 5.25 V 13 18.6 mA 4.0 V 1.0 124 Input Current Logic-High IIH -1.0 Input Current Logic-Low IIL -1.0 UNITS kI +1.0 FA +1.0 FA REF_IN Voltage Range 1.4 V REF_IN Input Resistance 1.0 MI 10 Bits DAC Number of Bits Monotonic Input Voltage Logic-High VIH Input Voltage Logic-Low VIL 2.0 0.8 RDBK_EN (D9, REG3) = Logic 1, RLOAD = COMP_OUT Logic-High 47k RDBK_EN (D9, REG3) = Logic 1, RLOAD = 47k COMP_OUT Logic-Low V V 3.3 V 0 V Recommended AC Operating Conditions PARAMETER SYMBOL CONDITIONS RF Frequency Range fRF (Note 6) RF Port Input Power PRF Continuous operation MIN 10 TYP MAX UNITS 500 MHz 15 dBm 3 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC 3.3V AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, one attenuator, VCC = 3.15V to 3.45V, RF ports are driven from 50I sources and loaded into 50I, input PRF = 0dBm, fRF = 10MHz to 500MHz, VCTRL = 1V to 2.5V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, TC = -40NC to +100NC. Typical values are for TC = +25NC, VCC = 3.3V, input PRF =0dBm, fRF = 55MHz, VCTRL = 1.0V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, unless otherwise noted.) (Notes 5, 7) PARAMETER Insertion Loss SYMBOL IL Loss Variation Over Temperature Input P1dB Minimum Input Second-Order Intercept Point Over Full Attenuation Range (Note 8) Minimum Input Third-Order Intercept Point Over Full Attenuation Range (Note 8) CONDITIONS MIN 1.5 Two attenuators, fRF = 55MHz, VCTRL = 1.0V TC = -40NC to +100NC 3.0 IP1dB IIP2 IIP3 5.0 UNITS dB dB 16.4 dBm 44.9 Two attenuators fRF1 + fRF2 term, fRF1 - fRF2 = 1MHz VCTRL = 1.0V to 2.0V PRF = 0dBm/tone applied to attenuator input 42.7 One attenuator VCTRL =1.0V to 2.5V fRF1 - fRF2 = 1MHz PRF = 0dBm/tone applied to attenuator input 30.8 Two attenuators VCTRL =1.0V to 2.0V fRF1 - fRF2 = 1MHz PRF = 0dBm/tone applied to attenuator input 29.9 dBm dBm Third Harmonic One attenuator, VCTRL = 1.0V to 2.5V, fRF = 55MHz Two attenuators, VCTRL = 1.0V to 2.5V, fRF = 55MHz MAX 0.28 One attenuator fRF1 +fRF2 term, fRF1 - fRF2 = 1MHz VCTRL = 1.0V to 2.5V PRF = 0dBm/tone applied to attenuator input Second Harmonic Attenuation Control Range TYP One attenuator 38.5 62 dBc 89.7 dBc 22.5 dB 45 dB Average Attenuation-Control Slope VCTRL = 1.4V to 2.3V 22.5 dB/V Maximum Attenuation-Control Slope VCTRL = 1.0V to 2.5V 40 dB/V S21 Attenuation Deviation from a straight line VCTRL = 1.4V to 2.1V 0.4 dB 4 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC 5V AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, one attenuator, VCC = 4.75V to 5.25V, RF ports are driven from 50I sources and loaded into 50I, input PRF = 0dBm, fRF = 10MHz to 500MHz, VCTRL = 1V to 4V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, TC = -40NC to +100NC. Typical values are for TC = +25NC, VCC = 5.0V, input PRF = 0dBm, fRF = 55MHz, VCTRL = 1.0V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, unless otherwise noted.) (Notes 5, 7) PARAMETER Insertion Loss SYMBOL IL Loss Variation Over Temperature Input P1dB Minimum Input Second-Order Intercept Point Over Full Attenuation Range (Note 8) Minimum Input Third-Order Intercept Point Over Full Attenuation Range (Note 8) CONDITIONS MIN 1.5 Two attenuators 3.0 TC = -40NC to +100NC IP1dB IIP2 IIP3 Maximum Attenuation-Control Slope Attenuation Flatness over any 125MHz band dB 5.0 dB dB dBm Two attenuators fRF1 +fRF2 term, fRF1 - fRF2 = 1MHz VCTRL = 1.0V to 4.0V PRF = 0dBm/tone applied to attenuator input 46.5 One attenuator VCTRL from 1.0V to 4.0V fRF1 - fRF2 = 1MHz PRF = 0dBm/tone applied to attenuator input 34.4 Two attenuators VCTRL from 1.0V to 4.0V fRF1 - fRF2 = 1MHz PRF = 0dBm/tone applied to attenuator input 32.3 dBm dBm Third Harmonic Average Attenuation-Control Slope UNIT 0.29 48.1 One attenuator, VCTRL = 1.0V to 4.0V, fRF = 55MHz Two attenuators VCTRL = 1.0V to 4.0V, fRF = 55MHz MAX 21.8 One attenuator fRF1 + fRF2 term, fRF1 - fRF2 = 1MHz VCTRL = 1.0V to 4.0V PRF = 0dBm/tone applied to attenuator input Second Harmonic Attenuation Control Range TYP One attenuator 38.5 63 dBc 97 dBc 22.4 dB 44.7 dB VCTRL = 1.5V to 3.1V 8.0 VCTRL = 1.5V to 3.5V 9.4 VCTRL = 1.5V to 3.5V 30 VCTRL = 1.0V to 3.1V, fRF = 10MHz to 250MHz 0.15 VCTRL = 1.0V to 3.1V, fRF = 250MHz to 500MHz 0.2 dB/V dB/V dB 5 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC 5V AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, one attenuator, VCC = 4.75V to 5.25V, RF ports are driven from 50I sources and loaded into 50I, input PRF = 0dBm, fRF = 10MHz to 500MHz, VCTRL = 1V to 4V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, TC = -40NC to +100NC. Typical values are for TC = +25NC, VCC = 5.0V, input PRF = 0dBm, fRF = 55MHz, VCTRL = 1.0V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, unless otherwise noted.) (Notes 5, 7) PARAMETER SYMBOL CONDITIONS MIN TYP CTRL Switching Time (Note 9) 15dB to 0dB range 390 0dB to 15dB range 780 CS Switching Time (Note 10) 15dB to 0dB range 700 0dB to 15dB range 2600 15dB to 0dB range (MODE 1 to 0) 700 0dB to 15dB range (MODE 0 to 1) 2600 MODE Switching Time (Note 11) MAX UNIT ns ns ns Input Return Loss 31 dB Output Return Loss 28 dB Group Delay 40 ps 25 ps Group Delay Flatness fRF = 30MHz to 88MHz Group Delay Change VCTRL = 1.0V to 4.0V -400 ps Insertion Phase Change vs. Attenuation Control VCTRL = 1.0V to 4.0V 5 deg S21 Attenuation Deviation from a Straight Line VCTRL = 1.5V to 3.1V 0.35 dB SERIAL PERIPHERAL INTERFACE (SPI) Maximum Clock Speed 20 MHz tCS (Note 12) 2 ns Data-to-Clock Hold Time tCH (Note 12) 2.5 ns CS to CLK Setup Time tEWS (Note 12) 3 ns CS Positive Pulse Width tEW (Note 12) 7 ns Clock Pulse Width tCW (Note 12) 5 ns Data-to-Clock Setup Time Note 5: Production tested at TC = +100C. All other temperatures are guaranteed by design and characterization. Note 6: Recommended functional range. Not production tested. Operation outside this range is possible, but with degraded performance of some parameters. Note 7: All limits include external component losses, connectors and PCB traces. Output measurements taken at the RF port of the typical application circuit. Note 8: fRF1 = 56MHz, fRF2 = 55MHz, PRF = 0dBm/tone applied to attenuator input. Note 9: Switching time is measured from 50% of the CTRL signal to when the RF output settles to 1dB. R3 = 0I Note 10:Switching time is measured from when CS is asserted to when the RF output settles to 1dB. Note 11:Switching time is measured from when MODE is asserted to when the RF output settles to 1dB. Note 12:Typical minimum time for proper SPI operation. 6 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (Typical Application Circuit, VCC = 5.0V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.). -10 TC = -40C 10 4.750 4.875 5.000 -10 -30 -30 -50 -50 5.250 5.125 -20 -40 -40 125 0 VCC (V) 250 375 0 500 125 ATTENUATION vs. RF FREQUENCY OVER CODE SETTINGS INPUT MATCH vs. DAC CODE C10 = C11 = 10nF -10 C10 = C11 = 10nF -10 10MHz -20 S22 (dB) S11 (dB) S21 (dB) 0 55MHz, 200MHz 10MHz -10 500 375 OUTPUT MATCH vs. DAC CODE 0 MAX19794 toc04 0 250 RF FREQUENCY (MHz) RF FREQUENCY (MHz) MAX19794 toc05 11 -20 C10 = C11 = 10nF MAX19794 toc06 12 0 S22 (dB) 13 S11 (dB) -30 -20 -30 -20 55MHz 100MHz, 200MHz -40 -40 100MHz C10 = C11 = 10nF -50 -30 0 125 250 375 -50 0 500 256 512 768 1024 256 768 1024 ATTENUATION vs. DAC CODE 0 MAX19794 toc07 C10 = C11 = 10nF -5 512 DAC CODE ATTENUATION vs. DAC CODE 0 fRF = 55MHz C10 = C11 = 10nF -5 -10 S21 (dB) -10 S21 (dB) 0 DAC CODE RF FREQUENCY (MHz) MAX19794 toc08 SUPPLY CURRENT (mA) TC = +25C C10 = C11 = 10nF MAX19794 toc02 TC = +85C 14 0 MAX19794 toc01 15 OUTPUT MATCH vs. RF FREQUENCY OVER CODE SETTINGS MAX19794 toc03 INPUT MATCH vs. RF FREQUENCY OVER CODE SETTINGS SUPPLY CURRENT vs. VCC -15 -20 -15 -20 TC = -40C, +25C, +85C 10MHz, 55MHz, 100MHz, 200MHz -25 -25 -30 -30 0 256 512 DAC CODE 768 1024 0 256 512 768 1024 DAC CODE 7 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = 5.0V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.). INPUT MATCH vs. RF FREQUENCY OVER CODE SETTINGS 0 C10 = C11 = 100pF 0 -10 C10 = C11 = 100pF -10 100MHz 10MHz -20 -40 REFERENCED TO INSERTION LOSS STATE POSITIVE PHASE = ELECTRICALLY SHORTER -30 0 256 512 -30 768 -30 -40 -50 1024 -20 -50 0 DAC CODE 125 250 375 500 0 125 RF FREQUENCY (MHz) ATTENUATION vs. RF FREQUENCY OVER CODE SETTINGS INPUT MATCH vs. DAC CODE C10 = C11 = 100pF 500MHz -10 400MHz 0 C10 = C11 = 100pF -10 500MHz -20 S22 (dB) S11 (dB) S21 (dB) -10 300MHz -30 375 500 OUTPUT MATCH vs. DAC CODE 0 MAX19794 toc12 0 250 RF FREQUENCY (MHz) 400MHz 300MHz -20 MAX19794 toc14 55MHz -10 -20 S22 (dB) 0 MAX19794 toc13 10 S11 (dB) -30 -20 200MHz -40 -40 200MHz C10 = C11 = 100pF -30 -50 0 125 250 375 500 -50 0 RF FREQUENCY (MHz) 256 512 768 1024 256 512 768 1024 DAC CODE ATTENUATION vs. DAC CODE ATTENUATION vs. DAC CODE 0 MAX19794 toc15 0 -5 fRF = 300MHz C10 = C11 = 100pF -5 -10 -15 200MHz -20 S21 (dB) -10 S21 (dB) 0 DAC CODE MAX19794 toc16 S21 PHASE CHANGE (DEG) 20 200MHz MAX19794 toc10 C10 = C11 = 10nF MAX19794 toc09 30 OUTPUT MATCH vs. RF FREQUENCY OVER CODE SETTINGS MAX19794 toc11 S21 PHASE CHANGE vs. DAC CODE -15 -20 TC = -40C, +25C, +85C 300MHz, 400MHz -25 -25 500MHz C10 = C11 = 100pF -30 -30 0 256 512 DAC CODE 768 1024 0 256 512 768 1024 DAC CODE 8 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = 5.0V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.). INPUT IP3 vs. VCNTL 0 40 35 300MHz C10 = C11 = 100pF 25 -50 256 512 768 2 INPUT IP3 vs. VCNTL 40 LSB, USB 4 4 C10 = C11 = 100pF 50 45 LSB, USB 35 1 VCNTL (V) 2 3 4 1 2 VCNTL (V) fRF = 55MHz PIN = 0dBm/ TONE 45 C10 = C11 = 10nF 45 INPUT IP3 (dBm) 50 4 INPUT IP3 vs. VCNTL 50 MAX19794 toc23 fRF = 500MHz PIN = 0dBm / TONE 3 VCNTL (V) INPUT IP3 vs. VCNTL 55 INPUT IP3 (dBm) fRF = 250MHz PIN = 0dBm/ TONE 40 30 40 3 fRF = 150MHz PIN = 0dBm/ TONE 30 3 55 INPUT IP3 (dBm) INPUT IP3 (dBm) 45 fRF = 100MHz PIN = 0dBm/ TONE 2 2 INPUT IP3 vs. VCNTL C10 = C11 = 10nF 35 LSB, USB 1 1 VCNTL (V) 50 MAX19794 toc20 40 C10 = C11 = 10nF 4 INPUT IP3 vs. VCNTL 45 35 3 VCNTL (V) DAC CODE 50 fRF = 55MHz PIN = 0dBm / TONE 30 1 1024 LSB, USB MAX19794 toc24 0 40 35 C10 = C11 = 10nF fRF = 10MHz LSB, USB PIN = 0dBm/ TONE 30 MAX19794 toc21 -25 200MHz INPUT IP3 (dBm) 45 MAX19794 toc22 INPUT IP3 (dBm) 400MHz 45 C10 = C11 = 10nF INPUT IP3 (dBm) 500MHz 25 50 MAX19794 toc18 MAX19794 toc17 S21 PHASE CHANGE (DEG) REFERENCED TO INSERTION LOSS STATE POSITIVE PHASE = ELECTRICALLY SHORTER INPUT IP3 vs. VCNTL 50 MAX19794 toc19 S21 PHASE CHANGE vs. DAC CODE 50 40 35 LSB, USB -40C, +25C, +85C, -40C, LSB, USB C10 = C11 = 100pF 35 30 1 2 3 VCNTL (V) 4 1 2 3 4 VCNTL (V) 9 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = 5.0V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = 25NC, unless otherwise noted.). 40 60 50 30 3 4 2 3 4 2 4 INPUT IP2 vs VCNTL 100 MAX19794 toc28 fRF = 150MHz PIN = 0dBm/TONE C10 = C11 = 10nF 3 VCNTL (V) 70 fRF = 250MHz PIN = 0dBm /TONE C10 = C11 = 10nF 90 INPUT IP2 (dBm) 60 80 70 60 50 50 1 2 3 4 1 2 VCNTL (V) INPUT IP2 vs VCNTL fRF = 500MHz PIN = 0dBm/TONE C10 = C11 = 100pF 80 70 60 fRF = 55MHz PIN = 0dBm /TONE C10 = C11 = 10nF 90 INPUT IP2 (dBm) 90 4 INPUT IP2 vs VCNTL 100 MAX19794 toc30 100 3 VCNTL (V) MAX19794 toc31 INPUT IP2 (dBm) 1 VCNTL (V) INPUT IP2 vs. VCNTL 80 70 50 1 VCNTL (V) 90 80 MAX19794 toc29 2 fRF = 100MHz PIN = 0dBm /TONE C10 = C11 = 10nF 60 40 1 MAX19794 toc27 fRF = 55MHz PIN = 0dBm /TONE C10 = C11 = 10nF 70 INPUT IP2 (dBm) 50 INPUT IP2 (dBm) INPUT IP2 (dBm) 60 INPUT IP2 vs. VCNTL 90 INPUT IP2 (dBm) C10 = C11 = 10nF MAX19794 toc25 fRF = 10MHz PIN = 0dBm/ TONE INPUT IP2 vs. VCNTL 80 MAX19794 toc26 INPUT IP2 vs. VCNTL 70 80 -40C, +25C, +85C 70 60 50 50 40 1 2 3 VCNTL (V) 4 1 2 3 4 VCNTL (V) 10 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = 5.0V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = 25NC, unless otherwise noted.). INPUT P1dB vs. RF FREQUENCY VCC = 5.25V +85C 21 20 C10 = C11= 100pF FOR fRF > 300MHz 0 125 250 21 VCTRL STEP FROM 1V TO 4V -30 0 125 250 500 375 500 0 RF FREQUENCY (MHz) 1000 1500 2000 TIME (ns) RESPONSE TIME VCTRL STEP RESPONSE TIME WITH CS STEP 0 MAX19794 toc35 0 -5 CS STEP OCCURS AT t = t0 -5 CODE 0 TO 500 -10 VCTRL STEP FROM 3.15V TO 1V S21 (dB) S21 (dB) -15 -25 C10 = C11 = 10nF FOR fRF < 250MHZ C10 = C11 = 100pF FOR fRF > 300MHZ RF FREQUENCY (MHz) -10 VCTRL STEP FROM 1V TO 3.15V -20 19 500 375 VCC = 4.75V 20 C10 = C11= 10nF FOR fRF < 250MHz 19 -10 22 MAX19794 toc36 22 VCC = 5.00V VCTRL STEP OCCURS AT t = t0 -5 S21 (dB) INPUT P1dB (dBm) 23 0 MAX19794 toc33 MAX19794 toc32 -40C, +25C -15 -15 CODE 0 TO 700 -20 -20 VCTRL STEP FROM 4V TO 1V -25 -25 VCTRL STEP OCCURS AT t = t0 CODE 0 TO 1023 -30 -30 250 500 750 0 1000 1000 RESPONSE TIME WITH CS STEP 4000 5000 0 MAX19794 toc37 -5 -5 MODE 0 TO 1 (CODE 700 TO 0) MODE 1 TO 0 (CODE 1023 TO 0) CODE 500 TO 0 -10 S21 (dB) -15 3000 RESPONSE TIME WITH MODE STEP 0 -10 2000 TIME (ns) TIME (ns) MAX19794 toc38 0 S21 (dB) INPUT P1dB (dBm) 23 RESPONSE TIME VCTRL STEP 24 MAX19794 toc34 INPUT P1dB vs. RF FREQUENCY 24 CODE 700 TO 0 MODE 0 TO 1 (CODE 0 TO 700) -15 MODE 0 TO 1 (CODE 0 TO 1023) -20 -20 CODE 1023 TO 0 -25 -25 CS STEP OCCURS AT t = t0 -30 0 500 1000 TIME (ns) 1500 2000 MODE STEP OCCURS AT t = t0 -30 0 1000 2000 3000 4000 5000 TIME (ns) 11 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.). -20 -30 C10 = C11 = 10nF -10 S22 (dB) TC = +25C 0 MAX19794 toc41 -10 TC = +85C 9 C10 = C11 = 10nF MAX19794 toc40 MAX19794 toc39 0 S11 (dB) -20 -30 TC = -40C -40 -40 8 3.25 3.35 -50 3.45 -50 0 125 VCC (V) 250 375 500 125 0 ATTENUATION vs. RF FREQUENCY OVER CODE SETTINGS INPUT MATCH vs. DAC CODE 0 MAX19794 toc42 0 -10 500 C10 = C11 = 10nF -10 10MHz S22 (dB) S11 (dB) S21 (dB) 0 10MHz 55MHz, 200MHz -20 375 OUTPUT MATCH vs. DAC CODE C10 = C11 = 10nF -10 250 RF FREQUENCY (MHz) RF FREQUENCY (MHz) MAX19794 toc43 3.15 -30 MAX19794 toc44 SUPPLY CURRENT (mA) 11 10 OUTPUT MATCH vs. RF FREQUENCY OVER CODE SETTINGS INPUT MATCH vs. RF FREQUENCY OVER CODE SETTINGS SUPPLY CURRENT vs. VCC 55MHz -20 -30 -20 -40 250 375 -50 -50 0 500 256 ATTENUATION vs. DAC CODE MAX19794 toc45 0 0 S21 (dB) -15 10MHz, 55MHz, 100MHz, 200MHz -15 TC = -40C, +25C, +85C 30 0 -25 -20 -30 -30 -30 768 1024 0 256 512 DAC CODE 768 1024 200MHz 100MHz -25 512 C10 = C11 = 10nF 10 -20 DAC CODE 1024 768 20 -20 256 512 S21 PHASE CHANGE vs. DAC CODE -10 0 256 DAC CODE fRF = 55MHz C10 = C11 = 10nF -5 -10 S21 (dB) 1024 ATTENUATION vs. DAC CODE C10 = C11 = 10nF -5 768 DAC CODE RF FREQUENCY (MHz) 0 512 S21 PHASE CHANGE (DEG) 125 MAX19794 toc46 0 MAX19794 toc47 C10 = C11 = 10nF -30 100MHz, 200MHz -40 100MHz 55MHz -10 10MHz REFERENCED TO INSERTION LOSS STATE POSITIVE PHASE = ELECTRICALLY SHORTER 0 256 512 768 1024 DAC CODE 12 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.). INPUT MATCH vs. RF FREQUENCY OVER CODE SETTINGS 0 MAX19794 toc50 C10 = C11 = 100pF -10 -10 -30 -20 S21 (dB) -20 S22 (dB) S11 (dB) -10 0 MAX19794 toc49 C10 = C11 = 100pF MAX19794 toc48 0 ATTENUATION vs. RF FREQUENCY OVER CODE SETTINGS OUTPUT MATCH vs. RF FREQUENCY OVER CODE SETTINGS -30 -20 -40 -50 -50 250 375 500 0 125 RF FREQUENCY (MHz) INPUT MATCH vs. DAC CODE C10 = C11 = 100pF 500MHz -10 -10 125 0 375 500 ATTENUATION vs. DAC CODE 0 C10 = C11 = 100pF -5 400MHz -10 -20 S21 (dB) S22 (dB) 250 RF FREQUENCY (MHz) 500MHz 300MHz -30 -30 200MHz -15 -20 300MHz 200MHz -40 200MHz 300MHz, 400MHz -25 500MHz -50 0 256 512 1024 768 -30 0 DAC CODE 256 512 768 1024 512 1024 -10 TC = -40C, +25C, +85C -20 50 S21 PHASE CHANGE (DEG) MAX19794 toc54 S21 PHASE CHANGE vs. DAC CODE fRF = 300MHz C10 = C11 = 100pF -5 768 DAC CODE ATTENUATION vs. DAC CODE 0 -15 256 0 DAC CODE REFERENCED TO INSERTION LOSS STATE POSITIVE PHASE = ELECTRICALLY SHORTER 25 MAX19794 toc55 -50 S21 (dB) S11 (dB) 500 C10 = C11 = 100pF 400MHz -20 -40 375 OUTPUT MATCH vs. DAC CODE 0 MAX19794 toc51 0 250 RF FREQUENCY (MHz) MAX19794 toc52 125 0 C10 = C11 = 100pF -30 MAX19794 toc53 -40 500MHz 400MHz 0 300MHz -25 -25 -30 0 256 512 DAC CODE 768 1024 200MHz C10 = C11 = 100pF -50 0 256 512 768 1024 DAC CODE 13 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.). 35 40 C10 = C11 = 100pF fRF = 250MHz PIN = 0dBm / TONE 50 35 45 40 35 LSB, USB MAX19794 toc58 C10 = C11 = 10nF INPUT IP3 vs. VCNTL 55 INPUT IP3 (dBm) 40 fRF = 100MHz PIN = 0dBm /TONE 45 INPUT IP3 (dBm) INPUT IP3 (dBm) 45 MAX19794 toc56 C10 = C11 = 10nF fRF = 55MHz PIN = 0dBm /TONE INPUT IP3 vs. VCNTL 50 MAX19794 toc57 INPUT IP3 vs. VCNTL 50 LSB, USB LSB, USB 30 2.0 2.5 30 1.0 1.5 VCNTL (V) 40 fRF = 55MHz PIN = 0dBm /TONE fRF = 55MHz PIN = 0dBm/ TONE 35 2.5 1.5 2.0 50 2.5 INPUT IP2 vs. VCNTL 50 C10 = C11 = 100pF 80 70 60 50 40 2.5 2.5 fRF = 500MHz PIN = 0dBm / TONE C10 = C11 = 100pF 80 70 60 50 40 2.0 2.0 INPUT IP2 vs. VCNTL INPUT IP2 (dBm) 60 VCNTL (V) 1.5 90 MAX19794 toc63 fRF = 250MHz PIN = 0dBm / TONE INPUT IP2 (dBm) 70 1.5 1.0 VCNTL (V) 90 MAX19794 toc62 C10 = C11 = 10nF 80 1.0 60 VCNTL (V) INPUT IP2 vs. VCNTL fRF = 100MHz PIN = 0dBm / TONE 70 40 1.0 VCNTL (V) 90 C10 = C11 = 10nF 80 -40C, +25C, +85C. LSB, USB 2.0 2.5 INPUT IP2 vs. VCNTL 25 1.5 2.0 90 30 LSB, USB 30 INPUT IP2 (dBm) C10 = C11 = 10nF 40 INPUT IP3 (dBm) INPUT IP3 (dBm) 45 1.0 1.5 VCNTL (V) INPUT IP2 (dBm) fRF = 500MHz PIN = 0dBm /TONE 50 35 1.0 INPUT IP3 vs. VCNTL 45 MAX19794 toc59 C10 = C11 = 100pF 2.5 VCNTL (V) INPUT IP3 vs. VCNTL 55 2.0 MAX19794 toc61 1.5 MAX19794 toc60 1.0 MAX19794 toc64 30 40 1.0 1.5 2.0 VCNTL (V) 2.5 1.0 1.5 2.0 2.5 VCNTL (V) 14 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Typical Operating Characteristics (continued) (Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I, VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.). INPUT P1dB vs. RF FREQUENCY 70 -40C, +25C, +85C 60 TA = -40C TA = +25C VCTRL STEP FROM 1V TO 2.08V -10 16 -15 VCTRL STEP FROM 1V TO 2.5V -20 TA = +85C 15 50 VCTRL STEP OCCURS AT t = t0 -5 S21 (dB) INPUT P1dB (dBm) 17 -25 40 1.5 2.0 14 2.5 -30 0 VCNTL (V) 50 100 150 200 -10 2000 RESPONSE TIME WITH CS STEP MAX19794 toc69 -5 CODE 0 TO 500 -10 S21 (dB) VCTRL STEP FROM 2.08V TO 1V -15 -20 1500 0 MAX19794 toc68 -5 1000 TIME (ns) RESPONSE TIME VCTRL STEP 0 S21 (dB) 500 0 RF FREQUENCY(MHz) -15 CODE 0 TO 700 CODE 0 TO 1023 -20 VCTRL STEP FROM 2.5V TO 1V -25 -25 VCTRL STEP OCCURS AT t = t0 CS STEP OCCURS AT t = t0 -30 -30 0 250 500 750 1000 0 1000 TIME (ns) 3000 4000 5000 TIME (ns) RESPONSE TIME WITH MODE STEP RESPONSE TIME WITH CS STEP 0 MAX19794 toc70 0 -5 -5 CODE 500 TO 0 -10 2000 MODE 1 TO 0 (CODE 700 TO 0) MODE 1 TO 0 (CODE 1023 TO 0) -10 S21 (dB) CODE 700 TO 0 -15 CODE 1023 TO 0 -15 MODE 0 TO 1 (CODE 0 TO 700) -20 -20 MAX19794 toc71 1.0 S21 (dB) INPUT IP2 (dBm) 80 C10 = C11 = 10nF 0 MAX19794 toc66 C10 = C11 = 10nF MAX19794 toc65 fRF = 55MHz PIN = 0dBm / TONE RESPONSE TIME VCTRL STEP 18 MAX19794 toc67 INPUT IP2 vs. VCNTL 90 MODE 0 TO 1 (CODE 0 TO 1023) -25 -25 MODE STEP OCCURS AT t = t0 CS STEP OCCURS AT t = t0 -30 -30 0 500 1000 TIME (ns) 1500 2000 0 1000 2000 3000 4000 5000 TIME (ns) 15 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC CS DOUT DIN CLK UP DWN GND TOP VIEW GND VCC Pin Configuration 27 26 25 24 23 22 21 20 19 17 16 MAX19794 15 11 10 GND 13 12 GND 1 2 3 4 5 6 7 8 9 GND EP* + MODE COMP_OUT DAC_LOGIC REF_SEL REF_IN VCC GND CTRL 14 IN_A GND IN_B GND 18 VCC GND GND GND RTNB VCC GND 28 29 30 31 32 33 34 35 36 OUT_A GND RTNA GND OUT_B TQFN 6mm x 6mm *INTERNALLY CONNECTED TO GND. Pin Description PIN NAME 1, 3, 6, 7, 9, 10, 12, 26, 27, 28, 30, 33, 34, 36 GND 2 OUT_A 4, 31 DESCRIPTION Ground. Connect to the board's ground plane using low-inductance layout techniques. Attenuator A RF Output. Internally matched to 50I over the operating frequency band. This pin, if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected. Attenuator Ground Returns. These pins require a cap to ground and need to be placed close RTNA, RTNB to each pin. This capacitor centers the RF band of operation. See the Typical Operating Characteristics section. 5 VCC Attentuator A Power Supply. Bypass to GND with a capacitor and a resistor as shown in the Typical Application Circuit. 8 IN_A Attenuator A RF Input. Internally matched to 50I over the operating frequency band. This pin, if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected. 11 CTRL Attenuator Control Voltage Input. Except in the test mode where no voltage can be applied to this pin. VCC must be present unless using a current-limiting resistor as noted in the Applications Information section. 16 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Pin Description (continued) PIN NAME 13 VCC 14 REF_IN 15 REF_SEL DESCRIPTION Analog Supply Voltage. Bypass to GND with capacitor as close as possible to the device. See the Typical Application Circuit. DAC Reference Voltage Input (Optional) DAC Reference Voltage Selection Logic Input Logic = 0 enable on-chip DAC reference. Logic = 1 use off-chip DAC reference (pin 14). 16 DAC_LOGIC DAC Logic Control Input. See Table 1. 17 COMP_OUT 18 MODE 19 DWN 20 UP 19, 20 DWN/UP 21 CLK SPI Clock Input 22 DIN SPI Data Input 23 DOUT 24 CS SPI Chip Selection Input 25 VCC Digital Supply Voltage. Bypass to GND with capacitor as close as possible to the device as possible. See the Typical Application Circuit. 29 OUT_B Attenuator B RF Output. Internally matched to 50I over the operating frequency band. This pin, if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected. 32 VCC Attenuator B Power Supply. Bypass to GND with capacitor and resistor as shown in the Typical Application Circuit. 35 IN_B Attenuator B RF Input. Internally matched to 50I over the operating frequency band. This pin, if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected. -- EP Comparator Logic OutputA 4.7pF capacitor could be used to reduce any potential rise time glitching when the comparator changes state. Attenuator Control Mode Logic Input Logic = 1 enable attenuator step control. Logic = 0 enable attenuator SPI control. Down Pulse Input Logic pulse = 0 for each step-down. Up Pulse Input Logic pulse = 0 for each step-up. Logic = 0 to both pins to reset the attenuator to a minimum attenuation state SPI Data Output Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes. These multiple via grounds are also required to achieve the noted RF performance. See the Layout Considerations section. 17 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Detailed Description The MAX19794 is a dual, general-purpose analog voltage variable attenuator (VVA) designed to interface with 50I systems operating in the 10MHz to 500MHz frequency range. Each attenuator provides 22.4dB of attenuation range with a linear control slope of 8dB/V. Both attenuators share a common analog control and can be cascaded together to yield 44.7dB of total dynamic range with a combined linear control slope of 16dB/V. Alternatively, the on-chip, 4-wire SPI-controlled 10-bit DAC can be used to control both attenuators. In addition, a step-up/down feature allows user-programmable attenuator stepping through command pulses without reprogramming the SPI interface. Application Information Attenuation Control and Features The device has various states that are used to control the analog attenuator along with some monitoring conditions. The device can be controlled by an external control voltage, an internal SPI bus, or a combination of the two. The various states are described in Table 1. The SPI bus has multiple registers that are used to control the device when not configured for the analog only mode. For the cases where CTRL is used, the control range is 1V to 4V for VCC = 5V, and is 1V to 2.5V for VCC = 3.3V. Up to 22.4dB of attenuation-control range is provided per attenuator. At the insertion-loss setting, the single attenuator's loss is approximately 1.5dB. If a larger attenuation-control range is desired, the second on-chip attenuator can be connected in series to provide an additional 22.4dB of gain-control range. The on-chip control driver simultaneously adjusts both on-chip attenuators. It is suggested that a current-limiting resistor be included in series with CTRL to limit the input current to less than 40mA, should the control voltage be applied when VCC is not present. A series resistor of greater than 200I provides complete protection for +5.0V control voltage ranges. Analog Mode Only Control In Table 1 state (0, 0), the attenuators are controlled using a voltage applied to the CTRL pin of the device and the on-chip DAC is disabled. In the case where none of the features of the SPI bus are needed, the part can be operated in a pure analog control mode by grounding pins 14 through 25. DAC Mode Control In Table 1 state (1, 0), the attenuators are controlled by the on chip 10-bit DAC register. See the Register/Mode section. In this condition, no signal is applied to the CTRL pin and the load on the CTRL pin should be >100kI. The DAC is set using the SPI loaded code in the registers along with the setting of the mode pin. Analog Mode Control with Alarm Monitoring In Table 1 state (0, 1), the attenuators are controlled using a voltage applied to the CTRL pin of the device. See Register/Mode section. In this condition, the DAC Table 1. Attenuator Control Logic States DAC_LOGIC RDBK_EN (D9, REG3) 0 0 S1 = closed S2, S3, S4 = open Controlled by external analog voltage on CTRL (pin 11). Disabled 1 0 S1, S3, S4 = open S2 = closed Controlled by on-chip DAC. No voltage applied to pin 11. Enabled 0 1 Controlled by external analog voltage on CTRL S1, S3, S4 = closed (pin 11). CTRL is compared with DAC output. S2 = open Comparator drives COMP_OUT (pin 17). 1 Controlled by on-chip DAC. The DAC output is connected to pin 11. Use this state to test the DAC output. In this condition, no voltage can be applied to pin 11 and the load on pin 11 must be > 100kI. 1 INTERNAL SWITCH STATES S1, S2 = closed S3, S4 = open ATTENUATOR 10-BIT DAC Enabled (update DAC code to estimate CTRL voltage on pin 11) Enabled 18 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC is enabled and a voltage is also applied to CTRL (pin 11). The on-chip switches are set to compare the DAC voltage to the CTRL voltage at the comparator input, and the output of the comparator COMP_OUT trips from high to low when the CTRL exceeds the on-chip DAC voltage. DAC Test Mode In Table 1 state (1, 1), the attenuators are controlled by the on chip 10-bit DAC register. See Register MODE UP/ DWN Operation section. In this condition, the DAC is enabled and the DAC voltage appears at the CTRL pin. In this condition, no signal can be applied to the CTRL pin and the load on the CTRL pin should be > 100kI. This mode is used only in production testing of the DAC voltage and is not recommended for customer use. Register MODE UP/DWN Operation The device uses four 13-bit registers for the operation of the device. The first bit is the read/write bit,the following two are address bits, while the remaining 10 are the desired data bits. The read/write bit determines whether the register is being written to or read from. The next two address bits select the desired register to write or read from. These address bits can be seen in Table 2. Table 3 describes the contents of the four registers. Figure 1 shows the configuration of the internal registers of the device, and Figure 2 shows the timing of the SPI bus. Register 0 is used to set the DAC code to the desired value, register 1 selects the step-up code, and register 2 selects the step-down code. The part also contains a MODE control pin (Table 4), along with UP and DWN controls(Table 5). When MODE is 0, the contents of register 0 get loaded into the 10-bit DAC register and set the value of the on-chip DAC. In this condition, the UP and DWN control pins have no effect on the part. In MODE 1, the effective DAC code fed to the 10-bit DAC register is equal to: m x Register 1 - n x Register 2 where m and n are the number of UP and DWN control steps accumulated, respectively. After powering up the part, UP and DWN should both be set to 0 to reset the m and n counters to be 0. This results in a 10-bit all 0 code out of the mathematical block in Figure 1. This is applied to the 10-bit DAC register that drives the DAC. To increase (decrease) the code using the UP (DWN) pin, the DWN (UP) pin must be high and the UP (DWN) pin should be pulsed low to high. The part is designed to produce no wraparounds when using UP and DWN stepping, so the DAC code maxes out at 1023 or goes no lower than 0. See Figure 3 for the UP and DWN control operation. Switching back to MODE 0 produces the same 10-bit DAC code as was previously loaded into register 0. Switching back to MODE = 1 results in the previous 10-bit DAC code from the register 1 and 2 combiner/multiplier block. Register 3 is used to set the RDBK_EN register in the write mode and is used to read back the RDBK_EN register and COMP_OUT in the read mode. SPI Interface The device can be controlled with a 4-wire SPI-compatible serial interface. Figure 2 shows a timing diagram for the interface. In the write mode, a 13-bit word is loaded into the device through the DIN pin with CS set low. The first bit of the word in the write mode is 0, and the next two bits select the register to be written to. See Table 2. The next 10 bits contain the data to be written to the selected register. After the 13 bits are shifted in, a low to high CS command is applied and this latches the 10 bits into the selected register. The entire write command is ignored if CS is pulsed low to high before the last data bit is successfully captured. For the read cycle, the first bit clocked in is a 1 and this establishes that a register is to be read. The next two clocked bits form the address of the register to be read. See Table 2. In this read mode, data starts to get clocked out of the DOUT pin after A0 is captured. The DOUT pin goes to a high-impedance state after the 10 bits are transmitted, or if CS goes high at any point in time during the transmission. Voltage Reference The device has an on-chip voltage reference for the DAC and also has a provision to operate with an offchip reference. Table 6 provides details in selecting the desired reference. 19 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Table 2. Component Suppliers R/W A1 A0 0 0 0 Write to register 0 using DIN DESCRIPTION 0 0 1 Write to register 1 using DIN 0 1 0 Write to register 2 using DIN 0 1 1 Write to register 3 using DIN 1 0 0 Read from register 0 using DOUT 1 0 1 Read from register 1 using DOUT 1 1 0 Read from register 2 using DOUT 1 1 1 Read from register 3 using DOUT Table 3. Register Definitions Register 0 (Read/Write 10-Bit DAC Code) D9 D8 D7 D6 D5 D4 D3 D2 D1 DAC MSB D0 DAC LSB Register 1 (Read/Write 10-Bit Step-Up Code) D9 D8 D7 D6 D5 D4 D3 D2 D1 Step-up MSB D0 Step-up LSB Register 2 (Read/Write 10-Bit Step-Down Code) D9 D8 D7 D6 D5 D4 D3 D2 D1 Step-down MSB D0 Step-down LSB Register 3 Write Bits RDBK_EN= Enable bit for voltage comparator that drives COMP_OUT (pin 17). D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Not used, set = 0 RDBK_EN Register 3 Read Bits RDBK_EN= Enable bit for voltage comparator that drives COMP_OUT (pin 17), COMP_OUT=Read Logic level of COMP_OUT (pin 17). D9 D8 RDBK_EN COMP_OUT D7 D6 D5 D4 D3 Not used, set = 0 20 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC DIN DOUT REGISTER 0 MODE OR 10-BIT DAC REGISTER UP m x REGISTER 1 - n x REGISTER 2 m = NUMBER OF UP PULSES n = NUMBER OF DOWN PULSES m REGISTER 1 n REGISTER 2 DOWN RESET TO ALL ZEROS WHEN UP/DOWN PULSED TOGETHER REGISTER 3 Figure 1. Register Configuration Diagram Table 4. Attenuator Control Mode Logic State MODE (PIN 17) ATTENUATOR 0 SPI Control Mode (DAC code is located in register 0) 1 Step Control Mode using UP and DWN pins. The step-up code is located in register 1 and step-down code in register 2). Table 5. Step Mode Logic State (MODE = 1) UP DWN ATTENUATOR Logic 0 Logic 0 Reset DAC for minimum attenuation state (DAC code = 0000000000). Logic 0 Pulse Logic 1 Increase DAC code* by amount located in register 1. UP pulsed from high to low to high (Figure 3). Logic 1 Logic 0 Pulse Decrease DAC code* by amount located in register 2. DWN pulsed from high to low to high (Figure 3). *Continued up or down stepping results in saturation (no code wrapping). Table 6. REF_SEL Logic State REF_SEL DAC REFERENCE 0 Uses on-chip DAC reference. 1 User provides off-chip DAC reference voltage on REF_IN (pin 14). 21 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC SPI Interface Programming DIN R/W A1 A0 D9, D8...D0 TO REGISTER 0, 1, 2, 3 1 UP HIGH-Z DOUT D9, D8...D0 FROM REGISTER 0, 1, 2, 3 0 HIGH-Z tCS 1 tCH DWN CLK 0 tEWS CS tCW NO DAC CODE CHANGE tES DAC CODE INCREASED BY STEP UP DAC CODE DAC CODE DECREASED RESET TO BY STEP DOWN ALL 0's tEW Figure 2. SPI Timing Diagram Figure 3. UP DWN Control Diagram (Mode = 1) Table 7. Typical Application Circuit Component Values DESIGNATION QTY C1, C2, C4 3 0.01FF Q5% 50V X7R ceramic capacitors (0402). C3 0 Not installed for two attenuators in cascade C5-C9 5 1000pF Q5% 50V COG ceramic capacitors (0402) C10, C11 DESCRIPTION 10MHz to 200MHz 0.01FF Q10% 50V X7R ceramic capacitors (0402) 250MHz to 500MHz 100pF Q5% 50V COG ceramic capacitors (0402) 2 C12 1 120pF Q5% 50V COG CER CAP (0402).Provides some external noise filtering along with R3. C13 0 Not installed. A 4.7pF capacitor could be used to reduce any potential rise time glitching when the comparator changes state. R1*, R2* 2 10I Q5% resistor (0402) R3 1 200I Q5% resistor (0402). This resistor is used to provide some lowpass noise filtering when used with C12. The value of R3 slows down the response time. R3 also provides protection for the device in case VCTRLis applied without VCC present. U1 1 MAX19794 *Add 2 additional 10I resistors between the VCC pins leading to C5 and C6 unless a VCC power plane is used. Layout Considerations A properly designed PCB is an essential part of any RF/microwave circuit. Keep RF signal lines as short as possible to reduce losses, radiation, and inductance. For best performance, route the ground-pin traces directly to the exposed pad underneath the package. This pad must be connected to the ground plane of the board by using multiple vias under the device to provide the best RF and thermal conduction path. Solder the exposed pad on the bottom of the device package to a PCB. RF Ground Return Capacitors The device requires RF ground return capacitors C10 and C11. The value of these capacitors optimize the dynamic range and frequency flatness for the RF band of interest. Some recommended values are shown in Table 7 along with the resulting performance in the Typical Operating Characteristics section. 22 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Power-Supply Bypassing Exposed Pad RF and Thermal Considerations Proper voltage-supply bypassing is essential for high frequency circuit stability. Bypass each VCC pin with capacitors placed as close as possible to the device. Place the smallest capacitor closest to the device. See the Typical Application Circuit and Table 7 for details. The exposed pad (EP) of the device's 36-pin TQFN package provides a low thermal-resistance path to the die. It is important that the PCB on which the device is mounted to conduct heat from this contact. In addition, provide the EP with a low-inductance RF ground path for the device. The EP must be soldered to a ground plane on the PCB, either directly or through an array of plated via holes. Soldering the pad to ground is also critical for efficient heat transfer. Use a solid ground plane wherever possible. Typical Application Circuit VCC C9 27 GND C6 GND C3 RF_AB IN_B GND DWN UP DIN DOUT CS VCC CLK 20 19 28 MAX19794 18 29 EP 17 S3 30 31 S4 16 S2 ATTEN_B DAC ATTENUATIONCONTROL CIRCUITRY 32 15 14 S1 33 13 34 12 ATTEN_A 35 11 36 10 1 GND C2 DWN 2 3 C10 4 5 6 R1 VCC 7 8 MODE MODE COMP_OUT COMP_OUT C13 DAC_LOGIC DAC_LOGIC REF_SEL REF_SEL REF_IN VCC REF_IN VCC GND CTRL GND C8 C7 R3 VCTRL C12 9 GND VCC UP 21 GND R2 CLK IN_A VCC 22 GND RTNB 23 VCC C11 24 RTNA GND 25 GND RFOUT_B OUT_B 26 OUT_A GND C4 GND GND CS DOUT DIN C1 RFIN_A C5 NOTE: FOR ATTENUATOR A ONLY CONFIGURATION, REMOVE C3 AND MOVE C2 DIAGONALLY TO CONNECT PIN 2 TO THE OUTPUT CONNECTION RF_AB. FOR ATTENUATOR B ONLY CONFIGURATION, REMOVE C2. FOR CASCADED CONFIGURATION, REMOVE C3 AND USE C2 TO CONNECT OUT_A TO IN_B. 23 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Package Information Ordering Information PART TEMP RANGE PIN-PACKAGE MAX19794ETX+ -40NC to +100NC 36 TQFN-EP* MAX19794ETX+T -40NC to +100NC 36 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. T = Tape and reel. For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 36 TQFN T3666+2 21-0141 90-0049 Chip Information PROCESS: BiCMOS 24 MAX19794 10MHz to 500MHz Dual Analog Voltage Variable Attenuator with On-Chip 10-Bit SPI-Controlled DAC Revision History REVISION NUMBER REVISION DATE 0 6/12 DESCRIPTION Initial release PAGES CHANGED -- Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 (c) 2012 Maxim Integrated Products 25 Maxim is a registered trademark of Maxim Integrated Products Inc.