MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
1
19-6381; Rev 0; 6/12
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/MAX19794.related.
General Description
The MAX19794 dual general-purpose analog voltage
variable attenuator (VVA) is designed to interface
with 50I systems operating in the 10MHz to 500MHz
frequency range. This device includes a patented control
circuit that provides 22.4dB of attenuation range (per
attenuator) with a typical linear control slope of 8dB/V.
Both attenuators share a common analog control.
They can be cascaded together to yield 44.7dB of
total attenuation range with a typical combined linear
control slope of 16dB/V (5V operation). Alternatively, the
on-chip, 4-wire SPI-controlled 10-bit DAC can be used
to control both attenuators. In addition, a step-up/down
feature allows user-programmable attenuator stepping
through command pulses without re-programming the
SPI interface.
The MAX19794 is a monolithic device designed using
one of Maxim’s proprietary SiGe BiCMOS processes. The
part operates from a single +5V supply or alternatively
operates from a single +3.3V supply. It is available
in a compact 36-pin TQFN package (6mm x 6mm x
0.8mm) with an exposed pad. Electrical performance
is guaranteed over the -40NC to +100NC extended
temperature range.
Applications
Broadband System Applications, Including
Wireless Infrastructure Digital and Spread-
Spectrum Communication Systems
WCDMA/LTE, TD-SCDMA/TD-LTE, WiMAX®,
cdma2000®, GSM/EDGE and MMDS Base
Stations
VSAT/Satellite Modems
Military Systems
Microwave Point to Point Systems
Lineup Gain Trim
Temperature Compensation Circuits
Automatic Level Control (ALC)
Transmitter Gain Control
Receiver Gain Control
General Test Equipment
Benefits and Features
S Wide Band Coverage
RF Frequency Range from 10MHz to 500MHz
S High Linearity
Greater than +34.4dBm IIP3 over the Full
Attenuation Range
+21.8dBm Input P1dB
S Integrates Two Analog Attenuators in One
Monolithic Device
S Two Convenient Control Options
Single Analog Voltage
On-Chip, SPI-Controlled 10-Bit DAC
S Step-Up/Down Pulse Command Inputs
S Flexible Attenuation Control Ranges
22.4dB (per Attenuator)
44.7dB (both Attenuators Cascaded)
S Linear dB/V Analog Control Response Curve
Simplifies Automatic Leveling Control and Gain
Trim Algorithms
S Excellent Attenuation Flatness over Wide
Frequency Ranges and Attenuation Settings
S On-Chip Comparator (for Successive
Approximation Measurement of Attenuator
Control Voltage)
S Low 13mA Supply Current
S Single +5V or 3.3V Supply Voltage
S Pin Similar with MAX19791, MAX19792, and
MAX19793
S Lead-Free Package
WiMAX is a registered certification mark and regisitered
service mark of WiMAX Forum.
cdma2000 is a registered trademark of Telecommunications
Industry Association.
EVALUATION KIT AVAILABLE
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
VCC ....................................................................... -0.3V to +5.5V
REF_IN ..............................-0.3V to Minimum (VCC + 0.3V, 3.6V)
REF_SEL,DAC_LOGIC,MODE, DWN, UP,
DIN, CLK, CS ................-0.3V to Minimum (VCC + 0.3V, 3.6V)
COMP_OUT, DOUT ..............................................-0.3V to +3.6V
IN_A, OUT_A, IN_B, OUT_B .......................-0.3V to VCC + 0.3V
CTRL (except for test mode) .......................-0.3V to VCC + 0.3V
Maximum CTRL Pin Load Current
(CTRL configured as an output) ....................................0.3mA
RF Input Power at IN_A, IN_B, OUT_A, OUT_B ........... +20dBm
Continuous Power Dissipation (Note 1) ..............................2.8W
Operating Case Temperature Range (Note 2) ...-40NC to +100NC
Maximum Junction Temperature .......................................150NC
Storage Temperature ....................................... -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
TQFN
Junction-to-Ambient Thermal Resistance (qJA)
(Notes 3, 4) .......................................................... +36°C/W
Junction-to-Case Thermal Resistance (qJC)
(Notes 1, 4) .......................................................... +10°C/W
ABSOLUTE MAXIMUM RATINGS
Note 3: Junction temperature TJ = TA + (BJA x VCC x ICC). This formula can be used when the ambient temperature of the PCB is
known. The junction temperature must not exceed +150NC.
Note 4: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS
3.3V DC ELECTRICAL CHARACTERISTICS
(VCC = 3.15V to 3.45V, VCTRL = 1V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, no RF signals applied, all input and output
ports terminated with 50I through DC blocks, TC = -40NC to +100NC, unless otherwise noted. Typical values are at VCC = 3.3V, VCTRL
= 1.0V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, TC = +25NC, unless otherwise noted.) (Note 5)
Note 1: Based on junction temperature TJ = TC + (BJC x VCC x ICC). This formula can be used when the temperature of the
exposed pad is known while the device is soldered down to a PCB. See the Application Information section for details. The
junction temperature must not exceed +150NC.
Note 2: TC is the temperature on the exposed pad of the package. TA is the ambient temperature of the device and PCB.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC 3.15 3.3 3.45 V
Supply Current ICC 9.5 14 mA
Control Voltage Range VCTRL 1.0 2.5 V
CTRL Input Resistance RCTRL 1.0 MI
Input CurrentLogic-High IIH -1.0 +1.0 FA
Input Current Logic-Low IIL -1.0 +1.0 FA
REF_IN Voltage 1.4 V
REF_IN Input Resistance 1.0 MI
DAC Number of Bits Monotonic 10 bits
Input Voltage Logic-High VIH 2.0 V
Input Voltage Logic-Low VIL 0.8 V
COMP_OUT Logic-High RDBK_EN (D9, REG3) = Logic 1,
RLOAD = 47kΩ3.3 V
COMP_OUT Logic-Low RDBK_EN (D9, REG3) = Logic 1,
RLOAD = 47kΩ0 V
3
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
5V DC ELECTRICAL CHARACTERISTICS
(VCC = 4.75V to 5.25V, VCTRL = 1.0V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, no RF signals applied, all input and output
ports terminated with 50I through DC blocks, TC = -40NC to +100NC, unless otherwise noted. Typical values are at VCC = 5.0V, VCTRL
= 1.0V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, TC = +25NC, unless otherwise noted.) (Note 5)
Recommended AC Operating Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC 4.75 5.0 5.25 V
Supply Current ICC 13 18.6 mA
Control Voltage Range VCTRL 1.0 4.0 V
CTRL Input Resistance RCTRL 124 kI
Input Current Logic-High IIH -1.0 +1.0 FA
Input Current Logic-Low IIL -1.0 +1.0 FA
REF_IN Voltage Range 1.4 V
REF_IN Input Resistance 1.0 MI
DAC Number of Bits Monotonic 10 Bits
Input Voltage Logic-High VIH 2.0 V
Input Voltage Logic-Low VIL 0.8 V
COMP_OUT Logic-High RDBK_EN (D9, REG3) = Logic 1, RLOAD =
47kΩ3.3 V
COMP_OUT Logic-Low RDBK_EN (D9, REG3) = Logic 1, RLOAD =
47kΩ0 V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RF Frequency Range fRF (Note 6) 10 500 MHz
RF Port Input Power PRF Continuous operation 15 dBm
4
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
3.3V AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, one attenuator, VCC = 3.15V to 3.45V, RF ports are driven from 50I sources and loaded into 50I, input
PRF = 0dBm, fRF = 10MHz to 500MHz, VCTRL = 1V to 2.5V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, TC = -40NC to +100NC.
Typical values are for TC = +25NC, VCC = 3.3V, input PRF =0dBm, fRF = 55MHz, VCTRL = 1.0V, VDAC_LOGIC = 0V, RDBK_EN (D9,
REG3) = Logic 0, unless otherwise noted.) (Notes 5, 7)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Insertion Loss IL One attenuator 1.5 dB
Two attenuators, fRF = 55MHz, VCTRL = 1.0V 3.0 5.0
Loss Variation Over Temperature TC = -40NC to +100NC0.28 dB
Input P1dB IP1dB 16.4 dBm
Minimum Input Second-Order
Intercept Point
Over Full Attenuation Range
(Note 8)
IIP2
One attenuator
fRF1 +fRF2 term,
fRF1 - fRF2 = 1MHz
VCTRL = 1.0V to 2.5V
PRF = 0dBm/tone applied to attenuator input
44.9
dBm
Two attenuators
fRF1 + fRF2 term,
fRF1 - fRF2 = 1MHz
VCTRL = 1.0V to 2.0V
PRF = 0dBm/tone applied to attenuator input
42.7
Minimum Input Third-Order
Intercept Point
Over Full Attenuation Range
(Note 8)
IIP3
One attenuator
VCTRL =1.0V to 2.5V
fRF1 - fRF2 = 1MHz
PRF = 0dBm/tone applied to attenuator input
30.8
dBm
Two attenuators
VCTRL =1.0V to 2.0V
fRF1 - fRF2 = 1MHz
PRF = 0dBm/tone applied to attenuator input
29.9
Second Harmonic 62 dBc
Third Harmonic 89.7 dBc
Attenuation Control Range
One attenuator, VCTRL = 1.0V to 2.5V,
fRF = 55MHz 22.5 dB
Two attenuators, VCTRL = 1.0V to 2.5V,
fRF = 55MHz 38.5 45 dB
Average Attenuation-Control
Slope VCTRL = 1.4V to 2.3V 22.5 dB/V
Maximum Attenuation-Control
Slope VCTRL = 1.0V to 2.5V 40 dB/V
S21 Attenuation Deviation from a
straight line VCTRL = 1.4V to 2.1V ±0.4 dB
5
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
5V AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, one attenuator, VCC = 4.75V to 5.25V, RF ports are driven from 50I sources and loaded into 50I, input
PRF = 0dBm, fRF = 10MHz to 500MHz, VCTRL = 1V to 4V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, TC = -40NC to +100NC.
Typical values are for TC = +25NC, VCC = 5.0V, input PRF = 0dBm, fRF = 55MHz, VCTRL = 1.0V, VDAC_LOGIC = 0V, RDBK_EN (D9,
REG3) = Logic 0, unless otherwise noted.) (Notes 5, 7)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
Insertion Loss IL One attenuator 1.5 dB
Two attenuators 3.0 5.0 dB
Loss Variation Over Temperature TC = -40NC to +100NC 0.29 dB
Input P1dB IP1dB 21.8 dBm
Minimum Input Second-Order
Intercept Point Over Full
Attenuation Range (Note 8)
IIP2
One attenuator
fRF1 + fRF2 term,
fRF1 - fRF2 = 1MHz
VCTRL = 1.0V to 4.0V
PRF = 0dBm/tone applied to attenuator input
48.1
dBm
Two attenuators
fRF1 +fRF2 term,
fRF1 - fRF2 = 1MHz
VCTRL = 1.0V to 4.0V
PRF = 0dBm/tone applied to attenuator input
46.5
Minimum Input Third-Order
Intercept Point
Over Full Attenuation Range
(Note 8)
IIP3
One attenuator
VCTRL from 1.0V to 4.0V
fRF1 - fRF2 = 1MHz
PRF = 0dBm/tone applied to attenuator input
34.4
dBm
Two attenuators
VCTRL from 1.0V to 4.0V
fRF1 - fRF2 = 1MHz
PRF = 0dBm/tone applied to attenuator input
32.3
Second Harmonic 63 dBc
Third Harmonic 97 dBc
Attenuation Control Range
One attenuator, VCTRL = 1.0V to 4.0V,
fRF = 55MHz 22.4 dB
Two attenuators VCTRL = 1.0V to 4.0V,
fRF = 55MHz 38.5 44.7 dB
Average Attenuation-Control
Slope
VCTRL = 1.5V to 3.1V 8.0
dB/V
VCTRL = 1.5V to 3.5V 9.4
Maximum Attenuation-Control
Slope VCTRL = 1.5V to 3.5V 30 dB/V
Attenuation Flatness over
any 125MHz band
VCTRL = 1.0V to 3.1V, fRF =
10MHz to 250MHz 0.15
dB
VCTRL = 1.0V to 3.1V, fRF =
250MHz to 500MHz 0.2
6
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
5V AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, one attenuator, VCC = 4.75V to 5.25V, RF ports are driven from 50I sources and loaded into 50I, input
PRF = 0dBm, fRF = 10MHz to 500MHz, VCTRL = 1V to 4V, VDAC_LOGIC = 0V, RDBK_EN (D9, REG3) = Logic 0, TC = -40NC to +100NC.
Typical values are for TC = +25NC, VCC = 5.0V, input PRF = 0dBm, fRF = 55MHz, VCTRL = 1.0V, VDAC_LOGIC = 0V, RDBK_EN (D9,
REG3) = Logic 0, unless otherwise noted.) (Notes 5, 7)
Note 5: Production tested at TC = +100°C. All other temperatures are guaranteed by design and characterization.
Note 6: Recommended functional range. Not production tested. Operation outside this range is possible, but with degraded per-
formance of some parameters.
Note 7: All limits include external component losses, connectors and PCB traces. Output measurements taken at the RF port of the
typical application circuit.
Note 8: fRF1 = 56MHz, fRF2 = 55MHz, PRF = 0dBm/tone applied to attenuator input.
Note 9: Switching time is measured from 50% of the CTRL signal to when the RF output settles to ±1dB. R3 = 0I
Note 10: Switching time is measured from when CS is asserted to when the RF output settles to ±1dB.
Note 11: Switching time is measured from when MODE is asserted to when the RF output settles to ±1dB.
Note 12: Typical minimum time for proper SPI operation.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT
CTRL Switching Time
(Note 9)
15dB to 0dB range 390 ns
0dB to 15dB range 780
CS Switching Time
(Note 10)
15dB to 0dB range 700 ns
0dB to 15dB range 2600
MODE Switching Time (Note 11) 15dB to 0dB range (MODE 1 to 0) 700 ns
0dB to 15dB range (MODE 0 to 1) 2600
Input Return Loss 31 dB
Output Return Loss 28 dB
Group Delay 40 ps
Group Delay Flatness fRF = 30MHz to 88MHz 25 ps
Group Delay Change VCTRL = 1.0V to 4.0V -400 ps
Insertion Phase Change vs.
Attenuation Control VCTRL = 1.0V to 4.0V 5 deg
S21 Attenuation Deviation from a
Straight Line VCTRL = 1.5V to 3.1V ±0.35 dB
SERIAL PERIPHERAL INTERFACE (SPI)
Maximum Clock Speed 20 MHz
Data-to-Clock Setup Time tCS (Note 12) 2 ns
Data-to-Clock Hold Time tCH (Note 12) 2.5 ns
CS to CLK Setup Time tEWS (Note 12) 3 ns
CS Positive Pulse Width tEW (Note 12) 7 ns
Clock Pulse Width tCW (Note 12) 5 ns
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
7
Typical Operating Characteristics
(Typical Application Circuit, VCC = 5.0V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.).
SUPPLY CURRENT vs. VCC
MAX19794 toc01
VCC (V)
SUPPLY CURRENT (mA)
5.1255.0004.875
TC = +25°C
TC = +85°C
11
12
13
14
15
10
4.750 5.250
TC = -40°C
INPUT MATCH vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19794 toc02
RF FREQUENCY (MHz)
S11 (dB)
-40
-30
-20
-10
0
-50
0 500
375250125
C10 = C11 = 10nF
OUTPUT MATCH vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19794 toc03
RF FREQUENCY (MHz)
S22 (dB)
-40
-30
-20
-10
0
-50
0 500
375250125
C10 = C11 = 10nF
S21 (dB)
-20
-10
0
-30
ATTENUATION vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19794 toc04
RF FREQUENCY (MHz)
3752501250 500
C10 = C11 = 10nF
INPUT MATCH vs. DAC CODE
MAX19794 toc05
DAC CODE
S11 (dB)
7685122560 1024
-40
-30
-20
-10
0
-50
C10 = C11 = 10nF
100MHz
10MHz
55MHz, 200MHz
OUTPUT MATCH vs. DAC CODE
MAX19794 toc06
DAC CODE
S22 (dB)
7685122560 1024
-40
-30
-20
-10
0
-50
C10 = C11 = 10nF
55MHz
10MHz
100MHz, 200MHz
ATTENUATION vs. DAC CODE
MAX19794 toc07
DAC CODE
S21 (dB)
7685122560 1024
0
C10 = C11 = 10nF
10MHz, 55MHz, 100MHz, 200MHz
-25
-20
-15
-10
-5
-30
ATTENUATION vs. DAC CODE
MAX19794 toc08
DAC CODE
S21 (dB)
7685122560 1024
0
TC = -40°C, +25°C, +85°C
-25
-20
-15
-10
-5
-30
fRF = 55MHz
C10 = C11 = 10nF
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
8
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 5.0V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.).
S21 PHASE CHANGE vs. DAC CODE
MAX19794 toc09
DAC CODE
S21 PHASE CHANGE (DEG)
7685122560 1024
30
-20
-10
0
10
20
-30
C10 = C11 = 10nF
REFERENCED TO INSERTION LOSS STATE
POSITIVE PHASE = ELECTRICALLY SHORTER
55MHz
100MHz
200MHz
10MHz
INPUT MATCH vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19794 toc10
S11 (dB)
-40
-30
-20
-10
0
-50
RF FREQUENCY (MHz)
3752501250 500
C10 = C11 = 100pF
OUTPUT MATCH vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19794 toc11
S22 (dB)
-40
-30
-20
-10
0
-50
RF FREQUENCY (MHz)
3752501250 500
C10 = C11 = 100pF
S21 (dB)
-20
-10
0
-30
ATTENUATION vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19794 toc12
RF FREQUENCY (MHz)
3752501250 500
C10 = C11 = 100pF
INPUT MATCH vs. DAC CODE
MAX19794 toc13
S11 (dB)
-40
-30
-20
-10
0
-50
DAC CODE
7685122560 1024
C10 = C11 = 100pF
200MHz
300MHz
400MHz
500MHz
OUTPUT MATCH vs. DAC CODE
MAX19794 toc14
S22 (dB)
-40
-30
-20
-10
0
-50
DAC CODE
7685122560 1024
C10 = C11 = 100pF
200MHz
300MHz
400MHz
500MHz
ATTENUATION vs. DAC CODE
MAX19794 toc15
DAC CODE
S21 (dB)
7685122560 1024
0
-25
-20
-15
-10
-5
-30
C10 = C11 = 100pF
200MHz
500MHz
300MHz, 400MHz
ATTENUATION vs. DAC CODE
MAX19794 toc16
DAC CODE
S21 (dB)
7685122560 1024
0
TC = -40°C, +25°C, +85°C
-25
-20
-15
-10
-5
-30
fRF = 300MHz
C10 = C11 = 100pF
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
9
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 5.0V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.).
S21 PHASE CHANGE vs. DAC CODE
MAX19794 toc17
DAC CODE
S21 PHASE CHANGE (DEG)
7685122560 1024
50
-25
0
25
-50
REFERENCED TO INSERTION LOSS STATE
POSITIVE PHASE = ELECTRICALLY SHORTER
200MHz
300MHz
400MHz
500MHz
C10 = C11 = 100pF
INPUT IP3 vs. VCNTL
MAX19794 toc18
VCNTL (V)
INPUT IP3 (dBm)
32
30
35
40
45
50
25
14
LSB, USB
C10 = C11 = 10nF
fRF = 10MHz
PIN = 0dBm/TONE
INPUT IP3 vs. VCNTL
MAX19794 toc19
VCNTL (V)
INPUT IP3 (dBm)
32
35
40
45
50
30
14
fRF = 55MHz
PIN = 0dBm/TONE
C10 = C11 = 10nF
LSB, USB
INPUT IP3 vs. VCNTL
MAX19794 toc20
VCNTL (V)
INPUT IP3 (dBm)
32
35
40
45
50
30
14
fRF = 100MHz
PIN = 0dBm/TONE
C10 = C11 = 10nF
LSB, USB
INPUT IP3 vs. VCNTL
MAX19794 toc21
VCNTL (V)
INPUT IP3 (dBm)
32
35
40
45
50
30
14
fRF = 150MHz
PIN = 0dBm/TONE
C10 = C11 = 10nF
LSB, USB
INPUT IP3 vs. VCNTL
MAX19794 toc22
VCNTL (V)
INPUT IP3 (dBm)
32
40
45
50
55
35
14
fRF = 250MHz
PIN = 0dBm/TONE
C10 = C11 = 100pF
LSB, USB
INPUT IP3 vs. VCNTL
MAX19794 toc23
VCNTL (V)
INPUT IP3 (dBm)
32
40
45
50
55
35
14
fRF = 500MHz
PIN = 0dBm/TONE
LSB, USB
C10 = C11 = 100pF
INPUT IP3 vs. VCNTL
MAX19794 toc24
VCNTL (V)
INPUT IP3 (dBm)
32
35
40
45
50
30
14
fRF = 55MHz
PIN = 0dBm/TONE
-40°C, +25°C, +85°C, -40°C,
LSB, USB
C10 = C11 = 10nF
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
10
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 5.0V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = 25NC, unless otherwise noted.).
INPUT IP2 vs. VCNTL
MAX19794 toc25
VCNTL (V)
INPUT IP2 (dBm)
32
40
50
60
70
30
14
fRF = 10MHz
PIN = 0dBm/TONE
C10 = C11 = 10nF
INPUT IP2 vs. VCNTL
MAX19794 toc26
VCNTL (V)
INPUT IP2 (dBm)
32
50
60
70
80
40
14
fRF = 55MHz
PIN = 0dBm/TONE
C10 = C11 = 10nF
INPUT IP2 vs. VCNTL
MAX19794 toc27
VCNTL (V)
INPUT IP2 (dBm)
32
60
70
80
90
50
14
fRF = 100MHz
PIN = 0dBm/TONE
C10 = C11 = 10nF
INPUT IP2 vs VCNTL
MAX19794 toc30
VCNTL (V)
INPUT IP2 (dBm)
32
60
70
80
90
100
50
14
fRF = 500MHz
PIN = 0dBm/TONE
C10 = C11 = 100pF
INPUT IP2 vs. VCNTL
MAX19794 toc28
VCNTL (V)
INPUT IP2 (dBm)
32
60
70
80
90
50
14
fRF = 150MHz
PIN = 0dBm/TONE
C10 = C11 = 10nF
INPUT IP2 vs VCNTL
MAX19794 toc31
VCNTL (V)
INPUT IP2 (dBm)
32
50
60
70
80
90
100
40
14
fRF = 55MHz
PIN = 0dBm/TONE
C10 = C11 = 10nF
-40°C, +25°C, +85°C
INPUT IP2 vs VCNTL
MAX19794 toc29
VCNTL (V)
INPUT IP2 (dBm)
32
60
70
80
90
100
50
14
fRF = 250MHz
PIN = 0dBm/TONE
C10 = C11 = 10nF
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
11
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 5.0V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = 25NC, unless otherwise noted.).
INPUT P1dB vs. RF FREQUENCY
MAX19794 toc32
RF FREQUENCY (MHz)
INPUT P1dB (dBm)
375250125
20
21
22
23
24
19
0 500
+85°C
-40°C, +25°C
C10 = C11= 10nF FOR fRF < 250MHz
C10 = C11= 100pF FOR fRF > 300MHz
INPUT P1dB vs. RF FREQUENCY
MAX19794 toc33
RF FREQUENCY (MHz)
INPUT P1dB (dBm)
375250125
20
21
22
23
24
19
0 500
VCC = 4.75V
VCC = 5.25V
VCC = 5.00V
C10 = C11 = 10nF FOR fRF < 250MHZ
C10 = C11 = 100pF FOR fRF > 300MHZ
RESPONSE TIME VCTRL STEP
MAX19794 toc34
TIME (ns)
S21 (dB)
15001000500
-25
-20
-15
-10
VCTRL STEP OCCURS AT t = t0
-5
0
-30
0 2000
VCTRL STEP FROM 1V TO 3.15V
VCTRL STEP FROM 1V TO 4V
RESPONSE TIME WITH CS STEP
MAX19794 toc37
TIME (ns)
S21 (dB)
15001000500
-25
-20
-15
-10
-5
0
-30
0 2000
CODE 500 TO 0
CODE 700 TO 0
CODE 1023 TO 0
CS STEP OCCURS AT t = t0
RESPONSE TIME VCTRL STEP
MAX19794 toc35
TIME (ns)
S21 (dB)
750500250
-25
-20
-15
-10
VCTRL STEP OCCURS AT t = t0
-5
0
-30
0 1000
VCTRL STEP FROM 3.15V TO 1V
VCTRL STEP FROM 4V TO 1V
TIME (ns)
S21 (dB)
4000300020001000
-25
-20
-15
-10
-5
0
-30
0 5000
MAX19794 toc38
MODE 0 TO 1 (CODE 700 TO 0)
MODE 1 TO 0 (CODE 1023 TO 0)
MODE 0 TO 1 (CODE 0 TO 700)
MODE 0 TO 1 (CODE 0 TO 1023)
MODE STEP OCCURS AT t = t0
RESPONSE TIME WITH MODE STEP
TIME (ns)
S21 (dB)
4000300020001000
-25
-20
-15
-10
-5
0
-30
0 5000
MAX19794 toc36
CS STEP OCCURS AT t = t0
CODE 0 TO 500
RESPONSE TIME WITH CS STEP
CODE 0 TO 700
CODE 0 TO 1023
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
12
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.).
SUPPLY CURRENT vs. VCC
MAX19794 toc39
VCC (V)
SUPPLY CURRENT (mA)
3.25 3.35
9
10
11
8
3.15 3.45
TC = -40°C
TC = +85°C
TC = +25°C
INPUT MATCH vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19794 toc40
RF FREQUENCY (MHz)
S11 (dB)
375250125
-40
-30
-20
C10 = C11 = 10nF
-10
0
-50
0 500
OUTPUT MATCH vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19794 toc41
RF FREQUENCY (MHz)
S22 (dB)
375250125
-40
-30
-20
C10 = C11 = 10nF
-10
0
-50
0 500
ATTENUATION vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19794 toc42
RF FREQUENCY (MHz)
S21 (dB)
375250125
-20
-10
0
-30
0 500
C10 = C11 = 10nF
ATTENUATION vs. DAC CODE
MAX19794 toc45
DAC CODE
S21 (dB)
768512256
-25
-20
-15
-10
-5
0
-30
0 1024
C10 = C11 = 10nF
10MHz, 55MHz, 100MHz, 200MHz
INPUT MATCH vs. DAC CODE
MAX19794 toc43
DAC CODE
S11 (dB)
768512256
-40
-30
-20
-10
0
-50
0 1024
C10 = C11 = 10nF
10MHz
100MHz
55MHz, 200MHz
ATTENUATION vs. DAC CODE
MAX19794 toc46
DAC CODE
S21 (dB)
768512256
-25
-20
-15
-10
-5
0
-30
0 1024
fRF = 55MHz
C10 = C11 = 10nF
TC = -40°C, +25°C, +85°C
OUTPUT MATCH vs. DAC CODE
MAX19794 toc44
DAC CODE
S22 (dB)
768512256
-40
-30
-20
-10
0
-50
0 1024
C10 = C11 = 10nF
10MHz
100MHz, 200MHz
55MHz
S21 PHASE CHANGE vs. DAC CODE
MAX19794 toc47
DAC CODE
S21 PHASE CHANGE (DEG)
768512256
-20
-10
0
10
20
30
-30
0 1024
C10 = C11 = 10nF 200MHz
100MHz
10MHz
55MHz
REFERENCED TO INSERTION LOSS STATE
POSITIVE PHASE = ELECTRICALLY SHORTER
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
13
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.).
INPUT MATCH vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19794 toc48
RF FREQUENCY (MHz)
S11 (dB)
375250125
-40
-30
-20
-10
0
-50
0 500
C10 = C11 = 100pF
OUTPUT MATCH vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19794 toc49
RF FREQUENCY (MHz)
S22 (dB)
375250125
-40
-30
-20
-10
0
-50
0 500
C10 = C11 = 100pF
ATTENUATION vs. RF FREQUENCY
OVER CODE SETTINGS
MAX19794 toc50
RF FREQUENCY (MHz)
S21 (dB)
375250125
-20
-10
0
-30
0 500
C10 = C11 = 100pF
INPUT MATCH vs. DAC CODE
MAX19794 toc51
DAC CODE
S11 (dB)
768512256
-40
-30
-20
-10
0
-50
0 1024
C10 = C11 = 100pF
500MHz
400MHz
300MHz
200MHz
OUTPUT MATCH vs. DAC CODE
MAX19794 toc52
DAC CODE
S22 (dB)
768512256
-40
-30
-20
-10
0
-50
0 1024
C10 = C11 = 100pF
500MHz
400MHz
300MHz
200MHz
ATTENUATION vs. DAC CODE
MAX19794 toc53
DAC CODE
S21 (dB)
768512256
-25
-20
-15
-10
-5
0
-30
0 1024
C10 = C11 = 100pF
200MHz
500MHz
300MHz, 400MHz
ATTENUATION vs. DAC CODE
MAX19794 toc54
DAC CODE
S21 (dB)
768512256
-25
-20
-15
-10
-5
0
-30
0 1024
fRF = 300MHz
C10 = C11 = 100pF
TC = -40°C, +25°C, +85°C
S21 PHASE CHANGE vs. DAC CODE
MAX19794 toc55
DAC CODE
S21 PHASE CHANGE (DEG)
768512256
-25
0
25
50
-50
0 1024
500MHz
400MHz
300MHz
REFERENCED TO INSERTION LOSS STATE
POSITIVE PHASE = ELECTRICALLY SHORTER
C10 = C11 = 100pF 200MHz
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
14
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.).
INPUT IP3 vs. VCNTL
MAX19794 toc56
VCNTL (V)
INPUT IP3 (dBm)
2.01.5
35
40
45
50
30
1.0 2.5
C10 = C11 = 10nF
LSB, USB
fRF = 55MHz
PIN = 0dBm /TONE
INPUT IP3 vs. VCNTL
MAX19794 toc57
VCNTL (V)
INPUT IP3 (dBm)
2.01.5
35
40
45
50
30
1.0 2.5
C10 = C11 = 10nF
LSB, USB
fRF = 100MHz
PIN = 0dBm /TONE
INPUT IP3 vs. VCNTL
MAX19794 toc58
VCNTL (V)
INPUT IP3 (dBm)
2.01.5
35
40
45
50
55
30
1.0 2.5
C10 = C11 = 100pF fRF = 250MHz
PIN = 0dBm /TONE
LSB, USB
INPUT IP3 vs. VCNTL
MAX19794 toc59
VCNTL (V)
INPUT IP3 (dBm)
2.01.5
35
40
45
50
55
30
1.0 2.5
C10 = C11 = 100pF fRF = 500MHz
PIN = 0dBm /TONE
LSB, USB
INPUT IP2 vs. VCNTL
MAX19794 toc62
VCNTL (V)
INPUT IP2 (dBm)
2.01.5
50
60
70
80
90
40
1.0 2.5
fRF = 100MHz
PIN = 0dBm/TONE C10 = C11 = 10nF
INPUT IP3 vs. VCNTL
MAX19794 toc60
VCNTL (V)
INPUT IP3 (dBm)
2.01.5
30
35
40
45
25
1.0 2.5
C10 = C11 = 10nF
-40°C, +25°C, +85°C. LSB, USB
fRF = 55MHz
PIN = 0dBm /TONE
INPUT IP2 vs. VCNTL
MAX19794 toc63
VCNTL (V)
INPUT IP2 (dBm)
2.01.5
50
60
70
80
90
40
1.0 2.5
fRF = 250MHz
PIN = 0dBm/TONE C10 = C11 = 100pF
INPUT IP2 vs. VCNTL
MAX19794 toc61
VCNTL (V)
INPUT IP2 (dBm)
2.01.5
50
60
70
80
90
40
1.0 2.5
fRF = 55MHz
PIN = 0dBm/TONE C10 = C11 = 10nF
INPUT IP2 vs. VCNTL
MAX19794 toc64
VCNTL (V)
INPUT IP2 (dBm)
2.01.5
50
60
70
80
90
40
1.0 2.5
fRF = 500MHz
PIN = 0dBm/TONE C10 = C11 = 100pF
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
15
Typical Operating Characteristics (continued)
(Typical Application Circuit, VCC = 3.3V, configured for single attenuator, RF ports are driven from 50I sources and loaded into 50I,
VDAC_LOGIC = 0V, RDBK_EN = logic 0, VCTRL = 1.0V, PIN = 0dBm, fRF = 55MHz, TC = +25NC, unless otherwise noted.).
INPUT IP2 vs. VCNTL
MAX19794 toc65
VCNTL (V)
INPUT IP2 (dBm)
2.01.5
50
60
70
80
90
40
1.0 2.5
fRF = 55MHz
PIN = 0dBm/TONE C10 = C11 = 10nF
-40°C, +25°C, +85°C
INPUT P1dB vs. RF FREQUENCY
MAX19794 toc66
RF FREQUENCY(MHz)
INPUT P1dB (dBm)
15010050
15
16
17
18
14
0 200
TA = +85°C
TA = +25°C TA = -40°C
C10 = C11 = 10nF
RESPONSE TIME VCTRL STEP
MAX19794 toc67
TIME (ns)
S21 (dB)
15001000500
-25
-20
-15
-10
-5
0
-30
0 2000
VCTRL STEP OCCURS AT t = t0
VCTRL STEP FROM 1V TO 2.08V
VCTRL STEP FROM 1V TO 2.5V
RESPONSE TIME WITH CS STEP
MAX19794 toc70
TIME (ns)
S21 (dB)
15001000500
-25
-20
-15
-10
-5
0
-30
0 2000
CODE 700 TO 0
CODE 500 TO 0
CODE 1023 TO 0
CS STEP OCCURS AT t = t0
RESPONSE TIME VCTRL STEP
MAX19794 toc68
TIME (ns)
S21 (dB)
750500250
-25
-20
-15
-10
-5
0
-30
0 1000
VCTRL STEP OCCURS AT t = t0
VCTRL STEP FROM 2.08V TO 1V
VCTRL STEP FROM 2.5V TO 1V
RESPONSE TIME WITH MODE STEP
MAX19794 toc71
TIME (ns)
S21 (dB)
4000300020001000
-25
-20
-15
-10
-5
0
-30
0 5000
MODE 1 TO 0 (CODE 700 TO 0)
MODE 1 TO 0 (CODE 1023 TO 0)
MODE 0 TO 1 (CODE 0 TO 700)
MODE 0 TO 1 (CODE 0 TO 1023)
MODE STEP OCCURS AT t = t0
RESPONSE TIME WITH CS STEP
MAX19794 toc69
TIME (ns)
S21 (dB)
4000300020001000
-25
-20
-15
-10
-5
0
-30
0 5000
CODE 0 TO 500
CODE 0 TO 700
CODE 0 TO 1023
CS STEP OCCURS AT t = t0
16
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Pin Description
Pin Configuration
PIN NAME DESCRIPTION
1, 3, 6, 7, 9, 10,
12, 26, 27, 28, 30,
33, 34, 36
GND Ground. Connect to the board’s ground plane using low-inductance layout techniques.
2 OUT_A Attenuator A RF Output. Internally matched to 50I over the operating frequency band. This pin,
if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected.
4, 31 RTNA, RTNB
Attenuator Ground Returns. These pins require a cap to ground and need to be placed close
to each pin. This capacitor centers the RF band of operation. See the Typical Operating
Characteristics section.
5 VCC Attentuator A Power Supply. Bypass to GND with a capacitor and a resistor as shown in the
Typical Application Circuit.
8 IN_A Attenuator A RF Input. Internally matched to 50I over the operating frequency band. This pin,
if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected.
11 CTRL
Attenuator Control Voltage Input. Except in the test mode where no voltage can be applied
to this pin. VCC must be present unless using a current-limiting resistor as noted in the
Applications Information section.
TQFN
6mm x 6mm
*INTERNALLY CONNECTED TO GND.
MODE
COMP_OUT
REF_SEL
REF_IN
CTRL
GND
VCC
GND
DAC_LOGIC
GND
RTNB
VCC
GND
IN_B
GND
GND
VCC
GND
GND
GND
RTNA
GND
OUT_A
GND
GND
VCC
CS
DOUT
DIN
CLK
UP
DWN
GND
TOP VIEW
GND
IN_A
OUT_B
MAX19794
35
36
34
33
12
11
10
13
14
12
EP*
4567
27 26 24 23 22
3
25
+
32
15
31
28
29
30 16
17
18
89
21 20 19
17
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Pin Description (continued)
PIN NAME DESCRIPTION
13 VCC Analog Supply Voltage. Bypass to GND with capacitor as close as possible to the device. See
the Typical Application Circuit.
14 REF_IN DAC Reference Voltage Input (Optional)
15 REF_SEL
DAC Reference Voltage Selection Logic Input
Logic = 0 enable on-chip DAC reference.
Logic = 1 use off-chip DAC reference (pin 14).
16 DAC_LOGIC DAC Logic Control Input. See Table 1.
17 COMP_OUT Comparator Logic OutputA 4.7pF capacitor could be used to reduce any potential rise time
glitching when the comparator changes state.
18 MODE
Attenuator Control Mode Logic Input
Logic = 1 enable attenuator step control.
Logic = 0 enable attenuator SPI control.
19 DWN Down Pulse Input
Logic pulse = 0 for each step-down.
20 UP Up Pulse Input
Logic pulse = 0 for each step-up.
19, 20 DWN/UP Logic = 0 to both pins to reset the attenuator to a minimum attenuation state
21 CLK SPI Clock Input
22 DIN SPI Data Input
23 DOUT SPI Data Output
24 CS SPI Chip Selection Input
25 VCC Digital Supply Voltage. Bypass to GND with capacitor as close as possible to the device as
possible. See the Typical Application Circuit.
29 OUT_B Attenuator B RF Output. Internally matched to 50I over the operating frequency band. This pin,
if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected.
32 VCC Attenuator B Power Supply. Bypass to GND with capacitor and resistor as shown in the Typical
Application Circuit.
35 IN_B Attenuator B RF Input. Internally matched to 50I over the operating frequency band. This pin,
if used, requires a DC block. If this attenuator is not used, the pin can be left unconnected.
— EP
Exposed Pad. Internally connected to GND. Solder this exposed pad to a PCB pad that uses
multiple ground vias to provide heat transfer out of the device into the PCB ground planes.
These multiple via grounds are also required to achieve the noted RF performance. See the
Layout Considerations section.
18
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Table 1. Attenuator Control Logic States
Detailed Description
The MAX19794 is a dual, general-purpose analog
voltage variable attenuator (VVA) designed to interface
with 50I systems operating in the 10MHz to 500MHz
frequency range. Each attenuator provides 22.4dB of
attenuation range with a linear control slope of 8dB/V.
Both attenuators share a common analog control and can
be cascaded together to yield 44.7dB of total dynamic
range with a combined linear control slope of 16dB/V.
Alternatively, the on-chip, 4-wire SPI-controlled 10-bit
DAC can be used to control both attenuators. In addition,
a step-up/down feature allows user-programmable
attenuator stepping through command pulses without
reprogramming the SPI interface.
Application Information
Attenuation Control and Features
The device has various states that are used to control the
analog attenuator along with some monitoring conditions.
The device can be controlled by an external control
voltage, an internal SPI bus, or a combination of the two.
The various states are described in Table 1. The SPI bus
has multiple registers that are used to control the device
when not configured for the analog only mode. For the
cases where CTRL is used, the control range is 1V to 4V
for VCC = 5V, and is 1V to 2.5V for VCC = 3.3V.
Up to 22.4dB of attenuation-control range is provided
per attenuator. At the insertion-loss setting, the single
attenuator’s loss is approximately 1.5dB. If a larger
attenuation-control range is desired, the second on-chip
attenuator can be connected in series to provide an
additional 22.4dB of gain-control range.
The on-chip control driver simultaneously adjusts both
on-chip attenuators. It is suggested that a current-limiting
resistor be included in series with CTRL to limit the input
current to less than 40mA, should the control voltage
be applied when VCC is not present. A series resistor
of greater than 200I provides complete protection for
+5.0V control voltage ranges.
Analog Mode Only Control
In Table 1 state (0, 0), the attenuators are controlled
using a voltage applied to the CTRL pin of the device and
the on-chip DAC is disabled. In the case where none of
the features of the SPI bus are needed, the part can be
operated in a pure analog control mode by grounding
pins 14 through 25.
DAC Mode Control
In Table 1 state (1, 0), the attenuators are controlled by
the on chip 10-bit DAC register. See the Register/Mode
section. In this condition, no signal is applied to the CTRL
pin and the load on the CTRL pin should be >100kI. The
DAC is set using the SPI loaded code in the registers
along with the setting of the mode pin.
Analog Mode Control with Alarm Monitoring
In Table 1 state (0, 1), the attenuators are controlled
using a voltage applied to the CTRL pin of the device.
See Register/Mode section. In this condition, the DAC
DAC_LOGIC RDBK_EN
(D9, REG3)
INTERNAL
SWITCH STATES ATTENUATOR 10-BIT DAC
0 0 S1 = closed
S2, S3, S4 = open
Controlled by external analog voltage on CTRL
(pin 11). Disabled
1 0 S1, S3, S4 = open
S2 = closed
Controlled by on-chip DAC. No voltage applied
to pin 11. Enabled
0 1 S1, S3, S4 = closed
S2 = open
Controlled by external analog voltage on CTRL
(pin 11). CTRL is compared with DAC output.
Comparator drives COMP_OUT (pin 17).
Enabled (update DAC
code to estimate CTRL
voltage on pin 11)
1 1 S1, S2 = closed
S3, S4 = open
Controlled by on-chip DAC. The DAC output is
connected to pin 11. Use this state to test the
DAC output. In this condition, no voltage can
be applied to pin 11 and the load on pin 11
must be > 100kI.
Enabled
19
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
is enabled and a voltage is also applied to CTRL (pin
11). The on-chip switches are set to compare the DAC
voltage to the CTRL voltage at the comparator input, and
the output of the comparator COMP_OUT trips from high
to low when the CTRL exceeds the on-chip DAC voltage.
DAC Test Mode
In Table 1 state (1, 1), the attenuators are controlled by
the on chip 10-bit DAC register. See Register MODE UP/
DWN Operation section. In this condition, the DAC is
enabled and the DAC voltage appears at the CTRL pin.
In this condition, no signal can be applied to the CTRL
pin and the load on the CTRL pin should be > 100kI.
This mode is used only in production testing of the DAC
voltage and is not recommended for customer use.
Register MODE UP/DWN Operation
The device uses four 13-bit registers for the operation of
the device. The first bit is the read/write bit,the following
two are address bits, while the remaining 10 are the
desired data bits. The read/write bit determines whether
the register is being written to or read from. The next two
address bits select the desired register to write or read
from. These address bits can be seen in Table 2. Table 3
describes the contents of the four registers.
Figure 1 shows the configuration of the internal registers
of the device, and Figure 2 shows the timing of the
SPI bus. Register 0 is used to set the DAC code to the
desired value, register 1 selects the step-up code, and
register 2 selects the step-down code.
The part also contains a MODE control pin (Table 4),
along with UP and DWN controls(Table 5). When MODE
is 0, the contents of register 0 get loaded into the 10-bit
DAC register and set the value of the on-chip DAC. In this
condition, the UP and DWN control pins have no effect on
the part. In MODE 1, the effective DAC code fed to the
10-bit DAC register is equal to:
m x Register 1 - n x Register 2
where m and n are the number of UP and DWN control
steps accumulated, respectively.
After powering up the part, UP and DWN should both
be set to 0 to reset the m and n counters to be 0. This
results in a 10-bit all 0 code out of the mathematical block
in Figure 1. This is applied to the 10-bit DAC register that
drives the DAC. To increase (decrease) the code using
the UP (DWN) pin, the DWN (UP) pin must be high and
the UP (DWN) pin should be pulsed low to high. The part
is designed to produce no wraparounds when using UP
and DWN stepping, so the DAC code maxes out at 1023
or goes no lower than 0. See Figure 3 for the UP and
DWN control operation.
Switching back to MODE 0 produces the same 10-bit DAC
code as was previously loaded into register 0. Switching
back to MODE = 1 results in the previous 10-bit DAC code
from the register 1 and 2 combiner/multiplier block.
Register 3 is used to set the RDBK_EN register in the
write mode and is used to read back the RDBK_EN
register and COMP_OUT in the read mode.
SPI Interface
The device can be controlled with a 4-wire SPI-compatible
serial interface. Figure 2 shows a timing diagram for the
interface. In the write mode, a 13-bit word is loaded into
the device through the DIN pin with CS set low. The first
bit of the word in the write mode is 0, and the next two
bits select the register to be written to. See Table 2. The
next 10 bits contain the data to be written to the selected
register. After the 13 bits are shifted in, a low to high CS
command is applied and this latches the 10 bits into the
selected register. The entire write command is ignored
if CS is pulsed low to high before the last data bit is
successfully captured.
For the read cycle, the first bit clocked in is a 1 and this
establishes that a register is to be read. The next two
clocked bits form the address of the register to be read.
See Table 2. In this read mode, data starts to get clocked
out of the DOUT pin after A0 is captured. The DOUT
pin goes to a high-impedance state after the 10 bits are
transmitted, or if CS goes high at any point in time during
the transmission.
Voltage Reference
The device has an on-chip voltage reference for the
DAC and also has a provision to operate with an off-
chip reference. Table 6 provides details in selecting the
desired reference.
20
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Register 3 Write Bits
RDBK_EN= Enable bit for voltage comparator that drives COMP_OUT (pin 17).
Register 3 Read Bits
RDBK_EN= Enable bit for voltage comparator that drives COMP_OUT (pin 17),
COMP_OUT=Read Logic level of COMP_OUT (pin 17).
Table 2. Component Suppliers
Table 3. Register Definitions
Register 0 (Read/Write 10-Bit DAC Code)
Register 1 (Read/Write 10-Bit Step-Up Code)
Register 2 (Read/Write 10-Bit Step-Down Code)
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RDBK_EN Not used,
set = 0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RDBK_EN COMP_OUT Not used,
set = 0
R/W A1 A0 DESCRIPTION
0 0 0 Write to register 0 using DIN
0 0 1 Write to register 1 using DIN
0 1 0 Write to register 2 using DIN
0 1 1 Write to register 3 using DIN
1 0 0 Read from register 0 using DOUT
1 0 1 Read from register 1 using DOUT
1 1 0 Read from register 2 using DOUT
1 1 1 Read from register 3 using DOUT
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DAC
MSB
DAC
LSB
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Step-up MSB Step-up LSB
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Step-down
MSB
Step-down
LSB
21
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Figure 1. Register Configuration Diagram
Table 4. Attenuator Control Mode Logic State
Table 5. Step Mode Logic State (MODE = 1)
Table 6. REF_SEL Logic State
*Continued up or down stepping results in saturation (no code wrapping).
MODE
(PIN 17) ATTENUATOR
0SPI Control Mode (DAC code is located in register 0)
1Step Control Mode using UP and DWN pins. The step-up code is located in register 1 and step-down code in
register 2).
UP DWN ATTENUATOR
Logic 0 Logic 0 Reset DAC for minimum attenuation state (DAC code = 0000000000).
Logic 0 Pulse Logic 1 Increase DAC code* by amount located in register 1.
UP pulsed from high to low to high (Figure 3).
Logic 1 Logic 0 Pulse Decrease DAC code* by amount located in register 2.
DWN pulsed from high to low to high (Figure 3).
REF_SEL DAC REFERENCE
0Uses on-chip DAC reference.
1User provides off-chip DAC reference voltage on REF_IN (pin 14).
m x REGISTER 1 - n x REGISTER 2
m = NUMBER OF UP PULSES
n = NUMBER OF DOWN PULSES
RESET TO ALL ZEROS WHEN UP/DOWN
PULSED TOGETHER
OR
10-BIT DAC
REGISTER
REGISTER 3
REGISTER 2
REGISTER 1
REGISTER 0
m
n
DOWN
UP
MODE
DINDOUT
22
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Layout Considerations
A properly designed PCB is an essential part of any
RF/microwave circuit. Keep RF signal lines as short as
possible to reduce losses, radiation, and inductance. For
best performance, route the ground-pin traces directly
to the exposed pad underneath the package. This pad
must be connected to the ground plane of the board by
using multiple vias under the device to provide the best
RF and thermal conduction path. Solder the exposed
pad on the bottom of the device package to a PCB.
RF Ground Return Capacitors
The device requires RF ground return capacitors C10
and C11. The value of these capacitors optimize the
dynamic range and frequency flatness for the RF band of
interest. Some recommended values are shown in Table
7 along with the resulting performance in the Typical
Operating Characteristics section.
Figure 2. SPI Timing Diagram Figure 3. UP DWN Control Diagram (Mode = 1)
SPI Interface Programming
Table 7. Typical Application Circuit Component Values
*Add 2 additional 10
I
resistors between the VCC pins leading to C5 and C6 unless a VCC power plane is used.
DESIGNATION QTY DESCRIPTION
C1, C2, C4 30.01FF Q5% 50V X7R ceramic capacitors (0402).
C3 0 Not installed for two attenuators in cascade
C5–C9 5 1000pF Q5% 50V COG ceramic capacitors (0402)
C10, C11 2
10MHz to 200MHz 0.01FF Q10% 50V X7R ceramic capacitors
(0402)
250MHz to 500MHz 100pF Q5% 50V COG ceramic capacitors
(0402)
C12 1 120pF Q5% 50V COG CER CAP (0402).Provides some external noise filtering along with R3.
C13 0 Not installed. A 4.7pF capacitor could be used to reduce any potential rise time glitching when
the comparator changes state.
R1*, R2* 210I Q5% resistor (0402)
R3 1
200I Q5% resistor (0402). This resistor is used to provide some lowpass noise filtering when
used with C12. The value of R3 slows down the response time. R3 also provides protection for
the device in case VCTRLis applied without VCC present.
U1 1 MAX19794
R/WA1A0 D9, D8...D0 TO REGISTER 0, 1, 2, 3
CS
CLK
DIN
D9, D8...D0 FROM REGISTER 0, 1, 2, 3
DOUT
tCS
HIGH-ZHIGH-Z
tCW tES
tEW
tCH
tEWS
UP
1
1
0
0
DWN
NO DAC
CODE CHANGE
DAC CODE
INCREASED
BY STEP UP
DAC CODE
DECREASED
BY STEP DOWN
DAC CODE
RESET TO
ALL 0's
23
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Power-Supply Bypassing
Proper voltage-supply bypassing is essential for high
frequency circuit stability. Bypass each VCC pin with
capacitors placed as close as possible to the device.
Place the smallest capacitor closest to the device. See
the Typical Application Circuit and Table 7 for details.
Exposed Pad RF and Thermal
Considerations
The exposed pad (EP) of the device’s 36-pin TQFN
package provides a low thermal-resistance path to the die.
It is important that the PCB on which the device is mounted
to conduct heat from this contact. In addition, provide the
EP with a low-inductance RF ground path for the device.
The EP must be soldered to a ground plane on the PCB,
either directly or through an array of plated via holes.
Soldering the pad to ground is also critical for efficient
heat transfer. Use a solid ground plane wherever possible.
Typical Application Circuit
MAX19794
EP
C1
RFIN_A
VCC
IN_B
GND
234 56 7
S1
S2
S3 S4
89
10
11
12
13
14
DAC
15
16
17
18
192021222324252627
28
29
ATTEN_B
ATTEN_A
30
31
32
33
34
35
36
OUT_A
GND
IN_A
OUT_B
1
ATTENUATION-
CONTROL
CIRCUITRY
GND
RTNA
GND
GND
GND
R1
C5
VCC
CTRL
GND C12
C7
C13
C8
VCTRL
REF_IN
R3
GND
GND
GND
GND
NOTE: FOR ATTENUATOR A ONLY CONFIGURATION, REMOVE C3 AND MOVE C2 DIAGONALLY TO CONNECT PIN 2 TO THE OUTPUT CONNECTION RF_AB.
FOR ATTENUATOR B ONLY CONFIGURATION, REMOVE C2.
FOR CASCADED CONFIGURATION, REMOVE C3 AND USE C2 TO CONNECT OUT_A TO IN_B.
GND
RTNB
REF_IN
REF_SEL REF_SEL
DAC_LOGIC DAC_LOGIC
MODE MODE
COMP_OUT COMP_OUT
VCC R2
C4
C3
C6
C9
C2
RFOUT_B
RF_AB
VCC
GND
GND
VCC
VCC
CS
CS
VCC
VCC
DOUT
DOUT
DIN
DIN
CLK
CLK
UP
UP
DWN
DWN
C11
C10
24
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Chip Information
PROCESS: BiCMOS
Ordering Information
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
PART TEMP RANGE PIN-PACKAGE
MAX19794ETX+ -40NC to +100NC36 TQFN-EP*
MAX19794ETX+T -40NC to +100NC36 TQFN-EP*
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND PATTERN
NO.
36 TQFN T3666+2 21-0141 90-0049
MAX19794
10MHz to 500MHz Dual Analog Voltage Variable
Attenuator with On-Chip 10-Bit SPI-Controlled DAC
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 6/12 Initial release —
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 25
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products Inc.
