MIC59P60BV - Micrel, Inc. - Datasheet.Live

August 2001 1 MIC59P60

MIC59P60 Micrel

Ordering Information

Part Number Temperature Range Package

MIC59P60BN –40°C to +85°C 20-Pin Plastic DIP

MIC59P60BV –40°C to +85°C 20-Pin PLCC

MIC59P60BWM –40°C to +85°C 20-Pin Wide SOIC

11 19 18 17 16 15 13 12

210

CLOCK

SERIAL

DATA IN

VSS

CLEAR

UVLO

THERMAL

SHUTDOWN ILIMIT

K OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8

SUB

VEE

MOS

BIPOLAR

OUTPUT

ENABLE/RESET

STROBE

VDD

SERIAL DATA OUT

FLAG

8-BIT SERIAL–PARALLEL SHIFT REGISTER

LATCHES

Features

•3.3 MHz Minimum Data-Input Rate

•Output Current Shutdown (500mA Typical)

•Under Voltage Lockout

•Thermal Shutdown

•Output Fault Flag

•CMOS, PMOS, NMOS, and TTL Compatible

•Internal Pull-Up/Pull-Down Resistors

•Low Power CMOS Logic and Latches

•High Voltage Current Sink Outputs

•Output Transient-Protection Diodes

•Single or Split Supply Operation

UVLO

I LIMIT

THERMAL

SHUTDOWN

SUB

SHIFT REGISTER

LATCHES

CLEAR

VEE

CLOCK

SERIAL DATA IN

VSS

VDD

SERIAL DATA OUT

STROBE

ENABLE/RESET

VEE

OUTPUT

FLAG

OUTPUT 1

OUTPUT 2

OUTPUT 3

OUTPUT 4

OUTPUT 5

OUTPUT 6

OUTPUT 7

OUTPUT 8

Pin Configuration

(DIP and SOIC)

MIC59P60

8-Bit Serial-Input Protected Latched Driver

General Description

The MIC59P60 serial-input latched driver is a high-voltage

(80V), high-current (500mA) integrated circuit comprised of

eight CMOS data latches, a bipolar Darlington transistor

driver for each latch, and CMOS control circuitry for the

common CLEAR, STROBE, CLOCK, SERIAL DATA INPUT,

and OUTPUT ENABLE functions. Similar to the MIC5842,

additional protection circuitry supplied on this device includes

thermal shutdown, under voltage lockout (UVLO), and over-

current shutdown.

The bipolar/CMOS combination provides an extremely low-

power latch with maximum interface flexibility. The MIC59P60

has open-collector outputs capable of sinking 500mA and

integral diodes for inductive load transient suppression with

a minimum output breakdown voltage rating of 80V (50V

sustaining). The drivers can be operated with a split supply,

where the negative supply is down to –20V and may be

paralleled for higher load current capability.

Using a 5V logic supply, the MIC59P60 will typically operate

at better than 5MHz. With a 12V logic supply, significantly

higher speeds are obtained. The CMOS inputs are compat-

ible with standard CMOS, PMOS, and NMOS circuits. TTL

circuits may require pull-up resistors. By using the serial data

output, drivers may be cascaded for interface applications

requiring additional drive lines.

Each of these eight outputs has an independent over current

shutdown of 500 mA. Upon over-current shutdown, the

affected channel will turn OFF and the flag will go low until VDD

is cycled or the ENABLE/RESET pin is pulsed high. Current

pulses less than 2µs will not activate current shutdown.

Temperatures above 165°C will shut down the device and

activate the error flag. The UVLO circuit prevents operation

at low VDD; hysteresis of 0.5V is provided.

Functional Diagram

Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com

MIC59P60 2 August 2001

MIC59P60 Micrel

Pin Description

Pin Name Description

1 CLEAR Sets All Latches OFF (open).

2,10 VEE Output Ground (Substrate). Most negative voltage in the system connects

here.

3 CLOCK Serial Data Clock. A CLEAR must also be clocked into the latches.

4 SERIAL DATA IN Serial Data Input pin.

SS Logic reference (Ground) pin.

DD Logic Positive Supply voltage.

7 SERIAL DATA OUT Serial Data Output pin. (Flow through).

8 STROBE Output Strobe pin. Loads output latches when High. A STROBE is needed

to CLEAR latches.

9 OUTPUT ENABLE/RESET When Low, Outputs are active. When High, device is inactive and reset

from a fault condition. An under voltage condition emulates a high OE/

RESET input.

11 K Transient suppression diode's cathode common pin.

12—19 OUTPUT N Open Collector outputs 8 through 1.

20 FLAG Error Flag. Open-collector output is Low upon Overcurrent Fault or

Overtemperature fault. OUTPUT ENABLE/RESET must be pulled high to

reset the flag and fault condition.

Absolute Maximum Ratings VSS = 0; TA = 25°C

Output Voltage (VCE) ....................................................80V

Output Voltage (VCE(SUS)) ...............................50V, Note 1

VDD with Reference to VSS ...........................................15V

VDD with Reference to VEE ...........................................25V

Emitter Supply Voltage (VEE) ......................................–20V

Input Voltage (VIN) ............................... –0.3V to VDD+0.3V

Protected Current............................................1.5A, Note 2

Power Dissipation (PD)

Plastic DIP (N).........................................................2.0W

Derate above TA = +25°C ............................20mW/°C

PLCC (V).................................................................1.4W

Derate above TA = +25°C ............................14mW/°C

Wide SOIC (WM) ....................................................1.2W

Derate above TA = +25°C ............................12mW/°C

Operating Temperature (TA)

Plastic DIP (N), PLCC (V), SOIC (WM)..–40°C to +85°C

Storage Temperature (TS) .......................–65°C to +150°C

Junction Temperature (TJ) ......................................+150°C

ESD ......................................................................... Note 3

Note 1: For inductive load applications.

Note 2: Each channel. VEE connection must be designed to minimize

inductance and resistance.

Note 3: Devices are input-static protected but can be damaged by

extremetly high static charges.

PLCC Pin

Configuration

CLOCK

SERIAL

DATA IN

STROBE

OUTPUT

ENABLE

SUB

OUT

123

12 1311

20 19

910

OUT 1

OUT 2

OUT 3

OUT 4

OUT 5

OUT 6

OUT 7

OUT 8

SERIAL DATA OUT

VSS

SERIAL DATA IN

STROBE

CLEAR

OE/RESET

VDD

FLAG

VEE

MIC59P60BV

CLOCK

VEE

Typical Inputs

Typical Output Driver

August 2001 3 MIC59P60

MIC59P60 Micrel

Electrical Characteristics

VDD = 5V, VSS = VEE = 0V; TA = +25°C; unless noted.

Limits

Characteristic Symbol Test Conditions Min. Typ. Max. Unit

Output Leakage Current ICEX VOUT = 80V 50 µA

VOUT = 80V, TA = +70°C 100

Collector-Emitter VCE(SAT) IOUT = 100mA 0.9 1.1 V

Saturation Voltage IOUT = 200mA 1.1 1.3

IOUT = 350mA 1.3 1.6

Collector-Emitter VCE(SUS) IOUT = 350mA, L = 2mH 50 V

Sustaining Voltage

Input Voltage VIN(0) 1.0 V

VIN(1) VDD = 12V 10.5 V

VDD = 10V 8.5

VDD = 5.0V, Note 4 3.5

Input Resistance RIN VDD = 12V 50 200 kΩ

VDD = 10V 50 300

VDD = 5.0V 50 600

Flag Output Current IOL VOL = 0.4V 15 mA

Flag Output Leakage IOH VOH = 12.0V 50 nA

Supply Current IDD(ON) All Drivers ON, VDD = 12V 6.4 10.0 mA

All Drivers ON, VDD = 10V 6.0 9.0

All Drivers ON, VDD = 5.0V 4.6 7.5

IDD (1 OUTPUT) One Driver ON, All others OFF, VDD = 12V 3.1 4.5 mA

One Driver ON, All others OFF, VDD = 10V 2.9 4.5

One Driver ON, All others OFF, VDD = 5V 2.3 3.6

IDD(OFF) All Drivers OFF, VDD = 12V 2.6 4.2 mA

All Drivers OFF, VDD = 10V 2.4 3.6

All Drivers OFF, VDD = 5.0V 1.9 3.0

Clamp Diode IRVR = 80V 50 µA

Leakage Current

Clamp Diode VFIF = 350mA 1.7 2.0 V

Forward Voltage

Over Current ILIM 500 mA

Shutdown Threshold

Start Up Voltage VSU Note 5 3.5 4.0 4.5 V

Minimum Supply (VDD)V

DD MIN 3.0 3.5 4.0 V

Thermal Shutdown 165 °C

Thermal Shutdown Hysteresis 10 °C

Note 4: Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to insure a minimum logic "1".

Note 5: Undervoltage lockout is guaranteed to release device at no more than 4.5V, and disable the device at no less than 3.0V

MIC59P60 4 August 2001

MIC59P60 Micrel

Timing Conditions

(TA = +25°C, Logic Levels are VDD and VSS, VDD = 5V)

A. Typical Data Active Time Before Clock Pulse (Data Set-Up Time) ...........................................................................75 ns

B. Minimum Data Active Time After Clock Pulse (Data Hold Time)..............................................................................75 ns

C. Minimum Data Pulse Width .....................................................................................................................................150 ns

D. Minimum Clock Pulse Width....................................................................................................................................150 ns

E. Minimum Time Between Clock Activation and Strobe .............................................................................................300 ns

F. Minimum Strobe Pulse Width...................................................................................................................................100 ns

G. Typical Time Between Strobe Activation and Output Transition .............................................................................500 ns

SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input

pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL

DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Holding CLEAR high results in a data

logic "0" being clocked into the shift register, turning off respective channels.

Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel conversion).

The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed

(STROBE tied high) will require that the ENABLE input be high to prevent invalid output states.

When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the latches

or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches. A positive OE/RESET pulse

resets the FLAG and the output after a current shutdown fault. Over-temperature faults are not latched and require no reset

pulse.

CLOCK

DATA IN

STROBE

OUTPUT

ENABLE

OUTN

MIC59P60 Truth Table

Serial Shift Register Contents Serial Latch Contents Output Contents

Data Clear Clock Data Strobe Output

Input Input Input I1I2I3…… I8Output Input I1I2I3…… I8Enable I1I2I3…… I8

HHR

1R2…… R7R7

LLR

1R2…… R7R7

XR1R2R

3…… R8R8

H OOO…… OL

XXX…… XXLR

1R2R3…… R8

P1P2P3…… P8P8HP

1P2P3…… P8LP

1P2P3……P8

XX X…… XH HHH…… H

L = Low Logic Level

H = High Logic Level

X = Irrelevant

P = Present State

R = Previous State

O = Output OFF

August 2001 5 MIC59P60

MIC59P60 Micrel

Typical Characteristic Curves

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

1.5

–50 0 50 100 150

SATURATION VOLTAGE (V)

TEMPERATURE (°C)

Output Saturation

Voltage vs. Temperature

= 350mA

= 100mA

= 5V to 12V

0.35

0.40

0.45

0.50

0.55

0.60

–50 0 50 100 150

SHUTDOWN THRESHOLD (A)

TEMPERATURE (°C)

= 5V

= 12V

Current Shutdown

Threshold vs. Temperature

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

1.5

-50 0 50 100 150

SATURATION VOLTAGE (V)

TEMPERATURE (°C)

Output Saturation

Voltage vs. Temperature

VDD = 12V

IL = 350mA

IL = 100mA

–50 0 50 100 150

SUPPLY CURRENT (mA)

TEMPERATURE (°C)

Supply Current

vs. Temperature

ALL OUTPUTS ON

ALL OUTPUTS OFF

= 12V

0.3 0.4 0.5 0.6 0.7 0.8 0.9

CURRENT LIMIT DELAY (µS)

OUTPUT CURRENT (A)

Current Shutdown

Delay vs. Output Current

= 12V

= 5V

–50 0 50 100 150

SUPPLY CURRENT (mA)

TEMPERATURE (°C)

ALL OUTPUTS ON

ALL OUTPUTS OFF

Supply Current

vs. Temperature

= 5V

MIC59P60 6 August 2001

MIC59P60 Micrel

Typical Applications

+48V

CLOCK

SERIAL

DATA IN

+5V

ENABLE 0.1µ

22µ +

CLEAR

FLAG

10k

UVLO

I LIMIT

THERMAL

SHUTDOWN

SUB

SHIFT REGISTER

LATCHES

Protected Solenoid Driver with Output Enable

Number of Outputs ON

(IOUT = 200mA Max. Allowable Duty Cycle at Ambient Temperature of

VDD = 12V) 25°C40°C50°C60°C70°C

8 80% 68% 60% 52% 44%

7 91% 77% 68% 59% 50%

6 100% 90% 79% 69% 58%

5 100% 100% 95% 82% 69%

4 100% 100% 100% 100% 86%

3 100% 100% 100% 100% 100%

2 100% 100% 100% 100% 100%

1 100% 100% 100% 100% 100%

Number of Outputs ON

(IOUT = 200mA Max. Allowable Duty Cycle at Ambient Temperature of

VDD = 5.0V) 25°C40°C50°C60°C70°C

8 85% 72% 64% 55% 46%

7 97% 82% 73% 63% 53%

6 100% 96% 85% 73% 62%

5 100% 100% 100% 88% 75%

4 100% 100% 100% 100% 93%

3 100% 100% 100% 100% 100%

2 100% 100% 100% 100% 100%

1 100% 100% 100% 100% 100%

VDD = 12V

Maximum Allowable Duty Cycle (Plastic DIP)

VDD = 5.0V

August 2001 7 MIC59P60

MIC59P60 Micrel

10k

RFC

1000p

+75V

Transmitter

10k

RFC1000p

+75V

10k

RFC

1000p

+75V

RFC

Antenna

Receiver

Diode

D1 D2 D3

(Latch 1) (Latch 5) (Latch 8)

Receive OFF ACTIVE OFF

Transmit ACTIVE OFF ACTIVE

+75V

PIN Diodes: UM9651

CLOCK

STROBE

DATA IN

–5V

+5V

0.01µ

0.1µ

100µ

UVLO

I LIMIT

THERMAL

SHUTDOWN

FLAG

+5V

10k

SUB

SHIFT REGISTER

LATCHES

Protected Negative/Positive PIN Diode Driver Transmit/Receive Switch

Hammer Driver

CLOCK

SERIAL

DATA IN

+5V +28V

28V

0.1µ

22µ +

FLAG

CLEAR

10k

UVLO

I LIMIT

THERMAL

SHUTDOWN

SUB

SHIFT REGISTER

LATCHES

MIC59P60 8 August 2001

MIC59P60 Micrel

Package Information

0.020

(0.508)

0.018±0.003

(0.457±0.076)

PIN 1

1.070

(27.178)

.250±0.005

(6.350±0.127)

0.060±0.005

(1.524±0.127)

0.100±0.010

(2.540±0.254)

MAX

0.030-0.110

(0.762-2.794) RAD

0.125

(3.175) MIN

0.020

(0.508) MIN

0.130±0.005

(3.302±0.127)

+0.025

–0.015

+0.635

–0.381

0.325

8.255

()

0°-10°

0.290-0.320

(7.336-8.128)

0.040

(1.016)TYP

20-Pin Plastic DIP (N)

0.022 (0.559)

0.018 (0.457)

5°

TYP

0.408 (10.363)

0.404 (10.262)

0.509 (12.929)

0.505 (12.827)

0.103 (2.616)

0.099 (2.515)

SEATING

PLANE

0.027 (0.686)

0.031 (0.787) 0.016 (0.046)

TYP

0.301 (7.645)

0.297 (7.544)

0.094 (2.388)

0.090 (2.286)

0.297 (7.544)

0.293 (7.442)

10° TYP

0.032 (0.813) TYP

0.330 (8.382)

0.326 (8.280)

7°

TYP

0.050 (1.270)

TYP

0.015

(0.381)R

0.015

(0.381)

MIN

PIN 1

DIMENSIONS:

INCHES (MM)

20-Pin Wide SOP (WM)

August 2001 9 MIC59P60

MIC59P60 Micrel

TOP VIEW

0.390

±0.020

0.351

±0.003

0.310

±.015

0.050

0.045

0.080

BOTTOM VIEW 0.035 R

±0.015

0.030 DIA

x 0.015 R DEPTH

DET AIL A

0.110

0.170

0.018

0.110

0.027

SIDE VIEW

DETAIL A

0.300

0.045

20-Pin PLCC (V)

MIC59P60 10 August 2001

MIC59P60 Micrel

August 2001 11 MIC59P60

MIC59P60 Micrel

MIC59P60 12 August 2001

MIC59P60 Micrel

MICREL INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or

other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.