Features
n165MHz closed-loop – -3dB bandwidth
n15ns settling to 0.05%
n1mV input offset voltage, 10µV/°C drift
n100mA output current
nExcellent AC and DC linearity
nDirect replacement for CLC231
Applications
nDriving flash A/D converters
nPrecision line driving
(a gain of 2 cancels matched-line losses)
nDAC current-to-voltage conversion
nLow-power, high-speed applications (50mW @ ±5V)
General Description
The KH231 Buffer/Amplifier is a wideband operational
amplifier designed specifically for high-speed, low-
gain applications. The KH231 is based on a current
feedback op amp topology-a unique design that both
eliminates the gain-bandwidth tradeoff and permits
unprecedented high-speed performance. (See table below.)
The KH231 Buffer/Amplifier is the ideal design alter-
native to low precision open-loop buffers and oscillation-
prone conventional op amps. The KH231 offers precise
gains from ±1.000 to ±-5.000 and linearity that is a
true 0.1%-even for demanding 50Ωloads. Open-loop
buffers, on the other hand, offer a nominal gain of
0.95 ±0.03 and a linearity of only 3% for typical loads.
A buffer’s settling time may look impressive but it is
usually specified at unrealistically large load resis-
tances or when the effects of thermal tail are not
included; the KH231 Buffer/Amplifier settles to 0.05%
in 15ns-while driving a 100Ωload.
Offsets and drifts, usually a low priority in conven-
tional high-speed op amp designs, were not ignored
in the KH231; the input offset voltage is typically 1mV
and input offset voltage drift is only 10µV/°C. The
KH231 is stable and oscillation-free across the entire
gain range and since it’s internally compensated, the
user is saved the trouble of designing external com-
pensation networks and having to “tweak” them in
production. The absence of a gain-bandwidth trade-
off in the KH231 allows performance to be predicted
easily; the table below shows how the bandwidth is
affected very little by changing the gain setting.
The KH231 is constructed using thin film resistor/bipolar
transistor technology, and is available in the following
versions:
The KH231 is constructed using thin film resistor/bipolar
transistor technology, and available in these versions:
KH231AI -25°C to +85°C 12-pin TO-8 can
KH231AK -55°C to +125°C 12-pin TO-8 can, features
burn-in & hermetic testing
KH231AM -55°C to +125°C 12-pin TO-8 can,
environmentally
screened and electrically
tested to MIL-STD-883
KH231HXC -55°C to +125°C SMD#: 5962-8959401HXC
KH231HXA -55°C to +125°C SMD#: 5962-8959401HXA
KH231
Fast Settling, Wideband Buffer/Amplifier (Av= ±1 to ±5)
REV. 1A January 2004
Small Signal Pulse Response
Output Voltage (400mV/div)
Time (5ns/div)
K
Av= -2
Av= 2
Supply
Voltage
8
Adjust
7
GND
9
-VCC
2
Adjust
3
GND
1
+VCC
6
V+
5
V-
4
NC
10
-VCC
Vo
+VCC
11
12
4
4
Collector
Supply
Output
Collector
Supply
Supply
Voltage
ICC Adjust
ICC Adjust
Case
ground
Non-Inverting
Input
Inverting
Input
Not
Connected
Case
ground
+
-
Bottom View
Pins 2 and 8 are used to adjust the supply current or to adjust the off-
set voltage (see text). These pins are normally left unconnected.
Typical Performance
Gain Setting
Parameter 1 2 5 -1 -2 -5 Units
-3dB bandwidth 180 165 130 165 150 115 MHz
rise time (2V) 1.8 2.0 2.5 2.0 2.2 2.9 ns
slew rate 2.5 3.0 3.0 3.0 3.0 3.0 V/ns
settling time (to 0.1%) 12 12 12 12 12 15 ns
www.cadeka.com
2REV. 1A January 2004
DATA SHEET KH231
PARAMETERS CONDITIONS TYP MIN & MAX RATINGS UNITS SYM
Ambient Temperature KH231AI +25°C -25°C +25°C +85°C
Ambient Temperature KH231AK/AM/HXC/HXA +25°C -55°C +25°C +125°C
FREQUENCY DOMAIN RESPONSE
=-3dB bandwidth (note 2) Vo≤2Vpp 165 >145 >145 >120 MHz SSBW
large-signal bandwidth Vo≤10Vpp 95 >80 >80 >60 MHz FPBW
gain flatness (note 2) Vo≤2Vpp
=peaking 0.1 to 50MHz 0.1 <0.6 <0.3 <0.6 dB GFPL
=peaking >50MHz 0.1 <1.5 <0.3 <0.8 dB GFPH
=rolloff at 100MHz 0.4 <0.6 <0.6 <1.0 dB GFR
group delay to 100MHz 3.5 ± 0.5 – – – ns GD
linear phase deviation to 100MHz 0.5 <2.0 <2.0 <2.0 ° LPD
reverse isolation
non-inverting 53 >43 >43 >43 dB RINI
inverting 36 >26 >26 >26 dB RIIN
TIME DOMAIN RESPONSE
rise and fall time 2V step 2.0 <2.4 <2.3 <2.7 ns TRS
10V step 5.0 <7.0 <6.5 <6.5 ns TRL
settling time to 0.05% 5V step 15 – – – ns TS
to 0.1% 2.5V step 12 <22 <17 <22 ns TSP
overshoot 5V step 5 <15 <10 <15 % OS
slew rate (overdriven input) 3.0 >2.5 >2.5 >1.8 V/ns SR
overload recovery <1% error
<50ns pulse, 200% overdrive 120 – – – ns OR
NOISE AND DISTORTION RESPONSE
=2nd harmonic distortion 0dBm, 20MHz -55 <-47 <-47 <-47 dBc HD2
=3rd harmonic distortion 0dBm, 20MHz -59 <-47 <-47 <-47 dBc HD3
equivalent input noise
noise floor >5MHz -153 <-150 <-150 <-150 dBm(1Hz) SNF
integrated noise 5MHz to 200MHz 70 <100 <100 <100 µVrms INV
STATIC, DC PERFORMANCE
* input offset voltage 1 <4.0 <2.0 <4.5 mV VIO
average temperature coefficient 10 <25 <25 <25 µV/°C DVIO
* input bias current non-inverting 5.0 <29 <21 <31 µA IBN
average temperature coefficient 50 <125 <125 <125 nA/°C DIBN
* input bias current inverting 10 <31 <15 < 35 µA IBI
average temperature coefficient 125 <200 <200 <200 nA/°C DIBI
* power supply rejection ratio 50 >45 >45 >45 dB PSRR
common mode rejection ratio 46 >40 >40 >40 dB CMRR
* supply current no load 18 <22 <22 <22 mA ICC
MISCELLANEOUS PERFORMANCE
non-inverting input resistance DC 400 >100 >200 >400 kΩRIN
non-inverting input capacitance 1.3 <2.5 <2.5 <2.5 pF CIN
output impedance @ 100MHz 5, 37 – – – Ω, nH RO
output voltage range no load ±12 >±11 >±11 >±11 V VO
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings Recommended Operating Conditions
VCC ±20V VCC ±5V to ±15V
Io±100mA Io±75mA
common mode input voltage, Vo(see Vcm and Vocommon mode input voltage ±(|VCC| -5)V
limits plot on page 3) gain range ±1 to ±5
differential input voltage ±3V
thermal resistance (see thermal model)
junction temperature +175°C
operating temperature AI: -25°C to +85°C
AK/AM: -55°C to +125°C
storage temperature -65°C to +150°C
lead temperature (soldering 10s) +300°C
KH231 Electrical Characteristics (TA= +25°C, Av= +2V, VCC = ±15V, RL= 100Ω, Rf= 250Ω; unless specified)
note 1: * AI/AK/AM/HXC/HXA 100% tested at +25°C
=AK/AM/HXC/HXA 100% tested at +25°C and sample
tested at -55°C and +125°C
=AI sample tested at +25°C
note 2: The output amplitude used in testing is 0.63Vpp. Performance
is guaranteed for conditions listed.
note 3: In the noninverting configuration, care should be taken when
choosing Ri, the input impedance setting resistor; bias
currents of typically 5µA but as high as 24µA can create an
input signal large enough to cause overload. It is therefore
recommended that Ri< (VCC/Av)/24µA.
note 4: These ratings protect against damage to the input stage
caused by saturation of either the input or output stages at
lower supply voltages, and against exceeding transistor
collector-emitter breakdown ratings at high supply voltages.
Vout(max) is calculated by assuming no output saturation.
Saturation is allowed to occur up to this calculated level of
Vout. Vcm is defined as the voltage at the non-inverting
input, pin 6.
KH231 DATA SHEET
REV. 1A January 2004 3
KH231 Typical Performance Characteristics (TA= +25°C, Av= +2, VCC = ±15V, RL= 100Ω,Rf= 250Ω; unless specified)
Non-Inverting Frequency Response
Normalized Magnitude (1dB/div)
Frequency (MHz)
K
0100 200
Gain
Phase
Phase (45 deg/div)
Av= 5
Av= 1
Av= 2
Av= 5
Av= 2
Av= 1
Inverting Frequency Response
Normalized Magnitude (1dB/div)
Frequency (MHz)
K
0100 200
Gain
Phase
Phase (45 deg/div)
Av= -5
Av= -1
Av= -2
Av= -5
Av= -2
Av= -1
Broadband Gain and Phase
Magnitude (10dB/div)
Frequency (MHz)
K
0500 1000
Gain
Phase
Phase (180 deg/div)
Av= 2
Bandwidth vs. VCC
Relative Bandwidth
±VCC (V)
K
46810 12 14 16
Pins 1 and 2 Shorted
Pins 8 and 9 shorted
0.4
0.6
0.8
1.0
1.2
Frequency Response vs. RL
(1dB/div)
Frequency (MHz)
K
0125 250
RL= 1K
Av= 2
RL= 200
RL= 100
RL= 50
Full Power Gain vs. Frequency
(1dB/div)
Frequency (MHz)
K
0100 200
Inverting
Non-Inverting
Av= 2
Vo= 10Vpp
2-Tone, 3rd Order Intermod. Intercept
Intercept Point (+dBm)
Frequency (MHz)
K
0100
20 40 60 80
Av= 2
20
30
35
40
50
45
25
Equivalent Input Noise
Noise Voltage (nV/√Hz)
Frequency (Hz)
K
100 10M
1k 10k 100k 1M
Inverting Current 23.8pA/√Hz
Non-Inverting Current 2.5pA/√Hz
Voltage 2.8nV/√Hz
1
10
100
Noise Current (pA/√Hz)
1
10
100
100M
Small Signal Pulse Response
Output Voltage (400mV/div)
Time (5ns/div)
K
Av= -2
Av= 2
Large Signal Pulse Response
Output Voltage (2V/div)
Time (5ns/div)
K
Av= -2
Av= 2
Settling Time
K
50ns/div
5ns/div
Settling Error (%)
Time (ns)
-0.20
-0.15
0.05
0.10
0.20
0.15
0
-0.05
-0.10
Vcm and VoVoltage Limits
K
note 4
on page 2
|Vout| max
|Vcm| max
Indicated Voltage
|±VCC| (V)
0510 20
0
5
10
20
15
15
|Vout| max
|Vcm| max
CMRR and PSRR
K
CMRR
PSRR
PSRR/CMRR (dB)
Frequency (Hz)
1 10 100 1k 10k 100k 100M
10
30
40
50
1M 10M
20
DATA SHEET KH231
4REV. 1A January 2004
Operation
The KH231 Buffer/Amplifier is based on the current feed-
back op amp topology, a design that uses current feed-
back instead of the usual voltage feedback.
The use of the KH231 is basically the same as that of the
conventional op amp (see Figures 1 and 2). Since the
device is designed specifically for low gain applications,
the best performance is obtained when the circuit is used
at gains between ±1 and ±5. Additionally, performance is
optimum when a 250Ωfeedback resistor is used.
Figure 1: Recommended non-inverting gain circuit
Figure 2: Recommended inverting gain circuit
Layout Considerations
To assure optimum performance the user should follow
good layout practices which minimize the unwanted
coupling of signals between nodes. During initial bread-
boarding of the circuit use direct point to point wiring,
keeping the lead lengths to less than 0.25”. The use of
solid, unbroken ground plane is helpful. Avoid wire-wrap
type pc boards and methods. Sockets with small, short
pin receptacles may be used with minimal performance
degradation although their use is not recommended.
During pc board layout keep all traces short and direct
The resistive body of Rgshould be as close as possible
to pin 5 to minimize capacitance at that point. For the
same reason, remove ground plane from the vicinity of
pins 5 and 6. In other areas, use as much ground plane
as possible on one side of the board. It is especially
important to provide a ground return path for current from
the load resistor to the power supply bypass capacitors.
Ceramic capacitors of 0.01 to 0.1µf (with short leads)
should be less than 0.15 inches from pins 1 and 9.
Larger tantalum capacitors should be placed within one
inch of these pins. VCC connections to pins 10 and 12
can be made directly from pins 9 and 1, but better supply
rejection and settling time are obtained if they are
separately bypassed as in figures 1 and 2. To prevent
signal distortion caused by reflections from impedance
mismatches, use terminated microstrip or coaxial cable
when the signal must traverse more than a few inches.
Since the pc board forms such an important part of the
circuit, much time can be saved if prototype boards of
any high frequency sections are built and tested early in
the design phase. Evaluation boards designed for either
inverting or non-inverting gains are available.
Distortion and Noise
The graphs of intercept point, I2and I3, versus
frequency on the preceding page make it easy to predict
the distortion at any frequency given the output voltage of
the KH231. First, convert the output voltage (Vo) to Vrms
= (Vpp/2√2) and then to P = [(10log10(20Vrms2)] to get the
power output in dBm. At the frequency of interest, its 2nd
harmonic will be S2= (I2-P)dB below the level of P. Its
third harmonic will be S3= 2(I3- P)dB below P, as will the
two-tone third order intermodulation products. These
approximations are useful for P < -1dB compression levels.
Approximate noise figure can be determined for the
KH231 using the equivalent input noise graph on the
preceding page. The following equation can be used to
determine noise figure (F) in dB.
Where Vnis the rms noise voltage and inis the rms noise
current. Beyond the breakpoint of the curves (i.e., where
they are flat), broadband noise figure equals spot noise fig-
ure, so ∆f should equal one (1) and Vnand inshould be
read directly off the graph. Below the breakpoint, the noise
must be integrated and ∆f set to the appropriate bandwidth.
33Ω
+15V
0.1
3.9 .01
Capactance in µF
1
12
5
3,7 RL
100Ω
10
11
33Ω
.01
0.1
3.9
-15V
9
+
-
KH231 Vo
Rf= 250Ω
6
Rg
Vin
Ri
49.9Ω
AR
R
vf
g
=1+
250Ω
33Ω
+15V
0.1
3.9 .01
Capactance in µF
1
12
5
3,7 RL
100Ω
10
11
33Ω
.01
0.1
3.9
-15V
9
+
-
KH231 Vo
Rf= 250Ω
For Zin = 50Ω, select
Rg|| Ri= 50Ω
6
100Ω
Vin
Ri
250Ω
Rg
AR
R
v
f
g
= −
F 10log 1
ViR
A
4kTR f
n
2n
2f2
v2
s
=+
+
∆
KH231 DATA SHEET
REV. 1A January 2004 5
θca = 65°C/W for the KH231 without heat sink in still air.
30°C/W for the KH231 with a Wakefield 215 heat
sink in still air.
10°C/W for the KH231 with a Wakefield 215 heat
sink at 300 ft/min air.
30°C/W for the KH231 with a Thermalloy 2240A
heat sink in still air.
5°C/W for the KH231 with a Thermalloy 2240A
heat sink at 500 ft/min air.
For example, with the KH231 operating at ±15V while
driving a 100Ωload at 15Vpp output (50% duty cycle
pulse waveform, DC = 0), P(npn) = P(pnp) = 190mW (Rcol
= 33) and P(cir) = 0.48W. Then with the Wakefield
215 heat sink and air flow of 300 ft/min the output
transistors’ Tjis 28°C above ambient and worst case Tjin
the rest of the circuit is 32°C above ambient. In still air,
however, the rise in Tjis 45°C and 49°C, respectively.
With no heat sink, the rise in Tjis 75°C and 79°C,
respectively! Under most conditions, HEAT SINKING IS
REQUIRED.
Other methods of heat sinking may be used, but for
best results, make contact with the base of the KH231
package, use a large thermal capacity heat sink and use
forced air convection.
Low VCC Operation: Supply Current Adjustment
The KH231 is designed to operate on supplies as low as
±5V. In order to improve full bandwidth at reduced sup-
ply voltages, the supply current (ICC) must be increased.
The plot of Bandwidth vs. VCC, shows the effect of short-
ing pins 1 and 2 and pins 8 and 9; this will increase both
bandwidth and supply current. Care should be taken to
not exceed the maximum junction temperatures; for this
reason this technique should not be used with supplies
exceeding ±10V. For intermediate values of VCC,
external resistors between pins 1 and 2 and pins 8 and 9
can be used.
Offset Voltage Adjustment
If trimming of the input offset voltage (Vos = Vni -Vin) is
desired, a resistor value of 10kΩto 1MΩplaced between
pins 8 and 9 will cause Vos to become more negative by
8mV to 0.2mV respectively. Similarly, a resistor placed
between pins 1 and 2 will cause Vos, to become more
positive.
Thermal Considerations
At high ambient temperatures or large internal power
dissipations, heat sinking is required to maintain
acceptable junction temperatures. Use the thermal
model on the previous page to determine junction
temperatures. Many styles of heat sinks are available for
TO-8 packages; the Thermalloy 2240 and 2268 are good
examples. Some heat sinks are the radial fin type which
cover the pc board and may interfere with external
components. An excellent solution to this problem is to
use surface mounted resistors and capacitors. They
have a very low profile and actually improve high
frequency performance. For use of these heat sinks with
conventional components, a 0.1” high spacer can be inserted
under the TO-8 package to allow sufficient clearance.
P(circuit) = (ICC)((+VCC) – (VCC)) where ICC = 16mA at ±15V
P(xxx) = [(±VCC) – Vout – (Icol) (Rcol + 4)] (Icol) (%Duty)
For positive Voand VCC, this is the power in the npn
device. For negative Voand VCC, this is the power in the
pnp device.
Icol = Vo/RLor 4mA, whichever is greater. (Include feed-
back R in RL.)
Rcol is a resistor (33Ωrecommended) between the xxx
collector and ±VCC.
The limiting factor for output current and voltage is junction
temperature. Of secondary importance is I(out), which
should not exceed 150mA.
Tj(pnp) = P(pnp) (100 + θca) + (P(cir) + P(npn))(θca) + Ta,
similar for Tj(npn).
Tj(cir) = P(cir)(48 + θca) + (P(pnp) + P(npn))(θca) + Ta.
+
-
Tambient
θca
Tcase
17.5°C/W
Tj(circuit)
Pcircuit
100°C/W
Tj(npn)
Pnpn
100°C/W
Ppnp
Tj(pnp)
KH231 Package Dimensions
DATA SHEET KH231
SYMBOL INCHES MILIMETERS
Minimun Maximum Minimum Maximum
A 0.142 0.181 3.61 4.60
φb 0.016 0.019 0.41 0.48
φD 0.595 0.605 15.11 15.37
φD10.543 0.555 13.79 14.10
e 0.400 BSC 10.16 BSC
e
10.200 BSC 5.08 BSC
e
20.100 BSC 2.54 BSC
F 0.016 0.030 0.41 0.76
k 0.026 0.036 0.66 0.91
k
10.026 0.036 0.66 0.91
L 0.310 0.340 7.87 8.64
α45°BSC 45°BSC
NOTES:
Seal: cap weld
Lead finish: gold per MIL-M-38510
Package composition:
Package: metal
Lid: Type A per MIL-M-38510
87 9
23 1
5
6
4
11
10
12
k1
e
φDD
1
TO-8
e1
e2
kα
L
A
F
φb
Life Support Policy
Cadeka’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Cadeka Microcircuits, Inc.
As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used
in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect
its safety or effectiveness.
Cadeka does not assume any responsibility for use of any circuitry described, and Cadeka reserves the right at any time without notice to change said circuitry and specifications.
www.cadeka.com © 2004 Cadeka Microcircuits, LLC