SP7651ER-L/TR - Sipex Corporation

SP7651

FEATURES

■2.5V to 20V Step Down Achieved Using Dual Input

■Output Voltage down to 0.8V

■3A Output Capability (Up to 5A with Air Flow)

■Built in Low RDSON Power FETs (40 mΩ typ)

■Highly Integrated Design, Minimal Components

■900 kHz Fixed Frequency Operation

■UVLO Detects Both VCC and VIN

■Over Temperature Protection

■Short Circuit Protection with Auto-Restart

■Wide BW Amp Allows Type II or III Compensation

■Programmable Soft Start

■Fast Transient Response

■High Efficiency: Greater than 92% Possible

■Asynchronous Start-Up into a Pre-Charged Output

■Small 7mm x 4mm DFN Package

Wide Input Voltage Range 3A, 900kHz, Buck Regulator

The SP7651 is a high voltage synchronous step-down switching regulator optimized for high efficiency. The part is

designed to be especially attractive for dual supply, 12V step down with 5V used to power the controller. This lower VCC

voltage minimizes power dissipation in the part. The SP7651 is designed to provide a fully integrated buck regulator

solution using a fixed 900kHz frequency, PWM voltage mode architecture. Protection features include UVLO, thermal

shutdown and output short circuit protection. The SP7651 is available in the space saving 7mm X 4mm DFN package.

Advanced

TYPICAL APPLICATION CIRCUIT

Now Available in Lead Free Packaging

DESCRIPTION

13 14

TOP VIEW

Heatsink Pad 1

Connect to Lx

Heatsink pad 2

Connect to GND

Heatsink pad 3

Connect to VIN

PGND

GND

VFB

COMP

UVIN

GND

VIN

VCC

GND

BST

DFN PACKAGE

7mm x 4mm

SP7651

PGND

VIN

CBST

6800pF

4.7uH, Irate=3.87A

22uF

CVCC

2.2uF

SP7651

PGND

GND

VFB

COMP

UVIN

GND

VIN

13 LX 14

LX 15

LX 16

NC 17

BST 18

GND 19

GND 20

GND 21

VCC 22

LX 23

LX 24

LX 25

LX 26

DBST

CSS

15nF

CP1

22pF

3.3V

0-3A

RSET

21.5k,1%

GND

22uF

Notes:

12V

VIN

1. U1 Bottom-Side Layout should

has three contacts isolated from

one another Vin SWNODE and GND

SD101AWS

VOUT

RZ3

7.15k,1%

CZ3

150pF

CZ2

1,000pF

68.1k,1%

RZ2

15k,1%

CF1

100pF

fs=900Khz

+5V VCC

ENABLE

2. RSET=54.48/(Vout-0.8V) (KOhm)

6.3V

(note 2)

16V

ELECTRICAL SPECIFICATIONS

Unless otherwise specified: -40°C < TAMB < 85°C, -40°C<Tj<125°C, 4.5V < VCC < 5.5V, 3V<Vin<20V, BST=LX + 5V, LX =

GND = 0V, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V.

The ♦ denotes the specifications which apply over the full temperature range, unless otherwise specified.

These are stress ratings only and functional operation of the device at

these ratings or any other above those indicated in the operation sections

of the specifications below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may affect reliability.

VCC .................................................................................................. 7V

VIN ........................................................................................................................................... 22V

ILX ............................................................................................................................................... 5A

BST ............................................................................................... 35V

BST-SWN ......................................................................... -0.3V to 7V

SWN ................................................................................... -1V to 20V

GH ......................................................................... -0.3V to BST+0.3V

GH-SWN ......................................................................................... 7V

All other pins .......................................................... -0.3V to VCC+0.3V

Storage Temperature .................................................. -65°C to 150°C

Power Dissipation .................................................... Internally Limited

Lead Temperature (Soldering, 10 sec) ...................................... 300°C

ESD Rating .......................................................................... 2kV HBM

Thermal Resistance ϑJC .................................................................................... 5°C/W

ABSOLUTE MAXIMUM RATINGS

RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC

TNERRUCTNECSEIUQ

)gnihctiwsoN(tnerruCylppuS5.13 AmV

V9.0=

)gnihctiws(tnerruCylppuS61DBTAm♦

)gnihctiwsoN(tnerruCylppuSTSB2.04.0AmV

V9.0=

)gnihctiws(tnerruCylppuSTSB8DBTAm♦

OLVU:NOITCETORP

dlohserhTtratSOLVU00.452.45.4V

siseretsyHOLVU001002003Vm

dlohserhTtratSNIVU3.25.256.2V

♦

siseretsyHNIVU002003004Vm

tnerruCtupnINIVU1AµV0.3=NIVU

ECNEREFERREIFILPMARORRE

ecnerefeRreifilpmArorrE297.0008.0808.0V erusaeM,.gifnoCniaGX2

Cº52=T,V5=

ecnerefeRreifilpmArorrE

erutarepmeTdnaeniLrevO 887.0008.0218.0V

♦

ecnatcudnocsnarTreifilpmArorrE6V/Am

niaGreifilpmArorrE06BddaoLoN

tnerruCkniSPMOC051AµV

V9.0=PMOC,V9.0=

tnerruCecruoSPMOC051AµV

V2.2=PMOC,V7.0=

tnerruCsaiBtupnI05002AnV

V8.0=

eloPlanretnI4zHM

pmalCPMOC5.2VV

Cº52=AT,V7.0=

tneiciffeoC.pmeTpmalCPMOC2-Cº/Vm

ELECTRICAL SPECIFICATIONS

Unless otherwise specified: -40°C < TAMB < 85°C, -40°C<Tj<125°C, 4.5V < VCC < 5.5V, 3V<Vin<20V, BST=LX + 5V, LX =

GND = 0V, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V.

The ♦ denotes the specifications which apply over the full temperature range, unless otherwise specified.

RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC

HTAPYALEDPOOL&PMAR,ROTARAPMOCMWP:POOLLORTNOC

edutilpmApmaR29.01.182.1V

tesffOPMAR1.1V

PMOCPMAR,Cº52=

gnihctiwSstratsHGlitnu

tneiciffeoC.pmeTtesffOPMAR2-Cº/Vm

htdiWesluPmuminiMHG09081sn♦

oitaRytuDelballortnoCmumixaM2979%

oitaRytuDmumixaM

erofebtsujderusaeM

snigebgnislup

oitaRytuDmumixaM001%selcyc02rofdilaV

oitaRrotallicsOlanretnI018009099zHk ♦

TRATSTFOS:SREMIT

:tnerruCegrahCSS01Aµ

:tnerruCegrahcsiDSS1Am♦V2.0=SS,tneserPtluaF

lamrehT&tiucriCtrohS:NOITCETORP

egatloVdlohserhTtiucriCtrohS2.052.03.0V

♦VderusaeM

FER

-)V8.0(

tuoemiTpucciH002smV

V5.0=

selcyCkcolCelbawollAforebmuN

elcyCytuD%001ta 02selcyC

selcyC02retfAesluPLGmuminiM5.0selcyCV

V7.0=

erutarepmeTnwodtuhSlamrehT541CºV

V7.0=

erutarepmeTyrevoceRlamrehT531Cº

siseretsyHlamrehT01Cº

EGATSREWOP:TUPTUO

RediShgiH

NOSD

04 ΩmV

I;V5=

TUO

A3=

BMA

Cº52=

RTEFsuonorhcnyS

NOSD

04 ΩmV

I;V5=

TUO

A3=

BMA

Cº52=

tnerruCtuptuOmumixaM3A

General Overview

The SP7651 is a fixed frequency, voltage mode,

synchronous PWM regulator optimized for high

efficiency. The part has been designed to be

especially attractive for split plane applications

utilizing 5V to power the controller and 2.5V to

28V for step down conversion.

The heart of the SP7651 is a wide bandwidth

transconductance amplifier designed to accom-

modate Type II and Type III compensation

schemes. A precision 0.8V reference, present on

the positive terminal of the error amplifier per-

mits the programming of the output voltage

down to 0.8V via the VFB pin. The output of the

error amplifier, COMP, which is compared to a

1.1V peak-to-peak ramp is responsible for trail-

ing edge PWM control. This voltage ramp, and

PWM control logic are governed by the internal

oscillator that accurately sets the PWM fre-

quency to 900kHz.

THEORY OF OPERATION

The SP7651 contains two unique control fea-

tures that are very powerful in distributed appli-

cations. First, asynchronous driver control is

enabled during start up, to prohibit the low side

NFET from pulling down the output until the

high side NFET has attempted to turn on. Sec-

ond, a 100% duty cycle timeout ensures that the

low side NFET is periodically enhanced during

extended periods at 100% duty cycle. This guar-

antees the synchronized refreshing of the BST

capacitor during very large duty ratios.

The SP7651 also contains a number of valuable

protection features. Programmable UVLO al-

lows the user to set the exact VIN value at which

the conversion voltage can safely begin down

conversion, and an internal VCC UVLO ensures

that the controller itself has enough voltage to

properly operate. Other protection features in-

PIN DESCRIPTION

#niPemaNniPnoitpircseD

3-1P

DNG

reifitcersuonorhcnysehtrofnoitcennocdnuorG

12-91,8,4DNG

erarevirdrewoprewoldnaCIehtfoyrtiucriclortnocehT.niPdnuorG

)-(ehtotsecartdnuorgrehtomorfyletarapesnruteR.nipsihtotdecnerefer

.tuoCfolanimret

tupnignitrevniehtsitI.nipnoitceteDtiucriCtrohSdnaegatloVkcabdeeF

roftniopkcabdeefegatlovtuptuoehtsasevresdnareifilpmArorrEehtfo

detsujdaebnacdnadesnessiegatlovtuptuoehT.retrevnoCkcuBeht

VrevenehW.redividrotsiserlanretxenahguorht

ehtwolebV52.0spord

puccihsretneCIehtdnadetcetedsitluaftiucrictrohsa,ecnereferevitisop

.edom

6PMOC

tupnignitrevniehtotdetcennocyllanretnisitI.reifilpmArorrEehtfotuptuO

dnanesohcsinoitanibmocretliflamitponA.rotarapmocMWPehtfo

Vrodnuorgrehtiednanipsihtotdetcennoc

egatlovehtezilibatsot

.pooledom

7NIVU VneewtebredividrotsiseratcennoC.egatlovniVroftupniOLVU

dna

egatlovgnitarepomuminimtesot

9SS

ehttesotDNGdnaSSneewtebroticapaclanretxenatcennoC.tratStfoS

woldlehsinipSSehT.tnerrucecruosAµ01ehtnodesabetartratstfos

.snoitidnoctluafllagnirudtnerruc)nim(Am1aaiv

31-01V

gnilpuocedaecalP.TEFSOMlennahc-NedishgihehtotnoitcennoctupnI

.DNGPdnanipsihtneewtebroticapac

62-32,61-41XLVdnanipsihtneewtebrotcudninatcennoC

TUO

22V

ylppussaibV5lanretxeroftupnI

71CNtcennoCoN

clude thermal shutdown and short-circuit detec-

tion. In the event that either a thermal, short-

circuit, or UVLO fault is detected, the SP7651 is

forced into an idle state where the output drivers

are held off for a finite period before a re-start is

attempted.

Soft Start

“Soft Start” is achieved when a power converter

ramps up the output voltage while controlling

the magnitude of the input supply source cur-

rent. In a modern step down converter, ramping

up the positive terminal of the error amplifier

controls soft start. As a result, excess source

current can be defined as the current required to

charge the output capacitor.

IVIN = COUT * (DVOUT / DTSOFT-START)

The SP7651 provides the user with the option to

program the soft start rate by tying a capacitor

from the SS pin to GND. The selection of this

capacitor is based on the 10uA pull up current

present at the SS pin and the 0.8V reference

voltage. Therefore, the excess source can be

redefined as:

IVIN = COUT * (DVOUT *10µA / (CSS * 0.8V)

Under Voltage Lock Out (UVLO)

The SP7651 contains two separate UVLO com-

parators to monitor the internal bias (VCC) and

conversion (VIN) voltages independently. The

VCC UVLO threshold is internally set to 4.25V,

whereas the VIN UVLO threshold is program-

mable through the UVIN pin. When the UVIN

pin is greater than 2.5V, the SP7651 is permitted

to start up pending the removal of all other

faults. Both the VCC and VIN UVLO compara-

tors have been designed with hysteresis to pre-

vent noise from resetting a fault.

Thermal and Short-Circuit

Protection

Because the SP7651 is designed to drive large

output current, there is a chance that the power

converter will become too hot. Therefore, an

internal thermal shutdown (145°C) has been

included to prevent the IC from malfunctioning

at extreme temperatures.

A short-circuit detection comparator has also

been included in the SP7651 to protect against

an accidental short at the output of the power

converter. This comparator constantly monitors

the positive and negative terminals of the error

amplifier, and if the VFB pin falls more than

250mV (typical) below the positive reference, a

short-circuit fault is set. Because the SS pin

overrides the internal 0.8V reference during soft

start, the SP7651 is capable of detecting short-

circuit faults throughout the duration of soft

start as well as in regular operation.

Handling of Faults:

Upon the detection of power (UVLO), thermal,

or short-circuit faults, the SP7651 is forced into

an idle state where the SS and COMP pins are

pulled low and the NFETS are held off. In the

event of UVLO fault, the SP7651 remains in this

idle state until the UVLO fault is removed.

Upon the detection of a thermal or short-circuit

fault, an internal 200ms timer is activated. In the

event of a short-circuit fault, a re-start is at-

tempted immediately after the 200ms timeout

expires. Whereas, when a thermal fault is de-

tected the 200ms delay continuously recycles

and a re-start cannot be attempted until the

thermal fault is removed and the timer expires.

Error Amplifier and Voltage Loop

Since the heart of the SP7651 voltage error loop

is a high performance, wide bandwidth

transconductance amplifier great care should be

taken to select the optimal compensation net-

work. Because of the amplifier’s current lim-

ited (+/-150µA) transconductance, there are

many ways to compensate the voltage loop or to

THEORY OF OPERATION

control the COMP pin externally. If a simple,

single pole, single zero response is desired, then

compensation can be as simple as an RC to

ground. If a more complex compensation is

required, then the amplifier has enough band-

width (45° at 4 MHz) and enough gain (60dB) to

run Type III compensation schemes with ad-

equate gain and phase margins at cross over

frequencies greater than 50kHz.

The common mode output of the error amplifier

is 0.9V to 2.2V. Therefore, the PWM voltage

ramp has been set between 1.1V and 2.2V to

ensure proper 0% to 100% duty cycle capability.

The voltage loop also includes two other very

important features. One is asynchronous start up

mode. Basically, the synchronous rectifier can

not turn on unless the high side NFET has

attempted to turn on or the SS pin has exceeded

1.7V. This feature prevents the controller from

“dragging down” the output voltage during

startup or in fault modes. The second feature is

a 100% duty cycle timeout that ensures synchro-

nized refreshing of the BST capacitor at very

high duty ratios. In the event that the high side

NFET is on for 20 continuous clock cycles, a

reset is given to the PWM flip flop half way

through the 21st cycle. This forces GL to rise for

the cycle, in turn refreshing the BST capacitor.

Power MOSFETs

The SP7651 contains a pair of integrated low

resistance N MOSFETs designed to drive up to

3A of output current. Maximum output current

could be limited by thermal limitations of a

particular application. The SP7651 incorpo-

rates a built-in over-temperature protection to

prevent internal overheating.

Voltage

V(VIN)

-0V

-V(Diode) V

V(VIN)+V(VCC)

BST

Voltage

V(VCC)

TIME

SWN

Voltage

VBST

VSWN

V(VCC)

The SP7651 can be set to different output

voltages. The relationship in the following

formula is based on a voltage divider from the

output to the feedback pin VFB, which is set

to an internal reference voltage of 0.80V.

Standard 1% metal film resistors of surface

mount size 0603 are recommended.

Vout = 0.80V ( R1 / R2 + 1 ) => R2 = R1 / [ (

Vout / 0.80V ) – 1 ]

Where R1 = 68.1KΩ and for Vout = 0.80V

setting, simply remove R2 from the board.

Furthermore, one could select the value of R1

and R2 combination to meet the exact output

voltage setting by restricting R1 resistance

range such that 50KΩ < R1 < 100KΩ for

overall system loop stability.

Setting Output Voltages

APPLICATIONS INFORMATION

Inductor Selection

There are many factors to consider in selecting

the inductor including core material, inductance

vs. frequency, current handling capability, effi-

ciency, size and EMI. In a typical SP7651 cir-

cuit, the inductor is chosen primarily by operat-

ing frequency, saturation current and DC resis-

tance. Increasing the inductor value will de-

crease output voltage ripple, but degrade tran-

sient response. Low inductor values provide the

smallest size, but cause large ripple currents,

poor efficiency and more output capacitance to

smooth out the larger ripple current. The induc-

tor must be able to handle the peak current at the

switching frequency without saturating, and the

copper resistance in the winding should be kept

as low as possible to minimize resistive power

loss. A good compromise between size, loss and

cost is to set the inductor ripple current to be

within 20% to 40% of the maximum output

current.

The switching frequency and the inductor oper-

ating point determine the inductor value as fol-

lows:

(max)(max )

(max)

)(

OUTrSIN

OUTINOUT

IKFV

VVV

L−

where:

Fs = switching frequency

Kr = ratio of the ac inductor ripple current to the

maximum output current

The peak to peak inductor ripple current is:

LFV

VVV

SIN

OUTINOUT

(max)

(max) )( −

Once the required inductor value is selected, the

proper selection of core material is based on

peak inductor current and efficiency require-

ments. The core must be large enough not to

saturate at the peak inductor current

(max)

OUTPEAK

II +=

and provide low core loss at the high switching

frequency. Low cost powdered iron cores are

inappropriate for 900kHz operation. Gapped

ferrite inductors are widely available for consid-

eration. Select devices that have operating data

shown up to 1MHz. Ferrite materials, on the

other hand, are more expensive and have an

abrupt saturation characteristic with the induc-

tance dropping sharply when the peak design

current is exceeded. Nevertheless, they are pre-

ferred at high switching frequencies because

they present very low core loss and the design

only needs to prevent saturation. In general,

ferrite or molyperm alloy materials will be used

with the SP7651.

Optimizing Efficiency

The power dissipated in the inductor is equal to

the sum of the core and copper losses. To mini-

mize copper losses, the winding resistance needs

to be minimized, but this usually comes at the

expense of a larger inductor. Core losses have a

more significant contribution at low output cur-

rent where the copper losses are at a minimum,

and can typically be neglected at higher output

currents where the copper losses dominate. Core

loss information is usually available from the

magnetic vendor. Proper inductor selection can

affect the resulting power supply efficiency by

more than 15-20%!

The copper loss in the inductor can be calculated

using the following equation:

WINDINGRMSLCuL

RIP

)()(

where IL(RMS) is the RMS inductor current that

can be calculated as follows:

IL(RMS) = IOUT(max) 1 + 1

(

IPP

)

3 IOUT(max)

Output Capacitor Selection

The required ESR (Equivalent Series Resis-

tance) and capacitance drive the selection of the

type and quantity of the output capacitors. The

ESR must be small enough that both the resis-

tive voltage deviation due to a step change in the

load current and the output ripple voltage do not

exceed the tolerance limits expected on the

output voltage. During an output load transient,

the output capacitor must supply all the addi-

tional current demanded by the load until the

SP7651 adjusts the inductor current to the new

value.

In order to maintain VOUT, the capacitance must

be large enough so that the output voltage is held

up while the inductor current ramps up or down

to the value corresponding to the new load

current. Additionally, the ESR in the output

capacitor causes a step in the output voltage

equal to the current. Because of the fast transient

response and inherent 100% and 0% duty cycle

capability provided by the SP7651 when ex-

posed to output load transient, the output ca-

pacitor is typically chosen for ESR, not for

capacitance value.

The output capacitor’s ESR, combined with the

inductor ripple current, is typically the main

contributor to output voltage ripple. The maxi-

mum allowable ESR required to maintain a

specified output voltage ripple can be calculated

by:

RESR ≤ ∆VOUT

IPK-PK

where:

∆VOUT = Peak to Peak Output Voltage Ripple

IPK-PK = Peak to Peak Inductor Ripple Current

The total output ripple is a combination of the

ESR and the output capacitance value and can

be calculated as follows:

∆

VOUT =

(

IPP (1 – D)

)

2 + (IPPRESR)2

COUTFS

FS = Switching Frequency

D = Duty Cycle

COUT = Output Capacitance Value

Input Capacitor Selection

The input capacitor should be selected for ripple

current rating, capacitance and voltage rating.

The input capacitor must meet the ripple current

requirement imposed by the switching current.

In continuous conduction mode, the source cur-

rent of the high-side MOSFET is approximately

a square wave of duty cycle VOUT/VIN. Most of

this current is supplied by the input bypass

capacitors. The RMS value of input capacitor

current is determined at the maximum output

current and under the assumption that the peak

to peak inductor ripple current is low, it is given

by: ICIN(rms) = IOUT(max)

√

D(1 - D)

The worse case occurs when the duty cycle D is

50% and gives an RMS current value equal to

IOUT/2.

Select input capacitors with adequate ripple

current rating to ensure reliable operation.

The power dissipated in the input capacitor is:

)(

)( CINESRrmsCINCIN RIP =

This can become a significant part of power

losses in a converter and hurt the overall energy

transfer efficiency. The input voltage ripple

primarily depends on the input capacitor ESR

and capacitance. Ignoring the inductor ripple

current, the input voltage ripple can be deter-

mined by:

APPLICATIONS INFORMATION

)(

)((max)

)(

ININS

OUTINOUTMAXOUT

CINESRoutIN

VCF

VVVI

RIV −

+=∆

The capacitor type suitable for the output capac-

itors can also be used for the input capacitors.

However, exercise extra caution when tantalum

capacitors are used. Tantalum capacitors are known

for catastrophic failure when exposed to surge

current, and input capacitors are prone to such

surge current when power supplies are connected

“live” to low impedance power sources.

Loop Compensation Design

The open loop gain of the whole system can be

divided into the gain of the error amplifier,

PWM modulator, buck converter output stage,

and feedback resistor divider. In order to cross

over at the selected frequency FCO, the gain of

the error amplifier has to compensate for the

attenuation caused by the rest of the loop at this

frequency.

The goal of loop compensation is to manipulate

loop frequency response such that its gain

crossesover 0db at a slope of -20db/dec. The

first step of compensation design is to pick the

loop cross over frequency.

High cross over frequency is desirable for fast

transient response, but often jeopardizes the

system stability. Cross over frequency should

be higher than the ESR zero but less than 1/5 of

the switching frequency. The ESR zero is con-

tributed by the ESR associated with the output

capacitors and can be determined by:

ƒZ(ESR) = 1

2π COUT RESR

The next step is to calculate the complex conju-

gate poles contributed by the LC output filter,

ƒP(LC) = 1

2π L COUT

When the output capacitors are of a Ceramic

Type, the SP7651 Evaluation Board requires a

Type III compensation circuit to give a phase

boost of 180° in order to counteract the effects of

an under damped resonance of the output filter

at the double pole frequency.

SP7651 Voltage Mode Control Loop with Loop Dynamic

(SRz2Cz2+1)(SR1Cz3+1) (SRESRCOUT+ 1)

[S^2LCOUT+S(RESR+RDC) COUT+1]

VIN

SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1) VRAMP_PP

VOUT

(Volts)

VREF

(Volts)

Notes: RESR = Output Capacitor Equivalent Series Resistance.

RDC = Output Inductor DC Resistance.

VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.

Condition: Cz2 >> Cp1 & R1 >> Rz3

Output Load Resistance >> RESR & RDC

R2VREF

(R1 + R2)or VOUT

VFBK

(Volts)

Type III Voltage Loop

Compensation

GAMP (s) Gain Block

PWM Stage

GPWM Gain

Block

Output Stage

GOUT (s) Gain

Block

Voltage Feedback

GFBK Gain Block

Definitions:

RESR = Output Capacitor Equivalent Series Resistance

RDC = Output Inductor DC Resistance

RRAMP_PP = SP7651 internal RAMP Amplitude Peak to Peak Voltage

Conditions:

CZ 2 >> Cp1 and R1 >> RZ 3

Output Load Resistance >> RESR and RDC

Bode Plot of Type III Error Amplifier Compensation.

CP1

RZ2

CZ2

VFB COMP

-0.8V

CF1

VOUT

68.1k, 1% RSET

CZ3

RZ3

RSET =54.48/ (VOUT -0.8) (kΩ)

Type III Error Amplifier Compensation Circuit

APPLICATIONS INFORMATION

Frequency

(Hz)

Error Amplifier Gain

Bandwidth Product

Condition:

C22 >> CP1, R1 >> RZ3

20 Log (RZ2/R1)

Gain

(dB)

1/6.28(R22) (CZ2)

1/6.28 (R1) (CZ3)

1/6.28 (R1) (CZ2)

1/6.28 (RZ2) (CP1)

1/6.28 (RZ3) (CZ3)

PACKAGE: 26 PIN DFN

Bottom View

DIMENSIONS in

(mm)

26 Pin DFN

0.800 0.850 0.900

2.00

2.730 2.780 2.830

0.350 0.450

0.17 0.22 0.27

SYMBOL MIN NOM MAX

0.050

3.95 4.05

6.95 7.05

7.00

2.05 2.10

0.178 0.203 0.228

0.400

1.78 1.83 1.88

4.00

0.45 0.50 0.55

0.000 -

Top View

E(7 x 4 mm)

Side View

26 Pin DFN

Corporation

ANALOG EXCELLENCE

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Sipex Corporation

Headquarters and

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

ORDERING INFORMATION

Part Number Temperature Package

SP7651ER/TR ......................................... -40°C to +85°C................................. 26 Pin 7 X 4 DFN

SP7651ER-L/TR ..................................... -40°C to +85°C ............. (Lead Free) 26 Pin 7 X 4 DFN

/TR = Tape and Reel

Pack quantity is 3000 DFN.