ICS9112CM-18 - Integrated Circuit Systems, Inc.

MK2308-2

MDS 2308-2 B 1Revision 111103

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ZERO DELAY, LOW SKEW BUFFER

Description

The MK2308-2 is a low jitter, low skew, high

performance Phase-Lock Loop (PLL) based zero delay

buffer for high speed applications. Based on ICS’

proprietary low jitter PLL techniques, the device

prov ides eight low skew outputs at speeds up to 160

MHz at 3.3 V. The MK2308 - 2 in clu d es a bank of four

outputs running at 1/2X. In the zero delay mode, the

rising edge of the input clock is aligned with the rising

edges of all eight outputs. Compared to competitive

CMOS devices, the MK2308-2 has the lowest jitter.

Features

•Packaged in 16-pin SOIC

•Zero input-output delay

•Four 1X outputs plu s four 1/2X outputs

•Output to output skew is less than 250 ps

•Output clocks up to 160 MHz at 3. 3 V

•Ability to generate 2X the input

•Full CMOS outputs with 18 mA output drive

capability at TTL levels at 3.3 V

•Spread SmartTM technology works with spread

spectrum clock generators

•Advanced, low power, sub micron CMOS process

•Operating voltage of 3.3 V or 5 V

Block Diagram

CLKA4

CLKB1

CLKA3

CLKB2

CLKB3

CLKA2

CLKA1

CLKB4

Control

Logic

S2, S1 2

PLL

FBIN

CLKIN

VDD

GND

BANK

ZERO DELAY, LOW SKEW BUFFER

MDS 2308-2 B 2Revision 111103

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

MK2308-2

Pin Assignment Feedback Configuration Table

Output Clock Mode Select Table

Pin Descriptions

GND

CLKA1

CLKA4

CLKA3

VDD

CLKB3CLKB2

FBIN

CLKB1

CLKA2

CLKIN

VDD

CLKB4

GND

16-pin (150 mil) SOIC

Feedback From CLKA1:A4 CLKB1:B4

Bank A CLKIN CLKIN/2

Bank B 2XCLKIN CLKIN

S2 S1 Clocks A1:A4 Clocks B1:B4 Internet Generation PLL Status

0 0 Tri-state (high impeda nce) Tri-state (high impedance) None On

0 1 Running Tri-state (high impedance) PLL On

1 0 Running Running Buffer only (no zero delay) Off

1 1 Running Running PLL On

Number Pin

Name Pin

Type Pin Description

1 CLKIN Input Clock input. Connect to input clock source.

2 - 3 CLKA1:A4 Output Clock A bank of four outp uts.

4 VDD Power Power supply. Connect pin to same voltage as pin 13 (either 3.3 V or 5 V).

5 GND Power Connect to ground.

6 - 7 CLKB1:B4 Output Clock B bank of four outputs. These are low skew divide by two of bank A.

8 S2 Input Select input 2. Selects mode for outputs per table above .

9 S1 Input Select input 1. Selects mode for outputs per table above .

10 - 11 CLKB1:B4 Output Clock B bank of four outputs. These are low skew divide by two of bank A.

12 GND Power Connect to ground.

13 VDD Power Power supply. Connect pin to same voltage as pin 4 (either 3.3 V or 5 V).

14 - 15 CLKA1:A4 Output Clock A bank of four outputs.

16 FBIN Input Feedback input. Determines outputs per table above.

ZERO DELAY, LOW SKEW BUFFER

MDS 2308-2 B 3Revision 111103

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

MK2308-2

External Components

The MK2308-2 requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.1µF should be connected betw e en VDD and GND, as close to the part as possible. A 33 Ω

series terminating resistor should be used on each clock output to reduce reflection s.

Absolute Maximum Ratings

Stresses above the rat ings listed below can cause permanent damage to the MK2308-2. These ratings,

which are standard v alues f or ICS commercially rated pa rts, are stress r atings only. Functional oper ation of

the device at these or any other conditions above those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can

affect product reliability. Electrical par ameters are guaranteed only over the recommended operating

temperature range.

Recommended Operation Conditions

DC Electrical Characteristics

VDD=3.3 V ±10%, Temp 0 to +70° /-40 to +85° C

Item Rating

Supply Voltage, VDD 7 V

All Inputs and Outputs -0.5 V to VDD+0.5 V

Ambient Operating Temperature 0 to +70 °C

Storage Temperature -65 to +150 °C

Junction Temperature 175 °C

Soldering Temperature 260 °C

Parameter Min. Typ. Max. Units

Ambient Operating Temperature 0 +70 °C

Power Supply Voltage (measured in respect to GND) +3.0 +5.5 V

Parameter Symbol Conditions Min. Typ. Max. Units

Operating Voltage VDD 3.0 5.5 V

Input High Voltage VIH CLKIN pin only (VDD/2)+1 VDD/2 V

Input Low Voltage VIL CLKIN pin only VDD/2 (VDD/2)-1 V

Input High Voltage VIH 2V

Input Low Voltage VIL 0.8 V

Output High Voltage VOH IOH = -18 mA 2.4 V

Output Low Voltage VOL IOL = 18 mA 0.4 V

Output High Voltage VOH IOH = -5 mA VDD-0.4 V

ZERO DELAY, LOW SKEW BUFFER

MDS 2308-2 B 4Revision 111103

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

MK2308-2

AC Electrical Characteristics

VDD = 3.3V ±10%, Temp 0 to +70°/ -40 to +85° C

Thermal Characteristics

Operating Supply Current

100 MHz, CLKIN IDD No Load

S1=S2=1 44 mA

Short Circuit Current IOS Each output ± 65 mA

Input Capacitance CIN S1, S1, FBIN 7 pF

Parameter Symbol Conditions Min. Typ. Max. Units

Input Frequency FBIN to CLKA1

S1=S2=1 20 160 MHz

Output Frequency FBIN to CLKA1

S1=S2=1 20 160 MHz

Output Rise Time tOR 0.8 to 2.0 V, CL=30 pF 1.5 ns

Output Fall Time tOF 0.8 to 2.0 V, CL=30 pF 1.5 ns

Output Clock Duty Cycle at 1.4V 40 50 60 %

Device to Device skew, equally

loaded rising edges at VDD/2 700 ps

Output to Output skew, equally

loaded rising edges at VDD/2 200 ps

Maximum Absolute Jitter 300 ps

Cycle to Cycle Jitter 30 pF loads

66.67 MHz outputs 400 ps

15 pF loads

66.67 MHz outputs 400 ps

Skew from Output Bank A to

Output Bank B All outputs equally

loaded 400 ps

Delay CLKIN Rising Edge to

FBIN Rising Edge measured at VDD/2 ±250 ps

PLL Lock Time tLOCK Stable po wer supply,

valid clocks on CLKIN,

FBIN

1ms

Parameter Symbol Conditions Min. Typ. Max. Units

Thermal Resistance Junction to

Ambient θJA Still air 120 °C/W

θJA 1 m/s air flow 115 °C/W

θJA 3 m/s air flow 105 °C/W

Thermal Resistance Junction to Case θJC 58 °C/W

ZERO DELAY, LOW SKEW BUFFER

MDS 2308-2 B 5Revision 111103

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

MK2308-2

Package Outline and Package Dimensions (16-pin SOIC, 150 Mil. Narrow Body)

Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit

Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of

third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is

intended for use in normal commercial applications. Any other applications such as those requiring exte nded

temperature range, high reliability, or other extraordinary environmental requirements are not recommended

without additional p rocessing by ICS. ICS reserves the ri ght to change any circuitry or specifications witho ut notice.

ICS does not authorize or warrant any ICS product for use in life support de vices or critical medical instruments.

Part / Order Number Marking Shipping

packaging Package Temperature

MK2308S-2 MK2308S-2 Tubes 16-pin SOIC 0 to 70° C

MK2308S-2T MK2308S-2T Tape and Reel 16-pin SOIC 0 to 70° C

MK2308S-2I MK2308S-2I Tubes 16-pin SOIC -40 to +85° C

MK2308S-2I T MK2308S-2IT Tape and Reel 16-pin SOIC -40 to +85° C

INDEX

AREA

1 2

SEATING

PLANE

- C -

.10 (.004) C

h x 45

Millimeters Inches

Symbol Min Max Min Max

A 1.35 1.75 .0532 .0688

A1 0.10 0.25 .0040 .0098

B 0.330.51.013.020

C 0.19 0.25 .0075 .0098

D 9.80 10.00 .3859 .3937

E 3.80 4.00 .1497 .1574

e 1.27 BASIC 0.050 BASIC

H 5.80 6.20 .2284 .2440

h 0.250.50.010.020

L 0.401.27.016.050

α0°8°0°8°