87946AYI-147LF/W - INTEGRATED DEVICE TECHNOLOGY

General Description

The 87946I-147 is a low skew, ÷1, ÷2 LVCMOS/LVTTL Fanout

Buffer . The 87946I-147 has two selectable single ended clock inputs.

The single ended clock inputs accept LVCMOS or LVTTL input

levels. The low impedance LVCMOS/LVTTL outputs are designed to

drive 50 series or parallel terminated transmission line s . The

effective fanout can be increased from 10 to 20 by utilizing the ability

of the outputs to drive two series terminated lines.

The divide select inputs, DIV_SELx , control the output frequency of

each bank. The outputs can be utilized in the ÷1, ÷2 or a combination

of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the

internal freque ncy dividers and also controls the active and high

impedance states of all outputs.

The 87946I-147 is characterized at full 3.3V for input VDD, and mixed

3.3V and 2.5V for output operating supply mode. Guaranteed bank,

output and part-to-part skew characteristics make the 87946I-147

ideal for those clock distribution applications demanding well defined

performance and repeatability.

Features

•Ten single ended LVCMOS/LVTTL outputs,

7 typical output impedance

•Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs

•CLK0 and CLK1 can accept the following inp ut levels:

LVCMOS and LVTTL

•Maximum input frequency: 250MHz

•Bank skew: 30ps (maximum)

•Output skew: 175ps (maximum)

•Part-to-part skew: 850ps (maximum)

•Multiple frequency skew: 200ps (maximum)

•3.3V core, 3.3V or 2.5V output supply modes

•-40°C to 85°C ambient operating temperature

•Lead-free packaging

Block Diagram Pin Assignment

87946I-147

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y Package

Top View

CLK0

CLK_SEL

CLK1

DIV_SELA

QA[0:2]

÷1

÷2

Pullup

Pulldown

DIV_SELB

DIV_SELC

QC[0:3]

Pulldown

MR/nOE Pulldown

QB[0:2]

Pulldown

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25

CLK_SEL

VDD

CLK0

CLK1

IV_SELA

IV_SELB

IV_SELC

GND

VDD

DDC

QC0

QC1

DDC

QC2

QC3

GND

QA0

VDDA

QA1

GND

QA2

VDDA

R/nOE

1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL

2.5V, 3.3V Fanout Buffer 87946I-147

Datasheet

87946I-147 D ata sheet

Pin Descriptions and Characteristics

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resisto rs. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1 CLK_SEL Input Pulldown Clock select input. When HIGH, selects CLK1.

When LOW, selects CLK0. LVCMOS / LVTTL interface levels.

DD Power Positive supply pin.

3, 4 CLK0, CLK1 Input Pullup Single-ended clock inputs. LVCMOS/LVTTL interface levels.

5 DIV_SELA Input Pulldown Controls frequency division for Bank A outp uts. See Table 3

LVCMOS/LVTTL interface levels.

6 DIV_SELB Input Pulldown Controls frequency division for Bank B outputs. See Table 3.

LVCMOS/LVTTL interface levels.

7 DIV_SELC Input Pulldown Controls frequency division for Bank C outputs. See Table 3.

LVCMOS/LVTTL interface levels.

8, 11 , 15, 20,

24, 27, 31 GND Power Power supply ground.

9, 13, 17 VDDC Power Output supply pins for Bank C outputs.

10, 12,

14, 16 QC0, QC1,

QC2, QC3 Output Single-ended Bank C clock outputs. LVCMOS/LVTTL interface levels.

7 typical output impedance.

18, 22 VDDB Power Output supply pins for Bank B outputs.

19,

21, 23 QB2,

QB1, QB0 Output Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.

7 typical output impedance.

25, 29 VDDA Power Output supply pins for Bank A outputs.

26,

28, 30 QA2,

QA1, QA0 Output Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.

7 typical output impedance.

32 MR/nOE Input Pulldown

Active HIGH Master Reset. Active LOW Output Enable. When logic HIGH,

the internal dividers are reset and the outputs are (High-Impedance). When

logic LOW, the internal dividers and the outputs are enabled. See Table 3.

LVCMOS/LVTTL interface levels.

Symbol Parameter Tes t Conditio ns Minimum Typical Maximum Units

CIN Input Capacitance 4pF

CPD

Power Dissipation Capacitance

= V

DDA

= V

DDB

= V

DDC

= 3.6V

25 pF

RPULLUP Input Pullup Resistor 51 k

RPULLDOWN Input Pulldown Resistor 51 k

ROUT Output Impedance 7 

87946I-147 D ata sheet

Function Tables

Table 3. Clock Input Function Table

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or

AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, VDD = VDDA = VDDB = VDDC = 3.3V ± 0.3V, TA = -40°C to 85°C

Inputs Outputs

MR/nOE DIV_SELA DIV_SELB DIV_SELC QA0:QA2 QB0:QB2 QC0:QC3

1 X X X High-Impedance High-Impedance High-Impedance

00XXf

IN/1 Active Active

01XXf

IN/2 Active Active

0 X 0 X Active fIN/1 Active

0 X 1 X Active fIN/2 Active

0 X X 0 Active Active fIN/1

0 X X 1 Active Active fIN/2

Item Rating

Supply Voltage, VDD 4.6V

Inputs, VI-0.5V to VDD + 0.5V

Outputs, VO -0.5V to VDDX+ 0.5V

Package Thermal Impedance, JA 47.9C/W (0 lfpm)

Storage Temp erature, TSTG -65C to 150C

Junction Temperature 125°C

Symbol Parameter Tes t Conditio ns Minimum Typical Maximum Units

VDD Positive Supply Voltage 3.0 3.3 3.6 V

VDDA, VDDB, VDDC Output Supply Voltage 3.0 3.3 3.6 V

IDD Power Supply Current 55 mA

IDDA, IDDB, IDDC Output Supply Current 23 mA

87946I-147 D ata sheet

Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDA = VDDB = VDDC = 2.5V ± 5%, TA = -40°C to 85°C

Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDB = VDDC = 3.3V ± 0.3V, TA = -40°C to 85°C

NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Information section. Load Test Circuit diagrams.

Symbol Parameter Tes t Conditio ns Minimum Typical Maximum Units

VDD Positive Supply Voltage 3.135 3.3 3.465 V

VDDA, VDDB, VDDC Output Supply Voltage 2.375 2.5 2.625 V

IDD Power Supply Current 55 mA

IDDA, IDDB, IDDC Output Supply Current 22 mA

Symbol Parameter Te st Conditions Minimum Typical Maximum Units

VIH Input High Voltage 2 VDD + 0.3 V

VIL

Input

Low

Voltage

MR/nOE,

DIV_SELA, DIV_SELB,

DIV_SELC, CLK_SEL -0.3 0.8 V

CLK0, CLK1 -0.3 1.3 V

IIH

Input

High

Current

MR/nOE,

DIV_SELA, DIV_SELB,

DIV_SELC, CLK_SEL VDD = VIN = 3.6V 150 µA

CLK0, CLK1 VDD = VIN = 3.6V 5 µA

IIL

Input

Low

Current

MR/nOE,

DIV_SELA, DIV_SELB,

DIV_SELC, CLK_SEL VDD = 3.6V, VIN = 0V -5 µA

CLK0, CLK1 VDD = 3.6V, VIN = 0V -150 µA

VOH Output High Voltage; NOTE 1 VDDA = VDDB = VDDC = 3.6V 2.6 V

VOL Output Low Voltage; NOTE 1 VDDA = VDDB = VDDC = 3.63V 0.5 V

IOZL Output Hi-Z Current Low VDDA = VDDB = VDDC = 3. 63V -5 µA

IOZH Output Hi-Z Current High VDDA = VDDB = VDDC = 3.63V 5 µ A

87946I-147 D ata sheet

Table 4D. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDA = VDDB = VDDC = 2.5V ± 5%, TA = -40°C to 85°C

NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Information section. Load Test Circuit diagrams.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage 2 VDD + 0.3 V

VIL

Input

Low

Voltage

MR/nOE,

DIV_SELA, DIV_SELB,

DIV_SELC, CLK_SEL -0.3 0.8 V

CLK0, CLK1 -0.3 1.3 V

IIH

Input

High

Current

MR/nOE,

DIV_SELA, DIV_SELB,

DIV_SELC, CLK_SEL VDD = VIN = 3.465V 150 µA

CLK0, CLK1 VDD = VIN = 3.465V 5 µA

IIL

Input

Low

Current

MR/nOE,

DIV_SELA, DIV_SELB,

DIV_SELC, CLK_SEL VDD = 3.465V, VIN = 0V -5 µA

CLK0, CLK1 VDD = 3.465V, VIN = 0V -150 µA

VOH Output High Voltage;

NOTE 1 VDDA = VDDB = VDDC = 2.625V 1.8 V

VOL Output Low Voltage; NOTE 1 VDDA = VDDB = VDDC = 2.625V 0.5 V

IOZL Output Hi-Z Current Low VDDA = VDDB = VDDC = 2.625V -5 µA

IOZH Output Hi-Z Current High VDDA = VDDB = VDDC = 2.625V 5 µA

87946I-147 D ata sheet

AC Electrical Characteristics

Table 5A. AC Characteristics, VDD = VDDA = VDDB = VDDC = 3.3V ± 0.3V, TA = -40°C to 85°C

NOTE: Electrical parameters are guaranteed ov er the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

NOTE 1: Measured from VDD/2 of the input to VDDX/2 of the output.

NOTE 2: Defined as skew within a bank of ou tputs at the same supply voltage and with eq ual load conditions.

NOTE 3: Defined as skew across banks of outputs at the same supply voltage and with equal load conditions. Measured at VDDX/2.

NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions.

NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using

the same type of inputs on each device, the outputs are measured at VDDX/2.

NOTE 6: These parameters are guaranteed by characterization. Not tested in production.

NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fMAX Output Frequency 250 MHz

tPD Propagation Delay;

NOTE 1 ƒ  250MHz 2 5 ns

tsk(b) Bank Skew, NOTE 2, 7 Measured on rising edge at VDDX/2 30 ps

tsk(o) Output Skew; NOTE 3, 7 M easured on rising edge at VDDX/2 175 ps

tsk(w) Multiple Frequency Skew;

NOTE 4, 7 Measured on rising edge at VDDX/2 275 ps

tsk(pp) Part-to-Part Skew;

NOTE 5, 7 Measured on rising edge at VDDX/2 850 ps

tR / tFOutput Rise/Fall Time; NOTE 6 20% to 80% 400 950 ps

tPW Output Pulse Width tPERIOD/2 - 1 tPERIOD/2 tPERIOD/2 + 1 %

tEN Output Enable Time;

NOTE 6 ƒ = 10MHz 3 ns

tDIS Output Disable Time; NOTE 6 ƒ = 10MHz 3 ns

87946I-147 D ata sheet

Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDA = VDDB = VDDC = 2.5V ± 5%, TA = -40°C to 85°C