ADVANCED INFORMATION MX28F320J3/640J3/128J3 32M/64M/128M [x8/x16] SINGLE 3V PAGE MODE FLASH MEMORY FEATURES * 2.7V to 3.6V operation voltage * Block Structure - 32 x 128Kbyte Erase Blocks (32M) - 64 x 128Kbyte Erase Blocks (64M) - 128 x 128Kbyte Erase Blocks (128M) * Fast random / page mode access time - 120/25 ns Read Access Time (32M) - 120/25 ns Read Access Time (64M) - 150/25 ns Read Access Time (128M) * 128-bit Protection Register - 64-bit Unique Device Identifier - 64-bit User Programmable OTP Cells * 32-Byte Write Buffer - 6 us/byte Effective Programming Time * Enhanced Data Protection Features Absolute Protection with VPEN = GND - Flexible Block Locking - Block Erase/Program Lockout during Power Transitions Software Feature * Support Common Flash Interface (CFI) - Flash device parameters stored on the device and provide the host system to access. * Automation Suspend Options - Block Erase Suspend to Read - Block Erase Suspend to Program - Program Suspend to Read Hardware Feature(Not for 48-TSOP/48-RTSOP) * A0 pin - Select low byte address when device is in byte mode. Not used in word mode. * STS pin - Indicates the status of the internal state machine. * VPEN pin - For Erase /Program/ Block Lock enable. * VCCQ Pin - The output buffer power supply, control the device 's output voltage. Performance * Low power dissipation - typical 15mA active current for page mode read - 80uA/(max.) standby current - Deep power-down current: 5uA * High Performance - Block erase time: 2s typ. - Byte programming time: 210us typ. - Block programming time: 0.8s typ. (using Write to Buffer Command) * Program/Erase Endurance cycles: five grades-- "C1" stands for 10 cycles "C2" stands for 100 cycles "C3" stands for 1,000 cycles "C4" stands for 10,000 cycles "C5" stands for 100,000 cycles (please refer to Ordering Information of page 47) Packaging - 48-Lead TSOP (for MX28F128J3) - 48-Lead RTSOP (for MX28F128J3) - 56-Lead TSOP - 48-ball Flip Chip CSP (for MX28F320J3/640J3) - 64-ball CSP Technology - MX28F128J3 using Nbit (0.25u) Flash Technology - MX28F320J3/640J3 using Nbit (0.35u) Flash Technology P/N:PM0858 REV. 0.4, JUN. 07, 2002 1 MX28F320J3/640J3/128J3 GENERAL DESCRIPTION The MXIC's MX28F320J3/640J3/128J3 series Flash use the most advance 2 bits/cell Nbit technology, double the storage capacity of memory cell. The device provide the high density Flash memory solution with reliable performance and most cost-effective. enable (CE0, CE1, CE2) and output enable (OE) controls. The device augment EPROM functionality with incircuit electrical erasure and programming. The device uses a command register to manage this functionality. The MXIC's Nbit technology reliably stores memory contents even after the specific erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms by utilizing the dielectric's character to trap or release charges from ONO layer. The device organized as by 8 bits or by 16 bits of output bus. The device is packaged in 48-Lead TSOP, 48-Lead RTSOP, 56-Lead TSOP, 48-ball Flip Chip CSP and 64ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The device uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The device offers fast access time and allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the device has separate chip The highest degree of latch-up protection is achieved P/N:PM0858 REV. 0.4, JUN. 07, 2002 2 MX28F320J3/640J3/128J3 PIN CONFIGURATION 48-TSOP (12mm x 20mm) (for MX28F128J3 word mode only) WE A17 A16 A15 A14 A13 A12 A11 A10 A9 A20 A22 A21 A19 A18 A8 A7 A6 A5 A4 A3 A2 A1 CE0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MX28F128J3 (x16 only) Normal Type 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND GND Q15 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC VCC A23 Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND RESET(*) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 WE A17 A16 A15 A14 A13 A12 A11 A10 A9 A20 A22 A21 A19 A18 A8 A7 A6 A5 A4 A3 A2 A1 CE0 (* RESET pin : high enable) 48-RTSOP (12mm x 20mm) (for MX28F128J3 word mode only) GND GND Q15 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC VCC A23 Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE GND RESET(*) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 MX28F128J3 (x16 only) Reverse Type (* RESET pin : high enable) P/N:PM0858 REV. 0.4, JUN. 07, 2002 3 MX28F320J3/640J3/128J3 56 TSOP (14mm x 20mm) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 A22 CE1 A21 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPEN RESET A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 NC WE OE STS Q15 Q7 Q14 Q6 GND Q13 Q5 Q12 Q4 VCCQ GND Q11 Q3 Q10 Q2 VCC Q9 Q1 Q8 Q0 A0 BYTE A23 CE2 Notes: 1. A22 exists on 64M, 128M densities. On 32M densities this pin is a no connect (NC). 2. A23 exists on 128M densities. On 32M and 64M densities this pin is a no connect (NC). 48 Flip Chip CSP (for MX28F320J3/640J3) 1 2 3 4 5 6 7 8 A A14 A12 A9 VPEN VCC A20 A8 A5 B A15 A11 WE RESET A19 A18 A6 A3 C A16 A13 A10 A22 A21 A7 A4 A2 D A17 Q14 Q5 Q11 Q2 Q8 CEO A1 E VCCQ Q15 Q6 Q12 Q3 Q9 Q0 GND F GND Q7 Q13 Q4 VCC Q10 Q1 OE 13 mm 8mm P/N:PM0858 REV. 0.4, JUN. 07, 2002 4 MX28F320J3/640J3/128J3 64 Ball CSP (10x13x1.2mm, 1.0mm-ball pitch) 1 2 3 4 5 6 7 8 A A1 A6 A8 VPEN A13 VCC A18 A22 B A2 GND A9 CE0 A14 DU A19 CE1 C A3 A7 A10 A12 A15 DU A20 A21 D A4 A5 A11 RESET DU DU A16 A17 E Q8 Q1 Q9 Q3 Q4 DU Q15 STS F BYTE Q0 Q10 Q11 Q12 DU DU OE G A23 A0 Q2 VCCQ Q5 Q6 Q14 WE CE2 DU VCC GND Q13 GND Q7 NC H 13 mm 10mm Notes: 1. Address A22 is only valid on 64M and 128M densities. Otherwise, it is a no connect (NC). 2. Address A23 is only valid on 128M densities. Otherwise, it is a no connect (NC). 3. Don't Use (DU) pins refer to pins that should not be connected. PIN DESCRIPTION SYMBOL PIN NAME SYMBOL PIN NAME A0 Byte Select Address STS STATUS Pin A1~A23 Address Input (32M:A0~A21, BYTE Byte Mode Enable 64M:A0~A22, 128M:A0~A23) VPEN ERASE/PROGRAM/BLOCK Lock Q0~Q15 Enable Data Inputs/Outputs CE0, CE1, CE2 Chip Enable Input VCCQ Output Buffer Power Supply WE Write Enable Input VCC Device Power Supply OE Output Enable Input GND Device Ground RESET Reset/Deep Power Down mode NC Pin Not Connected Internally (low enable for 56-TSOP & 64-CSP) DU Don't Use RESET Reset/Deep Power Down mode (high enable for 48-TSOP & 48-RTSOP) P/N:PM0858 REV. 0.4, JUN. 07, 2002 5 MX28F320J3/640J3/128J3 BLOCK DIAGRAM CE0 CE1 CE2 OE WE RESET(*) CONTROL INPUT HIGH VOLTAGE LOGIC LATCH BUFFER REGISTER FLASH ARRAY Y-DECODER AND WRITE STATE MACHINE (WSM) STATE X-DECODER ADDRESS A0-A23 PROGRAM/ERASE ARRAY SOURCE HV Y-PASS GATE SENSE AMPLIFIER PGM DATA HV COMMAND DATA DECODER COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15 I/O BUFFER * : RESET pin for 56-TSOP & 64-CSP; RESET pin for 48-TSOP & 48-RTSOP. P/N:PM0858 REV. 0.4, JUN. 07, 2002 6 MX28F320J3/640J3/128J3 Figure 1. Block Architecture Flash memory reads erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. A[23-0]: 128Mbit A[22-0]: 64Mbit A[21-0]: 32Mbit A[23-1]: 128Mbit A[22-1]: 64Mbit A[21-1]: 32Mbit 7FFFFF FFFFFF 127 7F0000 . . . 3FFFFF 63 3F0000 63 . . . 1FFFFF 128-Kbyte Block 31 1F0000 . . . 64-Kword Block 31 . . . 03FFFF 64 Mbit 3FFFFF 020000 01FFFF 64-Kword Block 128 Mbit 128-Kbyte Block . . . 3E0000 127 . . . 7FFFFF 7E0000 64-Kword Block 32 Mbit FE0000 128-Kbyte Block 01FFFF 128-Kbyte Block 1 128-Kbyte Block 0 000000 010000 00FFFF 64-Kword Block 1 64-Kword Block 0 000000 Byte Mode (x8) Word Mode (x16) Table 1. Chip Enable Truth Table CE2 CE1 CE0 DEVICE VIL VIL VIL Enabled VIL VIL VIH Disabled VIL VIH VIL Disabled VIL VIH VIH Disabled VIH VIL VIL Enabled VIH VIL VIH Enabled VIH VIH VIL Enabled VIH VIH VIH Disabled NOTE: For Single-chip applications, CE2 and CE1 can be strapped to GND. P/N:PM0858 REV. 0.4, JUN. 07, 2002 7 MX28F320J3/640J3/128J3 Table 2. Bus Operations Command Sequence Read Array Notes 4,5,6 RESET (12) VIH Output Standby RESET Read ID Read Disable Mode/ Query Deep Power Down Mode Read Read Status Status (WSM off) (WSM on) Write 6,10,11 VIH VIH VIH VIH VIH CE0,CE1,CE2(1) Enabled Enabled Disabled X Enabled Enabled Enabled Enabled Enabled OE (2) VIL VIH X X VIL VIL VIL VIL VIH WE (2) VIH VIH X X VIH VIH VIH VIH VIL Address X X X X X X X X See See X Figure 2 Table 6 X X X VPEN X X X VPENH Q (3) Data out High Z High Z High Z Note 8 Note 9 STS (default mode) High Z (7) X High Z High Z (7) (7) High Z (7) X VIH VIL (12) VIH Data out Q7=Data out Data in Q15-8=High Z Q6-0=High Z X NOTES: 1. See Table 1 on page 7 for valid CE configurations. 2. OE and WE should never be enabled simultaneously. 3. DQ refers to Q0-Q7 if BYTE is low and Q0-Q15 if BYTE is high. 4. Refer to DC Characteristics. When VPEN < VPENLK , memory contents can be read, but not altered. 5. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN . See DC Characteristics for VPENLK and VPENH voltages. 6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset/deep power-down mode. 7. High Z will be VOH with an external pull-up resistor. 8. See Section , "Read Identifier Codes" for read identifier code data. 9. See Section , "Read Query Mode Command" for read query data. 10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN= VPENH and VCC is within specification. 11.Refer to Table 3 on page 10 for valid DIN during a write operation. 12.RESET mode of 48-TSOP & 48-RTSOP types is high enabled to entering deep power down mode. P/N:PM0858 REV. 0.4, JUN. 07, 2002 8 MX28F320J3/640J3/128J3 FUNCTION OUTPUT DISABLE The device includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and byte/word/page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. When OE is at VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state. STANDBY A Deep Powerdown mode is enabled when the RESET pin of 56-TSOP & 64-CSP types is at GND or RESET pin of 48-TSOP & 48-RTSOP is at VIH, minimizing power consumption. When CE0, CE1 and CE2 disable the device (see table1) and place it in standby mode. The power consumption of this device is reduced. Data input/output are in a highimpedance(High-Z) state. If the memory is deselected during block erase, program or lock-bit configuration, the internal control circuits remain active and the device consume normal active power until the operation completes. READ DEEP POWER-DOWN The device has three read modes, which accesses to the memory array, the Device Identifier or the Status Register independent of the VPEN voltage. The appropriate read command are required to be written to the CUI. Upon initial device powerup or after exit from deep powerdown, the device automatically resets to read array mode. In the read array mode, low level input to CE0, CE1, CE2 and OE, high level input to WE and RESET or low level input to RESET, and address signals to the address inputs (A23-A0) output the data of the addressed location to the data input/output (Q15~Q0). When RESET pin of 56-TSOP & 64-CSP types is at VIL or RESET pin of 48-TSOP & 48-RTSOP types is at VIH, the device is in the deep power-down mode and its power consumption is substantially low around 5uA. During read modes, the memory is deselected and the data input/ output are in a high-impedance(High-Z) state. To return from deep power down mode requires RESET pin of 56TSOP & 64-CSP types at VIH or RESET pin of 48RTSOP & 48-RTSOP types at VIL. After return from powerdown, the CUI is reset to Read Array , and the Status Register is set to value 80H. When reading information in read array mode, the device defaults to asynchronous page mode. In this state, data is internally read and stored in a high-speed page buffer. A2:0 addresses data in the page buffer. The page size is 4 words or 8 bytes. Asynchronous word/byte mode is supported with no additional commands required. During block erase program or lock-bit configuration modes, RESET pin of 56-TSOP & 64-CSP types at VIL or RESET pin of 48-TSOP & 48-RTSOP types at VIH will abort either operation. Memory array data of the block being altered become invalid. In default mode, STS transitions low and remains low for a maximum time of tPLPH+tPHRH until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lockbit configuration. Time tPHWL is required after RESET goes to logic-high (VIH) or RESET goes to VIL before another command can be written. WRITE Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register and when VPEN=VPENH block erasure program and lock-bit configuration. The CUI is written when the device is enable, WE is active and OE is at high level. Address and data are latched on the earlier rising edge of WE and CE. Standard micro-processor write timings are used. READ QUERY The read query operation outputs block status information, CFI (Common Flash Interface) ID string, system interface information, device geometry information and MXIC extended query information. P/N:PM0858 REV. 0.4, JUN. 07, 2002 9 MX28F320J3/640J3/128J3 COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the CUI. Table 3 defines the valid register command sequences. When VPEN<VPENLK only read operations from the status register, query, indentifier code or blocks are enabled. When VPEN=VPENH enables block erase program and lock-bit configuration operations. Table 3. Command Definitions Command Read Read Read Read Clear Write to Word/byte Sector Sequence Array ID Query Status Status Buffer Program Erase 7,8,9 10,11 9,10 Register Register Notes 5 6 Bus Write Cycles Req'd 1 >2 >2 2 1 >2 2 2 First Bus Write Write Write Write Write Write Write Write X X X X X BA X BA FFH 90H 98H 70H 50H E8H 40H/10H 20H Second Bus Operation(2) Read Read Read Write Write Write Read Query Address(3) IA QA X BA PA BA Data(4,5) ID QD SRD N PD D0H Operation(2) Write Cycles Address(3) Data(4,5) Command Sector Sector Configur- Set Sector Clear Protection Sequence Erase, Erase, ation Lock-Bit Sector Program Program Program Suspend Resume Notes 10,12 10 Bus Write Cycles Req'd 1 1 2 2 2 2 First Bus Write Write Write Write Write Write X X X X X X B0H D0H B8H 60H 60H C0H Second Bus Operation(2) Write Write Write Write Write Cycle Address(3) X BA X PA Data(4,5) CC 01H D0H PD Operation(2) Write Cycle Address(3) Data(4,5) Lock-Bit 13 P/N:PM0858 REV. 0.4, JUN. 07, 2002 10 MX28F320J3/640J3/128J3 NOTES: 1. Bus operations are defined in Table 2. 2. X = Any valid address within the device. BA = Address within the block. IA = Identifier Code Address: see Figure 2 and Table 14. QA = Query database Address. PA = Address of memory location to be programmed. RCD = Data to be written to the read configuration register. This data is presented to the device on A 16-1 ; all other address inputs are ignored. 3. ID = Data read from Identifier Codes. QD = Data read from Query database. SRD = Data read from status register. See Table 15 for a description of the status register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. CC = Configuration Code. 4. The upper byte of the data bus (Q8-Q15) during command writes is a "Don't Care" in x16 operation. 5. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock codes. See Section 4.3 for read identifier code data. 6. If the WSM is running, only Q7 is valid; Q15-Q8 and Q6-Q0 float, which places them in a high impedance state. 7. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing. 8. The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N =000FH. The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. Please see Figure 4. "Write to Buffer Flowchart" for additional information. 9. The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued. 10.Attempts to issue a block erase or program to a locked block. 11.Either 40H or 10H are recognized by the WSM as the byte/word program setup. 12.Program suspends can be issued after either the Write-to-Buffer or Word-/Byte-Program operation is initiated. 13.The clear block lock-bits operation simultaneously clears all block lock-bits. P/N:PM0858 REV. 0.4, JUN. 07, 2002 11 MX28F320J3/640J3/128J3 Figure 2. Device Identifier Code Memory Map Word Address A[23-1]:128 Mbit A[22-1]:64 Mbit A[21-1]:32 Mbit 7FFFFF Block 127 Reserved for Future Implementation 7F0003 Block 127 Lock Configuration 7F0002 Reserved for Future Implementation 7F0000 7EFFFF (Block 64 through 126) 3FFFFF Block 63 Reserved for Future Implementation 3F0003 Block 63 Lock Configuration 3F0002 Reserved for Future Implementation 3F0000 3EFFFF (Block 32 through 62) Block 31 128 Mbit Reserved for Future Implementation 1F0003 Block 31 Lock Configuration 1F0002 64 Mbit Reserved for Future Implementation 1F0000 1EFFFF (Block 2 through 30) 01FFFF Block 1 Reserved for Future Implementation 010000 00FFFF Block 1 Lock Configuration 32 Mbit 010003 010002 Reserved for Future Implementation Block 0 Reserved for Future Implementation 000004 000003 000002 Block 0 Lock Configuration Device Code 000001 Manufacturer Code 000000 NOTE: A0 is not used in either x8 or x16 mode when obtaining these identifier codes. Data is always given on the low byte in x16 mode (upper byte contains 00h). P/N:PM0858 REV. 0.4, JUN. 07, 2002 12 MX28F320J3/640J3/128J3 Read Array Command The device is in Read Array mode on initial device power up and after exit from deep power down, or by writing FFH to the Command User Interface. The read configuration register defaults to asynchronous read page mode. The device remains enabled for reads until another command is written. The Read Array command functions independently of the VPEN voltage. Read Query Mode Command This section defines the data structure or "Database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. Query Structure Output The Query Database allows system software to gain information for controlling the flash component. This section describes the device CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest-order data outputs (DQ 0-7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two bytes of the Query structure, "Q" and "R" in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII "Q" in the low byte (DQ 0-7 ) and 00h in the high byte (DQ 8-15 ). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. P/N:PM0858 REV. 0.4, JUN. 07, 2002 13 MX28F320J3/640J3/128J3 In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h"," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. Table 4. Summary of Query Structure Output as a Function of Device and Mode Device Type/Mode Query start location in maximum device bus width addresses x16 device x16 mode 10h x16 device x8 mode N/A (1) Query data with maximum device bus width addressing Hex Offset 10: 11: 12: Hex Code 0051 0052 0059 N/A (1) ASCII Value "Q" "R" "Y" Query data with byte addressing Hex Offset 20: 21: 22: 20: 21: 22: Hex Code 51 00 52 51 51 52 ASCII Value "Q" "Null" "R" "Q" "Q" "R" NOTE: 1. The system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is "Not Applicable" for x8-configured devices. Table 5. Example of Query Structure Output of a x16- and x8-Capable Device Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ... Word Addressing Hex Code Value D15 - D0 0051 "Q" 0052 "R" 0059 "Y" P_IDLO PrVendor P_IDHI ID# PLO PrVendor PHI TblAdr A_IDLO AltVendor A_IDHI ID# ... ... Offset A7-A0 20h 21h 22h 23h 24h 25h 26h 27h 28h ... P/N:PM0858 Byte Addressing Hex Code Value D7 - D0 51 "Q" 51 "Q" 52 "R" 52 "R" 59 "Y" 59 "Y" P_IDLO PrVendor P_IDLO ID# P_IDHI ID# ... ... REV. 0.4, JUN. 07, 2002 14 MX28F320J3/640J3/128J3 Query Structure Overview The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database". The structure sub-sections and address locations are summarized below. Table 6. Query Structure (1) Offset Sub-Section Name Description 00h Manufacturer Code 01h Device Code (BA+2)h (2) Block Status Register Block-Specific Information 04-0Fh Reserved Reserved for Vendor-Specific Information 10h CFI Query Identification String Reserved for Vendor-Specific Information 1Bh System Interface Information Command Set ID and Vendor Data Offset 27h Device Geometry Definition Flash Device Layout P (3) Primary MXIC-Specific Extended Vendor-Defined Additional Information Specific to the Query Table Primary Vendor Algorithm NOTES: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 02000h is block 2s beginning location when the block size is 128 Kbyte). 3. Offset 15 defines "P" which points to the Primary Intel-Specific Extended Query Table. Block Status Register The block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Table 7. Block Status Register Offset (BA+2)h (1) Length 1 Description Block Lock Status Register Address Value BA+2: --00 or --01 BA+2: (bit 0): 0 or 1 BA+2: (bit 1-7): 0 BSR.0 Block Lock Status 0 = Unlocked 1 = Locked BSR 1-7: Reserved for Future Use NOTE: 1. BA = The beginning location of a Block Address (i.e., 008000h is block 1s (64-KB block) beginning location in word mode). P/N:PM0858 REV. 0.4, JUN. 07, 2002 15 MX28F320J3/640J3/128J3 CFI Query Identification String The CFI Query Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s). Table 8. CFI Identification Offset Length Description Add. 10 11: 12: 13: 14: 15: 16: 17: 18: 19: 1A: 10h 3 Query-unique ASCII string "QRY" 13h 2 15h 2 Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address 17h 2 19h 2 Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists Hex Code --51 --52 --59 --01 --00 --31 --00 --00 --00 --00 --00 Value Add. Hex Code Value 1B: --27 2.7 V 1C: --36 3.6 V 1D: --00 0.0V 1E: --00 0.0V 1F: 20: 21: 22: 23: 24: 25: 26: --07 --07 --0A --00 --04 --04 --04 --00 128us 128us 1s NA 2ms 2ms 16s NA "Q" "R" "Y" System Interface Information The following device information can optimize system interface software. Table 9. System Interface Information Offset 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Length 1 1 1 1 1 1 1 1 1 1 1 1 Description VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out = 2us "n" such that typical max. buffer write time-out = 2us "n" such that typical block erase time-out = 2ms "n" such that typical full chip erase time-out = 2ms "n" such that maximum word program time-out = 2 times typical "n" such that maximum buffer write time-out = 2 times typical "n" such that maximum block erase time-out = 2 times typical "n" such that maximum chip erase time-out = 2 times typical P/N:PM0858 REV. 0.4, JUN. 07, 2002 16 MX28F320J3/640J3/128J3 Device Geometry Definition This field provides critical details of the flash device geometry. Table 10. Device Geometry Definition Offset Length Description 27h 28h 1 2 2Ah 2 "n" such that device size = 2n in number of bytes Flash device interface: x8 async(28:00,29:00), x16 async(28:01,29:00), x8/x16 async(28:02,29:00) "n" such that maximum number of bytes in write buffer = 2n 2Ch 1 2Dh 4 Number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks 3. Symmetrically blocked partitions have one blocking region 4. Partition size = (total blocks) x (individual block size) Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Code See Table Below 27: 28: --02 x8/x16 29: --00 2A: --05 32 2B: --00 2C: --01 1 2D: 2E: 2F: 30: Device Geometry Definition Address 32M 64M 128M 27: --16 --17 --18 28: --02 --02 --02 29: --00 --00 --00 2A: --05 --05 --05 2B: --00 --00 --00 2C: --01 --01 --01 2D: --1F --3F --7F 2E: --00 --00 --00 2F: --00 --00 --00 30: --02 --02 --02 P/N:PM0858 REV. 0.4, JUN. 07, 2002 17 MX28F320J3/640J3/128J3 Primary-Vendor Specific Extended Query Table Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information. Table 11. Primary Vendor-Specific Extended Query Offset(1) Length P=31h (P+0)h 3 (P+1)h (P+2)h (P+3)h 1 (P+4)h 1 (P+5)h (P+6)h (P+7)h (P+8)h 4 (P+9)h (P+A)h (P+B)h (P+C)h (P+D)h 1 2 1 1 Description (Optional Flash Features and Commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature and command support (1=yes, 0=no) bits 9-31 are reserved; undefined bits are "0". If bit 31 is "1" then another 31 bit field of optional features follows at the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant Individual block locking supported bit 6 Protection bits supported bit 7 Page-mode read supported bit 8 Synchronous read supported Supported functions after suspend: read Array, Status,Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts Add. Hex Code 31: --50 32: --52 33: --49 34: --31 35: --31 36: --0A 37: --00 38: --00 39: --00 bit 0 = 0 bit 1 = 1 bit 2 = 1 bit 3 = 1(1) bit 4 = 0 bit 5 = 0 bit 6 = 1 bit 7 = 1 bit 8 = 0 3A: Value "P" "R" "I" "1" "1" No Yes Yes Yes(1) No No Yes Yes No --01 bit 0 = 1 --01 --00 bit 0 = 1 bit 1 = 0 Yes 3D: --33 3.3V 3E: --00 0.0V 3B: 3C: Yes No NOTE: 1. Future devices may not support the described "Legacy Lock/Unlock" function. Thus bit 3 would have a value of "0". P/N:PM0858 REV. 0.4, JUN. 07, 2002 18 MX28F320J3/640J3/128J3 Table 12. Protection Register Information Offset(1) Length P=31h (P+E)h 1 (P+F)h (P+10)h (P+11)h (P+12)h Description (Optional Flash Features and Commands) Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) protection register bytes. Some are pre-programmed with device-unique serial numbers. Others are user-programmable. Bits 0-15 point to the protection register lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bits 0-7 = Lock/bytes JEDEC-plane physical low address bits 8-15 = Lock/bytes JEDEC-plane physical high address bits 16-23 = "n" such that 2 n = factory pre-programmed bytes bits 24-31 = "n" such that 2 n = user-programmable bytes Add. Value 3F: Hex Code --01 40: --00 00h 01 NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h. Table 13. Page Read Information Offset(1) Length P=31h (P+13)h 1 (P+14)h 1 (P+15)h Description (Optional Flash Features and Commands) Page Mode Read capability bits 0-7 = "n" such that 2n HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Reserved for future use Add. Hex Code Value 44: --03 8 byte 45: --00 0 46: NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h. P/N:PM0858 REV. 0.4, JUN. 07, 2002 19 MX28F320J3/640J3/128J3 DEVICE OPERATION SILICON ID READ The Silicon ID Read mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. During the "Silicon ID Read" Mode, manufacturer's code (MXIC=C2H) can be read out by setting A0=VIL and device identifier can be read out by setting A0=VIH. To terminate the operation, it is necessary to write the read command. The "Silicon ID Read" command functions independently of the VPEN voltage. This command is valid only when the WSM is off or the device is suspended. To activate this mode, the two cycle "Silicon ID Read" command is requested. (The command sequence is illustrated in Table 14. Table 14. MX28F320J3/640J3/128J3 Silicon ID Codes and Verify Sector Protect Code Type Address (1) Code (HEX) Manufacture Code 00000 32M Device Code Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 C2H 1 1 0 0 0 0 1 0 00001 (00) 72H 0 1 1 1 0 0 1 0 64M 00001 (00) 73H 0 1 1 1 0 0 1 1 128M 00001 (00) 74H 0 1 1 1 0 1 0 0 Block Lock Configuration X0002 (2) - Block is Unlocked DQ0=0 - Block is Locked DQ0=1 - Reserved for Future Use DQ1-7 * Outputs C2H at protected sector address, 00H at unprotected sector address. ** Only the top and the bottom sectors have protect-bit feature. Sector address = (A20, A19, A18,A17,A16) = 00000B or 11111B P/N:PM0858 REV. 0.4, JUN. 07, 2002 20 MX28F320J3/640J3/128J3 Table 15. Status Register Definitions High Z Symbol When Status Busy? SR.7 No WRITE STATE MACHINE STATUS SR.6 Yes ERASE SUSPEND STATUS SR.5 Yes ERASE AND CLEAR LOCK-BITS STATUS SR.4 Yes SR.3 Yes PROGRAM AND SET LOCK-BIT STATUS PROGRAMMING VOLTAGE STATUS SR.2 Yes PROGRAM SUSPEND STATUS SR.1 Yes DEVICE PROTECT STATUS SR.0 Yes RESERVED Definition Notes "1" "0" Ready Busy Block Erase Suspended Block Erase in Progress/Completed Error in Block Erasure or Successful Block Clear Lock-Bits Erase or Clear Lock-Bits Error in Setting Lock-Bit Successful Set Block Lock Bit Low Programming Voltage Programming Voltage Detected, Operation OK Aborted Program suspended Program in progress/ completed Block Lock-Bit Detected, Unlock Operation Abort 1 2 3 4 5 Notes 1. Check STS or SR.7 to determine block erase, program, or lock-bit configuration completion. SR.6-SR.0 are not driven while SR.7 = 0 2. If both SR.5 and SR.4 are "1" after a block erase or lock-bit configuration attempt, an improper command sequence was entered. 3. SR.3 does not provide a continuous programming voltage level indication. The WSM interrogates and indicates the programming voltage level only after Block Erase, Program, Set Block Lock-Bit, or Clear Block Lock-Bits command sequences. 4. SR.1 does not provide a continuous indication of block lock-bit values. The WSM interrogates the block lock-bits only after Block Erase, Program, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set. Read the block lock configuration codes using the Read Identifier Codes command to determine block lock-bit status. 5. SR.0 is reserved for future use and should be masked when polling the status register. Table 16 . Extended Status Register Definitions High Z Symbol When Status Busy? XSR.7 No WRITE BUFFER STATUS XSR.6- Yes RESERVED XSR.0 Definition Notes "1" Write buffer available "0" Write buffer not available 1 2 Notes: 1. After a Buffer-Write command, XSR.7 = 1 indicates that a Write Buffer is available. 2. XSR.6-XSR.0 are reserved for future use and should be masked when polling the status register. P/N:PM0858 REV. 0.4, JUN. 07, 2002 21 MX28F320J3/640J3/128J3 the Q7 bit to a "1". In default mode, STS will also transition to VOH. READ STATUS REGISTER COMMAND The Status Register is read after writing the Read Status Register command of 70H to the Command User Interface. Also, after starting the internal operation the device is set to the Read Status Register mode automatically. At this time, A read array/program command sequence can also be issued during erase suspend to read or program data in other blocks. During a program operation with block erase suspended, status register bit SR.7 will return to "0" and STS output (in default mode) will transition to VOL The WSM will continue to run, idling in the SUSPEND state, regardless of the state of all input control pins. The contents of Status Register are latched on the later falling edge of OE or the first edge of CE0, CE1, CE2 that enables the device OE must be toggle to VIH or the device must be disable before further reads to update the status register latch. The Read Status Register command functions independently of the VPEN voltage. The only other valid commands while block erase is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and STS (in default mode) will return to VOL. VPEN must remain at VPENH (the same VPEN level used for block erase) while block erase is suspended. Block erase cannot resume until program operations initiated during block erase suspend have completed. CLEAR STATUS REGISTER COMMAND The Erase Status, Program Status, Block Status bits and protect status are set to "1" by the Write State Machine and can only be reset by the Clear Status Register command of 50H. These bits indicates various failure conditions. BLOCK ERASE COMMAND WRITE TO BUFFER COMMAND Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command of D0H. An address within the block to be erased is required (erase changes all block data to FFH). To program the device, a Write to Buffer command is issue first. A variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the Write to Buffer Setup command is issued along with the Block Address (see Figure , Write to Buffer Flowchart " on page ). After the command is issued, the extended Status Register (XSR) can be read when CE is VIL. XSR.7 indicates if the Write Buffer is available. Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). The CPU can detect block erase completion by analyzing the output of the STS pin or status register bit SR.7. Toggle OE, CE0 , CE1 , or CE2 to update the status register. The CUI remains in read status register mode until a new command is issued. Also, reliable block erasure can only occur when VCC is valid and VPEN = VPENH . If the buffer is available, the number of words/bytes to be program is written to the device. Next, the start address is given along with the write buffer data. Subsequent writes provide additional device addresses and data, depending on the count. After the last buffer data is given, a Write Confirm command must be issued. The WSM beginning copy the buffer data to the flash array. BLOCK ERASE SUSPEND COMMAND This command only has meaning while the WSM is executing Block erase operation, and therefore will only be responded to during Block erase operation. After this command has been executed, the WSM suspend the erase operations, and then return to Read Status Register mode. The WSM will set the Q6 bit to a "1". Once the WSM has reached the Suspend state, the WSM will set If an error occurs while writing, the device will stop writing, and status register bit SR.4 will be set to a "1" to indicate a program failure. The internal WSM verify only detects errors for "1" that do not successfully program to "0" . If a program error is detected, the status register should be cleared. Any time SR.4 and/or SR.5 is set, the P/N:PM0858 REV. 0.4, JUN. 07, 2002 22 MX28F320J3/640J3/128J3 device will not accept any more Write to Buffer commands. Reliable buffered writes can only occur when VCC is valid and VPEN = VPENH. Also, successful programming requires that the corresponding block lock-bit be reset. BYTE/WORD PROGRAM COMMANDS Byte/Word program is executed by a two-command sequence. The Byte/Word Program Setup command of 40H is written to the Command Interface, followed by a second write specifying the address and data to be written. The WSM controls the program pulse application and verify operation. The CPU can detect the completion of the program event by analyzing the STS pin or status register bit SR.7. If a byte/word program is attempted while VPEN_V PENLK, status register bits SR.4 and SR.3 will be set to "1". Successful byte/word programs require that the corresponding block lock-bit be cleared. If a byte/ word program is attempted when the corresponding block lockbit is set, SR.1 and SR.4 will be set to "1". SUSPEND/RESUME COMMAND Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The Block address is required when writing the Suspend/Resume Command. The device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and Suspend Status bits will determine when the erase operation or program operation has been suspended. When SR.7 = 1, SR.2 should also be set to "1", indicating that the device is in the program suspend mode. STS in level RY/BY mode will also transition to VOH. At this time, writing of the Read Array command to the CUI enables reading data from blocks other than that which is suspended. The only other valid commands while programming is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Program Resume. When the Resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes. Status register bits SR.2 and SR.7 will automatically clear and STS in RY/BY mode will return to VOL. P/N:PM0858 REV. 0.4, JUN. 07, 2002 23 MX28F320J3/640J3/128J3 Read Configuration The device will support both asynchronous page mode and standard word/byte reads. No configuration is required. Status register and identifier only support standard word/byte single read operations. Table 17. Read Configuration Register Definition RM 16(A16) R 8 R 15 R 7 R 14 R 6 R 13 R 5 R R R R 12 11 10 9 R R R R 4 3 2 1 Notes Read mode configuration effects reads from the flash array. Status register, query, and identifier reads support standard word/byte read cycles. These bits are reserved for future use. Set these bits to "0". RCR.16 = READ MODE (RM) 0 = Standard Word/Byte Reads Enabled (Default) 1 = Page-Mode Reads Enabled RCR.15-1= RESERVED FOR FUTURE ENHANCEMENTS (R) Configuration Command The Status (STS) pin can be configured to different states using the Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued or RP is asserted low. Initially, the STS pin defaults to RY/BY operation where RY/BY low indicates that the state machine is busy. RY/BY high indicates that the state machine is ready for a new operation or suspended. Table 19, "Configuration Coding Definitions" on page 28 displays the possible STS configurations. To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed by the desired configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described below. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 00h configuration code with the Configuration command resets the STS pin to the default RY/BY level mode. The possible configurations and their usage are described in Table 19, "Configuration Coding Definitions" on page 28. The Configuration command may only be given when the device is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in both status register bits SR.4 and SR.5 being set to "1"." When configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns. P/N:PM0858 REV. 0.4, JUN. 07, 2002 24 MX28F320J3/640J3/128J3 Table 18. Configuration Coding Definitions Reserved Pulse on Program Complete (1) bit 1 bits7-2 Pulse on Erase Compete (1) bit 0 Q7 - Q2 are reserved for future use. default (Q1-Q 0 = 00) RY/BY, level mode - used to control HOLD to a memory controller to prevent accessing a flash memory subsystem while any flash device's WSM is busy. configuration 01 ER INT, pulse mode - used to generate a system interrupt pulse when any flash device in an array has completed a Block Erase. Helpful for reformatting blocks after file system free space reclamation or "cleanup" configuration 10 PR INT, pulse mode -used to generate a system interrupt pulse when any flash device in an array has complete a Program operation. Provides highest performance for servicing continuous buffer write operations. configuration 11 ER/PR INT, pulse mode -used to generate system interrupts to trigger servicing of flash arrays when either erase or program operations are completed when a common interrupt service routine is desired. Q7 - Q2 = Reserved Q1 - Q0 = STS Pin Configuration Codes 00 = default, level mode RY/BY (device ready) indication 01 = pulse on Erase complete 10 = pulse on Program complete 11 = pulse on Erase or Program Complete Configuration Codes 01b, 10b, and 11b are all pulse mode such that the STS pin pulses low then high when the operation indicated by the given configuration is completed. Configuration Command Sequences for STS pin configuration (masking bits Q7- Q 2 to 00h) are as follows: Default RY/BY level mode: B8h, 00h ER INT (Erase Interrupt): B8h, 01h Pulse-on-Erase Complete PR INT (Program Interrupt): B8h, 02h Pulse-on-Program Complete ER/PR INT (Erase or Program Interrupt): B8h, 03h Pulse-on-Erase or Program Complete NOTE: 1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns. P/N:PM0858 REV. 0.4, JUN. 07, 2002 25 MX28F320J3/640J3/128J3 tion. To return to read array mode, write the Read Array command (FFH). Set Block Lock-Bit Commands This device provided the block lock-bits, to lock and unlock the individual block. To set the block lock-bit, the two cycle Set Block Lock-Bit command is requested. This command is invalid while the WSM is running or the device is suspended. Writing the set block lock-bit command of 60H followed by confirm command and an appropriate block address. After the command is written, the device automatically outputs status register data when read. The CPU can detect the completion of the set lockbit event by analyzing the STS pin output or status register bit SR.7. Also, reliable operations occur only when VCC and VPEN are valid. With VPEN _VPENLK , lockbit contents are protected against alteration. Programming the Protection Register The protection register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide parts and eight bits at a time for byte-wide parts. First write the Protection Program Setup command, C0H. The next write to the device will latch in address and data and program the specified location. Any attempt to address Protection Program commands outside the defined protection register address space will result in a status register error. Attempting to program a locked protection register segment will result in a status register error. Clear Block Lock-Bits Command All set block lock-bits can clear by the Clear Block LockBits command. This command is invalid while the WSM is running or the device is suspended. To Clear the block lock-bits, two cycle command is requested . The device automatically outputs status register data when read. The CPU can detect completion of the clear block lock-bits event by analyzing the STS pin output or status register bit SR.7. If a clear block lock-bits operation is aborted due to V PEN or V CC transitioning out of valid range, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. Locking the Protection Register The user-programmable segment of the protection register is lockable by programming Bit 1 of the PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. Bit 1 is set using the Protection Program command to program "FFFD" to the PR-LOCK location. After these bits have been programmed, no further changes can be made to the values stored in the protection register. Protection Program commands to a locked section will result in a status register error. Protection register lockout state is not reversible. Protection Register Program Command The device offer a 128-bit protection register to increase the security of a system design. The 128-bits protection register are divided into two 64-bit segments. One is programmed in the factory with a unique 64-bit number, which is unchangeable. The other one is left blank for customer designers to program as desired. Once the customer segment is programmed, it can be locked to prevent reprogramming. Reading the Protection Register The protection register is read in the identification read mode. The device is switched to this mode by writing the Read Identifier command 90H. Once in this mode, read cycles from addresses retrieve the specified informa- P/N:PM0858 REV. 0.4, JUN. 07, 2002 26 MX28F320J3/640J3/128J3 Figure 3. Protection Register Memory Map Word Address A[23 -1]: 128 Mbit A[22 -1]: 64 Mbit A[21 -1]: 32 Mbit 88H 4 Words User Programmed 85H 84H 4 Words Factory Programmed 81H 80H 1 Word Lock NOTE: A 0 is not used in x16 mode when accessing the protection register map (See Table 20 for x16 addressing). For x8 mode A 0 is used (See Table 21 for x8 addressing). P/N:PM0858 REV. 0.4, JUN. 07, 2002 27 MX28F320J3/640J3/128J3 Table 20. Word-Wide Protection Register Addressing Word Use A8 A7 A6 A5 A4 A3 A2 A1 LOCK Both 1 0 0 0 0 0 0 0 0 Factory 1 0 0 0 0 0 0 1 1 Factory 1 0 0 0 0 0 1 0 2 Factory 1 0 0 0 0 0 1 1 3 Factory 1 0 0 0 0 1 0 0 4 User 1 0 0 0 0 1 0 1 5 User 1 0 0 0 0 1 1 0 6 User 1 0 0 0 0 1 1 1 7 User 1 0 0 0 1 0 0 0 NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A23-A9 = 0. Table 21. Byte-Wide Protection Register Addressing Word LOCK LOCK 0 1 2 3 4 5 6 7 8 9 A B C D E F Use Both Both Factory Factory Factory Factory Factory Factory Factory Factory User User User User User User User User A8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A23-A9 = 0. P/N:PM0858 REV. 0.4, JUN. 07, 2002 28 MX28F320J3/640J3/128J3 Figure 4. Write to Buffer Flowchart Start Set Time-Out NO Write E8H to Block Address Read Extended Status Register XSR.7=1 ? NO Write to Buffer Time-Out ? YES YES Write Word or Byte Count to Block Address Write Buffer Data, Start Address YES X=0 Check X=N ? Abort Write to Buffer Command? YES Write to Another Block Address NO YES Write to Buffer Failed Write Next Buffer Data, Device Address X = X+1 Program Buffer to Flash Confirm D0H Another Write to Buffer ? Issue Read Status Command NO Read Status Register SR.7=1? NO YES Full Status Check if Desired Programming Complete P/N:PM0858 REV. 0.4, JUN. 07, 2002 29 MX28F320J3/640J3/128J3 Figure 5. Program Suspend/Resume Flowchart Start Write B0H Read Status Register SR.7=1 ? NO YES NO SR.2=1 ? Programming Completed YES Write FFH Read Array Data Done Reading NO YES Write D0H Write FFH Programming Resumed Read Array Data P/N:PM0858 REV. 0.4, JUN. 07, 2002 30 MX28F320J3/640J3/128J3 Figure 6. Byte/Word Programming Flowchart Bus Command Comments Operation Write Setup Byte/ Data=40H Word Program Addr=Location to Be Programmed Write Byte/Word Data=Data to Be Program Programmed Addr=Location to Be Programmed Read Status Register Data (Note 1) Standby Check SR.7 1=WSM Ready 0=WSM Busy 1. Toggling OE (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR full status check can be done after each program operation, or after a sequence of programming operations. Write FFH after the last program operation to place device in read array mode. Start Write 40H, Address Write Data and Address Read Status Register SR.7= 0 1 Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Bus Command Operation Standby Read Status Register Data (See Above) SR.3= 1 Check SR.3 1=Programming to Voltage Error Detect Standby Check SR.1 1=Device Protect Detect RP=VIH, Block Lock-Bit is Set Only required for systems Standby Check SR.4 1=Programming Error Toggling OE (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR.4, SR.3, and SR.1 are only cleared by the Clear Status Register Command in cases where multiple location are programmed before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. VPP Range Error 0 SR.1= 1 Device Protect Error 1 Programming Error 0 SR.4= Comments 0 Byte/Word Program Successful P/N:PM0858 REV. 0.4, JUN. 07, 2002 31 MX28F320J3/640J3/128J3 Figure 7. Block Erase Flowchart Start Write 20H to Block Address Write Confirm D0H to Block Address Read Status Register SR.7=1 ? NO Write B0H? YES NO YES Full Status Check If Desired Suspend Loop Write D0H YES Erase Flash Block(s) Completed P/N:PM0858 REV. 0.4, JUN. 07, 2002 32 MX28F320J3/640J3/128J3 Figure 8. Block Erase Suspend/Resume Flowchart Bus Command Operation Write Erase Suspend Read Start Write B0H Read Status Register SR.7= Standby 0 Standby 1 SR.6= 0 Write Erase Completed Erase Resume Comments Data=B0H Addr=X Status Register Data Addr=X Check SR.7 1=WSM Ready 0=WSM Busy Check SR.6 1=Block Erase Suspend 0=Block Erase Completed Data=D0H Addr=X 1 Read Program Read or Program? Read Array Data No Program Loop Done ? Yes Write D0H Write FFH Block Erase Resumed Read Array Data P/N:PM0858 REV. 0.4, JUN. 07, 2002 33 MX28F320J3/640J3/128J3 Figure 9. Set Block Lock-Bit Flowchart Start Write 60H, Block Address Write 01H, Block Address Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Set Lock-Bit Completed FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) NO SR.3=0 ? Voltage Range Error YES YES SR.4,5=1 ? Command Sequence Error NO NO SR.4=0 ? Set Lock-Bit Error YES Set Lock-Bit Successful P/N:PM0858 REV. 0.4, JUN. 07, 2002 34 MX28F320J3/640J3/128J3 Figure 10. Clear Lock-Bit Flowchart Start Write 60H Write D0H Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Set Lock-Bit Completed FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) NO SR.3=0 ? Voltage Range Error YES YES SR.4,5=1 ? Command Sequence Error NO NO SR.5=0 ? Clear Block Lock-Bits Error YES Clear Block Lock-Bit Successful P/N:PM0858 REV. 0.4, JUN. 07, 2002 35 MX28F320J3/640J3/128J3 Figure 11. Protection Register Programming Flowchart Start Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register NO SR.7=1 ? YES Full Status Check If Desired Program Completed FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1,1 SR.3, SR.4= SR.1, SR.4= SR.1, SR.4= VPEN Range Error 0,1 Protection Register Programming Error 1,1 Attempted Program to Locked Register-Aborted YES Program Successful P/N:PM0858 REV. 0.4, JUN. 07, 2002 36 MX28F320J3/640J3/128J3 ABSOLUTE MAXIMUM RATINGS OPERATING RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC Ambient Temperature with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V A9, OE, and RESET or RESET(Note 2) . . . . . . . . .-0.5 V to +12.5 V All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Commercial (C) Devices Ambient Temperature (TA ). . . . . . . . . . . . 0C to +70C VCC Supply Voltages VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 7. 2. Minimum DC input voltage on pins A9, OE, and RESET or RESET is -0.5 V. During voltage transitions, A9, OE, and RESET or RESET may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 6. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Rat-ings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. P/N:PM0858 REV. 0.4, JUN. 07, 2002 37 MX28F320J3/640J3/128J3 DC Characteristics Symbol Parameter ILI Input and V PEN Load Current ILO Output Leakage Current ICC1 VCC Standby Current ICC2 ICC3 Notes 1 Max 1 Unit uA 10 uA 25 80 uA 0.71 2 mA 2 5 uA 15 20 mA 24 29 mA 1 1,2,3 VCC Power-Down Current VCC Page Mode Read Current Typ 1,3 ICC4 VCC Word Mode Read Current 1,3 40 50 mA ICC5 VCC Program or Set Lock-Bit 1,4 Current VCC Block Erase or Clear 1,4 Block Lock-Bits Current VCC Program Suspend or Block 1,5 Erase Suspend Current 35 40 35 40 60 70 70 80 10 mA mA mA mA mA ICC6 ICC7 P/N:PM0858 Test Conditions VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or GND VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or GND CMOS Inputs, VCC = VCC Max, Device is disabled (see table 2) RESET=VCCQ0.2V or RESET=VIL TTL Inputs, VCC=VCC max, Device is disable (see table 2), RESET=VIH or RESET=VIL RESET=GND0.2V, or RESET=VIH IOUT(STS)=0mA CMOS Inputs, VCC=VCC Max, VCCQ=VCCQ Max Device is enabled (see Table 2) f=5MHz, IOUT=0mA CMOS Inputs, VCC=VCC Max, VCCQ=VCCQ Max Device is enabled (see Table 2) f=33MHz, IOUT=0mA CMOS Inputs, VCC=VCC Max, VCCQ=VCCQ Max Device is enabled (see Table 2) f=5MHz, IOUT=0MA CMOS Inputs, VPEN=VCC TTL Inputs, VPEN=VCC CMOS Inputs, VPEN=VCC TTL Inputs, VPEN=VCC Device is disabled (see Table 2) REV. 0.4, JUN. 07, 2002 38 MX28F320J3/640J3/128J3 DC Characteristics, Continued Symbol Parameter VIL Input Low Voltage VIH Input High Voltage VOL VOH Output Low Voltage Output High Voltage Notes 4 4 Min -0.5 2.0 2,4 2,4 VPENLK VPEN Lockout during Program, 4,6,7 Erase and Lock-Bit Operations VPENH VPEN during Block Erase, 6,7 Program, or Lock-Bit Operations VLKO VCC Lockout Voltage 8 Max 0.8 VCCQ+0.5 0.4 Unit V V V 0.2 V 0.85 x VCCQ VCCQ-0.2 2.7 2.2 V V 2.2 V 3.6 V Test Conditions VCCQ=VCCQ2/3 Min IOL=2mA VCCQ=VCCQ2/3 Min IOL=100uA VCCQ=VCCQ Min IOH=-2.5mA VCCQ=VCCQ Min IOH=-100uA V NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). 2. Includes STS. 3. CMOS inputs are either VCC 0.2 V or GND 0.2 V. TTL inputs are either VIL or VIH . 4. Sampled, not 100% tested. 5. ICCWS and ICCES are specified with the device de-selected. If the device is read or written while in erase suspend mode, the device's current draw is I CCR or I CCW . 6. Block erases, programming, and lock-bit configurations are inhibited when V PEN V PENLK , and not guaranteed in the range between VPENLK (max) and VPENH (min), and above VPENH (max). 7. Typically, VPEN is connected to VCC (2.7 V - 3.6 V). 8. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO , and not guaranteed in the range between VLKO (min) and VCC (min), and above VCC (max). P/N:PM0858 REV. 0.4, JUN. 07, 2002 39 MX28F320J3/640J3/128J3 Figure 12. Transient Input/Output Reference Waveform for VCCQ=3.0V-3.6V or VCCQ=2.7V-3.6 V VCCQ VCCQ/2 Output TEST POINTS Input VCCQ/2 0.0 Note:AC test inputs are driven at VCCQ for a Logic "1" and 0.0V for a Logic "0". Input timing being, and output timing ends, at VCCQ/2V (50% of VCCQ). Input rise and fall times (10% tp 90%)<5ns. Figure 13. Transient Equivalent Testing Load Circuit 1.3V 1N914 RL=3.3K ohm Device Under Test Out CL NOTE: CL Includes Jig Capacitance Test Configuration VCCQ = VCC = 3.0 V-3.6 V VCCQ = VCC = 2.7 V-3.6 V C L (pF) 30 30 P/N:PM0858 REV. 0.4, JUN. 07, 2002 40 MX28F320J3/640J3/128J3 AC Characteristics --Read-Only Operations (1,2) Versions VCC 3.0V-3.6V(3) 2.7V-3.6V(3) (All units in ns unless otherwise noted) VCCQ 3.0V-3.6V(3) 2.7V-3.6V(3) Sym Parameter Notes Min Min tAVAV Read/Write Cycle Time 32M 64M 7 128M tAVQV tELQV Address to Output Delay CEX to Output Delay tGLQV OE to Non-Array Output Delay tPHQV RESET High to Output Delay Max 120 120 120 120 150 150 Max 32M 120 120 64M 120 120 128M 150 150 32M 2 120 120 64M 2, 7 120 120 128M 2 150 150 2, 4 50 50 32M 180 180 64M 180 180 210 210 128M 8 tELQX CEX to Output in Low Z 5 0 0 tGLQX OE to Output in Low Z 5 0 0 tEHQZ CEX High to Output in High Z 5 35 35 tGHQZ OE High to Output in High Z 5 15 15 tOH Output Hold from Address, CEX, or OE 5 0 0 Change, Whichever Occurs First tELFL/tELFH CEX Low to BYTE High or Low 5 tFLQV/tFHQV BYTE to Output Delay tFLQZ BYTE to Output in High Z 5 tEHEL CEx High to CEx Low 5 tAPA Page Address Access Time tGLQV OE to Array Output Delay 10 10 1000 1000 1000 1000 0 0 5, 6 25 30 4 25 30 NOTES:CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2). 1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate. 2. OE may be delayed up to t ELQV -t GLQV after the first edge of CE0, CE1, or CE2 that enables the device (see Table 2) without impact on t ELQV . 3. See Figures 14-16, Transient Input/Output Reference Waveform for VCCQ = 3.0V - 3.6V or VCCQ = 2.7V-3.6 V, and Transient Equivalent Testing Load Circuit for testing characteristics. 4. When reading the flash array a faster tGLQV (R16) applies. Non-array reads refer to status register reads, query reads, or device identifier reads. 5. Sampled, not 100% tested. 6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV). 7. The performance of 64Mb depends on 120ns speed grade or 150ns speed grades. 8. tPHQV is RESET low to output delay for 48-TSOP & 48-RTSOP package types. P/N:PM0858 REV. 0.4, JUN. 07, 2002 41 MX28F320J3/640J3/128J3 Figure 14. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations (for 56TSOP & 64-CSP) VIH Address (A23-A3) VIL tAVAV VIH Address (A2-A0) VIL Valid Address Valid Address Valid Address Valid Address tEHEL Disable VIH CEx[E] Enable VIL tEHQZ tAVQV VIH OE [G] VIL tGHQZ tELQV VIH WE [W] tGLQV VIL tOH tAPA tPHQV tELQX DATA[D/Q] VOH Q0- Q15 VOL High Z Valid Output Valid Valid Output Output Valid Output High Z tGLQX VIH VCC VIL VIH RESET[P] VIL tELFL/tELFH tFLQV/tFHQV tFLQZ VIH BYTE [F] VIL NOTE: 1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2). 2. For standard word/byte read operations, tAPA will equal tAVQV. 3. When reading the flash array a faster tGLQV applies. Non-array reads refer to status register reads, query reads, or device identifier reads. P/N:PM0858 REV. 0.4, JUN. 07, 2002 42 MX28F320J3/640J3/128J3 Figure 15. AC Waveform for Both Page-Mode and Standard Word Read Operations (for 48-TSOP & 48-RTSOP) VIH Address (A23-A3) VIL tAVAV Address VIH (A2-A0) VIL Valid Address Valid Address Valid Address Valid Address tEHEL Disable VIH CEx[E] Enable VIL tEHQZ tAVQV VIH OE [G] VIL tGHQZ tELQV VIH WE [W] tGLQV VIL tOH tAPA tPHQV tELQX DATA[D/Q] VOH Q0- Q15 VOL High Z Valid Valid Valid Output Output Output Valid Output High Z tGLQX VIH VCC VIL RESET[P] VIH (Note 4) VIL NOTE: 1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2). 2. For standard word/byte read operations, tAPA will equal tAVQV. 3. When reading the flash array a faster tGLQV applies. Non-array reads refer to status register reads, query reads, or device identifier reads. 4. For 48-TSOP & 48-RTSOP the RESET pin is high enable. P/N:PM0858 REV. 0.4, JUN. 07, 2002 43 MX28F320J3/640J3/128J3 AC Characteristics--Write Operations (1,2) Versions Valid for All Speeds Symbol Parameter tPHWL (tPHEL ) RESET High Recovery to WE(CEX) Going Low tELWL (tWLEL ) Unit Notes Min Max 3,10 2 us CEX (WE) Low to WE(CEX) Going Low 4 0 ns tWP Write Pulse Width 4 70 ns tDVWH (tDVEH ) Data Setup to WE(CEX) Going High 5 50 ns tAVWH (tAVEH ) Address Setup to WE(CEX) Going High 5 55 ns tWHEH (tEHWH) CEX (WE) Hold from WE(CEX) High 0 ns tWHDX (tEHDX) Data Hold from WE(CEX) High 0 ns tWHAX (tEHAX) Address Hold from WE(CEX) High 0 ns tWPH Write Pulse Width High 6 30 ns tVPWH (tVPEH) VPEN Setup to WE(CEX) Going High 3 0 ns tWHGL (tEHGL) Write Recovery before Read 7 35 ns tWHRL (tEHRL) WE(CEX) High to STS Going Low 8 tQVVL VPEN Hold from Valid SRD, STS Going High 500 ns 3,8,9 0 4,9 64 75/85 us tWHQV6 (tEHQV6) Clear Block Lock-Bits Time 4 0.5 0.70 sec tWHRH1 (tEHRH1) Program Suspend Latency Time to Read 9 25 75/90 us tWHRH (tEHRH) 9 26 35/40 us tWHQV5 (tEHQV5) Set Lock-Bit Time Erase Suspend Latency Time to Read ns NOTES: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2). 1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics-Read-Only Operations. 2. A write operation can be initiated and terminated with either CE X or WE. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from CEX or WE going low (whichever goes low last) to CEX or WE going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. 5. Refer to Table 4 for valid A IN and D IN for block erase, program, or lock-bit configuration. 6. Write pulse width high (t WPH) is defined from CEX or WE going high (whichever goes high first) to CEX or WE going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL . 7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write. 8. STS timings are based on STS configured in its RY/BY default mode. 9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5=0). 10.For 48-TSOP & 48-RTSOP, the RESET pin is high enable. P/N:PM0858 REV. 0.4, JUN. 07, 2002 44 MX28F320J3/640J3/128J3 Figure 16. AC Waveform for Write Operations (for 56-TSOP & 64-CSP) A B C AIN AIN D E F VIH Address (A) VIL tAVWH (tAVEH) Disable VIH tWHAX (tEHAX) CEx,(WE)[E(W)] Enable VIL tWHGL (tEHGL) tWHEH (tEHWH) tPHWL (tPHEL) VIH OE VIL tELWL (tWLEL) tWPH tWHQZ/tWHRH Disable VIH WE,(CEx)[W(E)] Enable VIL tWP tOVWH (tDVEH) tWHDX (tEHDX) VIH DATA[D/Q] VIL DIN Valid SRD DIN DIN tWHRL (tEHRL) VOH STS[R] VOL VIH RESET [P] VIL tVPWH (tVPEH) tQVVL VPENH VPEN[V] VPENLK VIL NOTES: 1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2). STS is shown in its default mode (RY/BY). a. VCC power-up and standby. b. Write block erase, write buffer, or program setup. c. Write block erase or write buffer confirm, or valid address and data. d. Automated erase delay. e. Read status register or query data. f. Write Read Array command. P/N:PM0858 REV. 0.4, JUN. 07, 2002 45 MX28F320J3/640J3/128J3 Figure 17. AC Waveform for Write Operations (for 48-TSOP & 48-RSOP) A B C AIN AIN D E F VIH Address (A) VIL tAVWH (tAVEH) Disable VIH tWHAX (tEHAX) CEx,(WE)[E(W)] Enable VIL tWHGL (tEHGL) tWHEH (tEHWH) tPHWL (tPHEL) VIH OE VIL tELWL (tWLEL) tWPH tWHQZ/tWHRH Disable VIH WE,(CEx)[W(E)] Enable VIL tWP tOVWH (tDVEH) tWHDX (tEHDX) VIH DATA[D/Q] VIL DIN DIN Valid SRD DIN VIH RESET [P] (Note 2) VIL NOTES: 1. CEX low is defined as the first edge of CE0 , CE1 , or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2). STS is shown in its default mode (RY/BY). a. VCC power-up and standby. b. Write block erase, write buffer, or program setup. c. Write block erase or write buffer confirm, or valid address and data. d. Automated erase delay. e. Read status register or query data. f. Write Read Array command. 2. For 48-TSOP & 48-RTSOP, the RESET pin is high enable. P/N:PM0858 REV. 0.4, JUN. 07, 2002 46 MX28F320J3/640J3/128J3 Figure 18. AC Waveform for Reset Operation (for 56-TSOP & 64-CSP) VIH STS (R) VIL tPHRH VIH RESET (P) VIL tPLPH NOTE: 1. STS is shown in its default mode (RY/BY). Figure 19. AC Waveform for Reset Operation (for 48-TSOP & 48-RTSOP) VIH RESET (P) (Note 2) VIL tPLPH NOTE: 1. STS is shown in its default mode (RY/BY). 2. For 48-TSOP & 48-RTSOP, the RESET pin is high enable. Reset Specifications (1) Sym tPLPH tPHRH Parameter Notes RESET Pulse Low Time 2 (If RESET is tied to VCC , this specification is not applicable) (for 48-TSOP & 48-RSTOP, the tPLPH indicates the RESET Pulse High Time) RESET High to Reset during Block Erase, Program, or 3 Lock-Bit Configuration Min 35 Max Unit us 2 us NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RESET is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required RESET Pulse Low Time is 100ns. 3. A reset time, tPHQV, is required from the latter of STS (in RY/BY mode) or RESET going high until outputs are valid. P/N:PM0858 REV. 0.4, JUN. 07, 2002 47 MX28F320J3/640J3/128J3 ERASE AND PROGRAMMING PERFORMANCE(1) LIMITS PARAMETER MIN. TYP.(2) MAX. UNITS Block Erase Time 2.0 15.0 sec Write Buffer Byte Program Time 218 654 us Byte Program Time (Using Word/Byte Program Command) 210 630 us Block Program Time (Using Write to Buffer Command) 0.8 2.4 sec (Time to Program 32 bytes/16 words) Block Erase/Program Cycles Note: C1 10 C2 100 C3 1,000 C4 10,000 Cycles 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25C,3.3V. Additionally programming typically assume checkerboard pattern. LATCH-UP CHARACTERISTICS MIN. MAX. Input Voltage with respect to GND on all pins except I/O pins -1.0V 13.5V Input Voltage with respect to GND on all I/O pins -1.0V Vcc + 1.0V -100mA +100mA Current Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time. CAPACITANCE C, VCC=2.7V~3.6V TA=0 C to 70 Parameter Symbol Parameter Description Test Set TYP MAX UNIT CIN Input Capacitance VIN=0 6 8 pF COUT Output Capacitance VOUT=0 8 12 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA=25C, f=1.0MHz DATA RETENTION Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150 10 Years 125 20 Years P/N:PM0858 REV. 0.4, JUN. 07, 2002 48 MX28F320J3/640J3/128J3 ORDERING INFORMATION PLASTIC PACKAGE Part NO. Access Time Package type Cycles (ns) MX28F128J3TBC-15C1 150/25 48-TSOP 10 MX28F128J3RBC-15C1 150/25 48-RTSOP 10 MX28F128J3TC-15C3 150/25 56-TSOP 1,000 MX28F128J3TBC-15C3 150/25 48-TSOP 1,000 MX28F128J3RBC-15C3 150/25 48-RTSOP 1,000 MX28F128J3XCC-15C3 150/25 64-CSP 1,000 MX28F128J3TC-15C4 150/25 56-TSOP 10,000 MX28F128J3TBC-15C4 150/25 48-TSOP 10,000 MX28F128J3RBC-15C4 150/25 48-RTSOP 10,000 MX28F128J3XCC-15C1 150/25 64-CSP 10 MX28F128J3XCC-15C4 150/25 64-CSP 10,000 MX28F640J3TC-12C3 120/25 56-TSOP 1,000 MX28F640J3IAC-12C3 120/25 48-FCCSP 1,000 MX28F640J3XCC-12C3 120/25 64-CSP 1,000 MX28F640J3TC-15C4 150/25 56-TSOP 10,000 MX28F640J3IAC-15C4 150/25 48-FCCSP 10,000 MX28F640J3XCC-15C4 150/25 64-CSP 10,000 MX28F320J3TC-12C3 120/25 56-TSOP 1,000 MX28F320J3IAC-12C3 120/25 48-FCCSP 1,000 MX28F320J3XCC-12C3 120/25 64-CSP 1,000 MX28F320J3TC-12C4 120/25 56-TSOP 10,000 MX28F320J3IAC-12C4 120/25 48-FCCSP 10,000 MX28F320J3XCC-12C4 120/25 64-CSP 10,000 P/N:PM0858 REV. 0.4, JUN. 07, 2002 49 MX28F320J3/640J3/128J3 PACKAGE INFORMATION 48-Ball Flip Chip CSP P/N:PM0858 REV. 0.4, JUN. 07, 2002 50 MX28F320J3/640J3/128J3 56 TSOP P/N:PM0858 REV. 0.4, JUN. 07, 2002 51 MX28F320J3/640J3/128J3 64 CSP P/N:PM0858 REV. 0.4, JUN. 07, 2002 52 MX28F320J3/640J3/128J3 48 TSOP P/N:PM0858 REV. 0.4, JUN. 07, 2002 53 MX28F320J3/640J3/128J3 48 TSOP (Reverse ) P/N:PM0858 REV. 0.4, JUN. 07, 2002 54 MX28F320J3/640J3/128J3 REVISION HISTORY Revision No. Description 0.1 1. To add 32M/128M information 2. To modify the CSP package size from 13x10mm to 10x13mm 0.2 1. Add 48-TSOP 2. Technology name is changed from MXVAND to Nbit 3. 48-ball CSP name is added "Flip Chip" wording 4. 64-ball CSP naming is changed 5. Mis-tying : removing verify sector 5-1 Protection code from Table 14 5-2 Correct Program Suspend/Resume flowchart 5-3 Correct Block Erase Suspend/Resume flowchart 0.3 1. Added 48-RTSOP 2. Added deep power-down spec:5uA(max.) 3. Changed standby current from 120uA(max.) to 80uA(max.) 4. Added "Cx" on part number to distinguish different program 5. Changed spec of tPHWL(tPHEL) from 1us to 2us 6. Changed spec of tPHRH from 100ns to 2us 7. Changed speed spec of 32Mb from 110ns-->120ns 0.4 Deep power down mode is entering by RESET pin at VIH of 48-TSOP & 48-RTSOP types. 64-CSP & 56-TSOP is still kept RESET=VIL for entering deep power down mode. Removed reset command P/N:PM0858 Page All P3 P1 P1 P1 P1,4 Date JAN/17/2002 APR/04/2002 P8,19 P30 P31 P1,3,47 P1,9,11,38 P38 P1,3,46,47 P43 P45 P1,41,47 P3,5,6,8,9,20, P37,38,41~47 MAY/28/2002 JUN/07/2002 P10,11 REV. 0.4, JUN. 07, 2002 55 MX28F320J3/640J3/128J3 MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-6688 FAX:+886-3-563-2888 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-348-8385 FAX:+65-348-8096 TAIPEI OFFICE: TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.