19-5578; Rev 7; 8/11 I2C RTC with Trickle Charger Features The DS1340 is a real-time clock (RTC)/calendar that is pin compatible and functionally equivalent to the ST M41T00, including the software clock calibration. The device additionally provides trickle-charge capability on the VBACKUP pin, a lower timekeeping voltage, and an oscillator STOP flag. Block access of the register map is identical to the ST device. Two additional registers, which are accessed individually, are required for the trickle charger and flag. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. A built-in power-sense circuit detects power failures and automatically switches to the backup supply. Reads and writes are inhibited while the clock continues to run. The device is programmed serially through an I2C bidirectional bus. Enhanced Second Source for the ST M41T00 Available in a Surface-Mount Package with an Integrated Crystal (DS1340C) Fast (400kHz) I2C Interface Software Clock Calibration RTC Counts Seconds, Minutes, Hours, Day, Date, Month, and Year Automatic Power-Fail Detect and Switch Circuitry Trickle-Charge Capability Low Timekeeping Voltage Down to 1.3V Three Operating Voltage Ranges (1.8V, 3V, and 3.3V) Oscillator Stop Flag Available in 8-Pin SOP or SO Packages Underwriters Laboratories (UL) Recognized Applications Ordering Information Portable Instruments Point-of-Sale Equipment PART TEMP RANGE PINPACKAGE TOP MARK DS1340Z-18+ -40C to +85C 8 SO (0.150in) D1340-18 DS1340Z-3+ -40C to +85C 8 SO (0.150in) DS1340-3 DS1340Z-33+ -40C to +85C 8 SO (0.150in) D134033 DS1340U-18+ -40C to +85C 8 SOP DS1340U-3+ -40C to +85C 8 SOP 1340 -3 DS1340U-33+ -40C to +85C 8 SOP 1340 -33 Medical Equipment Telecommunications Typical Operating Circuit VCC VCC CRYSTAL VCC RPU RPU 1 X1 2 X2 6 SCL C1 8 VCC FT/OUT 7 1340 -18 DS1340C-18# -40C to +85C 16 SO DS1340C-18 DS1340C-3# -40C to +85C 16 SO DS1340C-3 DS1340C-33# -40C to +85C 16 SO DS1340C-33 +Denotes a lead(Pb)-free/RoHS-compliant package. CPU DS1340 5 SDA RPU = tR / CB VBACKUP GND 4 3 #Denotes a RoHS-compliant device that may include lead(Pb) that is exempt under RoHS requirements. The lead finish is JESD97 category e3, and is compatible with both lead-based and lead-free soldering processes. A "+" anywhere on the top mark denotes a lead(Pb)-free device. A "#" denotes a RoHS-compliant device. Pin Configurations appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 DS1340 General Description DS1340 I2C RTC with Trickle Charger ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC Pin Relative to Ground .....-0.3V to +6.0V Voltage Range on SDA, SCL, and FT/OUT Relative to Ground..................................-0.3V to (VCC + 0.3V) Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Lead Temperature (soldering, 10s) .................................+260C Soldering Temperature (reflow) .......................................+260C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (VCC = VCC MIN to VCC MAX, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL MIN TYP MAX DS1340-18 CONDITIONS 1.71 1.8 5.5 2.7 3.0 5.5 2.97 3.3 Supply Voltage (Note 2) VCC DS1340-3 Input Logic 1 (SDA, SCL) VIH (Note 2) Input Logic 0 (SDA, SCL) VIL (Note 2) Supply Voltage, Pullup (FT/OUT, SDA, SCL), VCC = 0V VPU (Note 2) DS1340-33 Backup Supply Voltage (Note 2) Trickle-Charge Current-Limiting Resistors VBACKUP DS1340-18 1.3 3.7 DS1340-3 1.3 3.7 DS1340-33 1.3 2000 I/O Leakage (SDA, FT/OUT) ILO SDA Logic 0 Output I OLSDA FT/OUT Logic 0 Output I OLSQW ICCA ICCS (Note 6) V V 5.5 (Note 5) ILI 2 5.5 R2 Input Leakage (SCL, CLK) VBACKUP Leakage Current V 250 VPF Standby Current (Note 8) V +0.3 x VCC (Notes 3, 4) Power-Fail Voltage (Note 2) Active Supply Current (Note 7) VCC + 0.3 R1 R3 V 5.5 0.7 x VCC -0.3 UNITS 4000 DS1340-18 1.51 1.6 1.71 DS1340-3 2.45 2.6 2.7 DS1340-33 2.70 2.88 2.97 -1 -1 +1 A +1 A VCC > 2V; VOL = 0.4V 3.0 1.7V < VCC < 2V; VOL = 0.2 x VCC VCC > 2V; VOL = 0.4V 3.0 1.7V < VCC < 2V; VOL = 0.2 x VCC 3.0 1.3V < VCC < 1.7V; VOL = 0.2x VCC DS1340-18; VCC = 1.89V 250 3.0 72 150 DS1340-3; VCC = 3.3V 108 200 DS1340-33; VCC = 5.5V 192 300 DS1340-18; VCC = 1.89V 60 100 DS1340-3; VCC = 3.3V 81 125 DS1340-33; VCC = 5.5V 100 150 IBACKUPLKG VBACKUP = 3.7V _______________________________________________________________________________________ V 100 mA mA A A A nA I2C RTC with Trickle Charger (VCC = 0V, VBACKUP = 3.7V, TA = -40C to +85C, unless otherwise noted.) (Note 1) PARAMETER VBACKUP Current VBACKUP Data-Retention Current SYMBOL CONDITIONS MIN TYP MAX UNITS IBACKUP1 OSC ON, FT = 0 (Note 9) 800 1150 IBACKUP2 OSC ON, FT = 1 (Note 9) 850 1250 IBACKUP3 OSC ON, FT = 0, VBACKUP = 3.0V, TA = +25C (Notes 9, 10) 800 1000 25.0 100 nA TYP MAX UNITS IBACKUPDR OSC OFF nA AC ELECTRICAL CHARACTERISTICS (VCC = VCC MIN to VCC MAX, TA = -40C to +85C, unless otherwise noted.) (Notes 1,14, Figure 1) PARAMETER SYMBOL SCL Clock Frequency f SCL Bus Free Time Between STOP and START Conditions tBUF Hold Time (Repeated) START Condition (Note 11) tHD:STA Low Period of SCL Clock tLOW High Period of SCL Clock tHIGH Data Hold Time (Notes 12, 13) tHD:DAT Data Setup Time (Note 14) t SU:DAT START Setup Time t SU:STA Rise Time of SDA and SCL Signals (Note 15) tR Fall Time of SDA and SCL Signals (Note 15) tF Setup Time for STOP Condition t SU:STO Capacitive Load for Each Bus Line CB I/O Capacitance (SCL, SDA) CI/O Pulse Width of Spikes that Must be Suppressed by the Input Filter t SP Oscillator Stop Flag (OSF) Delay t OSF CONDITIONS Standard mode Fast mode MIN 0 100 100 400 Standard mode 4.7 Fast mode 1.3 Standard mode 4.0 Fast mode 0.6 Standard mode 4.7 Fast mode 1.3 Standard mode 4.0 Fast mode 0.6 s s s s Standard mode 0 0.9 Fast mode 0 0.9 Standard mode 250 Fast mode 100 Standard mode 4.7 Fast mode 0.6 s 20 + 0.1CB 1000 Fast mode 20 + 0.1CB 300 Standard mode 20 + 0.1CB 20 + 0.1CB 300 Standard mode 4.7 Fast mode 0.6 s ns Standard mode Fast mode kHz 300 ns ns s (Note 15) 400 pF 10 pF Fast mode 30 ns (Note 16) 100 ms _______________________________________________________________________________________ 3 DS1340 DC ELECTRICAL CHARACTERISTICS DS1340 I2C RTC with Trickle Charger POWER-UP/POWER-DOWN CHARACTERISTICS (TA = -40C to +85C) (Figure 2) PARAMETER SYMBOL CONDITIONS MIN TYP (Note 17) MAX UNITS 2 ms Recovery at Power-Up tREC VCC Fall Time; VPF(MAX) to VPF(MIN) tVCCF 300 s VCC Rise Time; VPF(MIN) to VPF(MAX) tVCCR 0 s WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: Limits at -40C are guaranteed by design and not production tested. All voltages are referenced to ground. Measured at VCC = typ, VBACKUP = 0V, register 08h = A5h. The use of the 250 trickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled. Measured at VCC = typ, VBACKUP = 0V, register 08h = A6h. Measured at VCC = typ, VBACKUP = 0V, register 08h = A7h. ICCA--SCL clocking at max frequency = 400kHz. Specified with I2C bus inactive. Measured with a 32.768kHz crystal attached to the X1 and X2 pins. Limits at +25C are guaranteed by design and not production tested. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT only has to be met if the device does not stretch the low period (tLOW) of the SCL signal. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT to 250ns must be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR MAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. CB--total capacitance of one bus line in pF. The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the 0V VCC VCCMAX and 1.3V VBAT 3.7V range. This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs. SDA tBUF tF tHD:STA tLOW tSP SCL tHIGH tHD:STA tHD:DAT STOP tSU:STA tR START tSU:DAT REPEATED START NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). Figure 1. Data Transfer on I2C Serial Bus 4 _______________________________________________________________________________________ tSU:STO I2C RTC with Trickle Charger VPF VPF(MIN) DS1340 VCC VPF(MAX) VPF tR tF tREC INPUTS RECOGNIZED DON'T CARE RECOGNIZED HIGH-Z OUTPUTS VALID VALID Figure 2. Power-Up/Power-Down Timing Typical Operating Characteristics (VCC = +3.3V, TA = +25C, unless otherwise noted.) 100 800 -3.3V SUPPLY CURRENT (nA) 150 850 DS1340 toc02 DS1340 toc01 125 SUPPLY CURRENT (A) SUPPLY CURRENT (A) 200 IBACKUP1 (FT = 0) vs. VBACKUP ICCS vs. VCC FT = 0 150 100 -3.0V 75 DS1340 toc03 ICCSA vs. VCC FT = 0 250 -1.8V 50 750 700 650 600 550 500 50 25 450 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V) VCC (V) VBACKUP (V) IBACKUP2 (FT = 1) vs. VBACKUP IBACKUP3 vs. TEMPERATURE OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE (FT x 64) 850 VBACKUP = 3.0V 32768.6 32768.5 800 700 650 600 550 500 750 FREQUENCY (Hz) SUPPLY CURRENT (nA) 750 700 650 400 VBACKUP (V) 32768.3 32768.2 32768.1 32768.0 500 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 32768.4 600 550 450 DS1340 toc06 800 DS1340 toc05 DS1340 toc04 850 SUPPLY CURRENT (nA) 400 0 -40 -20 0 20 40 TEMPERATURE (C) 60 80 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VBACKUP (V) _______________________________________________________________________________________ 5 I2C RTC with Trickle Charger DS1340 Pin Description PIN NAME 8 16 1 -- X1 2 -- X2 FUNCTION Connections for a Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF. X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, X2, is left unconnected if an external oscillator is connected to X1. Connection for a Secondary Power Supply. For the 1.8V and 3V devices, VBACKUP must be held between 1.3V and 3.7V for proper operation. Diodes placed in series between the supply and the input pin may result in improper operation. VBACKUP can be as high as 5.5V on the 3.3V device. VBACKUP This pin can be connected to a primary cell such as a lithium coin cell. Additionally, this pin can be connected to a rechargeable cell or a super cap when used with the trickle-charge feature. UL recognized to ensure against reverse charging when used with a lithium battery (www.maxim-ic.com/qa/info/ul). 3 14 4 15 GND Ground 5 16 SDA Serial Data Input/Output. SDA is the data input/output for the I2C serial interface. The SDA pin is open drain and requires an external pullup resistor. 6 1 SCL Serial Clock Input. SCL is the clock input for the I2C interface and is used to synchronize data movement on the serial interface. 7 2 FT/OUT Frequency Test/Output. This pin is used to output either a 512Hz signal or the value of the OUT bit. When the FT bit is logic 1, the FT/OUT pin toggles at a 512Hz rate. When the FT bit is logic 0, the FT/OUT pin reflects the value of the OUT bit. This open-drain pin requires an external pullup resistor, and operates with either VCC or VBACKUP applied. The pullup voltage can be up to 5.5V, regardless of the voltage on VCC. If not used, this pin can be left unconnected. 8 3 VCC Primary Power Supply. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the device and VCC is below VPF, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. -- 4-13 N.C. No Connection. Must be connected to ground. Detailed Description The DS1340 is a low-power clock/calendar with a trickle charger. Address and data are transferred serially through a I2C bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The DS1340 has a built-in power-sense circuit that detects power failures and automatically switches to the backup supply. Power Control The power-control function is provided by a precise, temperature-compensated voltage reference and a comparator circuit that monitors the V CC level. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked 6 from any access. If V PF is less than V BACKUP , the device power is switched from VCC to VBACKUP when VCC drops below VPF. If VPF is greater than VBACKUP, the device power is switched from VCC to VBACKUP Table 1. Power Control SUPPLY CONDITION READ/WRITE ACCESS POWERED BY VCC < V PF, VCC < VBACKUP No VBAT VCC < V PF, VCC > VBACKUP No VCC VCC > V PF, VCC < VBACKUP Yes VCC VCC > V PF, VCC > VBACKUP Yes VCC _______________________________________________________________________________________ I2C RTC with Trickle Charger the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks (www.maxim-ic.com/RTCapps) for detailed information. Oscillator Circuit DS1340C Only The DS1340 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 2 specifies several crystal parameters for the external crystal. Figure 3 shows a functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is usually less than one second. The DS1340C integrates a standard 32,768Hz crystal into the package. Typical accuracy with nominal VCC and +25C is approximately +15ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature. Clock Accuracy The initial clock accuracy depends on the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 4 shows a typical PC board layout for isolating Table 2. Crystal Specifications* PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL MIN TYP fO 32.768 ESR CL 12.5 MAX UNITS kHz 80 Operation The DS1340 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code followed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VCC to VBACKUP when V CC drops below V PF . If V PF is greater than VBACKUP, the device power is switched from VCC to VBACKUP when VCC drops below VBACKUP. The registers are maintained from the VBACKUP source until VCC is returned to nominal levels. The functional diagram (Figure 5) shows the main elements of the serial RTC. k pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. LOCAL GROUND PLANE (LAYER 2) X1 RTC CRYSTAL X2 COUNTDOWN CHAIN CL1 CL2 RTC REGISTERS GND X2 X1 CRYSTAL Figure 4. Layout Example Figure 3. Oscillator Circuit Showing Internal Bias Network _______________________________________________________________________________________ 7 DS1340 when VCC drops below VBACKUP. The registers are maintained from the V BACKUP source until V CC is returned to nominal levels (Table 1). After VCC returns above VPF, read and write access is allowed tREC. DS1340 I2C RTC with Trickle Charger X1 FT/OUT CL CL X2 512Hz 32,768Hz MUX/ BUFFER DIVIDER AND CALIBRATION CIRCUIT "C" VERSION ONLY 1Hz VCC CLOCK AND CALENDAR REGISTERS POWER CONTROL VBACKUP N CONTROL LOGIC SERIAL INTERFACE AND ADDRESS REGISTER SCL SDA USER BUFFER (7 BYTES) DS1340 Figure 5. Functional Diagram Address Map Table 3 shows the DS1340 address map. The RTC registers are located in address locations 00h to 06h, and the control register is located at 07h. The trickle-charge and flag registers are located in address locations 08h to 09h. During a multibyte access of the timekeeping registers, when the address pointer reaches 07h--the end of the clock and control register space--it wraps around to location 00h. Writing the address pointer to the corresponding location accesses address locations 08h and 09h. After accessing location 09h, the address pointer wraps around to location 00h. On a I2C START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to reread the registers in case the main registers update during a read. Clock and Calendar The time and calendar information is obtained by reading the appropriate register bytes. Table 3 shows the RTC registers. The time and calendar data are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the Table 3. Address Map ADDRESS BIT 7 00H EOSC BIT 6 01H X 02H CEB CB 03H X X 04H X X 05H X X 06H BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION RANGE Seconds 00-59 10 Seconds Seconds 10 Minutes Minutes Minutes 00-59 Hours Century/Hours 0-1; 00-23 Day 01-07 01-31 10 Hours X X X Day 10 Date X 10 Month 10 Year Date Date Month Month 01-12 Year Year 00-99 07H OUT FT S CAL4 CAL3 CAL2 CAL1 CAL0 Control -- 08H TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0 Trickle Charger -- 09H OSF 0 0 0 0 0 0 0 Flag -- X = Read/Write bit Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. 8 _______________________________________________________________________________________ I2C RTC with Trickle Charger When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any START or STOP and when the register pointer rolls over to zero. The time information is read from these secondary registers while the clock continues to run. This eliminates the need to reread the registers in case the internal registers update during a read. The divider chain is reset whenever the seconds register is written. Write transfers occur on the acknowledge from the DS1340. Once the divider chain is reset, to BIT 7 TCS3 BIT 6 TCS2 BIT 5 TCS1 BIT 4 TCS0 1 OF 16 SELECT NOTE: ONLY 1010b ENABLES CHARGER BIT 3 DS1 BIT 2 DS0 avoid rollover issues, the remaining time and date registers must be written within one second. Special-Purpose Registers The DS1340 has three additional registers (control, trickle charger, and flag) that control the RTC, trickle charger, and oscillator flag output. Control Register (07h) Bit 7: Output Control (OUT). This bit controls the output level of the FT/OUT pin when the FT bit is set to 0. If FT = 0, the logic level on the FT/OUT pin is 1 if OUT = 1 and 0 if OUT = 0. The initial power-up OUT value is 1. Bit 6: Frequency Test (FT). When this bit is 1, the FT/OUT pin toggles at a 512Hz rate. When FT is written to 0, the OUT bit controls the state of the FT/OUT pin. The initial power-up value of FT is 0. Bit 5: Calibration Sign Bit (S). A logic 1 in this bit indicates positive calibration for the RTC. A 0 indicates negative calibration for the clock. See the Clock Calibration section for a detailed description of the bit operation. The initial power-up value of S is 0. Bits 4 to 0: Calibration Bits (CAL4 to CAL0). These bits can be set to any value between 0 and 31 in binary form. See the Clock Calibration section for a detailed description of the bit operation. The initial power-up value of CAL0-CAL4 is 0. Trickle-Charger Register (08h) The simplified schematic in Figure 6 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4-7) control the selection of the trickle charger. To prevent accidental enabling, only a BIT 1 BIT 0 ROUT1 ROUT0 TCS0-3 = TRICKLE-CHARGER SELECT DS0-1 = DIODE SELECT TOUT0-1 = RESISTOR SELECT 1 OF 2 SELECT 1 OF 3 SELECT R1 250 VCC R2 2k VBACKUP R3 4k Figure 6. Trickle Charger Functional Diagram _______________________________________________________________________________________ 9 DS1340 binary-coded decimal (BCD) format. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. Bit 7 of register 0 is the enable oscillator (EOSC) bit. When this bit is set to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled. The initial power-up value of EOSC is 0. The clock can be halted whenever the timekeeping functions are not required, minimizing VBAT current (IBACKUPDR) when VCC is not applied. Location 02h is the century/hours register. Bit 7 and bit 6 of the century/hours register are the century-enable bit (CEB) and the century bit (CB). Setting CEB to logic 1 causes the CB bit to toggle, either from a logic 0 to a logic 1, or from a logic 1 to a logic 0, when the years register rolls over from 99 to 00. If CEB is set to logic 0, CB does not toggle. DS1340 I2C RTC with Trickle Charger Table 4. Trickle-Charge Register TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0 X X X X 0 0 X X Disabled X X X X 1 1 X X Disabled X X X X X X 0 0 Disabled 1 0 1 0 0 1 0 1 No diode, 250 resistor 1 0 1 0 1 0 0 1 One diode, 250 resistor 1 0 1 0 0 1 1 0 No diode, 2k resistor 1 0 1 0 1 0 1 0 One diode, 2k resistor 1 0 1 0 0 1 1 1 No diode, 4k resistor 1 0 1 0 1 0 1 1 One diode, 4k resistor 0 0 0 0 0 0 0 0 Power-on reset value pattern on 1010 enables the trickle charger. All other patterns disable the trickle charger. The trickle charger is disabled when power is first applied. The diodeselect (DS) bits (bits 2, 3) select whether or not a diode is connected between VCC and VBACKUP. If DS is 01, no diode is selected; if DS is 10, a diode is selected. The ROUT bits (bits 0, 1) select the value of the resistor connected between VCC and VBACKUP. Table 3 shows the resistor selected by the resistor select (ROUT) bits and the diode selected by the diode select (DS) bits. Warning: The ROUT value of 250 must not be selected whenever VCC is greater than 3.63V. The user determines diode and resistor selection according to the maximum current desired for battery or super cap charging (Table 4). The maximum charging current can be calculated as illustrated in the following example. Assume that a 3.3V system power supply is applied to VCC and a super cap is connected to VBACKUP. Also assume that the trickle charger has been enabled with a diode and resistor R2 between VCC and VBACKUP. The maximum current IMAX would therefore be calculated as follows: IMAX = (3.3V - diode drop) / R2 (3.3V - 0.7V) / 2k 1.3mA As the super cap charges, the voltage drop between VCC and VBACKUP decreases and therefore the charge current decreases. Flag Register (09h) Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time period and may be used to judge the validity of the clock and calendar data. This bit is edge triggered and is set to logic 1 when the 10 FUNCTION internal circuitry senses that the oscillator has transitioned from a normal run state to a STOP condition. The following are examples of conditions that can cause the OSF bit to be set: 1) 2) 3) 4) The first time power is applied. The voltages present on VCC and VBACKUP are insufficient to support oscillation. The EOSC bit is set to 1, disabling the oscillator. External influences on the crystal (e.g., noise, leakage). The OSF bit remains at logic 1 until written to logic 0. It can only be written to logic 0. Attempting to write OSF to logic 1 leaves the value unchanged. Bits 6 to 0: All other bits in the flag register read as 0 and cannot be written. Clock Calibration The DS1340 provides a digital clock calibration feature to allow compensation for crystal and temperature variations. The calibration circuit adds or subtracts counts from the oscillator divider chain at the divide-by-256 stage. The number of pulses blanked (subtracted for negative calibration) or inserted (added for positive calibration) depends upon the value loaded into the five calibration bits (CAL4-CAL0) located in the control register. Adding counts speeds the clock up and subtracting counts slows the clock down. The calibration bits can be set to any value between 0 and 31 in binary form. Bit 5 of the control register, S, is the sign bit. A value of 1 for the S bit indicates positive calibration, while a value of 0 represents negative calibration. Calibration occurs within a 64-minute cycle. The first 62 minutes in the cycle can, once per minute, ______________________________________________________________________________________ I2C RTC with Trickle Charger slave on the I2C bus. Connections to the bus are made through the open-drain I/O lines SDA and SCL. Within the bus specifications a standard mode (100kHz max clock rate) and a fast mode (400kHz max clock rate) are defined. The DS1340 works in both modes. The following bus protocol has been defined (Figure 7): * Data transfer can be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. START data transfer: A change in the data line's state from high to low, while the clock line is high, defines a START condition. STOP data transfer: A change in the data line's state from low to high, while the clock line is high, defines a STOP condition. Data valid: The data line's state represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Note: Setting the calibration bits does not affect the frequency test output frequency. Also note that writing to the control register resets the divider chain. I2C Serial Data Bus The DS1340 supports a bidirectional I2C bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The DS1340 operates as a MSB FIRST MSB Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and STOP conditions is not limited, and is LSB MSB LSB SDA SLAVE ADDRESS SCL 1-7 IDLE START CONDITION R/W 8 ACK 9 DATA 1-7 ACK 8 REPEATED IF MORE BYTES ARE TRANSFERRED 9 DATA 1-7 ACK/ NACK 8 9 STOP CONDITION REPEATED START Figure 7. I2C Data Transfer Overview ______________________________________________________________________________________ 11 DS1340 have a one-second interval where the calibration is performed. Negative calibration blanks 128 cycles of the 32,768Hz oscillator, slowing the clock down. Positive calibration inserts 256 cycles of the 32,768Hz oscillator, speeding the clock up. If a binary 1 is loaded into the calibration bits, only the first two minutes in the 64minute cycle are modified. If a binary 6 is loaded, the first 12 minutes are affected, and so on. Therefore, each calibration step either adds 512 or subtracts 256 oscillator cycles for every 125,829,120 actual 32,678Hz oscillator cycles (64 minutes). This equates to +4.068ppm or -2.034ppm of adjustment per calibration step. If the oscillator runs at exactly 32,768Hz, each of the 31 increments of the calibration bits would represent +10.7 or -5.35 seconds per month, corresponding to +5.5 or -2.75 minutes per month. For example, if using the FT function, a reading of 512.01024Hz would indicate a +20ppm oscillator frequency error, requiring a -10(00 1010) value to be loaded in the S bit and the five calibration bits. DS1340 I2C RTC with Trickle Charger determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. Figures 8 and 9 detail how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. The DS1340 can operate in the following two modes: Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. 12 After each byte is received, an acknowledge bit is transmitted. Start and STOP conditions are recognized as the beginning and end of a serial transfer. Hardware performs address recognition after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS1340 address, which is 1101000, followed by the direction bit (R/W), which is 0 for a write. After receiving and decoding the slave address byte, the DS1340 outputs an acknowledge on SDA. After the DS1340 acknowledges the slave address + write bit, the master transmits a word address to the DS1340. This sets the register pointer on the DS1340, with the DS1340 acknowledging the transfer. The master can then transmit zero or more bytes of data, with the DS1340 acknowledging each byte received. The register pointer increments after each data byte is transferred. The master generates a STOP condition to terminate the data write. Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. The DS1340 transmits serial data on SDA while the serial clock is input on SCL. Start and STOP conditions are recognized as the beginning and end of a serial transfer. Hardware performs address recognition after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS1340 address, which is 1101000, followed by the direction bit (R/W), which is 1 for a read. After receiving and decoding the slave address byte, the DS1340 outputs an acknowledge on SDA. The DS1340 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. The DS1340 must receive a not acknowledge to end a read. ______________________________________________________________________________________ I2C RTC with Trickle Charger S 1101000 0 <WORD ADDRESS (n)> A <DATA (n)> XXXXXXXX A <DATA (n + 1)> XXXXXXXX S - START MASTER TO SLAVE A - ACKNOWLEDGE (ACK) P - STOP R/W - READ/WRITE OR DIRECTION BIT ADDRESS A DS1340 <SLAVE ADDRESS> <R/W> <DATA (n + X) XXXXXXXX A ... XXXXXXXX A P A P SLAVE TO MASTER DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) Figure 8. Data Write--Slave Receiver Mode <SLAVE ADDRESS> <R/W> S 1101000 1 <DATA (n)> A <DATA (n + 1)> XXXXXXXX A XXXXXXXX S - START MASTER TO SLAVE A - ACKNOWLEDGE (ACK) P - STOP A - NOT ACKNOWLEDGE (NACK) R/W - READ/WRITE OR DIRECTION BIT ADDRESS <DATA (n + X)> <DATA (n + 2)> A XXXXXXXX A ... XXXXXXXX SLAVE TO MASTER DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK. Figure 9. Data Read--Slave Transmitter Mode <SLAVE ADDRESS> <R/W> S 1101000 <DATA (n)> XXXXXXXX 0 A XXXXXXXX <DATA (n + 1)> A <SLAVE ADDRESS> <R/W> <WORD ADDRESS (n)> XXXXXXXX A Sr 1101000 1 <DATA (n + 2)> A S - START MASTER TO SLAVE Sr - REPEATED START A - ACKNOWLEDGE (ACK) P - STOP A - NOT ACKNOWLEDGE (NACK) R/W - READ/WRITE OR DIRECTION BIT ADDRESS XXXXXXXX A <DATA (n + X)> A ... XXXXXXXX A P SLAVE TO MASTER DATA TRANSFERRED (X + 1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK. Figure 10. Data Write/Read (Write Pointer, Then Read)--Slave Receive and Transmit ______________________________________________________________________________________ 13 DS1340 I2C RTC with Trickle Charger Handling, PC Board Layout, and Assembly The DS1340C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. Exposure to reflow is limited to 2 times maximum. Ultrasonic cleaning should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All N.C. (no connect) pins must be connected to ground. Moisture-sensitive packages are shipped from the factory dry-packed.Handling instructions listed on the package label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device (MSD) classifications. Pin Configurations TOP VIEW X1 1 8 VCC 7 FT/OUT X2 2 VBACKUP 3 6 SCL GND 4 5 SDA DS1340 SCL 1 16 SDA FT/OUT 2 15 GND VCC 3 SO, SOP 14 VBACKUP DS1340C N.C. 4 13 N.C. N.C. 5 12 N.C. N.C. 6 11 N.C. N.C. 7 10 N.C. N.C. 8 9 N.C. SO (300 mils) Package Information Chip Information PROCESS: CMOS SUBSTRATE CONNECTED TO GROUND Thermal Information Theta-JA: 170C/W (0.150in SO) Theta-JC: 40C/W (0.150in SO) Theta-JA: 221C/W (SOP) Theta-JC: 39C/W (SOP) Theta-JA: 89.6C/W (0.300in SO) Theta-JC: 24.8C/W (0.300in SO) 14 For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 SO (150 mils) S8+2 21-0041 90-0096 8 SOP U8+1 21-0036 90-0092 16 SO (300 mils) W16#H2 21-0042 90-0107 ______________________________________________________________________________________ I2C RTC with Trickle Charger REVISION NUMBER REVISION DATE 0 6/03 1 2 3 4 5 7/04 12/04 11/05 3/06 8/08 DESCRIPTION PAGES CHANGED Initial release. -- Changed "2-wire" to "I2C" throughout the data sheet. All Added UL recognition info bullet to the Features section and to the VBACKUP pin description. 1, 6 Added the "I/O Capacitance (SCL, SDA)" parameter (CI/O) to the AC Electrical Characteristics table. 2 Added "SDA, SCL" and "VCC = 0V" to the "Supply Voltage, Pullup (FT/OUT)" parameter and changed the symbol from "V IH" to "VPU " in the Recommended DC Operating Conditions table; in the DC Electrical Characteristics table, changed the "Oscillator Current" parameter to "VBACKUP Current." 3 Added the integrated-crystal and lead-free packages to the Ordering Information table; added the integrated-crystal packages to the Features, Pin Configurations, Pin Description. 1, 6 In Table 1, added increased crystal ESR with increased supply minimum voltage requirement. 6 Added the DS1340C Only section. 7 Updated Figure 5 to also show the "C Version" crystal. 7 Added the Handling, PC Board Layout, and Assembly section. 12 Added the integrated-crystal package Theta-JA and Theta-JC information to the Thermal Information section. 13 Updated the Ordering Information table to correct lead-free/RoHS packages. 1 In the General Description section, indicated that the time and date function continues while powered by VBACKUP. 1 Updated the Typical Operating Circuit by removing pin numbers and adding a bypass capacitor. 1 In the Pin Description, updated the VBACKUP description to indicate that no diodes should be placed between the battery and pin and added the UL link; changed the VCC description. 6 Added the Power Control section and new Table 1. 6 In the Handling, PC Board Layout, and Assembly section, added solder reflow information for the RoHS SO package. 13 Added Package Information table. 14 Removed leaded part numbers from the Ordering Information table. 1 Removed the tRPU parameter and RST waveform from Figure 2. Replaced tRST with tREC. 5 In the Typical Operating Characteristics section, updated/changed the "FT vs. VBACKUP" graph to "OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE (FT x 64)." 5 In the Pin Description, added pullup voltage information to the SDA, SCL, and FT/OUT descriptions. 6 Updated Figure 5. 8 In the Clock and Calendar section, added text explaining the use of EOSC to halt the oscillator. 9 Replaced Figure 7 with an updated version; changed Figures 8 and 9 and added Figure 10 with more comprehensive I2C figures. 13 ______________________________________________________________________________________ 15 DS1340 Revision History DS1340 I2C RTC with Trickle Charger Revision History (continued) REVISION NUMBER 6 7 REVISION DATE 10/10 8/11 DESCRIPTION PAGES CHANGED Updated the top mark information in the Ordering Information table. 1 Updated the soldering information in the Absolute Maximum Ratings section. 2 Updated the SDA and SCL pin descriptions in the Pin Description table. 6 Increased ESR from 45,60k (max) to 80k (max) in Table 2. 7 Updated the Package Information table. 14 Raised VCC(MAX) limits for the -18 and -3 versions from 1.89V and 3.3V to 5.5V to provide wide voltage functional operation; reorganized the EC tables and notes 2, 3 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.