AM29SL160CT100WCI - Advanced Micro Devices

Publicati on# 21635 Rev: CAmendment/0

Issue Date: February 21, 2000

Refer to AMD’s Website (www.amd.com) for the latest information.

Am29SL160C

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 1.8 Volt-onl y Super Lo w Voltage Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■Secured Silicon (SecSi) Sector: 256-byte sector

—

F actory locked and identifiable:

16 bytes available f or

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data

—

Customer lockable:

Customer may program own

custom data. Once locked, data cannot be changed

■Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero

■Package options

— 48-ball FBGA

— 48-pin TSOP

■Top or bottom boot block

■Manufactured on 0.32 µm process technology

■Compatible with JEDEC standards

— Pinout and software compatible with single-power-

supply flash standard

PERFORMANCE CHARACTERISTICS

■High performance

— Access time as fast 90 ns

— Program time: 8 µs/word typical using Accelerate

■Ultra low power consump tion (typic al values)

— 1 mA active read current at 1 MHz

— 5 mA active read current at 5 MHz

— 1 µA in standby or automatic sleep mode

■Minimum 1 million erase cycles guaranteed per

sector

■20 Year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■Supports Common Flash Memory Interface (CFI)

■Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in

same bank

■Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

■Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

HARDWARE FEATURES

■Any combination of sectors can be erased

■Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

■Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to reading array data

■WP#/ACC input pin

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect status

— Acceleration (ACC) function accelerates program

timing

■Sector protection

— Hardware method of locking a sector, either in-

system or using programming equipment, to prevent

any program or erase operation within that sector

— Tempo rary Sector Unp rot ect allows cha ngi ng dat a in

protected sectors in-system

2 Am29SL160C

GENERAL DESCRIPTION

The Am29SL160C is a 16 Mbit, 1.8 V volt-only Flash

memory organized as 2,097,152 bytes or 1,048,576

words. The data appears on DQ0–DQ15. The device

is offered in 48-pin TSOP and 48-ball FBGA pack-

ages. The word-wide data (x16) appears on DQ15–

DQ 0; t he byte-wide (x8) data appears on DQ7–DQ0.

This devic e is desi gned to be progr amm ed and era sed

in-system with a single 1.8 volt VCC supply. No VPP is re-

quired for program or erase operations. The device can

also be programmed in standard EPROM programmers.

The s tandard device offers acces s times o f 90, 100,

120, or 15 0 ns, allowing micr oprocessors to operate

without wait states. To eliminate b us content ion the de-

vice has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) cont rols.

The de vice requires only a single 1. 8 v o lt po wer sup-

ply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents ser ve as input to an inter nal state-machine that

controls the erase and programming circuitry. Wr ite

cycles also internally latch addresses and data

needed for the programming and erase operations.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an inter nal algor ithm that auto-

matically times the program pulse widths and verifies

proper cell m argin. The Unlock Bypass mode facili-

tates faster program ming times by requiring only two

write cycles to program data instead of four.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedd ed Er ase

algorithm—an inter nal algorithm that automatically

preprograms t he arra y (if it is not already progr ammed)

before executing the erase operation. During erase,

the device automa tically tim es the erase p ulse widths

and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/B Y#

pin, or by reading the DQ7 (Data # Polling) and DQ6

(toggle) status bits. After a program o r erase cycle

has been completed, the device is ready to read array

data or accept another command.

The se ctor erase architecture allows memor y sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature dis ables both pr ogram and e rase

operations i n any combination of the sector s of mem-

ory. This can be achieved in-system or via

programming equipment.

The Erase Sus pend feature enables the user to put

erase on hold for any period of time to read data from,

or pro gram data to, any sector that i s not se lected for

erasure . True backg ro und erase can thus be achie ved.

The hardware RESE T# pi n term inates any operation

in pr ogress an d resets th e inte rnal state m achine to

rea ding array data. The RESET# pin may be tied to the

system reset circuitr y. A system reset would thus also

reset the device , enabling the system microprocessor to

read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly re-

duced in both modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quali ty, reliability and cost effective-

n e s s . T he dev ice elec trically erases all b its within a

sector simultaneously v ia Fow ler-Nordheim tunne ling.

The data is programmed using hot electron injection.

Am29SL160C 3

PRODUCT SELECTOR GUIDE

Note:See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

Family Part Number Am29SL160C

Speed Options 90 100 120 150

Max access time, ns (tACC) 90 100 120 150

Max CE# access time, ns (tCE) 90 100 120 150

Max OE# access time, ns (tOE)35355065

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

BYTE#

WP#/ACC

CE#

OE#

STB

DQ0

–

DQ15 (A-1)

Sector Switches

RY/BY#

RESET#

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A19

21635C-1

4 Am29SL160C

CONNECTION DIAGRAMS

A15

A18

A14

A13

A12

A11

A10

A19

WE#

RESET#

WP#/ACC

RY/BY#

A17

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

21635C-2

Standard TSOP

Am29SL160C 5

CONNECTION DIAGRAMS (Continued)

Special Handling Instructions for FBGA

Packages

Specia l handling is required for Flash M emor y prod-

ucts in FBGA pack ages.

Flash memor y devices in FBGA packages may be

damaged if exp osed to ultrasonic cleaning method s.

The package and/or data integrity may be compro-

mised if the pack age body is exposed to temperatures

above 150°C for prolonged periods of time.

A1 B1 C1 D1 E1 F1 G1 H1

A2 B2 C2 D2 E2 F2 G2 H2

A3 B3 C3 D3 E3 F3 G3 H3

A4 B4 C4 D4 E4 F4 G4 H4

A5 B5 C5 D5 E5 F5 G5 H5

A6 B6 C6 D6 E6 F6 G6 H6

DQ15/A-1 VSS

BYTE#A16A15A14A12A13

DQ13 DQ6DQ14DQ7A11A10A8A9

VCC DQ4DQ12DQ5A19NCRESET#WE#

DQ11 DQ3DQ10DQ2NCA18WP#/ACCRY/BY#

DQ9 DQ1DQ8DQ0A5A6A17A7

OE# VSS

CE#A0A1A2A4A3

21635C-3

48-Ball FBGA

(Top View, Balls Facing Down)

6 Am29SL160C

PIN CONFIGURATION

A0–A19 = 20 addresses

DQ0–DQ14 = 15 data inputs/outputs

DQ15/A-1 = DQ15 (data input/outpu t, word mode),

A-1 (LSB address input, byte mode)

CE# = Chip enable

OE# = Output enable

WE# = Write enable

WP#/AC C = H ardware write protect/acceleration

RESET# = Hardware reset pin, active low

BYTE# = Selects 8-bit or 16-bit mode

RY/BY# = Ready/Busy# output

VCC = 1.8–2.2 V single power supply

VSS = De vice ground

NC = Pin not connec ted internally

LOGIC SYMBOL

21635C-4

20 16 or 8

DQ0–DQ15

(A-1)

A0–A19

CE#

OE#

WE#

RESET#

BYTE#

RY/BY#

WP#/ACC

Am29SL160C 7

ORDERING INFORMATION

Standard Prod ucts

AMD standard products are available in s everal packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in v olume for this device. Consult the local AMD sales

office to confirm av ailability of specific valid combinations and

to check on newly released combinations.

Am29SL160C T 90 E C N STANDARD PROCESSING

N = SecSi Sector factory-locked with random ESN

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C=Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

E = 48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

WC = 48-ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 8 x 9 mm package (FBC048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T= Top sector

B = Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29SL160C

16 Megab it (2 M x 8-Bit/1 M x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages

AM29SL160CT90,

AM29SL160CB90

EC, EI

AM29SL160CT100,

AM29SL160CB100

AM29SL160CT120,

AM29SL160CB120

AM29SL160CT150,

AM29SL160CB150

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29SL160CT90,

AM29SL160CB90

WCC,

WCI

A160CT90V,

A160CB90V

C, I

AM29SL160CT100,

AM29SL160CB100 A160CT10V,

A160CB10V

AM29SL160CT120,

AM29SL160CB120 A160CT12V,

A160CB12V

AM29SL160CT150,

AM29SL160CB150 A160CT15V,

A160CB15V

8 Am29SL160C
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are i nitiated through
the internal comm and register. The command register
itself d oes not occupy any addre ssable memor y lo ca-
tion. The regi st er is composed of latches that store the
comman ds, along with  the address  and data in for ma-
tion needed to execute the command. The contents of
the regi ster ser ve as inp uts to the inter nal sta te ma-
chine. The state mach ine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs  and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29SL160C Device Bus Operatio ns 
Legend:
L = Logic Low = VIL, H = Logic H igh = VIH, VID = 10  ±
 
1.0 V, VHH =  10 ±  0.5 V, X = Don’ t Care, AIN = Add ress In , DIN  = Data  In,
DOUT = Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector prot ect a nd sect or unpr otect  functi ons may also be implemented via  prog r amming e quipment.  See t he “Sec tor/Sec tor 
Block  Protect ion and  Unprote ction” secti on.
3. If WP#/A CC  = VIL, the two  outermost boot secto rs wil l be  protec ted. I f WP#/ACC = VIH, the two outermost boot sect ors wi ll  be 
protected or  unprotected as  pre viously set  by th e system. If  WP#/A CC = VHH, all sectors, i ncluding the two outermost boot sectors, 
will be unprotected. 
Word/Byte Configuration
The BYTE# pin controls  whether the device data I/O
pins DQ15–DQ0 oper ate  in t he b y te  or  word c onfigur a-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE# .
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by C E# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function. 
Requirements for Reading Arra y Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set  for reading array data
upon device power-up, o r after a hardware rese t. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessar y in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
Operation CE# OE# WE# RESET# WP#/ACC Addresses
(Note 1) DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE# 
= VIL
Read L L H H X AIN DOUT DOUT DQ8–DQ14 = High-Z, 
DQ15 = A-1
Write 
(Program/Erase) L H L H (Note 3) AIN DIN DIN
Standby VCC ± 
0.2 V XXVCC ± 
0.2 V X X High-Z High-Z High-Z
Output Disable L H H H X X High-Z High-Z High-Z
Reset X X X L X X High-Z High-Z High-Z
Sector Pro tec t 
(Note 2) LHL V
ID XSector Address, 
A6 = L, A1 = H, 
A0 = L DIN XX
Sector Unp rot ect  
(Note 2) LHL V
ID (Note 3) Sector Address, 
A6 = H, A1 = H, 
A0 = L DIN XX
Tempo rary Sector  
Unprotect XXX V
ID (Note 3) AIN DIN DIN High-Z

Am29SL160C 9
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See “Reading  Array  Data” fo r more information. Refer
to the AC  table for timing specifications and to Figure
13 for the timing diagram. ICC1 in the  DC C haracteri s-
tics table represents th e active current  spec ification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (w hich in-
cludes programming data to the device and erasing
sectors of memory), the system must drive  WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
infor mation. 
The device features an Unlo ck Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command
sequences.
An erase oper at ion can er ase  one sect or, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
section has details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the  system write s the autosele ct command se-
quence, the device enters the  autoselect m ode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. R efer to  the Autoselect Mode and Autose-
lect Command Sequence sections for more
information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for wr ite operations.
Accelerated Program Operation
The device offers accelerated program operation
through the ACC function, which is one of two func-
tions provided by the WP#/ACC pin. This function is
primar ily intended to allow faster in-system program -
ming of the device during the system production
process.
If the system asserts VHH on the pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode and uses the higher v oltage on the pin to reduce
the time r equired for program operation s. The system
would us e a two-cycle pr ogram comman d sequence
as required by the Unlock Bypass mode. Rem oving
VHH from  the WP #/ACC pin retur ns the  device to nor-
mal operation.
Program and Erase Operation Status
During an erase or program operation, the system
may check the s tatus of the operation by reading the
status bits on DQ7–DQ0. Standard read cycle timings
and ICC read specifications apply. Refer to “Write Op-
eration Status” for more information, and to “AC
Characteristics” for timing diagrams.
Standby Mode
When the  system is no t reading or wr iting to the de-
vice, it can place the  device in  the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input. 
The device enters the CMOS standby mode when the
CE# and  RESET# pin s are both held  at VCC ± 0.2 V.
(Note that this is a m ore restricte d vo ltage range than
VIH.) I f CE# and RESET# are  held at  VIH, but not within
VCC ± 0.2 V, the de vice will be in the st andby mode, b ut
the standby current will be greater. The device re-
quires standard access time (tCE) for read access
when the device is in either of these standby  modes,
before it is ready to read data.
The device also enters the standby mode when the
RESET # pin is  driven low. R efer to  the next section,
RESET#: Hardware Reset Pin.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification. 
Automatic Sleep Mode
The automatic sleep mode minimizes Flash dev ice en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 50
ns. The automatic  sleep mode is  independent of  th e
CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
ICC4 in the DC Characteristics table represents the au-
tomatic sleep mode current specification.

10 Am29SL160C

RESET#: Hard ware Reset Pin

The RESET# p in provides a hardware method of r e-

setting the device to reading array data. When the

RESET# pin is driven low for at least a per iod of tRP

the device immediately terminates any operation in

progress, tristates all output pins, and ignores all read/

write commands for t he dur ation of t he RESET# pulse .

The device also resets the internal state machine to

reading array data. The operation that was interrupted

shou ld be rei nitiated on ce the device is ready to ac-

cept another command sequence, to ensure data

integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS ± 0.2 V, the de vice

dra ws CMOS stan db y c urrent (ICC4). If RESET# is held

at VIL but n ot within VSS ± 0.2 V, the standby current

will be greater.

The RESET# pin may b e tie d to th e system reset cir-

cuitry. A system reset would thus also rese t the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pi n rema ins a “0” (busy) until the

internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The sys-

tem c an thus monitor RY /BY# to deter mine w hether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of tRE ADY (not during Embedded Algo-

rithms). The system can read data tRH after the

RESET# pin returns to VIH.

Refer to the “AC Characteristics” for RESET# parame-

ters and to Figure 14 for the timing diagram .

Output Disable Mode

When the OE# input is at VIH, output from the de v ic e is

disabled. The output pins are placed in the high im-

pedance state.

Am29SL160C 11

Table 2. Am29S L160CT Top Boot Sector Architecture

Note: Address range is A19:A-1 in b yte mode and A19:A0 in word mode. See “W ord/Byte Configurati on” section f or more inf ormation.

Sector

Sector Addre ss Sector Siz e

(Kbytes/Kwords)

Address Range (in Hexadecimal

A19 A18 A17 A16 A15 A14 A13 A12 Byte Mode (x8) Word Mode (x16)

SA000000XXX 64/32 000000h–00FFFFh 00000h–07FFFh

SA100001XXX 64/32 010000h–01FFFFh08000h–0FFFFh

SA200010XXX 64/32 020000h–02FFFFh10000h–17FFFh

SA300011XXX 64/32 030000h–03FFFFh18000h–1FFFFh

SA400100XXX 64/32 040000h–04FFFFh20000h–27FFFh

SA500101XXX 64/32 050000h–05FFFFh28000h–2FFFFh

SA600110XXX 64/32 060000h–06FFFFh30000h–37FFFh

SA700111XXX 64/32 070000h–07FFFFh38000h–3FFFFh

SA801000XXX 64/32 080000h–08FFFFh40000h–47FFFh

SA901001XXX 64/32 090000h–09FFFFh48000h–4FFFFh

SA1001010XXX 64/32 0A0000h–0AFFFFh50000h–57FFFh

SA1101011XXX 64/32 0B0000h–0BFFFFh58000h–5FFFFh

SA1201100XXX 64/32 0C0000h–0CFFFFh60000h–67FFFh

SA1301101XXX 64/32 0D0000h–0DFFFFh68000h–6FFFFh

SA1401110XXX 64/32 0E0000h–0EFFFFh70000h–77FFFh

SA1501111XXX 64/32 0F0000h–0FFFFFh78000h–7FFFFh

SA1610000XXX 64/32 100000h–10FFFFh80000h–87FFFh

SA1710001XXX 64/32 110000h–11FFFFh88000h–8FFFFh

SA1810010XXX 64/32 120000h–12FFFFh90000h–97FFFh

SA1910011XXX 64/32 130000h–13FFFFh98000h–9FFFFh

SA2010100XXX 64/32 140000h–14FFFFhA0000h–A7FFFh

SA2110101XXX 64/32 150000h–15FFFFhA8000h–AFFFFh

SA2210110XXX 64/32 160000h–16FFFFhB0000h–B7FFFh

SA2310111XXX 64/32 170000h–17FFFFhB8000h–BFFFFh

SA2411000XXX 64/32 180000h–18FFFFhC0000h–C7FFFh

SA2511001XXX 64/32 190000h–19FFFFhC8000h–CFFFFh

SA2611010XXX 64/32 1A0000h–1AFFFFhD0000h–D7FFFh

SA2711011XXX 64/32 1B0000h–1BFFFFhD8000h–DFFFFh

SA2811100XXX 64/32 1C0000h–1CFFFFhE0000h–E7FFFh

SA2911101XXX 64/32 1D0000h–1DFFFFhE8000h–EFFFFh

SA3011110XXX 64/32 1E0000h–1EFFFFhF0000h–F7FFFh

SA3111111000 8/4 1F0000h–1F1FFFhF8000h–F8FFFh

SA3211111001 8/4 1F2000h–1F3FFFhF9000h–F9FFFh

SA3311111010 8/4 1F4000h–1F5FFFhFA000h–FAFFFh

SA3411111011 8/4 1F6000h–1F7FFFhFB000h–FBFFFh

SA3511111100 8/4 1F8000h–1F9FFFhFC0004–FCFFFh

SA3611111101 8/4 1FA000h–1FBFFFhFD000h–FDFFFh

SA3711111110 8/4 1FC000h–1DFFFFhFE000h–FEFFFh

SA3811111111 8/4 1FE000h–1FFFFFhFF000h–FFFFFh

12 Am29SL160C

Table 3. Am29S L160CB Bottom Boot Sector Architecture

Note: Address range is A19:A-1 in b yte mode and A19:A0 in word mode. See “W ord/Byte Configurati on” section f or more inf ormation.

Sector

Sector Address Sector Size

(Kbytes/Kwords)

Address Range (in hexadecimal)

A19 A18 A17 A16 A15 A14 A13 A12 Byte Mode (x8) Word Mode (x16)

SA000000000 8/4 000000h–001FFFh 00000h–00FFFh

SA100000001 8/4 002000h–003FFFh01000h–01FFFh

SA200000010 8/4 004000h–005FFFh02000h–02FFFh

SA300000011 8/4 006000h–07FFFFh03000h–03FFFh

SA400000100 8/4 008000h–009FFFh04000h–04FFFh

SA500000101 8/4 00A000h–00BFFFh05000h–05FFFh

SA600000110 8/4 00C000h–00DFFFh06000h–06FFFh

SA700000111 8/4 00E000h–00FFFFh07000h–07FFFh

SA800001XXX 64/32 010000h–01FFFFh08000h–0FFFFh

SA900010XXX 64/32 020000h–02FFFFh10000h–17FFFh

SA1000011XXX 64/32 030000h–03FFFFh18000h–1FFFFh

SA1100100XXX 64/32 040000h–04FFFFh20000h–27FFFh

SA1200101XXX 64/32 050000h–05FFFFh28000h–2FFFFh

SA1300110XXX 64/32 060000h–06FFFFh30000h–37FFFh

SA1400111XXX 64/32 070000h–07FFFFh38000h–3FFFFh

SA1501000XXX 64/32 080000h–08FFFFh40000h–47FFFh

SA1601001XXX 64/32 090000h–09FFFFh48000h–4FFFFh

SA1701010XXX 64/32 0A0000h–0AFFFFh50000h–57FFFh

SA1801011XXX 64/32 0B0000h–0BFFFFh58000h–5FFFFh

SA1901100XXX 64/32 0C0000h–0CFFFFh60000h–67FFFh

SA2001101XXX 64/32 0D0000h–0DFFFFh68000h–6FFFFh

SA2101110XXX 64/32 0E0000h–0EFFFFh70000h–77FFFh

SA2201111XXX 64/32 0F0000h–0FFFFFh78000h–7FFFFh

SA2310000XXX 64/32 100000h–10FFFFh80000h–87FFFh

SA2410001XXX 64/32 110000h–11FFFFh88000h–8FFFFh

SA2510010XXX 64/32 120000h–12FFFFh90000h–97FFFh

SA2610011XXX 64/32 130000h–13FFFFh98000h–9FFFFh

SA2710100XXX 64/32 140000h–14FFFFhA0000h–A7FFFh

SA2810101XXX 64/32 150000h–15FFFFhA8000h–AFFFFh

SA2910110XXX 64/32 160000h–16FFFFhB0000h–B7FFFh

SA3010111XXX 64/32 170000h–17FFFFhB8000h–BFFFFh

SA3111000XXX 64/32 180000h–18FFFFhC0000h–C7FFFh

SA3211001XXX 64/32 190000h–19FFFFhC8000h–CFFFFh

SA3311010XXX 64/32 1A0000h–1AFFFFhD0000h–D7FFFh

SA3411011XXX 64/32 1B0000h–1BFFFFhD8000h–DFFFFh

SA3511100XXX 64/32 1C0000h–1CFFFFhE0000h–E7FFFh

SA3611101XXX 64/32 1D0000h–1DFFFFhE8000h–EFFFFh

SA3711110XXX 64/32 1E0000h–1EFFFFhF0000h–F7FFFh

SA3811111XXX 64/32 1F0000h–1FFFFFhF8000h–FFFFFh

Am29SL160C 13

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice iden tification, a nd sector protec tion verificatio n,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be

programmed with i ts correspondin g programming al-

gorithm. However, the autoselect codes can also be

accessed in-system through the command register.

When using programming equipmen t, the autoselect

mode requires VID on address pin A9. Address pins

A6, A1, and A 0 must be as shown in Table 4. In addi-

tion, when verifying sector protection, the sector

address must appear on the appropriate highest order

address bits (see Tables 2 and 3). Table 4 shows the

remai ning addre ss bits that a re don’t ca re. When all

necessar y bits have been set as required , the pro-

gramming equipment may then read the

corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 12. This method

does not require VID. See “Command Definitions” for

details on using the autoselect mode.

Table 4. Am29SL160C Autoselect Codes (High Voltage Method)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Note: Outputs for data bits DQ8–DQ15 are for BYTE#=VIH. DQ8–DQ15 are don’t care when BYTE#=VIL.

Description Mode CE# OE# WE#

A19

A12

A11

A10 A9

A7 A6

A2 A1 A0

DQ8

DQ15

DQ7

DQ0

Manufacturer ID: AMD L L H X X VID XLXLL X 01h

Device ID:

Am29SL160CT

(Top Boot Block)

Word L L H XXV

ID XLXLH22h E4

Byte L L H X E4

Device ID:

Am29SL160CB

(Bottom Boot Block)

Word L L H XXV

ID XLXLH22h E7

Byte L L H X E7

Sector Protection V erification L L H SA X VID XLXHL X01h

(protected)

X00h

(unprotected)

SecSi Sector Ind ica tor bit

(DQ7) LLHSAXV

ID XLXHH X 81h

(factory

locked)

14 Am29SL160C

Sector/Sector Block Protection and

Unprotection

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sect ors that are

protected or unprotected at the same time (see Tables

5 and 6).

T abl e 5. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection

Table 6. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector / Sector

Block A19–A 12 Sect or / S ector Block Size

SA0 00000XXX 64 Kbytes

SA1-SA3 00001XXX,

00010XXX,

00011XXX 192 (3x6 4) Kbyte s

SA4-SA7 001XXXXX 256 (4x64) Kby te s

SA8-SA11 010XXXXX 256 (4x64) Kbytes

SA12-SA15 011XXXXX 256 (4x64) Kby tes

SA16-SA19 100XXXXX 256 (4x64) Kby tes

SA20-SA23 101XXXXX 256 (4x64) Kby tes

SA24-SA27 110XXXXX 256 (4x64) Kby tes

SA28-SA30 11100XXX,

11101XXX,

11110XXX 192 (3x6 4) Kbyte s

SA31 11111000 8 Kbytes

SA32 11111001 8 Kbytes

SA33 11111010 8 Kbytes

SA34 11111011 8 Kbytes

SA35 11111100 8 Kbytes

SA36 11111101 8 Kbytes

SA37 11111110 8 Kbytes

SA38 11111111 8 Kbytes

Sector / Sector

Block A19– A 12 Sect or / S ector Block Si ze

SA38 11111XXX 64 Kbytes

Am29SL160C 15

The primary method requires VID on the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 1 shows the algo-

rithms and Figure 24 shows the timing diagram. This

method us es standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sec tors must

first be protected prior to the first sector unprotect

wr ite cycle.

The alternate method intended only for progra mming

equipment re quires VID on address pin A9 and OE#.

This method is c ompatible with programmer routines

written for earlier 3.0 volt-only AMD flash devices.

Publication number 21622 contains fur ther details.

Contact an AMD representative to request the docu-

ment containing further details.

The device is shipped with all sectors unprotected.

AMD o ffer s the option of programming a nd prot ecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possible to determine whether a sector is pro-

tected or unprotected. See “Autoselect Mode” for

details.

Write Protect (WP#)

The write protect f unction pro v ides a hardw are method

of protecting cer tain boot sectors without using VID.

This fun ction i s one of two p rovided by the W P#/AC C

pin.

If the s yst e m asserts VIL on the WP#/ACC pin, the de-

vice dis ables program and erase functions in the two

“outermost” 8 Kbyte boot sectors independently of

whether those sectors were protected or unprotected

using the method described in “Sector Protection/Un-

protection .” The two outer most 8 Kbyte boot sectors

are the two s ectors containing the lowest addresses in

a bottom-boot-configured device, or the two sectors

containing the highest addresses in a top-boot-config-

ured device.

If the system asser ts VIH on the WP#/ACC pin, the de-

vice reverts to wheth er the t w o outermost 8 Kby t e boot

sectors were last set to be prote cted or unprotected.

That is, s ector protection or unprotection for these two

sectors depends on whether they were last protected

or unprotec ted using the metho d descri bed in “Secto r

Protection/Unprotection.”

Note that if the system asser ts VHH on the WP#/ACC

pin, all s ectors, including th e two outerm ost sectors,

will be unprotected. VHH is intended for accelerated in-

system programming of the device during system pro-

duction. It is advisable, therefore, not to assert VHH on

this pin after the sy stem has been placed in the field

for use. If faster programming is desired, the system

may use the unlock bypass program command

sequence.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-s ystem. The

Sector Unprotect mode is activated by s etting the R E-

SET# pin to VID. Du ring this m ode, for mer ly pro tected

sectors can be prog r ammed or er ased b y selec ting the

sector addresses. Once VID is removed from the RE-

SET# pin, all the previously protected sectors are

protected again. Figure 2 shows the algorithm, and

Figure 22 shows the tim ing diagrams, for this feature.

16 Am29SL160C

Figure 1. In-System Sector Protect/Unprotect Algori thms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode No

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 µs

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

21635C-5

Am29SL160C 17

Figure 2. Temporary Sector Unprotect Operation

Secured Silicon (SecSi) Sector Flash

Memory Region

The Secured Silicon (SecSi) Sector is a flash m emor y

region that enables permanent part identification

through an Electronic Serial Number (ESN). The

SecSi Sector in this device is 256 by tes in length. The

devic e has a SecSi Sector indicator bit that allows the

system to determine whether or not the SecSi Sector

was factor y locke d. This indica tor bit is per manently

set at the fact or y and cannot be changed, which pre-

vent s a factory-locked part from being cloned.

AMD offers this device only with the SecSi Sector fac-

tory serialized and locked. The first sixteen bytes of

the SecSi Sector contain a random ESN. To utilize the

remainder SecSi Sector space, customers must pro-

vide their code to AMD throug h AMD’s E xpress Fl ash

service. The factory will program and permanently

protect the SecSi Sector (in addition to programming

and protecting the remainder of the device as

required).

The system can read the SecSi Sector by writing the

Enter SecSi Sector command sequence (see “Enter

SecSi Sector/Exit SecSi Sector Command Sequence”

section). Table 7 shows the layout for the SecSi Sec-

tor. In byte mode, A-1 is not used in the addressing

scheme. All other address bits not implied in the table

are don’t cares.

Table 7. SecSi Sector Addresses

The device continue s to read from the SecSi Sector

until the system issues the Exit SecSi Sector com-

mand sequence, or until power is removed from the

device. On power-up, or following a hardware reset,

the device rever ts to sending comm ands to the bo ot

sectors.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadver tent writes (refer to Table 12 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which m ight otherwise be caused by

spurious system level signals during VCC power-up

and power-down transitions, or from system nois e.

Low V CC Write Inhibit

When VCC is les s than VLKO, the device does not ac-

cept any write cycles. This protects data dur ing VCC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets. Subsequent wr ites are ignore d

until V CC is greater than VLKO. T he system must pro-

vide the prop er signals to the control pins to prevent

unintentional wr ites when VCC is great er than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of les s than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical In hibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,

CE# and WE # mus t be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH duri ng power up,

the device does not accept commands on the rising

edge of WE #. The inter nal state mac hine is automati-

cally reset to reading array data on power-up.

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect Completed

(Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sectors unprotected. (If WP#/ACC = VIL,

the outermost sectors will remain protected)

2. All previously protected sectors are protected once

again.

21635C-6

Description

Address Range

W ord Mode (x16) Byte Mode (x8)

16-byte random ESN 00–07h 000–00Fh

User-defin ed cod e or

factory erased (all 1s) 0C–7Fh 018–0FFh

18 Am29SL160C

COMMON FLASH MEMORY INTERFACE

(CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used fo r entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-ter m compatibility.

This device enters the CFI Query mode w hen the sys-

tem writes the CFI Query command, 98h, to address

55h in word mode (or address AAh in byte mode), any

time the devic e is ready to read array data. The sys-

tem can read CFI information at the addresses given

in Tables 8–11. To ter minate reading CFI data, the

system must write the reset command.

The system can also w rite the CFI query command

when the device is in the autoselect mode. T he devic e

enters the CFI quer y mode, and the system can read

CFI data at the addresses given in Tables 8–11. The

system must write the reset command to retur n the

device to the autoselect mode.

Fo r further information, please refer to the CFI Specifi-

cation and CFI Pub licatio n 100, a vailabl e via the World

Wide Web at http://www.amd.com/products/nvd/over-

view/cfi.html. Alternatively, contact an AMD

representative for copies of these documents.

Table 8. CFI Query Identificatio n String

Addresses

(Word Mode) Addresses

(Byte Mode) Data Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h Query Unique ASCII string “QRY”

13h

14h 26h

28h 0002h

0000h Primary OEM Command Set

15h

16h 2Ah

2Ch 0040h

0000h Address for Primary Extended Table

17h

18h 2Eh

30h 0000h

0000h Alternate OEM Command Set (00h = none exists)

19h

1Ah 32h

34h 0000h

0000h Address for Alternate OEM Extended Table (00h = none exists)

Am29SL160C 19

Table 9. System Interface Stri ng

Table 10. Device Geo metry Definition

Addresses

(Word Mode) Addresses

(Byte Mode) Data Description

1Bh 36h 0018h VCC Min . (wr ite /erase )

D7–D4: volt, D3–D0: 100 millivolt

1Ch 38h 0022h VCC Ma x. (wr it e/eras e)

D7–D4: volt, D3–D0: 100 millivolt

1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)

1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)

1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs

20h 40h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported)

21h 42h 000Ah Typical timeout per individual block erase 2N ms

22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)

23h 46h 0005h Max. timeout for byte/word write 2N times typical

24h 48h 0000h Max. timeout for buffer write 2N times typical

25h 4Ah 0004h Max. timeout per individual block erase 2N times typical

26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

Addresses

(Word Mode) Addresses

(Byte Mode) Data Description

27h 4Eh 0015h Device Size = 2N byte

28h

29h 50h

52h 0002h

0000h Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh 54h

56h 0000h

0000h Max. number of bytes in multi-byte write = 2N

(00h = not supported)

2Ch 58h 0002h Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

001Eh

0000h

0001h

Erase Block Region 2 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

Erase Block Region 3 Information

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Erase Block Region 4 Information

20 Am29SL160C
Table 11. Primary Vendor-Specific Extended Query
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the  command register in itiates device
operations. Table 12 defines the valid register com-
mand sequences. Writing incorrect address and
data values or writing them in the improper se-
quence resets the device to reading arra y data. 
All addresses are latched on the falling edge of WE#
or CE#, whiche ver happens later. All data is latc hed on
the rising edge of WE# or CE#, whichever happens
first. Refer to the a ppropria te timing diagram s in the
“A C Ch aract eristic s” section.
Reading Array Data
The device is automatically set to reading array data
after dev ice power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Eras e Suspend m ode. The sys-
tem can read array data using the standard read
timings, except that if it reads at an address within
eras e-suspended sectors, the device outputs status
data. After completing a program ming operation in the
Erase  Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspe nd/Erase Res ume Comm ands” for more infor-
mation on this mode.
The system 
must
 issue the reset command to re-en-
able the device for reading array data if DQ5 goes
high, or w hile in the au toselect mod e. See the “Rese t
Command” section, next.
See also “Requirements for Reading Array Data” in
the “Device Bus Operations” section for more infor ma-
tion. The  table provides the read parameters, and
Figure 13 shows the tim ing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command. 
The reset comma nd may be w ritten between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset comma nd may be w ritten between the se-
quence cycles in a program command sequence
before programming  begins. This res ets the device to
Addresses
(Word Mode) Addresses
(Byte Mode) Data Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h Query-unique ASCII string “PRI”
43h 86h 0031h Major version number, ASCII
44h 88h 0030h Minor version number, ASCII
45h 8Ah 0000h Address Sensitive Unlock
0 = Required, 1 = Not Required
46h 8Ch 0002h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 8Eh 0001h Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 90h 0001h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 92h 0004h Sector Protect/Unprotect scheme 
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah 94h 0000h Simultaneous Operation
00 = Not Supported, 01 = Supported
4Bh 96h 0000h Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 98h 0000h Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

Am29SL160C 21
readin g array data (also applies to programm ing in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The rese t comman d may be wr itten between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must
 be written to return to reading array data (also
applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operat ion,
writing the reset command retur ns the dev ice to read-
ing array data (also applies during Erase Suspend).
See “AC Characteristics” for parameters, and to Fi gure
14 for the timing diagram.
Autoselect Command Sequence
The autoselect command sequence  allows the host
system to access the manufact urer and device codes,
and deter mine whether or not a sector is protected.
Table 12 shows  the addr ess and d ata requiremen ts.
This method is an alternative to that shown in Table 4,
which is intended for PROM programmers and re-
quires VID on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and  the syste m may  read at any address  any
number of times, without initiating another command
sequence. A  read c ycle  at  addres s XX00h retrieves
the manufacturer code. A read cycle at address 01h in
word mode  (or 02h in byte mode) re turns the device
code. A read cycle containing  a sector address (SA)
and the address 02h in word mode (or 04h in byte
mode) retur ns 01h if that sector is pr otected, or 00h if
it is unprotected. Refer to Tables 2 and 3 for valid se c-
tor addresses.
The system must write the reset command to exit th e
autoselect mode and return to reading array data.
Enter SecSi Sector/Exit SecSi Sector 
Command Sequence
The SecSi Sector region provides a secured data area
containing a  random, sixteen-byte electro nic serial
number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi
Sector command sequence. The device continues to
access the SecSi Sector region until the system is-
sues the four-cycle Exit SecSi command sequence.
The Exit SecSi command sequence returns the device
to nor mal o peration. Table 12 sh ows the address  and
data requirements for both command sequences. See
also “Secured Silicon  (SecSi) Sector Flash Memory
Region” for further information. 
Word/Byte Program Command Sequence
The system may program the  device by word or byte,
depending on the state of the BYTE# pin.  Program-
ming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up com-
mand. The progr am address  and data are written next,
which in turn initiate the Embedded Program algo-
rithm. The system is 
not
 required to provide further
controls or timings. The device automatically gener-
ates the program pulses and ver ifies the progra mmed
cell margin. Table 12 shows the address and data re-
quirements for the byte program comm and sequence.
When  the E mbedded  Program a lgor ithm is  comple te,
the device then returns to reading  array data and ad-
dresses are no longer latched. The system can
determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. See “Write Operation
Status” for information on these status bit s. 
Any co mmands wr itten to th e device duri ng the Em-
bedded Program Algorithm are ignored.  Note  that  a
hardwa re  rese t immediately  ter minates the program-
ming operation. The Byte Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1 ”. Attempting to do so may
halt the operation and set DQ5 to “1”, or cause the
Data# Polling algorithm to indicate  th e operation was
successful. However, a succeeding read will show that
the data is still “0”. Only erase operations can co nver t
a “0” to a “1”.
Unlock Bypass C ommand Sequen ce
The unlock bypass feature allows the system to pro-
gra m b yt es or w ords  to t he  device faster than using  the
standard  program command  se quence. The unlock
bypass com mand sequ ence is ini tiated by first wr iting
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequenc e
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram comm and, A0h; the se cond cycle co ntains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two  unlock cy cles required in t he stan-
dard program command sequence, resulting  in faster
total programming time. Table 12 shows the require-
ments for the command sequence.
During the unlock bypass m ode, only the Unlock By-
pass Program a nd Unlock Bypass Reset comma nds
are valid. To exit the unlo ck bypass mode, the system
must issue the two-cycle unlock bypass reset com-

22 Am29SL160C

mand sequence. The first cycle must contain the data

90h; the second cycle the data 00h. Addresses are

don’t cares. The device then returns to reading array

data.

The device offers accelerated program operations

throug h the WP #/AC C pin. T his function is intend ed

only to speed in-system programming of the device

during system production. When the system asse rts

VHH on the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher vo ltage on the

WP#/ACC p in to accelera te the operati on. Note that

the WP#/ACC pin must not be at VHH for any operation

other than acc elerated programming, or device dam-

age may result. In addit ion, t he WP#/ACC pin must not

be left floating or unconnec ted; inconsistent behavior

of the de vice may result.

Figure 3 illustrates the algorithm for the program oper-

ation. See the Erase/Program Operations table in “AC

Characteristics” for parameters, and to Figure 17 for

timing diagrams.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

21635C-6

Note: See Table 12 for program command sequence.

Figure 3. Pr ogram Operation

Am29SL160C 23
Chip Erase Command Sequence
Chip erase is a six  b us cy cle oper ation.  The chip er ase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles ar e then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does 
not
 require the system to
preprogram prior  to erase. The Embedded Erase algo-
rithm automatically preprogr ams a nd v e rifies the entire
memory  for an all zero data pattern prior to electrical
erase. The system is not required to p rovide any con-
trols or timings during these operations. Table 12
shows the address  and data requirements for  the chip
erase command sequence.
Any comman ds wri tten to the chi p during th e Embed-
ded Erase algorithm are ignored. Note that a
hardw are reset dur ing the chip erase operation im-
medi ately ter min ates the op eration.  The Chip  Erase
command sequence should be reinitiated once t he de-
vice has returned to reading arra y dat a, to  ensure data
integrity.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write  Operation S tatus”  fo r information  on these  sta-
tus bits. When the Embedded Erase algorithm is
complete, the device returns to reading array  data and
addresses are no longer latched. 
Figure 4 illustrates the algor ithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 18 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence  is  in itiated by wr iting two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 12 shows the address and
data requirements for the sector erase command
sequence.
The device does 
not
 require the system to preprog ram
the memor y prior to erase. The Embedded Erase al-
gorithm automatically programs and verifies the sector
for an all zero data pattern prior to electrical erase.
The system is not required to provide any  controls or
timings during these operations. 
After the command sequence is written, a sector er ase
time-out of 50 µs begins. Dur ing the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
ma y be done in any sequence , and the nu mber of sec-
tors may b e from one sector to all sectors. The time
between these addition al cycles must be less than 50
µs, otherwise the last address and command might
not be accepted, and erasure may begin. It is  recom-
mended that processor interrupts be disabled during
this time to  ensure all comm ands are accepted. Th e
interrupts can be re-enabled after the last Sector
Erase command is  written. If the time between addi-
tional sector erase  commands can be assumed to be
less than 50 µs, the system need not monitor DQ3.
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the de -
vice to rea ding array data. The system mu st rewrite
the command sequence and any additional sector ad-
dresses and commands.
The sy stem can mon itor DQ3 to dete rmine  if the sec-
tor erase tim er has timed out. (See the “DQ3: Sector
Erase T imer” section.) Th e time-ou t begins  from the
rising edge of the final WE# pulse in the command
sequence.
Once the sector  erase operation has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored. Note that a hardware reset
during the sector erase operation immediately term i-
nates the operation. The Sector Erase command
sequence should be reinitiated once the device has re-
turned to reading array data, to ensure data integrity.
When the Embedded Eras e algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. (Ref er t o “ Write Opera tion  Sta tus” for
information on these status bits.)
Figure 4 illustrates the algor ithm for the erase opera-
tion. Re fe r to the Eras e/Program Operatio ns tables in
the “AC Characteristics” sec tion for parameters, and to
Figure 18 for timing diagrams.
Erase Suspend/Erase Resume 
Commands
The Erase  Suspend co mmand allo ws the s yste m to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sec tor
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip e rase operation or Emb edded Program alg o-
rithm. Writing the Erase Suspe nd command during the
Sector Erase time-out immediately terminates the
time-out period an d sus pends t he  er ase oper at ion.  Ad-
dresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maxi-
mum of 20 µs to suspend the erase operation.
However, when the Erase Suspend command is writ-
ten during the sector erase time-out, the device

24 Am29SL160C

immedia tely terminates the time-out period and sus -

pends the erase operation.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected f or eras ure. (The de vice “erase

suspends” all sectors selected for erasure.) Nor mal

read and write timings and command definitions apply.

Readi ng at any addre ss withi n erase-susp ended sec -

tors produces status data on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determ ine

if a sector i s actively erasing or is erase-suspended.

See “Wr ite Operation Status” for infor mation on these

status bits.

After an erase-suspended program operation is com-

plete, the system can once again read array data

within non-suspended sectors. The system can deter-

mine the status of the program operation using the

DQ7 or DQ6 status bits, ju st as in the standard pro-

gr am operati on. See “Writ e Operation Stat us” f or more

information.

The system may a lso write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the mem ory array. When the

device exits the autoselec t mode, the device reverts to

the Erase Suspend mode, and is read y for anothe r

valid operation. See “Autoselect Command Seq uence”

for more information.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase sus-

pend mode and continue the sector erase operation.

Fur ther writes of the Resume command are ignored.

Another Er ase Suspend command can be written after

the device has resumed erasing.

Notes:

1. See Table 12 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 4. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFH?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

21635C-7

Am29SL160C 25
Table 12. Am29SL160C Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read. 
RD = D ata read  f rom location RA d uring read  operati on.
PA = Address of the memory location to be programmed. Addresses 
latch on the falling edge of the WE# or CE# pulse, whichever happens 
later.
PD = Data to be programmed at location PA. Data latches on the rising 
edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or 
erased. Address bits A19–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect 
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t cares in by t e mode.
5. Unless otherwise noted, address bits A19–A11 are don’t cares.
6. No unlock or command cycles required when in read mode.
7. The Reset command is required to return to the read mode (or to 
the erase-suspend-read mode if previously in Erase Suspend) 
when in the autoselect mode, or if DQ5 goes high (while providing 
status information).
8. The fourth cycle of the autoselect command sequence is a read 
cycle. 
9. The data is 00h  for an unprotected sector and 01h for a protected 
sector. Data bits DQ15–DQ8 are don’t care. See the Autoselect 
Command Sequence section for more information.
10. The Unlock Bypas s command is required prior to the Unlock 
Bypass Program com ma nd.
11. The Unlock Bypass Reset command is required to return to the 
read mode when in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or 
enter the autoselect mode, when in the Erase Suspend mode. 
The Erase Suspend command is valid only during a sector erase 
operation.
13. The Erase Resume command is valid only during the Erase 
Suspend mode.
14. Command is valid when device is ready to read array data or 
when dev ice is in autoselect mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2–5)
First Second Third  Fourth  Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Autos elec t (Note 8)
Manufac turer ID Word 4555 AA 2AA 55 555 90 X00 01
Byte AAA 555 AAA
De vice ID
(Top Boot/Bottom 
Boot)
Word 4555 AA 2AA 55 555 90 X01 22E4/
22E7
Byte AAA 555 AAA X02 E4/E7
SecSi Sector Factor y  
Protect Word 4555 AA 2AA 55 555 90 X03
Byte AAA 555 AAA X06
Sector Protect Ver ify 
(Note 9) Word 4555 AA 2AA 55 555 90 (SA)X02
Byte AAA 555 AAA (SA)X04
Enter SecSi Sector Region Word 3555 AA 2AA 55 555 88
Byte AAA 555 AAA
Exit SecSi Sector Region Word 4555 AA 2AA 55 555 90 XXX 00
Byte AAA 555 AAA
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Unlock Bypass Word 3555 AA 2AA 55 555 20
Byte AAA 555 AAA
Unlock Bypass Program (Note 10) 2XXX A0 PA PD
Unlock Bypass Reset (Note 11) 2BA 90 XXX 00
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Suspend (Note 12) 1 BA B0
Erase Resume (Note 13) 1 BA 30
CFI Quer y (Note 14) Word 155 98
Byte AA

26 Am29SL160C

WRITE OPERATION STATUS

The devic e provides several bits to determine the sta-

tus of a program or eras e operation: DQ2, DQ3, DQ5,

DQ6, DQ7, and RY/BY#. Table 13 and the following

subsectio ns descri be the functions o f these bits. DQ7

and DQ6 each offer a method for determining whether

a program or erase operation is complete or in

progress. The device also provides a hardware-based

output signal, RY/BY#, to determi ne whether an em-

bedded program or erase operation is in progress or

has been completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host sys-

tem whether an Embedded Algorithm is in progress or

completed, or whether t he device is in Eras e Suspend.

Data# Polling is valid after the rising edge of the final

WE# pulse in the program or erase command

sequence.

During the Embedded Program algorithm, the dev ic e

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programm ing dur ing Erase Suspend. W hen the Em -

bedded Program algorithm is complete, the device

outputs the datum pro grammed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a progr am address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading

array data.

Dur ing th e Embe dded Erase algor ithm , Data# Pollin g

produc es a “0” on DQ 7. When the Embed ded Erase

algorithm is complete , or if the de v ice enters the Erase

Suspend mode, Data# Po lling produces a “1” on DQ7.

This is analogous to the complement/true datum out-

put descr ibed for the Embed ded Program algor ithm:

the erase fu nction changes all the bits in a sector to

“1”; prior to this, the device outputs the “complement,”

or “0.” The system must provide an address within any

of the sectors selected for erasure to read valid st atus

information on DQ7.

After an erase command sequ ence is wr itten, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active f or appro ximately 100 µs, then the

device retur ns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

When the system dete cts DQ7 has changed from th e

complement to true data, it can read valid data at

DQ7–DQ0 on the

following

read cycles. This is be-

cause DQ7 may change asynchronously with DQ0–

DQ6 while Outp ut Enable (OE#) is asser ted low. Fig-

ure 19, Data# Polling Timings (During Embedded

Algorithms), in the “AC Characteristics” section illus-

trates this.

Table 1 3 s hows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within

any sector selected for erasure. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

21635C-8

Figure 5. Data# P olli ng Algorithm

Am29SL160C 27
RY/BY#: Ready/Busy#
R Y /BY# is a dedicated, open-dr ain output  pin that indi-
cates whether an Embedded  Algorithm is in progress
or complete. The RY/BY# status is v ali d aft er the rising
edge of the final WE# pulse in the command se-
quence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied  together in parallel
with a pull-up resistor to VCC.
If the output is low (Busy),  the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the  device is  ready to read array data (includ-
ing during the Erase Suspend mode), or is in the
standb y mode.
Tab le 13 shows the output s f or RY/BY#. Figures 14, 17
and 18 shows RY/BY# for reset, program, and erase
operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indic ates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend m ode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising  edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cyc les to any address ca use
DQ6 to toggle (The system may use either OE# or
CE# to control the read cycles). When the operation is
complete, DQ6 stops toggling.
After  an erase command sequ ence is wr itten, if all
sectors s elected for erasing are pro tected, DQ6 tog-
gles fo r approximately 100 µs, then returns to readin g
arra y  data . If not  all selected secto rs are prot ected,  the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected. 
The syst em can use D Q6 and  DQ2 together  to deter-
mine whether a sector is  actively erasing or is erase-
suspended. When the device is actively erasing (that
is, th e Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters  the Erase Suspen d
mode, DQ6 stops toggling. H owever, the system must
also use  DQ2 to d eterm ine whi ch sectors  are erasing
or erase-sus pended. Alternatively, the s ystem can use
DQ7 (see the s ubsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggle s for approxima tely 1 µs after the pr ogram
command sequence is written, then retur ns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded  Pro-
gram algorithm is complete.
Table 13 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 20 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 21 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is , the  Embedded Er ase algo rithm is in progr ess),
or whether that s ector is erase-s uspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence. The device toggles DQ2 with
each OE# or CE# read cycle. 
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. But DQ2 cannot dist inguish whether the s ector is
actively erasing or is erase-suspended. DQ6, by  com-
parison, indicates whether the device is actively
erasing,  or is in Erase Suspend, but cannot distinguish
which sectors are selecte d for erasure. Thus, both sta-
tus bits a re requir ed for sector and m ode inform ation.
Refer to Table 13 to compare outputs for DQ2 and
DQ6. 
Figure 6 shows the toggle bit algor ithm in flowchar t
for m, and the section “DQ2: Toggle Bit II” explains the
algor ithm. Se e also th e DQ6: Togg le Bit I su bsectio n.
Figure 2 0 shows the toggle bit timi ng diagram. Figure
21 shows the differences between DQ2 and DQ6 in
graphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Ty pically,
the system  would note an d store the value of the tog-
gle bit after the first read. After the sec ond read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cy cle.
However, if after the initial two read cycles, the  system
deter mines  that the toggle bit  is still toggling, the  sys-
tem also should note whether the value of DQ5 is high
(see the sec tion on DQ5). If it is, the system should
then de termine again  whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling,  the device has successfully  completed the
program or er ase oper ation. If  it is still toggling, the de-

28 Am29SL160C

vice did not completed the operation succ essfully, and

the system must write the reset command to return to

reading array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

the toggle bit and DQ5 through successive read cy-

cles, determining the status as described in the

previous paragraph. Alter natively, it may choose to

perform other system tasks. In this case, the system

must start at the beginning of the algorithm when it re-

turns to determ ine the status of the operation (top of

Figure 6).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pu lse count limit. Under

these con ditions DQ5 p roduces a “1.” T his is a failure

condition that indicates the program or erase cycle

was not successfully completed.

The DQ5 failure condition may appear if the system

trie s to program a “ 1” to a location that is previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation

has exceeded the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase

command. When the time-out is complete, DQ3

sw itches from “0” to “1.” If the time between additional

sector e ras e commands fr om the system can b e as-

sumed to be less than 50 µs, the system need not

monitor DQ3. Se e also the “Sector Erase Comm and

Sequence” section.

After the sector erase command sequence is written,

the system should re ad the s tatus on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has

accepted the command sequence, and then read

DQ3. If DQ3 is “1”, the int ernally controlled e rase cycle

has begun; all fur ther commands (other than Erase

Suspend) are ignored until the erase oper at ion is com-

plete. If DQ3 is “0”, the device will accept additional

sector erase commands. To ensure the command has

been accepted, the system software s hould check the

status of DQ3 pr ior to and following each subse quent

secto r erase comma nd. If DQ3 is hig h o n the secon d

status check, the last command might not have been

accepted. Table 13 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

21635C-9

Figure 6. Toggle Bit Algorith m

(Notes

1, 2)

(Note 1)

Am29SL160C 29

Table 13. W rite Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

Operation DQ7

(Note 2) DQ6 DQ5

(Note 1) DQ3 DQ2

(Note 2) RY/BY#

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0

Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase

Suspend

Mode

Reading within Erase

Suspended Sector 1 No toggle 0 N/A Toggle 1

Reading within Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

30 Am29SL160C

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1). . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

A9, OE#,

and RESET# (Note 2) . . . . . . . .–0.5 V to +11.0 V

All other pins (Note 1) . . . . .–0.5 V to VCC + 0.5 V

Output Short Circuit Current (Note 3) . . . . . . 100 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot VSS to –2.0 V for periods of up to 20 ns. See

Figure 7. Maximum DC voltage on input or I/O pins is

VCC +0.5 V. During voltage transitions, input or I/O pins

may ov ershoot to VCC +2.0 V for periods up to 20 ns. See

Figure 8.

2. Minimum DC input v oltage on pins A9, OE#, RESET#, and

WP#/A CC is –0.5 V. During voltag e tr ansi tions, A9, OE#,

WP#/A CC, and RESET# may o vershoot VSS to –2.0 V f or

periods of up to 20 ns. See Figure 7. Maximum DC input

vol tage on pin A9 is +11.0 V whic h may overshoot to +12.5

V for periods up to 20 ns. Maximum DC input v oltage on pin

WP#/A CC is +10.0 V which may overs hoot to +11.5 V for

periods up to 20 ns .

3. No more than one out put may be shorted to ground at a

time. Dur ation of the s hort circuit shou ld not be greater than

one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temper ature (TA). . . . . . . . . . . . 0°C to +70°C

Industrial (I) De vices

Ambient Temper ature (TA). . . . . . . . . . –40°C to +85°C

VCC Supply Voltages

VCC, all speed opt ions. . . . . . . . . . . . +1.8 V to +2.2 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

Figure 7. Maximum Negative Overshoot

Waveform Figure 8. Maximum Positive Overshoot

Waveform

20 ns

0.0 V

VSS

–0.5 V

20 ns

VSS

–2.0 V

21635C-10

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

21635C-11

Am29SL160C 31
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 1 mA/MHz, with OE# at VIL. Ty pica l VCC is 2.0 V.
2. The maximum ICC specifications are tested with VCC = V CCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 50 ns.
5. Not 100% tested.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, 
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 11.0 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC, 
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current 
(Notes 1, 2)
CE# = VIL, OE# = VIH,
Byte Mode 5 MHz 5 10
mA
1 MHz 1 3
CE# = VIL, OE# = VIH,
Word Mode 5 MHz 5 10
1 MHz 1 3
ICC2 VCC Active Write Current 
(Notes 2, 3, 5) CE# = VIL, OE# = VIH 20 30 mA
ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC±0.2 V 1 5 µA
ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.2 V 1 5 µA
ICC5 Automatic Sleep Mode 
(Notes 2, 3) VIH = VCC ± 0.2 V; 
VIL = VSS ± 0.2 V 15µA
VIL Input Low Voltage –0.5 0.2 x VCC V
VIH Input High Voltage 0.8 x VCC VCC + 0.3 V
VHH
Volta ge for WP#/ACC Sector 
Protect/Unprotect and Program 
Acceleration 8.5 9.5 V
VID Voltage for Autoselect and 
Temporary Sector Unprotect VCC = 2.0 V 9.0 11.0 V
VOL Output Low Voltage IOL = 100 µA, VCC = VCC min 0.1
VOH Output High Voltage IOH = –100 µA, VCC = VCC min V
CC–0.1
VLKO Low VCC Lock-Out Voltage 
(Note 4) 1.2 1.5 V

32 Am29SL160C

DC CHARACTERISTICS (Continued)

Zero Power Flash

00 500 1000 1500 2000 2500 3000 3500 4000

Supply Curr e nt in mA

Time in ns

Note: Addresses are switching at 1 MHz

21635C-12

Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

12345

Frequency in MHz

Supply Current in mA

Note: T = 25

21635C-13

Figure 10. Typical ICC1 vs. Frequency

1.8 V

2.2 V

Am29SL160C 33

TEST CONDITIONS

Table 14. Test Specifications

KEY TO SWITCHING WAVEFORMS

Device

Under

Test

21635C-14

Figure 11. Test Setup

Test Condition 90, 100 120, 150 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap aci tan ce) 30 100 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–2.0 V

Input timing measurement

reference levels 1.0 V

Output timing measurement

reference levels 1.0 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changi ng from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

2.0 V

0.0 V 1.0 V 1.0 V OutputMeasurement LevelInput

21635C-15

Figure 12. Input Wa veforms and Measurement Levels

34 Am29SL160C

AC CHARACTERISTICS

Read Operations

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 14 for test specifications.

Parameter

Description

Speed Option

JEDEC Std Test Setup 90 100 120 150 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 90 100 120 150 ns

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL Max 90 100 120 150 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 100 120 150 ns

tGLQV tOE Output Enable to Output Delay Max 35 35 50 65 ns

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 50 50 60 60 ns

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 50 50 60 60 ns

tOEH Output Enable

Hold Time (Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 30 ns

tAXQX tOH Output Hold Time From Addresses, CE#

or OE#, Whichever Occurs First (Note 1) Min 0 ns

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

0 V

RY/BY#

RESET#

tDF

tOH

21635C-16

Figure 13. Read Operations Timings

Am29SL160C 35

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

tREADY RESET# Pin Low (During Embedded

Algorithms) to Read or Write (see Note) Max 20 µs

tREADY RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (see Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH RESET# High Time Before Read (see Note) Min 200 ns

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

21635C-17

Figure 14. RESET# Timings

36 Am29SL160C

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Description 90 100 120 150JEDEC Std Unit

tELFL/tELFH CE# to BYTE# Switching Low or High Max 10 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 50 50 60 60 ns

tFHQV BYTE# Switching High to Output Active Min 90 100 120 150 ns

DQ15

Output

Data Output

(DQ0–DQ7)

CE#

OE#

BYTE#

tELFL

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFLQZ

BYTE#

Switching

from word

to byte

mode

DQ15

Output

Data Output

(DQ0–DQ7)

BYTE#

tELFH

DQ0–DQ14 Data Outpu t

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFHQV

BYTE#

Switching

from byte

to word

mode

21635C-18

Figure 15. BYTE# Timings for Read Operations

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.

21635C-19

Figure 16. BYTE# Timings for Write Operations

CE#

WE#

BYTE#

The falling edge of the last WE# signal

tHOLD (tAH)

tSET

(tAS)

Am29SL160C 37

AC CHARACTERISTICS

Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter

90 100 120 150JEDEC Std Description Unit

tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 150 ns

tAVWL tAS Address Setup Time Min 0 ns

tWLAX tAH Address Hold Time Min 50 50 60 70 ns

tDVWH tDS Da ta Se tup Tim e Min 50 50 60 70 ns

tWHDX tDH Data Hold Time Min 0 ns

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Tim e Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 50 50 60 70 ns

tWHWL tWPH Write Pulse Width High Min 30 ns

tWHWH1 tWHWH1

Programming Operation (Notes 1, 2) Byte Typ 10 µs

Word Typ 12

Accelerated Program Operation, Byte or Word

(Note 2) Typ 8 µs

tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 sec

tVCS VCC Setup Time Min 50 µs

tRB Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Min 200 ns

38 Am29SL160C

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

tDS

tAH

tDH

tWP

tWHWH1

tWC tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tCS

Status DOUT

Program Command Sequence (last two cycles)

RY/BY#

tRB

tBUSY

tCH

Notes:

1. PA = program addre ss, PD = program data, DOUT is the true data at the program address.

2. Illustration shows de vice in word mode.

21635C-20

Figure 17. Pr ogram Operation Timings

Am29SL160C 39

AC CHARACTERISTICS

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

tRB

tBUSY

Notes:

1. SA = sector addres s (for Sector Erase), VA = Valid Address f or reading status data (see “Write Operatio n Statu s”).

2. Illustration shows device in word mode.

21635C-21

Figure 18. Chip/Sector Erase Operation Timings

40 Am29SL160C

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: V A = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

21635C-22

Figure 19. Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

DQ6/DQ2

RY/BY#

BUSY

Addresses VA

OEH

VA VA

ACC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

Note: V A = V alid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

21635C-23

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

Am29SL160C 41

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

All Speed OptionsJEDEC Std Description Unit

tVIDR VID Rise and Fall Time Min 500 ns

tVHH VHH Rise and Fall Time Min 500 ns

tRSP RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

21635C-24

Figure 21. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

RESET#

tVIDR

VID

0 or 1.8 V

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 1.8 V

21635C-25

Figure 22. Temporary Sector Unprotect Timing Diagram

42 Am29SL160C

AC CHARACTERISTICS

Figure 23. Accelerated Program Timing Diagram

WP#/ACC

tVHH

VHH

VIL or VIH

tVHH

VIL or VIH

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

RESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Protect/Unprotect Verify

VID

VIH

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

21635C-26

Figure 24. Sector Protect/Unprotect Timing Diagram

Am29SL160C 43

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter

90 100 120 150JEDEC Std Description Unit

tAVAV tWC Write Cycle Time (Note 1) Min 90 100 120 150 ns

tAVEL tAS Addre ss Set up Tim e M in 0 ns

tELAX tAH Address Hold Time Min 50 50 60 70 n s

tDVEH tDS Data Setup Time Min 50 50 60 70 ns

tEHDX tDH Data Hold Time Min 0 ns

tGHEL tGHEL Read Recovery Time Before Wr ite

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 50 50 60 70 ns

tEHEL tCPH CE# Pulse Width High Min 30 ns

tWHWH1 tWHWH1

Programming Ope ration

(Notes 1, 2) Byte Typ 10 µs

Word Typ 12

Accelerated Program Operation, Byte or Word

(Note 2) Typ 8 µs

tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 sec

44 Am29SL160C

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written, DOUT = data written

2. Figure indicates the la st tw o bus cycles of command sequence .

3. Word mode address used as an example.

21635C-27

Figure 25. Alternate CE# Controlled Write Operation Timin gs

Am29SL160C 45

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 2.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case co nditi ons of 90°C, VCC = 1.8 V, 1,000,000 cycles.

3. The typical chi p prog r ammi ng time is c onsider ably less than the maxim um chi p prog r amming time list ed, si nce most b yt es

progra m faster than the max im um prog r am t imes l isted.

4. In the pre-pro gr ammi ng step of t he Embedded Er as e algorithm, all b yt es are prog r ammed to 00h before erasure.

5. System-level o verhead is the t ime r equired to execute the two- or four-bus-cycle s equence for the program command. See Table

12 for further information on command definitions.

6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time.

TSOP PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 2 15 s Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time 70 s

Byte Programming Time 10 300 µs

Excludes system level

overhead (Note 5)

Word Programming Time 12 360 µs

Accelerated Program Time, Word/Byte 8 240 µs

Chip Programming Time

(Note 3)

Byte Mode 20 160 s

Word Mode 14 120 s

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(including A9, OE #, and RESE T#) –1.0 V 11.0 V

Input voltage with respect to VSS on all I/O pins –0.5 V VCC + 0.5 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C 10 Years

125°C 20 Years

46 Am29SL160C

PH YS ICAL DIMENSIONS *

TS 048—48-Pin Standard TSOP (measured in millimeters)

* For reference only. BSC is an ANSI standard for Basic Space Centering.

Dwg rev AA; 10/99

Am29SL160C 47

PH YS ICAL DIMENSIONS

FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm (measured in millimeters)

Dwg rev AF; 10/99

48 Am29SL160C

REVISION SUMMARY

Revision A+1 (January 1999)

Distinctive Characteristics

WP#/AC C pin:

In the third subbullet, deleted referenc e

to increased erase perfor manc e.

Device Bus Operations

Accelerated Program and Erase Operations:

Deleted

all references to accelerated erase .

Sector/Sector Block Protection and Unprotection:

Change d section na me and text to include ta bles and

references to sector block protection and unprotecti on.

AC Character istics

Accelerated Program Timing Diagram:

Deleted refer-

ence in title to accelerated erase.

Revision A+2 (March 23, 1999)

Connection Diagrams

Corrected the TSOP pinout on pins 13 and 14.

Revision A+3 (April 12, 1999)

Global

Modified the des cription of acc elerated programming

to emphasize that it is in tended only to speed in-sys-

tem programming of the device during the system

production process .

Distinctive Characteristics

Secured Silicon (SecSi) Sector bullet:

Added the 8-

byte unique serial number to descr iption.

Device Bus Operations table

Modified N ote 3 to indicate sector protection be havior

when VIH is asser ted on WP#/AC C. Applied Note 3 to

the WP#/ACC column for write operations.

Ordering Information

Added the “N” designator to the optional processing

section.

Secured Silicon (SecSi) Sector Flash Memory

Region

Modified explanator y text to indi cate that dev ices now

have an 8-byte unique ESN in addition to the 16-byte

random ESN. Added table for address range

clarification.

Revision A+4 (May 14, 1999)

Global

Deleted all references to the unique ESN.

Revision A+5 (July 23, 1999)

Global

Added 90 ns speed option.

Revision A+6 (September 1, 1999)

AC Character istics

Hardware Reset (RESET#) table:

Deleted tRPD specifi-

cation.

Erase/Program Operations table:

Deleted tOES

specification.

Revision A+7 (September 7, 1999)

Distinctive Characteri stics

Ultra low power consumption bullet:

Correc ted values

to match those in the DC Charac teristics table.

AC Character istics

Alter na te C E# Contr olled Erase/P rogram O perations :

Deleted tOES specification.

Revision B (December 14, 1999)

AC Characteristics—Figure 17. Program

Operations Timing and Figure 18. Chip/Sector

Erase Operations

Deleted tGHWL and changed OE# waveform to start at

high.

Physi cal Dimensions

Replaced figures with more detailed illustrations.

Revision C (February 21, 2000)

Remov ed “Advance I nf ormation” designat ion from data

sheet. Data sheet parameters are now stable; only

speed, package, and temperature range combinations

are expected to change in future revisions.

Device Bus Operations table

Changed standby voltage specification to VCC ± 0.2 V.

Standby Mode

Changed standby voltage specification to VCC ± 0.2 V.

DC Characteristics tab le

Changed test conditi ons for ICC3, ICC4, ICC5 to VCC ± 0.2

Am29SL160C 49

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respec tive companies.