Am29SL160C 27
RY/BY#: Ready/Busy#
R Y /BY# is a dedicated, open-dr ain output pin that indi-
cates whether an Embedded Algorithm is in progress
or complete. The RY/BY# status is v ali d aft er the rising
edge of the final WE# pulse in the command se-
quence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel
with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is ready to read array data (includ-
ing during the Erase Suspend mode), or is in the
standb y mode.
Tab le 13 shows the output s f or RY/BY#. Figures 14, 17
and 18 shows RY/BY# for reset, program, and erase
operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indic ates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device has entered the Erase
Suspend m ode. Toggle Bit I may be read at any ad-
dress, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cyc les to any address ca use
DQ6 to toggle (The system may use either OE# or
CE# to control the read cycles). When the operation is
complete, DQ6 stops toggling.
After an erase command sequ ence is wr itten, if all
sectors s elected for erasing are pro tected, DQ6 tog-
gles fo r approximately 100 µs, then returns to readin g
arra y data . If not all selected secto rs are prot ected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
The syst em can use D Q6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, th e Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspen d
mode, DQ6 stops toggling. H owever, the system must
also use DQ2 to d eterm ine whi ch sectors are erasing
or erase-sus pended. Alternatively, the s ystem can use
DQ7 (see the s ubsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggle s for approxima tely 1 µs after the pr ogram
command sequence is written, then retur ns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 13 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 20 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 21 shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is , the Embedded Er ase algo rithm is in progr ess),
or whether that s ector is erase-s uspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence. The device toggles DQ2 with
each OE# or CE# read cycle.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. But DQ2 cannot dist inguish whether the s ector is
actively erasing or is erase-suspended. DQ6, by com-
parison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selecte d for erasure. Thus, both sta-
tus bits a re requir ed for sector and m ode inform ation.
Refer to Table 13 to compare outputs for DQ2 and
DQ6.
Figure 6 shows the toggle bit algor ithm in flowchar t
for m, and the section “DQ2: Toggle Bit II” explains the
algor ithm. Se e also th e DQ6: Togg le Bit I su bsectio n.
Figure 2 0 shows the toggle bit timi ng diagram. Figure
21 shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Ty pically,
the system would note an d store the value of the tog-
gle bit after the first read. After the sec ond read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cy cle.
However, if after the initial two read cycles, the system
deter mines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the sec tion on DQ5). If it is, the system should
then de termine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or er ase oper ation. If it is still toggling, the de-