MB95630H Series
New 8FX 8-bit Microcontrollers
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002-04627 Rev. *A Revised March 29, 2016
The MB95630H Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the
microcontrollers of this series contain a variety of peripheral functi ons.
Features
■F2MC-8FX CPU core
❐Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
■Clock
❐Selectable main clock source
• Main oscillation clock (up to 16.25 MHz, maximum ma-
chine clock frequency: 8.125 MHz)
• External clock (up to 32.5 MHz, maximum machine clock
frequency: 16.25 MHz)
• Main CR clock (4 MHz 2%)
• Main CR PLL clock
- The main CR PLL clock frequency becomes 8 MHz
2% when the PLL multiplication rate is 2.
- The main CR PLL clock frequency becomes 10 MHz
2% when the PLL multiplication rate is 2.5.
- The main CR PLL clock frequency becomes 12 MHz
2% when the PLL multiplication rate is 3.
- The main CR PLL clock frequency becomes 16 MHz
2% when the PLL multiplication rate is 4.
❐Selectable subclock source
• Suboscillation clock (32.768 kHz)
• External clock (32.768 kHz)
• Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)
■Timer
❐8/16-bit composite timer 2 channels
❐8/16-bit PPG 3 channels
❐16-bit PPG timer 1 channel (can work independently or
together with the multi-pu lse generator)
❐16-bit reload timer 1 channel (can work independently or
together with the multi-pu lse generator)
❐Time-base timer 1 channel
❐Watch presca l e r 1 channel
■UART/SIO 1 channel
❐Full duplex double buffer
❐Capable of clock asynchronous (UART) serial data transfer
and clock synchronous (SIO) serial data transfer
■I2C bus interface 1 channel
❐Built-in wake-up function
■Multi-pulse generator (MPG) (for DC motor control) 1 channel
❐16-bit reload timer 1 channel
❐16-bit PPG timer 1 channel
❐Waveform sequencer (including a 16-bit timer equipped with
a buffer and a compare clear function)
■LIN-UART
❐Full duplex double buffer
❐Capable of clock asynchronous serial data transfer and clock
synchronous serial data transfer
■External interrupt 10 channels
❐Interrupt by edge detection (rising edge, falling edge, and
both edges can be selected)
❐Can be used to wake up the device from different low power
consumption (standby) modes
■8/10-bit A/D converter 8 channels
❐8-bit or 10-bit resolution can be selected.
■Low power consumption (standby) modes
❐There are four standby modes as follows:
• Stop mode
• Sleep mode
•Watch mode
• Time-base timer mode
❐In standby mode, two further options can be selected: normal
standby mode and deep standby mode.
■I/O port
❐MB95F632H/F633H/F634H/F636H (number of I/O ports: 28)
• General-purpose I/O ports (CMOS I/O): 25
• General-purpose I/O ports (N-ch open drain): 3
❐MB95F632K/F633K/F634K/F636K (number of I/O ports: 29)
• General-purpose I/O ports (CMOS I/O): 25
• General-purpose I/O ports (N-ch open drain): 4
■On-chip debug
❐1-wire serial control
❐Serial writing supported (asynchronous mode)
■Hardware/software wa tchdog timer
❐Built-in hardware watchdog timer
❐Built-in software watchdog timer
■Power-on reset
❐A power-on reset is generated when the power is switched
on.
■Low-voltage detection reset circuit (only available on
MB95F632K/F633K/F634K/F636K)
❐Built-in low-voltage detection function (The combination of
detection voltage and release voltage can be selected from
four options.)
■Comparator
■Clock supervisor counter
❐Built-in clock supervisor counter
■Dual operation Flash memory
❐The program/erase operation and the read operation can be
executed in different banks (upper bank/lower bank) simul-
taneously.
■Flash memory security function
❐Protects the content of the Flash memory.
MB95630H Series
Document Number: 002-04627 Rev. *A Page 2 of 102
Contents
Features ............................................................................. 1
1. Product Line-up............................................................ 3
2. Packages And Corresponding Products.................... 5
3. Differences Among Products And Notes On
Product Selection............................................................. 5
4. Pin Assignment ............................................................ 6
5. Pin Functions................................................................ 8
6. I/O Circuit Type........... .............. .............. ... .............. ... 12
7. Handling Precautions................................................. 14
7.1 Precautions for Product Design........................... 14
7.2 Precautions for Package Mounting ..................... 15
7.3 Precautions for Use Environment........................ 17
8. Notes On Device Handling ......................................... 17
9. Pin Connection........................................................... 18
10. Block Diagram .......................................................... 19
11. CPU Core................................................................... 20
12. Memory Space.......................................................... 21
13. Areas For Specific Applications ............................. 23
14. I/O Map....................................................................... 24
15. I/O Ports..................................................................... 30
15.1 Port 0................................................................. 31
15.2 Port 1................................................................. 39
15.3 Port 6................................................................. 46
15.4 Port F................................................................. 51
15.5 Port G................................................................ 53
16. Interrupt Source Table............ ... .............. ... ... .......... 56
17. Pin States In Each Mode.......................................... 57
18. Electrical Characteristics......................................... 61
18.1 Absolute Maximum Ratings............................... 61
18.2 Recommended Operating Conditions............... 63
18.3 DC Characteristics ............................................ 64
18.4 AC Characteristics............................................. 67
18.5 A/D Converter................................................... 85
18.6 Flash Memory Program/Erase Characteristics. . 89
19. Sample Characteristics............................................ 90
20. Mask Options. ........................................................... 97
21. Ordering Information................................................ 97
22. Package Dimension.................................................. 98
23. Major Changes In This Edition.............. .. .............. 101
Document History Page........... ........ .............. ... ........... 101
Sales, Solutions, and Legal Information.................... 102
MB95630H Series
Document Number: 002-04627 Rev. *A Page 3 of 102
1. Product Line-up
Part number
Parameter
MB95F632H MB95F633H MB95F634H MB95F636H MB95F632K MB95F633K MB95F634K MB95F636K
Type Flash memory product
Clock
supervisor
counter It supervises the main clock oscillation and the subclock oscillation.
Flash mem or y
capacity 8 Kbyte 12 Kbyte 20 Kbyte 36 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte 36 Kbyte
RAM capacity 256 bytes 512 bytes 1024 bytes1024 bytes 256 bytes 512 bytes 1024 bytes1024 bytes
Power-on reset Yes
Low-voltage
detection reset No Yes
Reset input Dedicated Selected through softwar e
CPU functions
• Number of basic instructions : 136
• Instruction bit length : 8 bits
• Instruction length : 1 to 3 bytes
• Data bit length : 1, 8 and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz)
General-
purpose I/O
• I/O port : 28
•CMOS I/O :25
• N-ch open drain : 3
• I/O port : 29
• CMOS I/O : 25
• N-ch open drain : 4
Time-base timerInterval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
Hardware/
software
watchdog timer
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
• The sub-CR clock can be used as the source clock of the software watchdo g timer.
Wild register It can be used to replace 3 bytes of data.
LIN-UART
• A wide rang e of communication speed can be selected by a ded icated reload timer.
• It has a full duplex double buffer.
• Both clock synchronous serial data transfer and clock asynchronous serial data transfer are
enabled.
• The LIN function can be used as a LIN master or a LIN slave.
8/10-bit
A/D converter 8 channels
8-bit or 10-bit resolution can be selected.
8/16-bit
composite timer
2 channels
• The timer can be configured as an “8-bit time r × 2 channels” or a “16-bi t timer × 1 channel”.
• It has the following functions: interval timer function, PWC function, PWM function and input
capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
MB95630H Series
Document Number: 002-04627 Rev. *A Page 4 of 102
Part number
Parameter
MB95F632H MB95F633H MB95F634H MB95F636H MB95F632K MB95F633K MB95F634K MB95F636K
External
interrupt
10 channels
• Interrupt by edge detection (The ri sing edge, falling edge, an d both edges can be selected.)
• It can be used to wake up the device from differ ent standby modes.
On-chip debug • 1-wire serial control
• It supports serial writing (asynchronous mode).
UART/SIO
1 channel
• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate
generator and an error detection function.
• It uses the NRZ type transfer format.
• LSB-first data transfer and MSB-first data transfer are available to use.
• Both clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial
data transfe r ar e en ab le d.
I2C bus
interface
1 channel
• Master/slave transmission and reception
• It has the following functions: bus error function, arbitration functio n, transfer direct ion de-
tection function, wake-up function, and functions of generating and detecting repeated
START conditions.
8/16-bit PPG 3 channels
• Each channel can be used as an “8-bit timer 2 channels” or a “16-bit timer 1 channel”.
• The counter operating clock can be selected from eight clock sources.
16-bit PPG
timer
1 channel
• PWM mode and one-shot mode are available to use.
• The counter operating clock can be selected from eight clock sources.
• It supports external trigger start.
• It can work independently or together with the multi-pulse generator.
16-bit reload
timer
1 channel
• Two clock modes and two counter operating modes are available to use.
• It can output square wave.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• Two counter operating modes: reload mode and one-shot mode
• It can work independently or together with the multi-pulse generator.
Multi-pulse
generator (for
DC motor
control)
• 16-bit PPG timer: 1 channel
• 16-bit reload timer operations: toggle output, one-shot output
• Event counter: 1 channel
• Waveform sequencer (including a 16-bit timer equipped with a buffer and a compare clear
function)
Watch prescalerEight different time intervals can be selected.
Comparator 1 channel
MB95630H Series
Document Number: 002-04627 Rev. *A Page 5 of 102
2. Packages And Corresponding Products
: Available
3. Differences Among Products And Notes On Product Selection
• Current consumption
When using the on-chip debug function, take account of the curren t consu mption of Flash memory program/erase.
For details of current consumption, see “Electrical Characteristics”.
• Package
For details of information on each package, see “Packages And Corresponding Products” an d “Package Dimension”.
• Operating voltage
The operating voltage varies, depending on wheth er the on-chip debug function is used or not.
For details of operating voltage, see “Electrical Characteristics”.
• O n- ch ip de bu g func tio n
Part number
Parameter
MB95F632H MB95F633H MB95F634H MB95F636H MB95F632K MB95F633K MB95F634K MB95F636K
Flash mem or y
• It supports automatic programming (Embedded Algorithm), and program/erase/erase-
suspend/erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Flash security feature for protecting the content of the Flash memory
Standby mode
There are four stan d by m od es as follo ws:
• Stop mode
• Sleep mode
•Watch mode
• Time-base timer mode
In standby mode, two further options can be selected: normal standby mode and deep
standby mode.
Package FPT-32P-M30
DIP-32P-M06
LCC-32P-M19
Part number
Package
MB95F632H MB95F633H MB95F634H MB95F636H MB95F632K MB95F633K MB95F634K MB95F636K
FPT-32P-M30
DIP-32P-M06
LCC-32P-M19
Number of program/erase cycles 1000 10000 100000
Data retention time 20 years 10 years 5 years
MB95630H Series
Document Number: 002-04627 Rev. *A Page 6 of 102
The on-chip debug fu nction requires that VCC, VSS and one serial wire be connected to an evaluation tool. For details
of the connection method, refer to “CHAPTER 25 EXAMPLE OF SERIAL PROGRAMMING CONNECTION” in “New
8FX MB95630H Series Hardware Manual”.
4. Pin Assignment
Vss
PF1/X1
PF0/X0
PF2/RST
P17/TO1/SNI0
P16/UI0/PPG21
P15/UO0/PPG20
P14/UCK0/PPG01
P13/PPG00
P12/DBG/EC0
P11/PPG11
P10/PPG10/CMP0_O
PG2/X1A/SNI2
PG1/X0A/SNI1
Vcc
C
P67/PPG21/TRG1/OPT5
P66/PPG20/PPG1/OPT4
P65/PPG11/OPT3
P64/EC1/PPG10/OPT2
(TOP VIEW)
LQFP32
FPT-32P-M30
32
31
30
29
28
27
26
25
24
23
22
21
P07/INT07/AN07
P06/INT06/AN06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
20
19
18
17
1
2
3
4
5
6
7
8
P63/TO11/PPG01/OPT1
P62/TO10/PPG00/OPT0
P61/INT09/SCL/TI1
P60/INT08/SDA/DTTI
9
10
11
12
P00/INT00/AN00/CMP0_P
P01/INT01/AN01/CMP0_N
P02/INT02/AN02/SCK
13
14
15
P03/INT03/AN03/SOT 16
MB95630H Series
Document Number: 002-04627 Rev. *A Page 7 of 102
P17/TO1/SNI0
P16/UI0/PPG21
P15/UO0/PPG20
P14/UCK0/PPG01
P13/PPG00
P12/DBG/EC0
P11/PPG11
P10/PPG10/CMP0_O
P07/INT07/AN07
P06/INT06/AN06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
PF2/RST
PF0/X0
PF1/X1
Vss
PG2/X1A/SNI2
PG1/X0A/SNI1
Vcc
C
P67/PPG21/TRG1/OPT5
P66/PPG20/PPG1/OPT4
P65/PPG11/OPT3
P64/EC1/PPG10/OPT2
(TOP VIEW)
SH-DIP32
DIP-32P-M06
32
31
30
29
28
27
26
25
24
23
22
21
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/INT01/AN01/CMP0_N
P00/INT00/AN00/CMP0_P
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
P63/TO11/PPG01/OPT1
P62/TO10/PPG00/OPT0
P61/INT09/SCL/TI1
13
14
15
P60/INT08/SDA/DTTI 16
Vss
PF1/X1
PF0/X0
PF2/RST
P17/TO1/SNI0
P16/UI0/PPG21
P15/UO0/PPG20
P14/UCK0/PPG01
P13/PPG00
P12/DBG/EC0
P11/PPG11
P10/PPG10/CMP0_O
PG2/X1A/SNI2
PG1/X0A/SNI1
Vcc
C
P67/PPG21/TRG1/OPT5
P66/PPG20/PPG1/OPT4
P65/PPG11/OPT3
P64/EC1/PPG10/OPT2
(TOP VIEW)
QFN32
LCC-32P-M19
32
31
30
29
28
27
26
25
24
23
22
21
P07/INT07/AN07
P06/INT06/AN06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
20
19
18
17
1
2
3
4
5
6
7
8
P63/TO11/PPG01/OPT1
P62/TO10/PPG00/OPT0
P61/INT09/SCL/TI1
P60/INT08/SDA/DTTI
9
10
11
12
P00/INT00/AN00/CMP0_P
P01/INT01/AN01/CMP0_N
P02/INT02/AN02/SCK
13
14
15
P03/INT03/AN03/SOT 16
MB95630H Series
Document Number: 002-04627 Rev. *A Page 8 of 102
5. Pin Functions
Pin no. Pin name I/O
circuit
type*4Function I/O type
LQFP32*1,
QFN32*2SH-DIP32*3Input Output OD*5PU*6
15
PG2
C
General-purpose I/O port
Hysteresis CMOS —
X1A Subclock I/O oscillation pin
SNI2 Trigger input pin for the positio n
detection function of the MPG
waveform sequencer
26
PG1
C
General-purpose I/O port
Hysteresis CMOS —
X0A Subclock input oscillation pin
SNI1 Trigger input pin for the positio n
detection function of the MPG
waveform sequencer
37V
CC —Power supply pin ————
48C
—Decoupling capacitor connection pin ————
59
P67
D
General-purpose I/O port
High-current pin
Hysteresis CMOS —
PPG21 8/16-bit PPG ch. 2 output pin
TRG1 16-bit PPG timer ch. 1 trigger input
pin
OPT5 MPG waveform sequencer output
pin
610
P66
D
General-purpose I/O port
High-current pin
Hysteresis CMOS —
PPG20 8/16-bit PPG ch. 2 output pin
PPG1 16-bit PPG timer ch. 1 output pin
OPT4 MPG waveform sequencer output
pin
711
P65
D
General-purpose I/O port
High-current pin Hysteresis CMOS —PPG11 8/16-bit PPG ch. 1 output pin
OPT3 MPG waveform sequencer output
pin
812
P64
D
General-purpose I/O port
High-current pin
Hysteresis CMOS —
EC1 8/16-bit composite timer ch. 1 clock
input pin
PPG10 8/16-bit PPG ch. 1 output pin
OPT2 MPG waveform sequencer output
pin
MB95630H Series
Document Number: 002-04627 Rev. *A Page 9 of 102
Pin no. Pin name I/O
circuit
type*4Function I/O type
LQFP32*1,
QFN32*2SH-DIP32*3Input Output OD*5PU*6
913
P63
D
General-purpose I/O port
High-current pin
Hysteresis CMOS —
TO11 8/16-bit composite timer ch. 1
output pin
PPG01 8/16-bit PPG ch. 0 output pin
OPT1 MPG waveform sequencer
output pin
10 14
P62
D
General-purpose I/O port
High-current pin
Hysteresis CMOS —
TO10 8/16-bit composite timer ch. 1
output pin
PPG00 8/16-bit PPG ch. 0 output pin
OPT0 MPG waveform sequencer
output pin
11 15
P61
I
General-purpose I/O port
CMOS CMOS —
INT09 External interrupt input pin
SCL I2C bus interface ch. 0 clock I/O
pin
TI1 16-bit reload timer ch. 1 input pin
12 16
P60
I
General-purpose I/O port
CMOS CMOS —
INT08 External interrupt input pin
SDA I2C bus interface ch. 0 data I/O
pin
DTTI MPG waveform sequencer input
pin
13 17
P00
E
General-purpose I/O port
Hysteresis/
analog CMOS —
INT00 External interrupt input pin
AN00 8/10-bit A/D converter analog
input pin
CMP0_P Comparator non-inverting analog
input (positive input) pin
14 18
P01
E
General-purpose I/O port
Hysteresis/
analog CMOS —
INT01 External interrupt input pin
AN01 8/10-bit A/D converter analog
input pin
CMP0_N Comparator inverting analog
input (negative input) pin
MB95630H Series
Document Number: 002-04627 Rev. *A Page 10 of 102
Pin no. Pin name I/O
circuit
type*4Function I/O type
LQFP32*1,
QFN32*2SH-DIP32*3Input Output OD*5PU*6
15 19
P02
E
General-purpose I/O port
Hysteresis/
analog CMOS —
INT02 External interrupt input pin
AN02 8/10-bit A/D converter analog
input pin
SCK LIN-UART clock I/O pin
16 20
P03
E
General-purpose I/O port
Hysteresis/
analog CMOS —
INT03 External interrupt input pin
AN03 8/10-bit A/D converter analog
input pin
SOT LIN-UART data output pin
17 21
P04
F
General-purpose I/O port
CMOS/
analog CMOS —
INT04 External interrupt input pin
AN04 8/10-bit A/D converter analog
input pin
SIN LIN-UART data input pin
EC0 8/16-bit composite timer ch. 0
clock input pin
18 22
P05
E
General-purpose I/O port
Hysteresis/
analog CMOS —
INT05 External interrupt input pin
AN05 8/10-bit A/D converter analog
input pin
TO00 8/16-bit composite timer ch. 0
output pin
19 23
P06
E
General-purpose I/O port
Hysteresis/
analog CMOS —
INT06 External interrupt input pin
AN06 8/10-bit A/D converter analog
input pin
TO01 8/16-bit composite timer ch. 0
output pin
20 24
P07
E
General-purpose I/O port Hysteresis/
analog CMOS —
INT07 External interrupt input pin
AN07 8/10-bit A/D converter analog
input pin
21 25 P10 GGeneral-purpose I/O port Hysteresis CMOS —PPG10 8/16-bit PPG ch. 1 output pin
CMP0_O Comparator digital output pin
MB95630H Series
Document Number: 002-04627 Rev. *A Page 11 of 102
: Available
*1:FPT-32P-M30
*2:LCC-32P-M19
*3:DIP-32P-M06
*4:For the I/O circuit types, see “I/O Circuit Type”.
*5:N-ch open drain
*6:Pull-up
Pin no. Pin name I/O
circuit
type*4Function I/O type
LQFP32*1,
QFN32*2SH-DIP32*3Input Output OD*5PU*6
22 26 P11 GGeneral-purpose I/O port Hysteresis CMOS —
PPG11 8/16-bit PPG ch. 1 output pin
23 27
P12
H
General-purpose I/O port
Hysteresis CMOS —
DBG DBG input pin
EC0 8/16-bit composite timer ch. 0
clock input pin
24 28 P13 GGeneral-purpose I/O port Hysteresis CMOS —
PPG00 8/16-bit PPG ch. 0 output pin
25 29 P14 GGeneral-purpose I/O port Hysteresis CMOS —UCK0 UART/SIO ch. 0 clock I/O pin
PPG01 8/16-bit PPG ch. 0 output pin
26 30 P15 GGeneral-purpose I/O port Hysteresis CMOS —UO0 UART/SIO ch. 0 data output pin
PPG20 8/16-bit PPG ch. 2 output pin
27 31 P16 JGeneral-purpose I/O port CMOS CMOS —UI0 UART/SIO ch. 0 data input pin
PPG21 8/16-bit PPG ch. 2 output pin
28 32
P17
G
General-purpose I/O port
Hysteresis CMOS —
TO1 16-bit reload timer ch. 1 output
pin
SNI0 Trigger input pin for the positio n
detection function of the MPG
waveform sequencer
29 1
PF2
A
General-purpose I/O port
Hysteresis CMOS —
RST
Reset pin
Dedicated reset pin on
MB95F632H/F633H/F634H/
F636H
30 2 PF0 BGeneral-purpose I/O port Hysteresis CMOS ——
X0 Main clock input oscillation pin
31 3 PF1 BGeneral-purpose I/O port Hysteresis CMOS ——
X1 Main clock I/O oscillation pin
32 4 VSS — Power supply pin (GND) ————
MB95630H Series
Document Number: 002-04627 Rev. *A Page 12 of 102
6. I/O Circuit Type
Type Circuit Remarks
A• N-ch open drain output
• Hysteresis input
• Reset output
B• O scillation circ uit
• High-speed side
Feedback resistance:
approx. 1 M
• CMOS output
• Hysteresis input
C• O scillation circ uit
• Low-speed side
Feedback resistance:
approx. 5 M
• CMOS output
• Hysteresis input
• Pull-up control
N-ch
Reset output / Digital output
Reset input / Hysteresis input
Standby control / Port select
Clock input
Port select
Digital output
Digital output
Standby control
Hysteresis input
Digital output
Digital output
Standby control
Hysteresis input
Port select
X1
X0
N-ch
P-ch
N-ch
P-ch
Clock input
X1A
X0A
Standby control / Port select
N-ch
P-ch
Port select
Digital output
Digital output
Standby control
Hysteresis input
N-ch
Digital output
Digital output
Digital output
Standby control
Hysteresis input
P-ch
RPull-up control
Port select
P-ch
RPull-up control
MB95630H Series
Document Number: 002-04627 Rev. *A Page 13 of 102
Type Circuit Remarks
D• CMOS output
• Hysteresis input
• Pull-up control
• High current output
E• CMOS output
• Hysteresis input
• Pull-up control
• Analog input
F• CMOS output
•CMOS input
• Pull-up control
• Analog input
G• CMOS output
• Hysteresis input
• Pull-up control
H• N-ch open drain output
• Hysteresis input
N-ch
P-ch
P-ch
RPull-up control
Digital output
Digital output
Standby control
Hysteresis input
N-ch
P-ch
P-ch
RPull-up control
Digital output
Digital output
Analog input
A/D control
Standby control
Hysteresis input
N-ch
P-ch
P-ch
RPull-up control
Digital output
Digital output
Analog input
A/D control
Standby control
CMOS input
N-ch
P-ch
P-ch
RPull-up control
Digital output
Digital output
Standby control
Hysteresis input
N-ch
Standby control
Hysteresis input
Digital output
MB95630H Series
Document Number: 002-04627 Rev. *A Page 14 of 102
7. Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the
conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions
that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor
devices.
7.1 Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
Absolute Maximum Ratings
Semiconductor devices can be perm anently damaged by application of stress (volta ge, current, temperature, etc.) in
excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's
electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges
may adversely affect reliability and could result in device failure.
No warranty is made with respect to u ses, ope ra ting con dition s, or combin ations not r epresen ted o n the da ta sheet.
Users considering application outside the listed conditions are advised to contact their sales representative before-
hand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply
and input/out pu t fun ctions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration
within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage
or over-current conditions at the design stage.
Type Circuit Remarks
I• N-ch open drain output
•CMOS input
J• CMOS output
•CMOS input
• Pull-up control
N-ch
Digital output
Standby control
CMOS input
N-ch
P-ch
P-ch
RPull-up control
Digital output
Digital output
Standby control
CMOS input
MB95630H Series
Document Number: 002-04627 Rev. *A Page 15 of 102
(2) Protection of Output Pins
Shorting of output pins to s upply pins or ot her output pins, or connection to large capacitance can cause large
current flows. Su ch cond itio ns if present for extended periods of time can damage the device.
Therefore, avoid th is type of conn ection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins
should be connected through an appropriate resistance to a power supply pin or ground pin.
Latch-up
Semiconductor devices are constr ucted by the formation of P-type an d N-type areas on a substrate. When sub jected
to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing
large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is
called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause
injury or damage from high heat, smoke or flame. To prevent this from happening, do the following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from electromag-
netic interference, etc. Customers are requested to observe applicable regulations and standards in the design of
products.
Fail-Safe Design
Any semiconducto r devices ha ve inhere ntly a certain rate of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions.
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement equipm ent, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation
may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability
are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls,
medical devices for life support, etc.) are requested to consult with sales representatives before such use. The
company will not be responsible for damages arising from such use without prior approval.
7.2 Precautions for Package Mounting
Package mounting may be ei ther lead insertion type or surfa ce mount type. In either case, for heat resistance during
soldering, you should only mount under Cypress’s recommended conditions. For detailed information about mount
conditions, contact your sales representative.
Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering
on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and
using the flow soldering (wave soldering ) method of applying liquid solder . In this case, the soldering process usually
MB95630H Series
Document Number: 002-04627 Rev. *A Page 16 of 102
causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting
processes should conform to Cypress recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to
contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts
and IC leads be verified before mounting.
Surface Mount Type
Surface mount packaging has lon ger and thi nner leads tha n lead-inser tion packaging, an d therefore leads are more
easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased
susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established
a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress
ranking of recommended conditions.
Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering,
junction strength may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause
absorption of moisture. During mounting, the application of hea t to a package th at has absorbed moisture can cause
surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store
products in locat i on s whe re tem p er at ur e ch an ge s ar e slig ht.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures
between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary , Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags,
with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recom-
mended conditions for baking.
Condition: 125°C/24 h
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following
precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on
the level of 1 M).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock
loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for sto ra g e of co mple te d bo ar d assemblies.
MB95630H Series
Document Number: 002-04627 Rev. *A Page 17 of 102
7.3 Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity
levels are anticipa te d, cons ide r an ti- hu m idit y proc essin g .
(2) Discharge of Static Electricity
When high-voltage char ges exist close to semico nductor devices, discha rges can cause abnormal operation. In
such cases, use anti-static measures or processing to prevent dischar ges.
(3) Corrosive Gase s, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will advers ely affect
the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should
provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances.
If devices begin to smoke or burn, ther e is danger of the release of toxic gases.
Customers considering the use of Cypress products in other special environmental conditions should consult with
sales representatives.
8. Notes On Device Handling
• Prev enting latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither
a medium-withstand voltage pin no r a high-withstand voltage pi n, or if a voltage out of the rating range of power sup-
ply voltage mentioned in “18.1 Absolute Maximum Ratings” of “Electrical Characteristics” is applied to the VCC pin or
the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply curren t increases significantly, which may cause a component to be thermally
destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfu nction may occur when power supply voltage fluctuate s rapidly even though the flu ctuation is within the guar-
anteed operating r ange of the VCC power supply voltage.
As a rule of voltage sta bilization, su ppress voltage flu ctuation so th at the fluctuation in VCC ripple (p-p value) at the
commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluc tuation
rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from sub-
clock mode or stop mode.
MB95630H Series
Document Number: 002-04627 Rev. *A Page 18 of 102
9. Pin Connection
• Treatment of unused pins
If an unused input pin is left unconnected, a component ma y be permanently damage d due to malfunctions or latch-
ups. Always pull up or pull down an unused input pin through a resistor of at least 2 k. Set an unuse d inpu t/output
pin to the output state an d leav e it unco nne cted, or set it to the inp ut s tate an d treat it th e same as an un used input
pin. If there is an unused output pin, leave it unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the
ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the
power supply and ground outside the device. In addition, connect the curr ent supply source to th e VCC pin and the
VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of appro ximately 0.1 µF as a bypass capacitor between the VCC
pin and the VSS pin at a location close to this device.
•DBG pin
Connect the DBG pin to an external pull-up resistor of 2 k or above.
After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released.
The DBG pin beco mes a communication pin in debug mode. Since the actual pull-up resistance de pends on the tool
used and the interconnection length, refer to the tool document when selecting a pull-up resistor.
•RST
pin
Connect the RST pin to an external pull-up resistor of 2 k or above.
To pr event the device from un intentionally entering the reset mode due to noise, minimize the interconne ction length
between a pull-up resistor and the RST pin and that between a pull-up resistor and the VCC pin when designing the
layout of the printed circuit board.
The PF2/RST pin functio ns as the reset input/output pin afte r power-on. In addition, the re set output of the PF2/RST
pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the general-purpose I/O
function can be selected by the RSTEN bit in the SYSC register.
•C pin
Use a ceramic capacitor or a capacito r with equivalent fr equency characteristics. The decoupling capacitor for the
VCC pin must have a capacitance equal to or larger than the capacitanc e of CS. For the connection to a decoupling
capacitor CS, see the diagram below. To prevent the device from uninten tionally entering a mode to which the de vice
is not set to transit due to noise, minimize the distance between the C pin and CS and the distance betwee n CS an d
the VSS pin when designing the layout of a printed circuit board.
• Note on serial communication
In serial communication, reception of wrong data may occur due to noise or other causes. Therefore, design a printed
C
Cs
DBG
RST
• DBG/RST/C pins connection diagram
MB95630H Series
Document Number: 002-04627 Rev. *A Page 19 of 102
circuit board to prevent n oise from occurring. Taking account of the reception of wrong data, take measures such a s
adding a checksum to the end of data in order to detect errors. If an er ror is detected, retransmit the data.
10. Block Diagram
Reset with LVD Dual operation Flash with
security function
(36/20/12/8 Kbyte)
F
2
MC-8FX CPU
RAM (1024/512/256 bytes)
Oscillator
circuit CR oscillator
Clock control
On-chip debug
Wild register
External interrupt
Interrupt controller
LIN-UART
Internal bus
8/16-bit composite timer ch. 0
8/10-bit A/D converter
16-bit reload timer
MPG
16-bit PPG timer
8/16-bit PPG ch. 1
8/16-bit composite timer ch. 1
Waveform sequencer
UART/SIO
I
2
C bus interface ch. 0
8/16-bit PPG ch. 0
8/16-bit PPG ch. 2
Port Port
PF2
*1
/RST
*2
PF1/X1
*2
PF0/X0
*2
(PG2/X1A
*2
)
(PG1/X0A
*2
)
P02/INT02 to P07/INT07
External interrupt
P00/INT00, P01/INT01,
P60/INT08, P61/INT09
C
(P02/SCK)
(P03/SOT)
(P04/SIN)
(P14/UCK0)
(P15/UO0)
(P16/UI0)
(P62
*3
/PPG00), P13/PPG00
(P63
*3
/PPG01), P14/PPG01
(P66
*3
/PPG20), P15/PPG20
(P67
*3
/PPG21), P16/PPG21
(P60
*1
/SDA)
(P61
*1
/SCL)
(P12
*1
/DBG)
(P05/TO00)
(P06/TO01)
P12/EC0, (P04/EC0)
(P00/AN00 to P07/AN07)
(P62
*3
/TO10)
(P63
*3
/TO11)
(P64
*3
/EC1)
Comparator
(P00/CMP0_P)
(P01/CMP0_N)
(P10/CMP0_O)
(P61/TI1)
(P17/TO1)
P62
*3
/OPT0 to P67
*3
/OPT5
P17/SNI0, PG1/SNI1, PG2/SNI2
(P60/DTTI)
(P61/TI1)
(P67
*3
/TRG1)
(P66
*3
/PPG1)
P10/PPG10, (P64
*3
/PPG10)
P11/PPG11, (P65
*3
/PPG11)
Vcc
Vss
*1:
*2:
*3:
P12, P60, P61 and PF2 are N-ch open drain pins.
Software select
P62 to P67 are high-current pins.
Note: Pins in parentheses indicate that those pins are shared among different peripheral functions.
MB95630H Series
Document Number: 002-04627 Rev. *A Page 20 of 102
11. CPU Core
• Memory space
The memory space of the MB95630H Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area,
a data area, and a pr ogram area. The memory space includ es areas intended for specific purposes such as general-
purpose regis t e rs and a vecto r ta ble . The memo ry maps of the MB95630H Series are shown below.
• Memory maps
MB95F633H/F633K MB95F634H/F634KMB95F632H/F632K
I/O area
Access prohibited
RAM 256 bytes
Registers
Access prohibited
Extended I/O area
Access prohibited
Flash memory 4 Kbyte
Flash memory 4 Kbyte
0x0000
0x0080
0x0090
0x0100
0x0190
0x0F80
0x1000
0x2000
0xF000
0xFFFF
I/O area
Access prohibited
0x0000
0x0080
0x0090
I/O area
Access prohibited
0x0000
0x0080
0x0090
Registers
0x0100
0x0200
0x0290
Registers
0x0100
0x0200
Access prohibited
Extended I/O area
Flash memory 4 Kbyte
0x0F80
0x1000
0x2000
Flash memory 4 Kbyte
0x1000
0x2000
Flash memory 4 Kbyte
Extended I/O area
0x0F80
0x1000
Access prohibited
RAM 512 bytes
Access prohibited
Flash memory 8 Kbyte
0xE000
0xFFFF
Access prohibited
0x8000
0x2000
Access prohibited
0xC000
RAM 1024 bytes
Flash memory 16 Kbyte
0x0490
0xFFFF
MB95F636H/F636K
I/O area
Access prohibited
0x0000
0x0080
0x0090
Registers
0x0100
0x0200
Extended I/O area
0x0F80
Access prohibited
RAM 1024 bytes
Flash memory 32 Kbyte
0x0490
0xFFFF
MB95630H Series
Document Number: 002-04627 Rev. *A Page 21 of 102
12. Memory Space
The memory space of the MB95630H Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area,
a data area, and a program area. The memory space includes areas for specific applications such as general-pur-
pose registers and a vector table.
• I/ O ar ea (ad d re sse s: 0x 00 00 to 0x007F)
• This area contains the control registers and data registers for built-in peripheral functions.
• As the I/O area forms part of the memory space, it can be accessed in the same way as the memory. It can also
be accessed at high -speed by usin g dire ct ad dr e ssin g ins tru ctions.
• Extended I/O area (addresses: 0x0F80 to 0x0FFF)
• This area contains the control registers and data registers for built-in peripheral functions.
• As the extended I/O area forms part of the memory space, it can be accessed in the same way as the memory.
• Data area
• Static RAM is incorporated in the data area as the internal data area.
• The internal RAM size varies according to product.
• The RAM area from 0x0090 to 0x00FF can be accessed at high-speed by using direct addressing instructions.
• In MB95F636H/F636K, the area fr om 0x0090 to 0x047F is an extend ed direct addressing area. It can be accessed
at high-speed by direct addressing instructions with a direct bank pointer set.
• In MB95F634H/F634K, the area fr om 0x0090 to 0x047F is an extend ed direct addressing area. It can be accessed
at high-speed by direct addressing instructions with a direct bank pointer set.
• In MB95F633H/F633K, the area fr om 0x0090 to 0x028F is an extend ed direct addressing area. It can be accessed
at high-speed by direct addressing instructions with a direct bank pointer set.
• In MB95F632H/F632K, the area fr om 0x0090 to 0x018F is an extend ed direct addressing area. It can be accessed
at high-speed by direct addressing instructions with a direct bank pointer set.
• In MB95F633H/F633K/F634H/F634K/F636H/F636K, the area from 0x0100 to 0x01FF ca n be used as a gener al-
purpose register area.
• In MB95F632H/F632K, the area from 0x0100 to 0x018F can be used as a general-purpose register area.
• Program area
• The Flash memory is incorporated in the program area as the internal program area.
• The Flash memory size varies according to product.
• The area from 0xFFC0 to 0xFFFF is used as the vector table.
• The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register.
MB95630H Series
Document Number: 002-04627 Rev. *A Page 22 of 102
• Memory space map
Direct addressing area
Extended direct addressing area
I/O area
Access prohibited
0x0000
0x0080
0x0090
Registers
(General-purpose register area)
0x0100
0x0200
0x047F
Vector table area
Extended I/O area
0x0F80
0x0FFF
0x1000
Access prohibited
Program area
Data area
0x048F
0x0490
0xFFFF
0xFFC0
MB95630H Series
Document Number: 002-04627 Rev. *A Page 23 of 102
13. Areas For Specific Applications
The general-purpose register area and vector table area are used for the specific applications.
• General-purpose register area (Addresses: 0x0100 to 0x01FF*1)
• This area contains the auxiliary registers used for 8-bit arithmetic operations, transfer, etc.
• As this area forms part of the RAM area, it can also be used as conventional RAM.
• When the area is used as general- purpose re gisters, general-pu rpose register ad dressing enables hig h-speed ac-
cess with short instructions.
• Non-volatile register data area (Addresses: 0xFFBB to 0xFFBF)
• The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register . For details, refer to “CHAPTER
26 NON-VOLATILE REGISTER (NVR) INTERFACE” in “New 8FX MB95630H Series Hardware Manual”.
• Vector table area (Addresses: 0xFFC0 to 0xFFFF)
• This area is used as the vector table for vector call instructions (CALLV), interrupts, and resets.
• The top of the Flash memory area is alloca ted to the vector ta ble area. Th e start address of a ser vice routine is set
to an address in the vector table in the form of data.
“Interrupt Source Table” lists the vector table addresses corresponding to vector call instructions, interrupts, and re-
sets.
For details, refer to “CHAPTER 4 RESET”, “CHAPTER 5 INTERRUPTS” and “A.2 Special Instruction ■Special In-
struction ● CALLV #vct” in “New 8FX MB95630H Series Hardware Manual”.
• Direct bank pointer and access area
*1:Due to the memory size limit, the available access area is up to “0x018F” in MB95F632H/F632K.
*2:Due to the memory size limit, the available access area is up to “0x028F” in MB95F633H/F633K.
Direct bank pointer (DP[2:0]) Operand-specified dir Access area
0bXXX (It does not affect mapping.) 0x0000 to 0x007F 0x0000 to 0x007F
0b000 (Initial value) 0x0090 to 0x00FF 0x0090 to 0x00FF
0b001
0x0080 to 0x00FF
0x0100 to 0x017F
0b010 0x0180 to 0x01FF*1
0b011 0x0200 to 0x027F
0b100 0x0280 to 0x02FF*2
0b101 0x0300 to 0x037F
0b110 0x0380 to 0x03FF
0b111 0x0400 to 0x047F
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Document Number: 002-04627 Rev. *A Page 24 of 102
14. I/O Map
Address Register
abbreviation Register name R/W Initial value
0x0000 PDR0 Port 0 data register R/W 0b00000000
0x0001 DDR0 Port 0 direction register R/W 0b00000000
0x0002 PDR1 Port 1 data register R/W 0b00000000
0x0003 DDR1 Port 1 direction register R/W 0b00000000
0x0004 — (Disabled) — —
0x0005 WATR Oscillation stabilization wait time setting register R/W 0b11111111
0x0006 PLLC PLL control register R/W 0b000X0000
0x0007 SYCC System clock control register R/W 0bXXX11011
0x0008 STBC Standby control register R/W 0b00000000
0x0009 RSRR Reset source register R/W 0b000XXXXX
0x000A TBTC Time-base timer control registe r R/W 0b00000000
0x000B WPCR Watch prescaler control register R/W 0b00000000
0x000C WDTC Watchdog timer control register R/W 0b00XX0000
0x000D SYCC2 System clock control register 2 R/W 0bXXXX0011
0x000E STBC2 Standby control register 2 R/W 0b00000000
0x000F
to
0x0015 — (Disabled) — —
0x0016 PDR6 Port 6 data register R/W 0b00000000
0x0017 DDR6 Port 6 direction register R/W 0b00000000
0x0018
to
0x0027 — (Disabled) — —
0x0028 PDRF Port F data register R/W 0b00000000
0x0029 DDRF Port F direction register R/W 0b00000000
0x002A PDRG Port G data register R/W 0b00000000
0x002B DDRG Port G direction register R/W 0b00000000
0x002C PUL0 Port 0 pull-up register R/W 0b00000000
0x002D PUL1 Port 1 pull-up register R/W 0b00000000
0x002E
to
0x0032 — (Disabled) — —
0x0033 PUL6 Port 6 pull-up register R/W 0b00000000
0x0034 — (Disabled) — —
0x0035 PULG Port G pull-up register R/W 0b00000000
0x0036 T01CR1 8/16-bit composite timer 01 status control register 1 R/W 0b00000000
MB95630H Series
Document Number: 002-04627 Rev. *A Page 25 of 102
Address Register
abbreviation Register name R/W Initial value
0x0037 T00CR1 8/16-bit composite timer 00 status control register 1 R/W 0b00000000
0x0038 T11CR1 8/16-bit composite timer 11 status control register 1 R/W 0b00000000
0x0039 T10CR1 8/16-bit composite timer 10 status control register 1 R/W 0b00000000
0x003A PC01 8/16-bit PPG timer 01 control register R/W 0b00000000
0x003B PC00 8/16-bit PPG timer 00 control register R/W 0b00000000
0x003C PC11 8/16-bit PPG timer 11 control register R/W 0b00000000
0x003D PC10 8/16-bit PPG timer 10 control register R/W 0b00000000
0x003E PC21 8/16-bit PPG timer 21 control register R/W 0b00000000
0x003F PC20 8/16-bit PPG timer 20 control register R/W 0b00000000
0x0040 TMCSRH1 16-bit reload timer control status register (upper) R/W 0b00000000
0x0041 TMCSRL1 16-bit reload timer control status register (lower) R/W 0b00000000
0x0042 CMR0C Comparator control register R/W 0b00000101
0x0043 — (Disabled) — —
0x0044 PCNTH1 16-bit PPG status control register (upper) R/W 0b00000000
0x0045 PCNTL1 16-bit PPG status control register (lower) R/W 0b00000000
0x0046,
0x0047 — (Disabled) — —
0x0048 EIC00 External interrupt circuit control register ch. 0/ch. 1 R/W 0b00000000
0x0049 EIC10 External interrupt circuit control register ch. 2/ch. 3 R/W 0b00000000
0x004A EIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 0b00000000
0x004B EIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 0b00000000
0x004C EIC01 External interrupt circuit control register ch. 8/ch. 9 R/W 0b00000000
0x004D — (Disabled) — —
0x004E LVDR LVD reset voltage selection ID register R/W 0b00000000
0x004F — (Disabled) — —
0x0050 SCR LIN-UART serial control register R/W 0b00000000
0x0051 SMR LIN-UART serial mode register R/W 0b00000000
0x0052 SSR LIN-UART serial status register R/W 0b00001000
0x0053 RDR LIN-UART receive data register R/W 0b00000000
TDR LIN-UART transmit data register
0x0054 ESCR LIN-UART extended status control register R/W 0b00000100
0x0055 ECCR LIN-UART extended communication control register R/W 0b000000XX
0x0056 SMC10 UART/SIO serial mode control register 1 R/W 0b00000000
0x0057 SMC20 UART/SIO serial mode control register 2 R/W 0b00100000
0x0058 SSR0 UART/SIO serial status an d data register R/W 0b00000001
0x0059 TDR0 UART/SIO serial output data register R/W 0b00000000
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Address Register
abbreviation Register name R/W Initial value
0x005A RDR0 UART/SIO serial input data register R 0b00000000
0x005B
to
0x005F — (Disabled) — —
0x0060 IBCR00 I2C bus control register 0 ch. 0 R/W 0b00000000
0x0061 IBCR10 I2C bus control register 1 ch. 0 R/W 0b00000000
0x0062 IBSR0 I2C bus status register ch. 0 R/W 0b00000000
0x0063 IDDR0 I2C data register ch. 0 R/W 0b00000000
0x0064 IAAR0 I2C address register ch. 0 R/W 0b00000000
0x0065 ICCR0 I2C clock control register ch. 0 R/W 0b00000000
0x0066 OPCUR 16-bit MPG output control register (upper) R/W 0b00000000
0x0067 OPCLR 16-bit MPG output control register (lower) R/W 0b00000000
0x0068 IPCUR 16-bit MPG input control register (upper) R/W 0b00000000
0x0069 IPCLR 16-bit MPG input control registe r (lower) R/W 0b00000000
0x006A NCCR 16-bit MPG noise cancellation control register R/W 0b00000000
0x006B TCSR 16-bit MPG timer control status register R/W 0b00000000
0x006C ADC1 8/10-bit A/D converter control register 1 R/W 0b00000000
0x006D ADC2 8/10-bit A/D converter control register 2 R/W 0b00000000
0x006E ADDH 8/10-bit A/D converter data register (upper) R/W 0b00000000
0x006F ADDL 8/10-bit A/D converter data re gis te r (low er ) R/W 0b00000000
0x0070 — (Disabled) — —
0x0071 FSR2 Flash memory status register 2 R/W 0b00000000
0x0072 FSR Flash memory status register R/W 0b000X0000
0x0073 SWRE0 Flash memo ry sector write control register 0 R/W 0b00000000
0x0074 FSR3 Flash memory status register 3 R 0b000XXXXX
0x0075 FSR4 Flash memory status register 4 R/W 0b00000000
0x0076 WREN Wild register address compare enable register R/W 0b00000000
0x0077 WROR Wild register data test setting register R/W 0b00000000
0x0078 — Mirror of register bank pointer (RP) and direct bank
pointer (DP) ——
0x0079 ILR0 Interrupt level setting register 0 R/W 0b11111111
0x007A ILR1 Interrupt level setting register 1 R/W 0b11111111
0x007B ILR2 Interrupt level setting register 2 R/W 0b11111111
0x007C ILR3 Interrupt level setting register 3 R/W 0b11111111
0x007D ILR4 Interrupt level setting register 4 R/W 0b11111111
0x007E ILR5 Interrupt level setting register 5 R/W 0b11111111
0x007F — (Disabled) — —
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Address Register
abbreviation Register name R/W Initial value
0x0F80 WRARH0 Wild register address setting register (upper) ch . 0 R/W 0b00000000
0x0F81 WRARL0 Wild register address setting register (lower) ch. 0 R/W 0b00000000
0x0F82 WRDR0 Wild register data setting register ch. 0 R/W 0b00000000
0x0F83 WRARH1 Wild register address setting register (upper) ch . 1 R/W 0b00000000
0x0F84 WRARL1 Wild register address setting register (lower) ch. 1 R/W 0b00000000
0x0F85 WRDR1 Wild register data setting register ch. 1 R/W 0b00000000
0x0F86 WRARH2 Wild register address setting register (upper) ch . 2 R/W 0b00000000
0x0F87 WRARL2 Wild register address setting register (lower) ch. 2 R/W 0b00000000
0x0F88 WRDR2 Wild register data setting register ch. 2 R/W 0b00000000
0x0F89
to
0x0F91 — (Disabled) — —
0x0F92 T01CR0 8/16-bit composite timer 01 status control register 0 R/W 0b00000000
0x0F93 T00CR0 8/16-bit composite timer 00 status control register 0 R/W 0b00000000
0x0F94 T01DR 8/16-bit composite timer 01 data register R/W 0b00000000
0x0F95 T00DR 8/16-bit composite timer 00 data register R/W 0b00000000
0x0F96 TMCR0 8/16-b it co mp o site time r 00 /0 1 tim er mo de con tro l
register R/W 0b00000000
0x0F97 T11CR0 8/16-bit composite timer 11 status control register 0 R/W 0b00000000
0x0F98 T10CR0 8/16-bit composite timer 10 status control register 0 R/W 0b00000000
0x0F99 T11DR 8/16-bit composite timer 11 data register R/W 0b00000000
0x0F9A T10DR 8/16-bit composite timer 10 data register R/W 0b00000000
0x0F9B TMCR1 8/16-bit composite timer 10/11 timer mode control
register R/W 0b00000000
0x0F9C PPS01 8/16-bit PPG01 cycle setting buffer register R/W 0b11111111
0x0F9D PPS00 8/16-bit PPG00 cycle setting buffer register R/W 0b11111111
0x0F9E PDS01 8/16-bit PPG01 duty setting buffer register R/W 0b11111111
0x0F9F PDS00 8/16-bit PPG00 duty setting buffer register R/W 0b11111111
0x0FA0 PPS11 8/16-bit PPG11 cycle setting buffer register R/W 0b11111111
0x0FA1 PPS10 8/16-bit PPG10 cycle setting buffer register R/W 0b11111111
0x0FA2 PDS11 8/16-bit PPG11 duty setting buffer register R/W 0b11111111
0x0FA3 PDS10 8/16-bit PPG10 duty setting buffer register R/W 0b11111111
0x0FA4 PPGS 8/16-bit PPG start register R/W 0b00000000
0x0FA5 REVC 8/16-bit PPG output inversion register R/W 0b00000000
0x0FA6 PPS21 8/16-bit PPG21 cycle setting buffer register R/W 0b11111111
0x0FA7 PPS20 8/16-bit PPG20 cycle setting buffer register R/W 0b11111111
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Address Register
abbreviation Register name R/W Initial value
0x0FA8 TMRH1 16-bit reload timer timer register (upper) R/W 0b00000000
TMRLRH1 16-bit reload timer reload register (upper)
0x0FA9 TMRL1 16-bit reload timer timer register (lower) R/W 0b00000000
TMRLRL1 16-bit reload timer reload register (lower)
0x0FAA PDS21 8/16-bit PPG21 duty setting buffer register R/W 0b11111111
0x0FAB PDS20 8/16-bit PPG20 duty setting buffer register R/W 0b11111111
0x0FAC
to
0x0FAF — (Disabled) — —
0x0FB0 PDCRH1 16-bit PPG downcounter register (upper) R 0b00000000
0x0FB1 PDCRL1 16-b it PPG downcounter register (lower) R 0b00 000000
0x0FB2 PCSRH1 16-bit PPG cycle setting buffer register (upper) R/W 0b11111111
0x0FB3 PCSRL1 16-bit PPG cycle setting buffer register (lower) R/W 0b11111111
0x0FB4 PDUTH1 16-bit PPG duty setting buffer register (upper) R/W 0b11111111
0x0FB5 PDUTL1 16-bit PPG duty setting buffer register (lower) R/W 0b11111111
0x0FB6
to
0x0FBB — (Disabled) — —
0x0FBC BGR1 LIN-UART baud rate generator register 1 R/W 0b00000000
0x0FBD BGR0 LIN-UART baud rate generator register 0 R/W 0b00000000
0x0FBE PSSR0 UART/SIO dedicated baud rate generator prescaler
select register R/W 0b00000000
0x0FBF BRSR0 UART/SIO dedicated baud rate generator ba ud rate
setting register R/W 0b00000000
0x0FC0
to
0x0FC2 — (Disabled) — —
0x0FC3 AIDRL A/D input disable register (lower) R/W 0b00000000
0x0FC4 OPDBRH0 16-bit MPG output data buffer register (upper) ch. 0 R/W 0b00000000
0x0FC5 OPDBRL0 16-bit MPG output data buffer register (lower) ch. 0 R/W 0b00000000
0x0FC6 OPDBRH1 16-bit MPG output data buffer register (upper) ch. 1 R/W 0b00000000
0x0FC7 OPDBRL1 16-bit MPG output data buffer register (lower) ch. 1 R/W 0b00000000
0x0FC8 OPDBRH2 16-bit MPG output data buffer register (upper) ch. 2 R/W 0b00000000
0x0FC9 OPDBRL2 16-bit MPG output data buffer register (lower) ch. 2 R/W 0b00000000
0x0FCA OPDBRH3 16-bit MPG output data buffer register (upper) ch. 3 R/W 0b00000000
0x0FCB OP DBRL3 16-bit MPG outp ut dat a bu ffer register (l ow er ) ch . 3 R/W 0b00000000
0x0FCC OPDBRH4 16-bit MPG output data buffer register (upper) ch. 4 R/W 0b00000000
0x0FCD OPDBRL4 16-bit MPG output data buffer register (lower) ch. 4 R/W 0b00000000
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Address Register
abbreviation Register name R/W Initial value
0x0FCE OPDBRH5 16-bit MPG output data buffer register (upper) ch. 5 R/W 0b00000000
0x0FCF OPDBRL5 16-bit MPG output data buffer register (lower) ch. 5 R/W 0b00000000
0x0FD0 OPDBRH6 16-bit MPG output data buffer register (upper) ch. 6 R/W 0b00000000
0x0FD1 OPDBRL6 16-bit MPG output data buffer register (lower) ch. 6 R/W 0b00000000
0x0FD2 OPDBRH7 16-bit MPG output data buffer register (upper) ch. 7 R/W 0b00000000
0x0FD3 OPDBRL7 16-bit MPG output data buffer register (lower) ch. 7 R/W 0b00000000
0x0FD4 OPDBRH8 16-bit MPG output data buffer register (upper) ch. 8 R/W 0b00000000
0x0FD5 OPDBRL8 16-bit MPG output data buffer register (lower) ch. 8 R/W 0b00000000
0x0FD6 OPDBRH9 16-bit MPG output data buffer register (upper) ch. 9 R/W 0b00000000
0x0FD7 OPDBRL9 16-bit MPG output data buffer register (lower) ch. 9 R/W 0b00000000
0x0FD8 OPDBRHA 16-bit MPG output data buffer register (upper) ch. A R/W 0b00000000
0x0FD9 OPDBRLA 16-bit MPG output data buffer register (lower) ch. A R/W 0b00000000
0x0FDA OPDBRHB 16-bit MPG output data buffer register (upper) ch. B R/W 0b00000000
0x0FDB OPDBR LB 16-bit MPG output dat a buffer registe r (lower) ch. B R/W 0b 0 00 0 0000
0x0FDC OPDUR 16-bit MPG output data register (upper) R 0b0000XXXX
0x0FDD OPDLR 16-bit MPG output data register (lower) R 0bXXXXXXXX
0x0FDE CPCUR 16-bit MPG compare clear register (upper) R/W 0bXXXXXXXX
0x0FDF CPCLR 16-bit MPG compare clear register (lower) R/W 0bXXXXXXXX
0x0FE0,
0x0FE1 — (Disabled) — —
0x0FE2 TMBUR 16-bit MPG timer buffer register (upper) R 0bXXXXXXXX
0x0FE3 TMBLR 16-bit MPG timer buffer register (lower) R 0bXXXXXXXX
0x0FE4 CRTH Main CR clock trimming register (upper) R/W 0b000XXXXX
0x0FE5 CRTL Main CR clock trimming register (lower) R/W 0b000XXXXX
0x0FE6 — (Disabled) — —
0x0FE7 CRTDA Main CR clock temperature depende nt adjustment
register R/W 0b000XXXXX
0x0FE8 SYSC System configuration register R/W 0b1100 00 11
0x0FE9 CMCR Clock monitoring control register R/W 0b00000000
0x0FEA CMDR Clock monitoring data register R 0b00000000
0x0FEB WDTH Watchdog timer selection ID register (upper) R 0bXXXXXXXX
0x0FEC WDTL Watchdog timer selection ID register (lower) R 0bXXXXXXXX
0x0FED,
0x0FEE — (Disabled) — —
0x0FEF WICR Interrupt pin selection circuit control register R/W 0b01000 000
0x0FF0
to
0x0FFF — (Disabled) — —
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• R/W access symbols
• Initial value symbols
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned.
15. I/O Ports
• L ist of po rt reg iste rs
R/W : Readable/writable (The read value is the same as the write value.)
R, RM/W : Readable/writable (The read value is different from the write value. The write value is read by the read-
modify-write (RMW) type of instructio n.)
R/W : Readable/Writable
R : Read only
0 : The initial value of this bit is “0”.
1 : The initial value of this bit is “1”.
X : The initial value of this bit is undefined.
Register name Read/Write Initial value
Port 0 data register PDR0 R, RM/W 0b00000000
Port 0 direction register DDR0 R/W 0b00000000
Port 1 data register PDR1 R, RM/W 0b00000000
Port 1 direction register DDR1 R/W 0b00000000
Port 6 data register PDR6 R, RM/W 0b00000000
Port 6 direction register DDR6 R/W 0b00000000
Port F data register PDRF R, RM/W 0b00000000
Port F direction register DDRF R/W 0b00000000
Port G data register PDRG R, RM/W 0b00000000
Port G direction register DDRG R/W 0b00000000
Port 0 pull-up register PUL0 R/W 0b00000000
Port 1 pull-up register PUL1 R/W 0b00000000
Port 6 pull-up register PUL6 R/W 0b00000000
Port G pull-up register PULG R/W 0b00000000
A/D input disable register (lower) AIDRL R/W 0b00000000
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15.1 Port 0
Port 0 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95630H Series Hardware Manual”.
15.1.1 Port 0 configuration
Port 0 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 0 data register (PDR0)
• Port 0 direction register (DDR0)
• Port 0 pull-up register (PUL0)
• A/D input disable register (lo w er) (AIDRL)
15.1.2 Block diagrams of port 0
• P00/INT00/AN00/CMP0_P pin
This pin has the following pe ripheral functions:
• External interrupt circuit input pin (INT00)
• 8/10-bit A/D converter analog input pin (AN00)
• Comparator non-inverting analog input (positive inpu t) pin (CMP0_P)
• P01/INT01/AN01/CMP0_N pin
This pin has the following pe ripheral functions:
• External interrupt circuit input pin (INT01)
• 8/10-bit A/D converter analog input pin (AN01)
• Comparator inverting analog input (negative input) pin (CMP0_N)
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• Block diagram of P00/INT00/AN00/CMP0_P an d P01/INT01/AN01/CMP0_N
PDR0 Pin
PDR0 read
PDR0 write
Executing bit manipulation instruction
Internal bus
DDR0 read
DDR0 write
PUL0 read
PUL0 write
AIDRL read
AIDRL write
DDR0
PUL0
AIDRL
0
1
Stop mode, watch mode (SPL = 1)
Comparator analog input
Comparator analog input disable
Peripheral function input
Peripheral function input enable
(INT00 and INT01)
A/D analog input
Hysteresis
Pull-up
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• P02/INT02/AN02/SCK pin
This pin has the following pe ripheral functions:
• External interrupt circuit input pin (INT02)
• 8/10-bit A/D converter analog input pin (AN02)
• LIN-UART clock I/O pin (SCK)
• P03/INT03/AN03/SOT pin
This pin has the following pe ripheral functions:
• External interrupt circuit input pin (INT03)
• 8/10-bit A/D converter analog input pin (AN03)
• LIN-UART data output pin (SOT)
• P05/INT05/AN05/TO00 pin
This pin has the following pe ripheral functions:
• External interrupt circuit input pin (INT05)
• 8/10-bit A/D converter analog input pin (AN05)
• 8/16-bit composite timer ch. 0 output pin (TO00)
• P06/INT06/AN06/TO01 pin
This pin has the following pe ripheral functions:
• External interrupt circuit input pin (INT06)
• 8/10-bit A/D converter analog input pin (AN06)
• 8/16-bit composite timer ch. 0 output pin (TO01)
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• Blo ck dia gr a m of P02/INT 0 2/AN02/SCK, P03/IN T0 3 /AN0 3 /SOT, P05/INT05/AN05/TO00 and P06/INT06/AN06/TO01
PDR0 Pin
PDR0 read
PDR0 write
Executing bit manipulation instruction
DDR0 read
DDR0 write
PUL0 read
PUL0 write
AIDRL read
AIDRL write
DDR0
PUL0
AIDRL
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable
(INT02, INT03, INT05 and INT06)
Peripheral function output enable
Peripheral function output
A/D analog input
Hysteresis
Pull-up
Internal bus
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• P04/INT04/AN04/SIN/EC0 pin
This pin has the following pe ripheral functions:
• External interrupt circuit input pin (INT04)
• 8/10-bit A/D converter analog input pin (AN04)
• LIN-UART data input pin (SIN)
• 8/16-bit composite timer ch. 0 clock input pin (EC0)
• Blo ck dia gr a m of P04/INT 0 4/AN04/SIN/EC0
PDR0 Pin
PDR0 read
PDR0 write
Executing bit manipulation instruction
DDR0 read
DDR0 write
PUL0 read
PUL0 write
AIDRL read
AIDRL write
DDR0
PUL0
AIDRL
0
1
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable (INT04)
A/D analog input
CMOS
Pull-up
Internal bus
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• P07/INT07/AN07 pin
This pin has the following pe ripheral functions:
• External interrupt circuit input pin (INT07)
• 8/10-bit A/D converter analog input pin (AN07)
• Blo ck dia gr a m of P07/ INT 0 7/A N07
PDR0 Pin
PDR0 read
PDR0 write
Executing bit manipulation instruction
DDR0 read
DDR0 write
PUL0 read
PUL0 write
AIDRL read
AIDRL write
DDR0
PUL0
AIDRL
0
1
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable (INT07)
A/D analog input
Hysteresis
Pull-up
Internal bus
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15.1.3 Port 0 registers
• Port 0 register functions
• Correspondence between registers and pins for port 0
15.1.4 Port 0 operations
• O pe ra tio n as an output port
• A pin becomes an output port if the bit in the DDR0 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such periphe ral functions.
• When a pin is used as an output port, it outputs the value of the PDR0 register to external pins.
• If data is written to the PDR0 register, the value is stored in the output latch and is output to the pin set a s an output
port as it is.
• Reading the PDR0 register returns the PDR0 register value.
• Operation as an input port
• A pin beco mes an input port if the bit in the DDR0 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such periphe ral functions.
• When using a pin shared with the analog input functio n as an input port, set the corresponding bit in the A/D input
disable register (lower) (AIDRL) to “1”.
• If data is written to the PDR0 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR0 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR0 register, the PDR0 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripher al function corresponding to that pin.
• The pin value can be read from the PDR0 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can b e read by the r ead operation on the PDR0 register. However , if the read-
modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 regi st er value is returned.
Register
abbreviation Data Read Read by read-modify-write
(RMW) instruction Write
PDR0 0 Pin state is “L” level. PDR0 value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDR0 value is “1”. As output port, outputs “H” level.
DDR0 0 Port input enabled
1 Port output enabled
PUL0 0 Pull-up disabled
1 Pull-up enabled
AIDRL 0 Analog input enabled
1 Port input enabled
Correspondence bet ween related register bits and pins
Pin name P07 P06 P05 P04 P03 P02 P01 P00
PDR0
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DDR0
PUL0
AIDRL
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• Operation as a peripheral function input pin
• To set a pin as an input port, set the b it in the DDR0 re gister corres ponding to the inpu t pin of a peri pheral function
to “0”.
• When using a pin shared with the analog input function as another peripheral function input pin, configure it as an
input port by setting the bit in the AIDRL register corresponding to that pin to “1”.
• Reading the PDR0 register returns the pin value, regardless o f whether the perip heral func tion uses th at pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0
register value is returned.
• O pe ra tio n at rese t
If the CPU is reset, all bits in the DDR0 register are initialized to “0” and port input is enabled. As for a pin shared with
analog input, its port input is disabled because the AIDRL register is initialized to “0”.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR0 reg-
ister value. The input of that pin is locked to “L” level a nd blocked in orde r to prevent le aks due to input open . How-
ever, if the interrupt input is enabled for the external interrupt (INT00 to INT07), the input is enabled and not
blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation as an analog input pin
• Set the bit in the DDR0 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin
in the AIDRL register to “0”.
• For a pin shared with other peripheral functions, disabl e the output of such peripheral f unctions. In addition, set the
corresponding bit in the PUL0 register to “0”.
• Operation as an external interrupt input pin
• Set the bit in the DDR0 register corresponding to the extern al interrupt input pin to “0”.
• For a pin shared with other peripheral functions, disable the output of such periphe ral functions.
• The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt,
disable the external interrupt function corresponding to that pin.
• Operation of the pull-up register
Setting the bit in th e PUL0 reg ister to “1 ” makes th e pu ll-u p r esistor be inter nal ly con nected to th e pin. Whe n the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL0 register.
• Operation as a comparator input pin (only for P00 and P01)
• Set the bit in the AIDRL register corresponding to the comparator input pin to “0”.
• Regardless of the value of the PDR0 register and that o f th e DDR0 regist er, if the comparator analog inpu t e nable
bit in the comparator control register (CMR0C:VCID) is set to “0”, the comparator input function is enabled.
• To disable the comparator input function, set the VCID bit to “1”.
• For details of the comparator, refer to “CHAPTER 27 COMPARATOR” in “New 8FX MB95630H Series Hardware
Manual”.
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15.2 Port 1
Port 1 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95630H Series Hardware Manual”.
15.2.1 Port 1 configuration
Port 1 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 1 data register (PDR1)
• Port 1 direction register (DDR1)
• Port 1 pull-up register (PUL1)
15.2.2 Block diagrams of port 1
• P10/PPG10/CMP0_O pin
This pin has the following pe ripheral functions:
• 8/16-bit PPG ch. 1 output pin (PPG10)
• Comparator digital output pin (CMP0_O)
• P11/PPG11 pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 1 output pin (PPG11)
• P13/PPG00 pin
This pin has the following peripheral function:
• 8/16-bit PPG ch. 0 output pin (PPG00)
• P15/UO0/PPG20 pin
This pin has the following pe ripheral functions:
• UART/SIO ch. 0 data output pin (UO0)
• 8/16-bit PPG ch. 2 output pin (PPG20)
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• Blo ck dia gra m of P10/ PPG1 0 /CMP0 _O , P11/PPG11, P13/PPG00 and P15/UO0/PPG20
PDR1 Pin
PDR1 read
PDR1 write
Executing bit manipulation instruction
DDR1 read
DDR1 write
PUL1 read
PUL1 write
DDR1
PUL1
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
Internal bus
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• P12/DBG/EC0 pin
This pin has the following pe ripheral functions:
• DBG input pin (DBG)
• 8/16-bit composite timer ch. 0 clock input pin (EC0)
• Blo ck dia gra m of P12/ DBG /EC0
• P14/UCK0/PPG01 pin
This pin has the following pe ripheral functions:
• UART/SIO ch. 0 clock I/O pin (UCK0)
• 8/16-bit PPG ch. 0 output pin (PPG01)
PDR1 Pin
PDR1 read
PDR1 write
Executing bit manipulation instruction
DDR1 read
DDR1 write
DDR1
0
1
Stop mode, watch mode (SPL = 1)
OD
Hysteresis
Internal bus
Peripheral function input
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• Blo ck dia gra m of P14/ UCK0/PPG 0 1
PDR1 Pin
PDR1 read
PDR1 write
Executing bit manipulation instruction
DDR1 read
DDR1 write
PUL1 read
PUL1 write
DDR1
PUL1
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
Internal bus
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• P16/UI0/PPG21 pin
This pin has the following pe ripheral functions:
• UART/SIO ch. 0 data input pin (UI0)
• 8/16-bit PPG ch. 2 output pin (PPG21)
• Blo ck dia gra m of P16/ UI0 /PPG 21
• P17/TO1/SNI0 pin
This pin has the following pe ripheral functions:
• 16-bit reload timer ch. 1 output pin (TO1)
• Trigger input pin for the position detection function of the MPG waveform sequencer (SNI0)
PDR1 Pin
PDR1 read
PDR1 write
Executing bit manipulation instruction
DDR1 read
DDR1 write
PUL1 read
PUL1 write
DDR1
PUL1
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
CMOS
Pull-up
Internal bus
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• Blo ck dia gra m of P17/ TO1/SNI0
PDR1 Pin
PDR1 read
PDR1 write
Executing bit manipulation instruction
DDR1 read
DDR1 write
PUL1 read
PUL1 write
DDR1
PUL1
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function output enable
Peripheral function input
Peripheral function output
Hysteresis
Pull-up
Internal bus
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15.2.3 Port 1 registers
• Port 1 register functions
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
• Correspondence between registers and pins for port 1
*: Though P12 has no pull-up function, bit2 in the PUL1 register can still be accessed. The operation of P12 is not af-
fected by the setting of bit2 in the PUL1 register.
15.2.4 Port 1 operations
• O pe ra tio n as an output port
• A pin becomes an output port if the bit in the DDR1 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such periphe ral functions.
• When a pin is used as an output port, it outputs the value of the PDR1 register to external pins.
• If data is written to the PDR1 register, the value is stored in the output latch and is output to the pin set a s an output
port as it is.
• Reading the PDR1 register returns the PDR1 register value.
• Operation as an input port
• A pin beco mes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such periphe ral functions.
• If data is written to the PDR1 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR1 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR1 register, the PDR1 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripher al function corresponding to that pin.
• The pin value can be read from the PDR1 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can b e read by the r ead operation on the PDR1 register. However , if the read-
modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 regi st er value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the b it in the DDR1 re gister corres ponding to the inpu t pin of a peri pheral function
Register
abbreviation Data Read Read by read-modify-write
(RMW) instruction Write
PDR1 0 Pin state is “L” level. PDR1 value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDR1 value is “1”. As output port, outputs “H” level.*
DDR1 0 Port input enabled
1 Port output enabled
PUL1 0 Pull-up disabled
1 Pull-up enabled
Correspondence bet ween related register bits and pins
Pin name P17 P16 P15 P14 P13 P12 P11 P10
PDR1 bit7 bit6 bit5 bit4 bit3 bit2* bit1 bit0DDR1
PUL1
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to “0”.
• Reading the PDR1 register returns the pin value, regardless o f whether the perip heral func tion uses th at pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1
register value is returned.
• O pe ra tio n at rese t
If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR1 reg-
ister value. The input of that pin is locked to “L” level a nd blocked in orde r to prevent le aks due to input open . How-
ever, if the interrupt input of P14/UCK0 and P16/UI0 is enabled by the external interrupt control register ch. 0
(EIC00) of the external inte rrupt circuit a nd the interrupt p in selection circuit control r egister (WICR) of the interrup t
pin selection circuit, the input is enabled and is not blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in th e PUL1 reg ister to “1 ” makes th e pu ll-u p r esistor be inter nal ly con nected to th e pin. Whe n the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL1 register.
15.3 Port 6
Port 6 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95630H Series Hardware Manual”.
15.3.1 Port 6 configuration
Port 6 is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port 6 data register (PDR6)
• Port 6 direction register (DDR6)
• Port 6 pull-up register (PUL6)
15.3.2 Block diagrams of port 6
• P60/INT08/SDA/DTTI pin
This pin has the following pe ripheral functions:
• External interrupt circuit input pin (INT08)
•I
2C bus interface ch. 0 data I/O pin (SDA)
• MPG waveform sequencer input pin (DTTI)
• P61/INT09/SCL/TI1 pin
This pin has the following pe ripheral functions:
• External interrupt circuit input pin (INT09)
•I
2C bus interface ch. 0 clock I/O pin (SCL)
• 16-bit reload timer ch. 1 input pin (TI1)
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• Blo ck dia gr a m of P60/ INT0 8/SDA/DTTI and P61/ INT 0 9/S C L/ T I1
• P62/TO10/PPG00/OPT0 pin
This pin has the following pe ripheral functions:
• 8/16-bit composite timer ch. 1 output pin (TO10)
• 8/16-bit PPG ch. 0 output pin (PPG00)
• MPG waveform sequencer output pin (OPT0)
• P63/TO11/PPG01/OPT1 pin
This pin has the following pe ripheral functions:
• 8/16-bit composite timer ch. 1 output pin (TO11)
• 8/16-bit PPG ch. 0 output pin (PPG01)
• MPG waveform sequencer output pin (OPT1)
• P65/PPG11/OPT3 pin
This pin has the following pe ripheral functions:
• 8/16-bit PPG ch. 1 output pin (PPG11)
• MPG waveform sequencer output pin (OPT3)
• P66/PPG20/PPG1/OPT4 pin
This pin has the following pe ripheral functions:
• 8/16-bit PPG ch. 2 output pin (PPG20)
• 16-bit PPG timer ch. 1 output pin (PPG1)
• MPG waveform sequencer output pin (OPT4)
• Block diagram of P62/TO10/PPG00/OPT0, P6 3/TO11/PPG01/OPT1, P65/PPG11/OPT3 and
PDR6
PDR6 read
PDR6 write
Executing bit manipulation instruction
DDR6 read
DDR6 write
DDR6
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable
(INT08 and INT09)
Peripheral function output enable
Peripheral function output
CMOS
Pin
OD
Internal bus
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P66/PPG20/PPG1/OPT4
• P6 4/ EC1 /PPG 10 /O PT2 pin
This pin has the following pe ripheral functions:
• 8/16-bit composite timer ch. 1 clock input pin (EC1)
• 8/16-bit PPG ch. 1 output pin (PPG10)
• MPG waveform sequencer output pin (OPT2)
• P67/PPG21/TRG1/OPT5 pin
This pin has the following pe ripheral functions:
• 8/16-bit PPG ch. 2 output pin (PPG21)
• 16-bit PPG timer ch. 1 trigger input pin (TRG1)
• MPG waveform sequencer output pin (OPT5)
PDR6 Pin
PDR6 read
PDR6 write
Executing bit manipulation instruction
DDR6 read
DDR6 write
PUL6 read
PUL6 write
DDR6
PUL6
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
Internal bus
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• Blo ck dia gra m of P64/ EC1 /PPG 10 /O PT 2 and P6 7/PPG21/TRG1/O PT 5
15.3.3 Port 6 registers
• Port 6 register functions
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
• Correspondence between registers and pins for port 6
Register
abbreviation Data Read Read by read-modify-write
(RMW) instruction Write
PDR6 0 Pin state is “L” level. PDR6 value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDR6 value is “1”. As output port, outputs “H” level.*
DDR6 0 Port input enabled
1 Port output enabled
PUL6 0 Pull-up disabled
1 Pull-up enabled
Correspondence bet ween related register bits and pins
Pin name P67 P66 P65 P64 P63 P62 P61 P60
PDR6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DDR6
PUL6 --
PDR6 Pin
PDR6 read
PDR6 write
Executing bit manipulation instruction
DDR6 read
DDR6 write
PUL6 read
PUL6 write
DDR6
PUL6
0
1
1
0
Stop mode, watch mode (SPL = 1)
Peripheral function input
Peripheral function input enable
Peripheral function output enable
Peripheral function output
Hysteresis
Pull-up
Internal bus
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15.3.4 Port 6 operations
• O pe ra tio n as an output port
• A pin becomes an output port if the bit in the DDR6 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such periphe ral functions.
• When a pin is used as an output port, it outputs the value of the PDR6 register to external pins.
• If data is written to the PDR6 register, the value is stored in the output latch and is output to the pin set a s an output
port as it is.
• Reading the PDR6 register returns the PDR6 register value.
• Operation as an input port
• A pin beco mes an input port if the bit in the DDR6 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such periphe ral functions.
• If data is written to the PDR6 register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDR6 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDR6 register, the PDR6 register value is returned.
• Operation as a peripheral function output pin
• A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output
enable bit of a peripher al function corresponding to that pin.
• The pin value can be read from the PDR6 register even if the peripheral function output is enabled. Therefore, the
output value of a peripheral function can b e read by the r ead operation on the PDR6 register. However , if the read-
modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 regi st er value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the b it in the DDR6 re gister corres ponding to the inpu t pin of a peri pheral function
to “0”.
• Reading the PDR6 register returns the pin value, regardless o f whether the perip heral func tion uses th at pin as its
input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6
register value is returned.
• O pe ra tio n at rese t
If the CPU is reset, all bits in the DDR6 register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR6 reg-
ister value. The input of that pin is locked to “L” level a nd blocked in orde r to prevent le aks due to input open . How-
ever, if the interrupt input from the external interrupt (INT08 , INT09) is enabled, or if the interrupt inpu t of P64/EC1
and P67/TRG1 is enabled by the external interrupt control register ch. 0 (EIC00) o f the external interrupt circuit and
the interrupt pin selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled
and is not blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in th e PUL6 reg ister to “1 ” makes th e pu ll-u p r esistor be inter nal ly con nected to th e pin. Whe n the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL6 register.
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15.4 Port F
Port F is a general-purpose I/O port. This section focuses on its functions as a gen eral-pur pose I/O port. For de tails of
peripheral functions, refer to their respective chapters in “New 8FX MB95630H Series Hardware Manual”.
15.4.1 Port F configuration
Port F is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port F data register (PDRF)
• Port F direction register (DDRF)
15.4.2 Block diagrams of port F
•PF0/X0 pin
This pin has the following peripheral function:
• Main clock input oscillation pin (X0)
•PF1/X1 pin
This pin has the following peripheral function:
• Main clock I/O oscillation pin (X1)
• Blo ck dia gra m of PF0/ X0 an d PF1/X1
PDRF Pin
PDRF read
PDRF write
Executing bit manipulation instruction
DDRF read
DDRF write
DDRF
0
1
Stop mode, watch mode (SPL = 1)
Internal bus
Hysteresis
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•PF2/RST pin
This pin has the following peripheral function:
• Rese t pin (RST)
• Blo ck dia gra m of PF2/ RST
15.4.3 Port F registers
• Port F register functions
*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z.
• Correspondence between registers and pins for port F
*: PF2/RST is the dedicated reset pin on MB95F632H/F633H/F634H/F636H.
15.4.4 Port F operations
• O pe ra tio n as an output port
• A pin becomes an output port if the bit in the DDRF register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such periphe ral functions.
• When a pin is used as an output port, it outputs the value of the PDRF register to external pins.
• If data is written to the PDRF register, the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Rea din g the PDRF re gister returns the PDRF re gis ter valu e.
Register
abbreviation Data Read Read by read-modify-write
(RMW) instruction Write
PDRF 0 Pin state is “L” level. PDRF value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDRF value is “1”. As output port, outputs “H” level.*
DDRF 0 Port input enabled
1 Port output enabled
Correspondence bet ween related register bits and pins
Pin name-----PF2*PF1PF0
PDRF -----bit2bit1bit0
DDRF
PDRF
PDRF read
PDRF write
Executing bit manipulation instruction
DDRF read
DDRF write
DDRF
0
1
1
0
Stop mode, watch mode (SPL = 1)
Reset input
Reset input enable
Reset output enable
Reset output
Pin
OD
Internal bus
Hysteresis
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• Operation as an input port
• A pin beco mes an input port if the bit in the DDRF register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such periphe ral functions.
• If data is written to the PDRF register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDRF register returns the pin value. However, if the read-modify-write (RMW) type of instruction is
used to read the PDRF register, the PDRF register value is returned.
• O pe ra tio n at rese t
If the CPU is reset, all bits in the DDRF register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to en ter the high imped ance state re gardless of the DDRF reg -
ister value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
15.5 Port G
Port G is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of
peripheral functions, refer to their respective chapters in “New 8FX MB95630H Series Hardware Manual”.
15.5.1 Port G configuration
Port G is made up of the following elements.
• General-purpose I/O pins/peripheral function I/O pins
• Port G data register (PDRG)
• Port G direction register (DDRG)
• Port G pull-up register (PULG)
15.5.2 Block diagram of port G
• PG1/X0A/SNI1 pin
This pin has the following pe ripheral functions:
• Subclock input oscillation pin (X0A)
• Trigger input pin for the position detection function of the MPG waveform sequencer (SNI1)
• PG2/X1A/SNI2 pin
This pin has the following pe ripheral functions:
• Subclock I/O oscillation pin (X1A)
• Trigger input pin for the position detection function of the MPG waveform sequencer (SNI2)
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• Blo ck dia gra m of PG1/ X0A/SNI1 and PG2/X1A/SNI2
15.5.3 Port G registers
• Port G register functions
• Correspondence between registers and pins for port G
15.5.4 Port G operations
• O pe ra tio n as an output port
• A pin becomes an output port if the bit in the DDRG register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such periphe ral functions.
• When a pin is used as an output port, it outputs the value of the PDRG register to external pins.
Register
abbreviation Data Read Read by read-modify-write
(RMW) instruction Write
PDRG 0 Pin state is “L” level. PDRG value is “0”. As output port, outputs “L” level.
1 Pin state is “H” level. PDRG value is “1”. As output port, outputs “H” level.
DDRG 0 Port input enabled
1 Port output enabled
PULG 0 Pull-up disabled
1 Pull-up enabled
Correspondence bet ween related register bits and pins
Pin name-----PG2PG1-
PDRG -----bit2bit1-DDRG
PULG
PDRG Pin
PDRG read
PDRG write
Executing bit manipulation instruction
DDRG read
DDRG write
PULG read
PULG write
DDRG
PULG
0
1
Stop mode, watch mode (SPL = 1)
Peripheral function input
Hysteresis
Pull-up
Internal bus
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Document Number: 002-04627 Rev. *A Page 55 of 102
• If data is written to the PDRG register , the value is stored in the output latch and is output to the pin set as an output
port as it is.
• Reading the PDRG register returns the PDRG register value.
• Operation as an input port
• A pin beco mes an input port if the bit in the DDRG register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such periphe ral functions.
• If data is written to the PDRG register, the value is stored in the output latch but is not output to the pin set as an
input port.
• Reading the PDRG register returns the pin value. However, if the re ad-modify-write (RMW ) type of instruction is
used to read the PDRG register, the PDRG register value is returned.
• Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDRG register co rresponding to the input pin of a periph eral function
to “0”.
• Reading the PDRG register re turns the pin value, re gardless of whether the peripheral function uses that pi n as its
input pin. However , if the read-modify-write (RMW) type of instruction is used to read th e PDRG register , the PDRG
register value is returned.
• O pe ra tio n at rese t
If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled.
• Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop
mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRG reg-
ister value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged
and the output level is maintained.
• Operation of the pull-up register
Setting the bit in the PUL G register to “1” makes the p ull-up resistor be internally con nected to the pin. When the pin
output is “L” level, the pull-up resistor is disconnected regardless of the value of the PULG register.
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16. Interrupt Source Table
Interrupt source Interrupt
request
number
Ve ct or ta bl e
address Interrupt level
setting register Priority order of
interrupt sources
of the same level
(occurring
simultaneously)
Upper Lower Register Bit
External interrupt ch. 0 IRQ00 0xFFFA 0xFFFB ILR0 L00 [1:0] High
Low
External interrupt ch. 4
External interrupt ch. 1 IRQ01 0xFFF8 0xFFF9 ILR0 L01 [1:0]
External interrupt ch. 5
External interrupt ch. 2 IRQ02 0xFFF6 0xFFF7 ILR0 L02 [1:0]
External interrupt ch. 6
External interrupt ch. 3 IRQ03 0xFFF4 0xFFF5 ILR0 L03 [1:0]
External interrupt ch. 7
UART/SIO ch. 0 IRQ04 0xFFF2 0xFFF3 ILR1 L04 [1:0]
MPG (DTTI)
8/16-bit composite timer ch. 0
(lower) I RQ05 0xFFF0 0xFFF1 ILR 1 L05 [1:0]
8/16-bit composite timer ch. 0
(upper) IRQ06 0xFFE E 0xFFEF ILR1 L06 [1:0]
LIN-UART (reception) IRQ07 0xFFEC 0xFFED ILR1 L07 [1:0]
LIN-UART (transmission) IRQ08 0xFFEA 0xFFEB ILR2 L08 [1:0]
8/16-bit PPG ch. 1 (lower) IRQ09 0xFFE8 0xFFE9 ILR2 L09 [1:0]
8/16-bit PPG ch. 1 (upper) IRQ10 0xFFE6 0xFFE7 ILR2 L10 [1:0]
8/16-bit PPG ch. 2 (upper) IRQ11 0xFFE4 0xFFE5 ILR2 L11 [1:0]
8/16-bit PPG ch. 0 (upper) IRQ12 0xFFE2 0xFFE3 ILR3 L12 [1:0]
8/16-bit PPG ch. 0 (lower) IRQ13 0xFFE0 0xFFE1 ILR3 L13 [1:0]
8/16-bit composite timer ch. 1
(upper) IRQ14 0xFFDE 0x FFDF ILR3 L14 [1:0]
8/16-bit PPG ch. 2 (lower) I RQ15 0xFFDC 0xFFDD ILR3 L15 [1:0]
16-bit reload timer ch. 1 IRQ16 0xFFDA 0xFFDB ILR4 L16 [1:0]MPG (write timing/compare clear)
I2C bus interface
16-bit PPG timer ch. 1 IRQ17 0xFFD8 0xFFD9 ILR4 L17 [1:0]MPG (position detection/compare
interrupt)
8/10-bit A/D converter IRQ18 0xFFD6 0xFFD7 ILR4 L18 [1:0]
Time-base timer IRQ19 0xFFD4 0xFFD5 ILR4 L19 [1:0]
Watch prescaler IRQ20 0xFFD2 0xFFD3 ILR5 L20 [1:0]
Comparator
External interrupt ch. 8 IRQ21 0xFFD0 0xFFD1 ILR5 L21 [1:0]
External interrupt ch. 9
8/16-bit composite timer ch. 1
(lower) I RQ22 0xFFCE 0xFFCF ILR5 L22 [1:0]
Flash memory IRQ23 0xFFCC 0xFFCD ILR5 L23 [1:0]
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17. Pin States In Each Mode
Pin name Normal
operation Sleep mode Stop mode Watch mode On reset
SPL=0 SPL=1 SPL=0 SPL=1
PF0/X0
Oscillation input Oscillation input Hi-Z Hi-Z Hi-Z Hi-Z —
I/O port*4I/O port*4
- Previous state
kept
- Input
blocked*2*4
-Hi-Z
- Input
blocked*2*4
- Previous state
kept
- Input
blocked*2*4
-Hi-Z
- Input
blocked*2*4
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
PF1/X1
Oscillation input Oscillation input Hi-Z Hi-Z Hi-Z Hi-Z —
I/O port*4I/O port*4
- Previous state
kept
- Input
blocked*2*4
-Hi-Z
- Input
blocked*2*4
- Previous state
kept
- Input
blocked*2*4
-Hi-Z
- Input
blocked*2*4
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
PG1/X0A/
SNI1
Oscillation input Oscillation input Hi-Z Hi-Z Hi-Z Hi-Z —
I/O port*4/
peripheral func-
tion I/O
I/O port*4/
peripheral func-
tion I/O
- Previous state
kept
- Input
blocked*2*4
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input
blocked*2*4
- Previous state
kept
- Input
blocked*2*4
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input
blocked*2*4
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
PG2/X1A/
SNI2
Oscillation input Oscillation input Hi-Z Hi-Z Hi-Z Hi-Z —
I/O port*4/
peripheral
function I/O
I/O port*4/
peripheral
function I/O
- Previous state
kept
- Input
blocked*2*4
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input
blocked*2*4
- Previous state
kept
- Input
blocked*2*4
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input
blocked*2*4
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
PF2/RST I/O port Reset input Reset input Reset input Reset input Reset input Reset input*3
P60/INT08/
SDA/DTTI
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P61/INT09/
SCL/TI1
P62/TO10/
PPG00/
OPT0 I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
- Previous state
kept
- Input blocked*2
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P63/TO11/
PPG01/
OPT1
MB95630H Series
Document Number: 002-04627 Rev. *A Page 58 of 102
Pin name Normal
operation Sleep mode Stop mode Watch mode On reset
SPL=0 SPL=1 SPL=0 SPL=1
P64/EC1/
PPG10/
OPT2
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P65/PPG11/
OPT3 I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
- Previous state
kept
- Input blocked*2
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P66/PPG1/
PPG20/
OPT4
P67/TRG1/
PPG21/
OPT5
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P10/PPG10/
CMP0_O I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
- Previous state
kept
- Input blocked*2
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P11/PPG11
P12/DBG/
EC0
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
-Hi-Z
- Input blocked*2
- Previous state
kept
- Input blocked*2
-Hi-Z
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P13/PPG00 I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
- Previous state
kept
- Input blocked*2
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
MB95630H Series
Document Number: 002-04627 Rev. *A Page 59 of 102
Pin name Normal
operation Sleep mode Stop mode Watch mode On reset
SPL=0 SPL=1 SPL=0 SPL=1
P14/UCK0/
PPG01
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P15/UO0/
PPG20
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
- Previous state
kept
- Input blocked*2
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P16/UI0/
PPG21
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P17/TO1/
SNI0
I/O port/
peripheral
function I/O
I/O port/
peripheral
function I/O
- Previous state
kept
- Input blocked*2
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
- Previous state
kept
- Input blocked*2
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
-Hi-Z
- Input
enabled*1
(However, it
does not
function.)
P00/INT00/
AN00/
CMP0_P
I/O port/
peripheral
function I/O/
analog input
I/O port/
peripheral
function I/O/
analog input
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
blocked*2
P01/INT01/
AN01/
CMP0_N
P02/INT02/
AN02/SCK
P03/INT03/
AN03/SOT
MB95630H Series
Document Number: 002-04627 Rev. *A Page 60 of 102
SPL: Pin state setting bit in the standby control register (STBC:SPL)
Hi-Z: High impedance
*1:“Input enabled” means that the input function is enabled. While the input function is enabled, a pull-up or pull-down
operation has to be performed in order to prevent leaks due to external input. If a pin is used as an output port, its
pin state is the same as that of other ports.
*2:“Input blocked” means direct input gate operation from the pin is disabled.
*3:The PF2/RST pin stays at the state shown when configured as a reset pin.
*4:The pin stays at the state shown when configured as a general-purpose I/O port.
Pin name Normal
operation Sleep mode Stop mode Watch mode On reset
SPL=0 SPL=1 SPL=0 SPL=1
P04/INT04/
AN04/SIN/
EC0
I/O port/
peripheral
function I/O/
analog input
I/O port/
peripheral
function I/O/
analog input
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Previous state
kept
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
- Hi-Z (However,
the setting of
the pull-up
control is
effective.)
- Input blocked*2
(However, an
external
interrupt can
be input when
the external
interrupt
request is
enabled.)
-Hi-Z
- Input
blocked*2
P05/INT05/
AN05/TO00
P06/INT06/
AN06/TO01
P07/INT07/
AN07
MB95630H Series
Document Number: 002-04627 Rev. *A Page 61 of 102
18. Electrical Characteristics
18.1 Absolute Maximum Ratings
*1:These parameters are based on the condition that VSS is 0.0 V.
*2:V1 and V0 must not exceed VCC 0.3 V. V1 must not exceed the rated voltage. However, if the maximum current
to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating.
*3:Specific pins: P00 to P07, P10, P11, P13 to P17, P62 to P67, PF0, PF1, PG1, PG2
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage*1VCC VSS 0.3 VSS 6V
Input voltage*1VIVSS 0.3 VSS 6V*2
Output voltage*1VOVSS 0.3 VSS 6V*2
Maximum clamp current ICLAMP 22 mA Applicable to specific pins*3
Total maximum clamp
current |ICLAMP| — 20 mA Applicable to specific pins*3
“L” level maximum
output current IOL —15mA
“L” level average current
IOLAV1
—
4
mA
Other than P62 to P67
Average output current =
operating current operating ratio (1 pin)
IOLAV2 12 P62 to P67
Average output current =
operating current operating ratio (1 pin)
“L” level total maximum
output current IOL — 100 mA
“L” level total average
output current IOLAV —37mA
Total average output current =
operating current operating ratio
(Total number of pins)
“H” level maximum
output current IOH —15 mA
“H” level average
current
IOHAV1
—
4
mA
Other than P62 to P67
Average output current =
operating current operating ratio (1 pin)
IOHAV2 8P62 to P67
Average output current =
operating current operating ratio (1 pin)
“H” level total maximum
output current IOH —100 mA
“H” level total average
output current IOHAV —47 mA Total average output current =
operating current operating ratio
(Total number of pins)
Power consumption Pd— 320 mW
Operating temperature TA40 85 C
Storage temperature Tstg 55 150 C
MB95630H Series
Document Number: 002-04627 Rev. *A Page 62 of 102
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between
the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistor should b e set to a value at which the current to be in put to the microcontro ller pin
when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient
current or stationary current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage)
input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other devices.
• If the HV (High Volta ge) signal is inp ut when the microcontrol ler po we r supp ly is off (not fixed at 0 V), since power
is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power
supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Ex am ple of a re co mm e nd e d circ uit :
WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolut e maxim u m ra tin gs.
Do not exceed any of the s e ra tin gs .
HV(High Voltage) input (0 V to 16 V)
Protective diode
VCC
N-ch
P-ch
R
Limiting
resistor
• Input/Output equivalent circuit
MB95630H Series
Document Number: 002-04627 Rev. *A Page 63 of 102
18.2 Recommended Operating Conditions (VSS = 0.0 V)
*1:The minimum power supply voltage becomes 2.88 V when a prod uct with the low-voltage detection reset is used or
when the on-chip debug mode is used.
*2:Use a ceramic ca pacitor or a capacitor w ith equivalent frequency characteristics. The decoupling capacitor for the
VCC pin must have a capacitance equal to or larger than the capacitanc e of CS. For the connection to a decoupling
capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to
noise, minimize the distance between the C pin and CS and the distance betwee n CS and the VSS pin when design ing
the layout of a printed circuit board.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and
could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations no t represented on this
data sheet. If you are conside ring application under any condition s other than listed h erein, please contact
sales repres en ta tive s be fo re h and.
Parameter Symbol Value Unit Remarks
Min Max
Power supply voltage VCC 2.4*15.5 VIn normal operation
2.3 5.5 Hold condition in stop mode
Decoupling capacitor CS0.022 1 µF *2
Operating temperature TA 40 85 COther than on-chip debug mode
535 On-chip debug mode
C
Cs
DBG
*
RST
• DBG / RST / C pins connection diagram
*: Connect the DBG pin to an external pull-up resistor of 2 k or above. After power-on, ensure th at the
DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a com-
munication pin in debug mode. Since the actua l pull-up resistance dep ends on the tool used and the
interconnection length, refer to the tool document when selecting a pull-up resistor.
MB95630H Series
Document Number: 002-04627 Rev. *A Page 64 of 102
18.3 DC Characteristics (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 C to 85°C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
“H” level
input
voltage
VIHI P04, P16, P60,
P61 — 0.7 VCC —VCC 0.3 V CMOS input level
VIHS
P00 to P07,
P10 to P17,
P60 to P67,
PF0, PF1,
PG1, PG2
— 0.8 VCC —VCC 0.3 V Hysteresis input
VIHM PF2 — 0.8 VCC —VCC 0.3 V Hysteresis input
“L” level
input
voltage
VILI P04, P16, P60,
P61 —V
SS 0.3 — 0.3 VCC V CMOS input level
VILS
P00 to P07,
P10 to P17,
P60 to P67,
PF0, PF1,
PG1, PG2
—V
SS 0.3 — 0.2 VCC V Hysteresis input
VILM PF2 — VSS 0.3 — 0.2 VCC V Hysteresis input
Open-drain
output
application
voltage
VDP12, P60, P61,
PF2 —V
SS 0.3 — Vss 5.5 V
“H” level
output
voltage
VOH1
Output pins
other than P12,
P62 to P67,
PF2
IOH = 4 mA V CC 0.5 — — V
VOH2 P62 to P67 IOH = 8 mA VCC 0.5 — — V
“L” level
output
voltage
VOL1 Output pins
other than P62
to P67 IOL = 4 mA — — 0.4 V
VOL2 P62 to P67 IOL = 12 mA — — 0.4 V
Input leak
current (Hi-Z
output leak
current)
ILI All input
pins 0.0 V < VI < VCC 5—5µA
When the internal
pull-up resistor is
disabled
Internal
pull-up
resistor RPULL
P00 to P07,
P10, P11,
P13 to P17,
P62 to P67,
PG1, PG2
VI = 0 V 25 50 100 kWhen the internal
pull-up resistor is
enabled
Input
capacitance CIN Other than VCC
and VSS f = 1 MHz — 5 15 pF
MB95630H Series
Document Number: 002-04627 Rev. *A Page 65 of 102
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 C to 85°C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ*1Max*2
Power
supply
current*3
ICC
VCC
(External clock
operation)
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
—3.65.8mA
Except during Flash
memory programming
and erasing
—7.513.8mA
During Flash memory
programming and
erasing
— 4.1 9.1 mA At A/D conversion
ICCS
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
—1.3 3mA
ICCL
FCL = 32 kHz
FMPL = 16 kHz
Subclock mode
(divided by 2)
TA = 25°C
— 49 145 µA
ICCLS
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = 25°C
— 10 15 µA In deep standby mode
ICCT
FCL = 32 kHz
Watch mode
Main stop mode
TA = 25°C
— 7 13 µA In deep standby mode
ICCMPLL
VCC
FMCRPLL = 16 MHz
FMP = 16 MHz
Main CR PLL clock
mode
(multiplied by 4)
TA = 25°C
—4.76.8mA
ICCMCR FCRH = 4 MHz
FMP = 4 MHz
Main CR clock mode —1.14.6mA
ICCSCR Sub-CR clock mode
(divided by 2)
TA = 25°C — 58.1 230 µA
ICCTS VCC
(External clock
operation)
FCH = 32 MHz
Time-base timer mode
TA = 25°C — 345 395 µA In deep standby mode
ICCH Substop mode
TA = 25°C — 6 10 µA In deep standby mod e
MB95630H Series
Document Number: 002-04627 Rev. *A Page 66 of 102
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40 C to 85°C)
*1:VCC = 5.0 V, TA = 25°C
*2:VCC = 5.5 V, TA = 85°C (unless otherwise sp ecif ied )
*3:• The power supply current is determined by the external clock. When the low-voltage detection circuit is selected,
the power supply current is the sum of adding the cu rrent consumption of the low- vo ltage d etection circu it ( I LVD) to
one of the values from ICC to ICCH. In addition, when both the low-voltage detection option and the CR oscillator are
selected, the power supply current is the sum of adding up the current consumption of the low-voltage detection
circuit (ILVD), the current consumption of the CR oscillators (ICRH, ICRL) and a specified value. In on-chip debug mode,
the CR oscillator (ICRH) and the low-voltage detection circuit are always in operation, and current consumption
therefore increases accordingly.
• See “4. AC Characteristics Clock Timing” for FCH, FCL, FCRH and FMCRPLL.
• See “4. AC Characteristics Source Clock/Machine Clock” fo r FMP and FMPL.
• The power supply current value in standby mo de is measur ed in deep sta ndb y mo de. The current co nsumpt ion in
normal standby is higher than that in deep standby mode. The power supply current value in normal standby can
be found by adding the current consumption difference between normal standby mode and deep standby mode
(INSTBY) to the power supply current value in deep standby mode. For details of normal standby and deep standby
mode, refer to “CHAPTER 3 CLOCK CONTROLLER” in “New 8FX MB95630H Series Hardware Manual”.
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ*1Max*2
Power
supply
current*3
IV
VCC
Current
consumption of the
comparator —60160µA
ILVD
Current
consumption of the
low-voltage
detection circuit
—4 7µA
ICRH Current
consumption of the
main CR oscillator —240320µA
ICRL
Current
consumption of the
sub-CR oscillator
oscillating at
100 kHz
—720µA
INSTBY
Current
consumption
difference between
normal standby
mode and deep
standby mode
TA = 25°C
—2030µA
MB95630H Series
Document Number: 002-04627 Rev. *A Page 67 of 102
18.4 AC Characteristics
18.4.1 Clock Timing (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = 40°C to 85°C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Clock
frequency
FCH X0, X1 — 1 — 16.25 MHz When the main oscillation
circuit is used
X0 X1: open 1 — 12 MHz When the main external clock
is usedX0, X1 * 1 — 32.5 MHz
FCRH ——
3.92 4 4.08 MHz Operating conditions
• The main CR clock is used.
•0
C TA 70C
3.8 4 4.2 MHz
Operating conditions
• The main CR clock is used.
• 40 C TA 0 C,
70 C TA 85 C
FMCRPLL ——
7.84 8 8.16 MHz Operating conditions
• PLL multiplication rate: 2
•0
C TA 70C
7.6 8 8.4 MHz
Operating conditions
• PLL multiplication rate: 2
• 40 C TA 0 C,
70 C TA 85 C
9.8 10 10.2 MHz Operating conditions
• PLL multiplication rate: 2.5
•0
C TA 70C
9.5 10 10.5 MHz
Operating conditions
• PLL multiplication rate: 2.5
• 40 C TA 0 C,
70 C TA 85 C
11.76 12 12.24 MHz Operating conditions
• PLL multiplication rate: 3
•0
C TA 70C
11.4 12 12.6 MHz
Operating conditions
• PLL multiplication rate: 3
• 40 C TA 0 C,
70 C TA 85 C
15.68 16 16.32 MHz Operating conditions
• PLL multiplication rate: 4
•0
C TA 70C
15.2 16 16.8 MHz
Operating conditions
• PLL multiplication rate: 4
• 40 C TA 0 C,
70 C TA 85 C
FCL X0A, X1A — — 32.768 — kHz When the suboscillation
circuit is used
— 32.768 — kHz When the sub-external clock
is used
FCRL — — 50 100 150 kHz When the sub-CR clock is
used
MB95630H Series
Document Number: 002-04627 Rev. *A Page 68 of 102
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = 40°C to 85°C)
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Clock cycle
time tHCYL
X0, X1 61.5 1000 ns When the main oscillation
circuit is used
X0 X1: open 83.4 1000 ns When an external clock is
used
X0, X1 * 30.8 1000 ns
tLCYL X0A, X1A
30.5 µs When the subclock is used
Input clock
pulse width tWH1, tWL1 X0 X1: open 33.4
ns When an external clock is
used, the duty ratio should
range between 40% and 60%.
X0, X1 * 12.4
ns
tWH2, tWL2 X0A —15.2µs
Input clock
rising time and
falling time tCR, tCF
X0, X0A X1: open — 5ns
When an external clock is
used
X0, X1,
X0A, X1A *——5ns
CR oscillation
start time
tCRHWK ————50µs
When the main CR clock is
used
tCRLWK ————30µs
When the sub-CR clock is
used
PLL oscillation
start time tMCRPLLWK ————100µs
When the main CR PLL clock
is used
X0, X1
0.8 VCC
0.2 VCC 0.2 VCC
0.8 VCC
tWH1 tWL1
0.2 VCC
tHCYL
tCR tCF
• Input waveform generated when an external clock (main clock) is used
When a crystal oscillator or
a ceramic oscillator is used
When an external cloc
k
is used
X0 X1 X0 X1
FCH
FCH
When an external clock is used
(X1 is open)
X0 X1
Open
FCH
• Figure of main clock input port external connection
MB95630H Series
Document Number: 002-04627 Rev. *A Page 69 of 102
X0A
0.8 VCC
0.2 VCC 0.2 VCC
0.8 VCC
tWH2 tWL2
0.2 VCC
tLCYL
tCR tCF
• Input waveform generated when an external clock (subclock) is used
When a crystal oscillator or
a ceramic oscillator is used
When an external cloc
k
is used
X0A X1A X0A X1A
Open
F
CL
F
CL
• Figure of subclock input port external connection
tCRHWK 1/FCRH
Main CR clock
Oscillation starts Oscillation stabilizes
• Input waveform generated when an internal clock (main CR clock) is used
tCRLWK 1/FCRL
Sub-CR clock
Oscillation starts Oscillation stabilizes
• Input waveform generated when an internal clock (sub-CR clock) is used
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18.4.2 Source Clock/Machine Clock (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C)
Parameter Symbol Pin
name Value Unit Remarks
Min Typ Max
Source clock
cycle time*1tSCLK —
61.5 — 2000 ns When the main extern al clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
62.5 — 250 ns When the main CR clock is used
Min: FCRH = 4 MHz, multiplied by 4
Max: FCRH = 4 MHz, no division
—61—µs
When the suboscillation clock is used
FCL = 32.768 kHz, divided by 2
—20—µs
When the sub-CR clock is used
FCL = 100 kHz, divided by 2
Source clock
frequency
FSP
—
0.5 — 16.25 MHz When the main oscillation clock is used
— 4 — MHz When the main CR clock is used
FSPL
— 16.384 — kHz When the suboscillation clock is used
— 50 — kHz When the sub-CR clock is used
FCRL = 100 kHz, divided b y 2
Machine clock
cycle time*2
(minimum
instruction
execution time)
tMCLK —
61.5 — 32000 ns When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
250 — 4000 ns When the main CR clock is used
Min: FSP = 4 MHz, no division
Max: FSP = 4 MHz, divided by 16
61 — 976.5 µs When the suboscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20 — 320 µs When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
tMCRPLLWK
1/FMCRPLL
Main CR PLL clock
Oscillation starts Oscillation stabilizes
• Input waveform generated when an internal clock (main CR PLL clock) is used
MB95630H Series
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*1:This is the clock befo re it is div ided acc ording to the di vision ratio set by the machine clock division ratio select bits
(SYCC:DIV[1:0]). This source clock is divided to become a machine cloc k according to the division r atio set by th e
machine clock division ratio select bits (SYCC:DIV[1:0]). In add ition, a so urce clo ck can be selected from the fo llow-
ing.• Main clock divided by 2
• Main CR clock
• PLL multiplication of main CR clock (Select a multip lica tio n rate from 2, 2. 5, 3 and 4.)
• Subclock divided by 2
• Sub-CR clock divided by 2
*2:This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
Machine clock
frequency
FMP
—
0.031 — 16.25 MHz When the main oscillation clock is used
0.25 — 16 MHz When the main CR clock is used
FMPL
1.024 — 16.384 kHz When the suboscillation clock is used
3.125 — 50 kHz When the sub-CR clock is used
FCRL = 100 kHz
Parameter Symbol Pin
name Value Unit Remarks
Min Typ Max
FCH
(Main oscillation clock) Divided by 2
Divided by 2
Divided by 2
FMCRPLL
(Main CR PLL clock)
FCRH
(Main CR clock)
FCL
(Suboscillation clock)
FCRL
(Sub-CR clock)
SCLK
(Source clock) MCLK
(Machine clock)
Machine clock divide ratio select bits
(SYCC:DIV[1:0])
Clock mode select bits
(SYCC:SCS[2:0])
Division circuit
×
×
×
×
1
1/4
1/8
1/16
• Sch em a tic dia gr a m of the clo ck ge ne ra tio n block
MB95630H Series
Document Number: 002-04627 Rev. *A Page 72 of 102
18.4.3 External Re set (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C)
*: See “Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Value Unit Remarks
Min Max
RST “L” level
pulse width tRSTL 2 tMCLK*ns
Operating voltage (V)
A/D converter operation range
5.5
5.0
4.0
3.5
3.0
2.7
2.4
16 kHz 3 MHz 10 MHz 16.25 MHz
Source clock frequency (F
SP
/F
SPL
)
• Operating voltage - Operating frequency (TA = 40°C to 85°C)
0.2 VCC
RST
0.2 VCC
tRSTL
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Document Number: 002-04627 Rev. *A Page 73 of 102
18.4.4 Power-on Reset (VSS = 0.0 V, TA = 40°C to 85°C)
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the power
supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as shown below.
18.4.5 Peripheral Input Timing (VCC = 5.0 V10%, V SS = 0.0 V, TA = 40°C to 85°C)
*: See “Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Condition Value Unit Remarks
Min Max
Power supply rising time tR
50 ms
Power supply cutoff time tOFF 1ms Wait time until power-on
Parameter Symbol Pin name Value Unit
Min Max
Peripheral input “H” pulse wid th tILIH INT00 to INT09, EC0, EC1, TI1,
TRG1 2 tMCLK*ns
Peripheral input “L” pulse width tIHIL 2 tMCLK*ns
0.2 V0.2 V
tOFF
tR
2.5 V
0.2 V
V
CC
V
CC
2.3 V
V
SS
Hold condition in stop mode
Set the slope of rising to
a value below 30 mV/ms.
INT00 to INT09,
EC0, EC1, TI1,
TRG1
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tILIH tIHIL
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Document Number: 002-04627 Rev. *A Page 74 of 102
18.4.6 LIN-UART Timing
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0) (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C)
*1:There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling
edge of the serial clock.
*2:The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3:See “Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK Internal clock
operation output pin:
CL = 80 pF 1 TTL
5 tMCLK*3—ns
SCK SOT delay time tSLOVI SCK, SOT 50 50 ns
Valid SIN SCKtIVSHI SCK, SIN tMCLK*3 80 — ns
SCK valid SIN hold time tSHIXI SCK, SIN 0 — ns
Serial clock “L” pulse width tSLSH SCK
External clock
operation output pin:
CL = 80 pF 1 TTL
3 tMCLK*3tR—ns
Serial clock “H” pulse width tSHSL SCK tMCLK*3 10 — ns
SCK SOT delay time tSLOVE SCK, SOT — 2 tMCLK*3 60 ns
Valid SIN SCKtIVSHE SCK, SIN 30 — ns
SCK valid SIN hold time tSHIXE SCK, SIN tMCLK*3 30 — ns
SCK falling time tFSCK — 10 ns
SCK rising time tRSCK — 10 ns
0.2 VCC 0.2 VCC
0.8 VCC
t
SLOVI
tIVSHI tSHIXI
0.8 VCC
0.2 VCC
SCK
SOT
SIN
0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
tSCYC
• Internal shift clock mode
MB95630H Series
Document Number: 002-04627 Rev. *A Page 75 of 102
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C)
*1:There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling
edge of the serial clock.
*2:The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3:See “Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK Internal clock
operation output pin:
CL = 80 pF 1 TTL
5 tMCLK*3—ns
SCK SOT delay time tSHOVI SCK, SOT 50 50 ns
Valid SIN SCKtIVSLI SCK, SIN tMCLK*3 80 — ns
SCK valid SIN hold time tSLIXI SCK, SIN 0 — ns
Serial clock “H” pulse width tSHSL SCK
External clock
operation output pin:
CL = 80 pF 1 TTL
3 tMCLK*3 tR—ns
Serial clock “L” pulse width tSLSH SCK tMCLK*3 10 — ns
SCK SOT delay time tSHOVE SCK, SOT — 2 tMCLK*3 60 ns
Valid SIN SCKtIVSLE SCK, SIN 30 — ns
SCK valid SIN hold time tSLIXE SCK, SIN tMCLK*3 30 — ns
SCK falling time tFSCK — 10 ns
SCK rising time tRSCK — 10 ns
0.2 V
CC
0.2 V
CC
0.8 V
CC
0.8 V
CC
tSLOVE
t
IVSHE
t
SHIXE
0.8 V
CC
0.2 V
CC
SCK
SOT
SIN
0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
t
SLSH
t
SHSL
t
R
0.8 V
CC
t
F
• External shift clock mode
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0.2 VCC
0.8 VCC
0.8 VCC
t
SHOVI
tIVSLI tSLIXI
0.8 VCC
0.2 VCC
SCK
SOT
SIN
0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
tSCYC
• Internal shift clock mode
0.2 V
CC
0.2 V
CC
0.2 V
CC
0.8 V
CC
tSHOVE
t
IVSLE
t
SLIXE
0.8 V
CC
0.2 V
CC
SCK
SOT
SIN
0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
t
SHSL
t
SLSH
t
F
0.8 V
CC
t
R
• External shift clock mode
MB95630H Series
Document Number: 002-04627 Rev. *A Page 77 of 102
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1) (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C)
*1:There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling
edge of the serial clock.
*2:The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3:See “Source Clock/Machine Clock” for tMCLK.
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1) (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C)
*1:There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling
edge of the serial clock.
*2:The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3:See “Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock
operation output pin:
CL = 80 pF 1 TTL
5 tMCLK*3—ns
SCK SOT delay time tSHOVI SCK, SOT 50 50 ns
Valid SIN SCKtIVSLI SCK, SIN tMCLK*3 80 — ns
SCK valid SIN hold time tSLIXI SCK, SIN 0 — ns
SOT SCKdelay time tSOVLI SCK, SOT 3tMCLK*3 70 — ns
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal clock
operation output pin:
CL = 80 pF 1 TTL
5 tMCLK*3—ns
SCK SOT delay time tSLOVI SCK, SOT 50 50 ns
Valid SIN SCKtIVSHI SCK, SIN tMCLK*3 80 — ns
SCK valid SIN hold time tSHIXI SCK, SIN 0 — ns
SOT SCKdelay time tSOVHI SCK, SOT 3tMCLK*3 70 — ns
0.8 VCC
0.2 VCC 0.2 VCC
tSHOVI
tSOVLI
tIVSLI tSLIXI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
SCK
SOT
SIN 0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
tSCYC
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Document Number: 002-04627 Rev. *A Page 78 of 102
18.4.7 Low-voltage Detection (VSS = 0.0 V, TA = 40°C to 85°C)
*: The release voltage and the detection voltage can be selected by u sing the LVD re set volt age se lection ID regist er
(LVDR) in the low-voltage detection reset circuit. For details of the LVDR register, refer to “CHAPTER 16 LOW-
VOLTAGE DETECTION RESET CIRCUIT” in “New 8FX MB95630H Series Hardware Manual”.
Parameter Symbol Value Unit Remarks
Min Typ Max
Release voltage* VDL
2.52 2.7 2.88
V At power supply rise
2.61 2.8 2.99
2.89 3.1 3.31
3.08 3.3 3.52
Detection voltage* VDL
2.43 2.6 2.77
V At power supply fall
2.52 2.7 2.88
2.80 3 3.20
2.99 3.2 3.41
Hysteresis width VHYS ——100mV
Power supply start
voltage Voff ——2.3V
Power supply end
voltage Von 4.9 — — V
Power supply voltage
change time
(at power supply rise) tr650 — — µs Slope of power supply that the reset
release signal generates within the
rating (VDL+)
Power supply voltage
change time
(at power supply fall) tf650 — — µs Slope of power supply that the reset
detection signal generate s within the
rating (VDL-)
Reset release delay
time td1 ——30µs
Reset detection delay
time td2 ——30µs
LVD reset threshold
voltage transition
stabilization time tstb 10 — — µs
0.2 VCC
0.8 VCC 0.8 VCC
tSLOVI
tSOVHI
tIVSHI tSHIXI
0.8 VCC
0.2 VCC
0.8 V
CC
0.2 V
CC
SCK
SOT
SIN 0.7 VCC
0.3 VCC
0.7 VCC
0.3 VCC
tSCYC
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Document Number: 002-04627 Rev. *A Page 79 of 102
VHYS
td2 td1
tr
tf
VCC
Von
Voff
VDL+
VDL-
time
time
Internal reset signal
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18.4.8 I2C Bus Interface Timing (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C)
*1:R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2:The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the
SCL signal at “L” (tLOW) does not extend.
*3:A Fast-mode I2C-bus device can b e used in a St andard- mode I 2C-bus system, provided that the condition of tSU;DAT
250 ns is fulfilled.
Parameter Symbol Pin name Condition
Value
Unit
Standard-
mode Fast-mode
Min Max Min Max
SCL clock frequency fSCL SCL
R = 1.7 k,
C = 50 pF*1
01000400kHz
(Repeated) START condition hold
time
SDA SCL tHD;STA SCL, SDA 4.0 — 0.6 — µs
SCL clock “L” width tLOW SCL 4.7 — 1.3 — µs
SCL clock “H” width tHIGH SCL 4.0 — 0.6 — µs
(Repeated) START condition setup
time
SCL SDA tSU;STA SCL, SDA 4.7 — 0.6 — µs
Data hold time
SCL SDA tHD;DAT SCL, SDA 0 3.45*2 00.9
*3 µs
Data setup time
SDA SCL tSU;DAT SCL, SDA 0.25 — 0.1 — µs
STOP condition setup time
SCL SDA tSU;STO SCL, SDA 4 — 0.6 — µs
Bus free time between STOP
condition and START condition tBUF SCL, SDA 4.7 — 1.3 — µs
SDA
SCL
t
WAKEUP
t
HD;STA
t
SU;DAT
f
SCL
t
HD;STA
t
SU;STA
t
LOW
t
HD;DAT
t
HIGH
t
SU;STO
t
BUF
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Document Number: 002-04627 Rev. *A Page 81 of 102
(VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C)
Parameter Symbol Pin
name Condition Value*2Unit Remarks
Min Max
SCL clock
“L” width tLOW SCL
R = 1.7 k,
C = 50 pF*1
(2 nm/2)tMCLK 20 — ns Master mode
SCL clock
“H” width tHIGH SCL (nm/2)tMCLK 20 (nm/2)tMCLK 20 ns Master mode
START
condition
hold time tHD;STA SCL,
SDA (-1 nm/2)tMCLK 20 (-1 nm)tMCLK 20 ns
Master mode
Maximum value
is applied when
m, n = 1, 8.
Otherwise, the
minimum value is
applied.
STOP
condition
setup time tSU;STO SCL,
SDA (1 nm/2)tMCLK 20 (1 nm/2)tMCLK 20 ns Master mo de
START
condition
setup time tSU;STA SCL,
SDA (1 nm/2)tMCLK 20 (1 nm/2)tMCLK 20 ns Master mo de
Bus free time
between
STOP
condition
and START
condition
tBUF SCL,
SDA (2 nm 4) tMCLK 20 — ns
Data hold
time tHD;DAT SCL,
SDA 3 tMCLK 20 — ns Master mode
Data setup
time tSU;DAT SCL,
SDA (-2 nm/2) tMCLK 20 (-1 nm/2) tMCLK 20 ns
Master mode
It is assumed that
“L” of SCL is not
extended. The
minimum value is
applied to the first
bit of continuous
data. Otherwise,
the maximum
value is applied.
Setup time
between
clearing
interrupt and
SCL rising
tSU;INT SCL (nm/2) tMCLK 20 (1 nm/2) tMCLK 20 ns
The minimum
value is applied
to the interrupt at
the ninth SCL.
The maximum
value is applied
to the interrupt at
the eighth SCL.
SCL clock
“L” width tLOW SCL 4 tMCLK 20 — ns At reception
SCL clock
“H” width tHIGH SCL 4 tMCLK 20 — ns At reception
MB95630H Series
Document Number: 002-04627 Rev. *A Page 82 of 102
(Continued) (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C)
*1:R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2:•See “Source Clock/Mac hin e Clock” for tMCLK.
• m represents the CS[4:3] bits in the I2C clock control register ch. 0 (ICCR0).
• n represents the CS[2:0] bits in the I2C clock control register ch. 0 (ICCR0).
• The actual timing of the I2C bus interface is determined by the values of m and n set by the machine clock (tMCLK)
and the CS[4:0] bits in the ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz tMCLK (machine clock) 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8) : 0.9 MHz < tMCLK 1 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 MHz < tMCLK 2 MHz
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 MHz < tMCLK 4 MHz
(m, n) = (1, 98), (5, 22), (6, 22), (7, 22) : 0.9 MHz < tMCLK 10 MHz
(m, n) = (8, 22) : 0.9 MHz < tMCLK 16.25 MHz
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8) : 3.3 MHz < tMCLK 4 MHz
(m, n) = (1, 22), (5, 4) : 3.3 MHz < tMCLK 8 MHz
(m, n) = (1, 38), (6, 4), (7, 4), (8, 4) : 3.3 MHz < tMCLK 10 MHz
(m, n) = (5, 8) : 3.3 MHz < tMCLK 16.25 MHz
Parameter Symbol Pin
name Condition Value*2Unit Remarks
Min Max
START condition
detection tHD;STA SCL,
SDA
R = 1.7 k,
C = 50 pF*1
2 tMCLK 20 — ns
No START
condition is
detected when 1
tMCLK is used at
reception.
STOP condition
detection tSU;STO SCL,
SDA 2 tMCLK 20 — ns
No STOP condition
is detected when 1
tMCLK is used at
reception.
RESTART
condition detection
condition tSU;STA SCL,
SDA 2 tMCLK 20 — ns
No RESTART
condition is
detected when 1
tMCLK is used at
reception.
Bus free time tBUF SCL,
SDA 2 tMCLK 20 — ns At reception
Data hold time tHD;DAT SCL,
SDA 2 tMCLK 20 — ns At slave
transmission mode
Data setup time tSU;DAT SCL,
SDA tLOW 3 tMCLK 20 — ns At slave
transmission mode
Data hold time tHD;DAT SCL,
SDA 0 — ns At recept ion
Data setup time tSU;DAT SCL,
SDA tMCLK 20 — ns At reception
SDA SCL
(with wakeup
function in use) tWAKEUP SCL,
SDA
Oscillation
stabilization wait time
2 tMCLK 20 —ns
MB95630H Series
Document Number: 002-04627 Rev. *A Page 83 of 102
18.4.9 UART/SIO, Serial I/O Timing (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C)
*: See “Source Clock/Machine Clock” for tMCLK.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC UCK0
Internal clock operation
4 tMCLK*— ns
UCK UO time tSLOV UCK0, UO0 190 190 ns
Valid UI UCK tIVSH UCK0, UI0 2 tMCLK*— ns
UCK valid UI hold time tSHIX UCK0, UI0 2 tMCLK*— ns
Serial clock “H” pulse width tSHSL UCK0
External clock operation
4 tMCLK*— ns
Serial clock “L” pulse width tSLSH UCK0 4 tMCLK*— ns
UCK UO time tSLOV UCK0, UO0 — 190 ns
Valid UI UCK tIVSH UCK0, UI0 2 tMCLK*— ns
UCK valid UI hold time tSHIX UCK0, UI0 2 tMCLK*— ns
0.2 V
CC
0.2 V
CC
0.8 V
CC
t
SLOV
t
IVSH
t
SHIX
0.8 V
CC
0.2 V
CC
UCK0
UO0
UI0
0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
t
SCYC
• Internal shift clock mode
MB95630H Series
Document Number: 002-04627 Rev. *A Page 84 of 102
18.4.10 MPG Input Timing (VCC = 5.0 V10%, VSS = 0.0 V, TA = 40°C to 85°C)
18.4.11 Comp arator Timing (VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = 40°C to 85°C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Max
Input pulse width tTIWH,
tTIWL SNI0 to SNI2,
DTTI —4 t
MCLK —ns
Parameter Pin name Value Unit Remarks
Min Typ Max
Voltage range CMP0_P,
CMP0_N 0—V
CC 1.3 V
Offset voltage CMP0_P,
CMP0_N 15 — 15 mV
Delay time CMP0_O — 650 1200 ns Overdrive 5 mV
— 140 420 ns Overdrive 50 mV
Power down delay CMP0_O — — 1200 ns Powe r do wn recove ry
PD: 1 0
Power up
stabilization time CMP0_O — — 1200 ns Output stabilization time at power up
t
SLOV
t
IVSH
t
SHIX
0.8 V
CC
0.2 V
CC
UCK0
UO0
UI0
0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
0.2 V
CC
0.2 V
CC
0.8 V
CC
0.8 V
CC
t
SLSH
t
SHSL
• External shift clock mode
0.8 VCC
SNI0 to SNI2, DTTI
0.8 VCC
0.2 VCC 0.2 VCC
tTIWH tTIWL
MB95630H Series
Document Number: 002-04627 Rev. *A Page 85 of 102
18.5 A/D Converter
18.5.1 A/D Converter Electrical Characteristics (VCC = 2.7 V to 5.5 V, VSS = 0.0 V, TA = 40°C to 85°C)
18.5.2 Notes on Using A/D Converter
• External impedance of analog input and its sampling time
The A/D converter of the MB95630H Series has a sample and hold circuit. If the external impedance is too high to
keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is
insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision stan-
dard, considering the relationship between the external impedance and minimum sampling time, either adjust the
register value a nd op er ating freq uen cy o r decr ease th e e xterna l imp eda nce so that the samp ling time is lo nge r than
the minimum value. In addition, if suff icient sampling tim e cannot be secured, connect a cap acitor of abo ut 0.1 µ F to
the analog input pin.
Parameter Symbol Value Unit Remarks
Min Typ Max
Resolution
—
——10bit
Total error 3—3LSB
Linearity error 2.5 — 2.5 LSB
Differential linearity
error 1.9 — 1.9 LSB
Zero transition
voltage V0T VSS 1.5 LSB VSS 0.5 LSB VSS 2.5 LSB V
Full-scale transition
voltage VFST VCC 4.5 LSB VCC 2 LSB VCC 0.5 LSB V
Compare time — 3 — 10 µs 2.7 V VCC 5.5 V
Sampling time — 0.941 — µs
2.7 V VCC 5.5 V,
with external
impedance 3.3 k
and external
capacitance = 10 pF
Analog input current IAIN 0.3 — 0.3 µA
Analog input voltage VAIN VSS —VCC V
Note: The values are reference values.
4.5 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.5 V
1.45 kΩ (Max)
2.7 kΩ (Max)
14.89 pF (Max)
VCC R C
14.89 pF (Max)
ComparatorAnalog input
During sampling: ON
RC
• Analog input equivalent circuit
MB95630H Series
Document Number: 002-04627 Rev. *A Page 86 of 102
• A/D conversion error
As |VCC VSS| decreases, the A/D conversion error increases proportionately.
[External impedance = 0 kΩ to 100 kΩ]
External impedance [kΩ]
Minimum sampling time [μs]
02468101214161820
100
80
60
40
20
0
[External impedance = 0 kΩ to 20 kΩ]
External impedance [kΩ]
Minimum sampling time [μs]
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
20
15
10
5
0
Note: External capacitance = 10 pF
• Relationship between external impedance and minimum sampling time
MB95630H Series
Document Number: 002-04627 Rev. *A Page 87 of 102
18.5.3 Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation th at can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point
(“0000000000” “0000000001”) of a device to the full-scale transition point (“1111111111” “1111111110”) of
the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero tran-
sition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
VFST
Ideal I/O characteristics
0x001
0x002
0x003
0x004
0x3FD
0x3FE
0x3FF
Digital output
Digital output
2 LSB
V0T
1 LSB
0.5 LSB
Total error
Analog inputAnalog input
0x001
0x002
0x003
0x004
0x3FD
0x3FE
0x3FF
Actual conversion
characteristic
Ideal characteristic
Actual conversion
characteristic
N
VNT
: A/D converter digital output value
: Voltage at which the digital output transits from 0x(N − 1) to 0xN
{1
LSB
×
(N
−
1)
+
0.5
LSB}
VNT
Total error of digital output N VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB LSB=
VCC − VSS
1024 V1 LSB =
VSS VCC VSS VCC
MB95630H Series
Document Number: 002-04627 Rev. *A Page 88 of 102
Zero transition error
Linearity error
Full-scale transition error
0x001
0x002
0x003
0x004
0x3FD
0x3FE
0x3FF
Digital output
Differential linearity error of digital output N V(N+1)T − VNT
1 LSB − 1=
Linearity error of digital output N VNT − {1 LSB × N + V0T}
1 LSB
=
Digital output
Analog input
0x001
0x002
0x3FC
0x3FD
0x003
0x3FE
0x3FF
0x004
Actual conversion
characteristic
Actual conversion
characteristic
V0T (measurement value)
Actual conversion
characteristic
Actual conversion
characteristic
VFST
(measurement
value)
VSS VCC
VSS VCC VSS VCC
VSS VCC
Analog input
Digital output
Analog input
Ideal characteristic
{1 LSB × N + V0T}
Actual conversion
characteristic
Ideal
characteristic
Actual conversion
characteristic
V0T (measurement value)
VFST
(measurement
value)
VNT
Differential linearity error
0x(N−2)
0x(N−1)
0xN
0x(N+1)
Digital output
Analog input
Actual conversion
characteristic
Ideal characteristic
VNT
Actual conversion
characteristic V(N+1)T
N
VNT
: A/D converter digital output value
: Voltage at which the digital output transits from 0x(N − 1) to 0xN
V0T (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC − 2 LSB [V]
Ideal
characteristic
MB95630H Series
Document Number: 002-04627 Rev. *A Page 89 of 102
18.6 Flash Memory Program/Erase Characteristics
*1:VCC = 5.5 V, TA = 25°C, 0 cycle
*2:VCC = 2.4 V, TA = 85°C, 100000 cycles
*3:These values were converted from the result of a techno logy reliability assessment. (T hese values were converted
from the result of a high temperature accelerated test using the Arrhenius equation with the average temperature
being 85°C.)
Parameter Value Unit Remarks
Min Typ Max
Sector erase tim e
(2 Kbyte sector) —0.3*
11.6*2s The time of writing “0x00” prior to erasure is exclud ed.
Sector erase tim e
(32 Kbyte sector) —0.6*
13.1*2s The time of writing “0x00” prior to erasure is exclud ed.
Byte writing time — 17 272 µs System-level overhead is excluded.
Program/erase cycle 100000 — — cycle
Power supply voltage
at program/erase 2.4 — 5.5 V
Flash memory data
retention time
20*3——
year
Aver age TA = 85°C
Number of program/erase cycles: 1000 or below
10*3—— A verage T A = 85°C
Number of program/erase cycles: 1001 to 10000
inclusive
5*3—— Av erage TA = 85°C
Number of program/erase cycles: 10001 or above
MB95630H Series
Document Number: 002-04627 Rev. *A Page 90 of 102
19. Sample Characteristics
• Power supply current temperature characteristics
0
5
10
15
1234567
ICC[mA]
VCC[V]
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
ICC VCC
TA 25C, FMP 2, 4 , 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
0
5
10
15
−500+50 +100 +150
ICC[mA]
TA[°C]
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
0
2
1
3
4
5
6
1234567
ICCS[mA]
VCC[V]
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
0
2
1
3
4
5
6
−500−50 +100 +150
I
CCS
[mA]
T
A
[°C]
F
MP
= 16 MHz
F
MP
= 10 MHz
F
MP
= 8 MHz
F
MP
= 4 MHz
F
MP
= 2 MHz
0
20
80
60
40
140
120
100
1234567
ICCL[μA]
VCC[V]
0
20
80
60
40
140
120
100
−50 0 +50 +100 +150
ICCL[μA]
TA[°C]
ICC TA
VCC 5.5 V, F MP 2, 4, 8, 10, 1 6 MHz (divided by 2)
Main clock mode with the external clock operating
ICCS VCC
TA 25C, FMP 2, 4 , 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
ICCS TA
VCC 5.5 V, FMP 2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
ICCL VCC
TA 25C, FMPL 16 kHz (divided by 2)
Subclock mode with the external clock operating
ICCL TA
VCC 5.5 V, FMPL 16 kHz (divided by 2)
Subclock mode with the external clock operating
MB95630H Series
Document Number: 002-04627 Rev. *A Page 91 of 102
0
2
8
6
4
20
18
16
14
12
10
−50 0+50 +100 +150
ICCT[μA]
TA[°C]
ICCT TA
VCC 5.5 V, FMPL 16 kHz (divided by 2)
Watch mode with the external clock operating
0
10
20
30
−50 0+50 +100 +150
ICCLS[μA]
TA[°C]
ICCLS TA
VCC 5.5 V, FMPL 16 kHz (divided by 2)
Subsleep mode with the external clock operating
0
10
20
30
1234567
ICCLS[μA]
VCC[V]
0
2
8
6
4
20
18
16
14
12
10
1234567
ICCT[μA]
VCC[V]
0
200
100
300
400
500
600
1234567
ICCTS[μA]
VCC[V]
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
0
200
100
300
400
500
600
−50 0+50 +100 +150
ICCTS[μA]
TA[°C]
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
ICCLS VCC
TA 25C, FMPL 16 kHz (divided by 2)
Subsleep mode with the external clock o perating
ICCT VCC
TA 25C, FMPL 16 kHz (divided by 2)
Watch mode with the external clock operating
ICCTS VCC
TA 25C, FMP 2, 4 , 8, 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock
operating
ICCTS TA
VCC 5.5 V, F MP 2, 4, 8, 10, 1 6 MHz (divided by 2)
Time-base timer mode with the external clock
operating
MB95630H Series
Document Number: 002-04627 Rev. *A Page 92 of 102
0
8
4
12
16
20
−50 0+50 +100 +150
ICCH[μA]
TA[°C]
ICCH TA
VCC 5.5 V, FMPL (stop)
Substop mode with the external clock stopping
0
8
4
12
16
20
1234567
ICCH[μA]
VCC[V]
0
8
6
4
2
10
1234567
ICCMCR[mA]
VCC[V]
0
8
6
4
2
10
−50 0+50 +100 +150
ICCMCR[mA]
TA[°C]
0
8
6
4
2
10
1234567
ICCMPLL[mA]
VCC[V]
0
8
6
4
2
10
−50 0+50 +100 +150
ICCMPLL[mA]
TA[°C]
ICCH VCC
TA 25C, FMPL (stop)
Substop mode with the external clock stopping
ICCMCR VCC
TA 25C, FMP 4 MHz (no division)
Main CR clock mode
ICCMCR TA
VCC 5.5 V, FMP 4 MHz (no division)
Main CR clock mode
ICCMPLL VCC
TA 25C, FMP 16 MHz (PLL multiplication rate: 4)
Main CR PLL clock mode
ICCMPLL TA
VCC 5.5 V, FMP 16 MHz (PLL multiplication rate: 4)
Main CR PLL clock mode
MB95630H Series
Document Number: 002-04627 Rev. *A Page 93 of 102
0
150
100
50
200
−50 0+50 +100 +150
ICCSCR[μA]
TA[°C]
ICCSCR TA
VCC 5.5 V, FMPL 50 kHz (divided by 2)
Sub-CR clock mode
0
150
100
50
200
1234567
ICCSCR[μA]
VCC[V]
ICCSCR VCC
TA 25C, FMPL 50 kHz (divided by 2)
Sub-CR clock mode
MB95630H Series
Document Number: 002-04627 Rev. *A Page 94 of 102
• Input voltage characteristics
0
1
2
4
5
234567
V
IHI
/V
ILI
[V]
V
CC
[V]
3
V
IHI
V
ILI
0
1
2
4
5
234567
V
IHS
/V
ILS
[V]
V
CC
[V]
3
V
IHS
V
ILS
VIHI VCC and VILI VCC
TA 25CVIHS VCC and VILS VCC
TA 25C
0
1
2
4
5
234567
V
IHM
/V
ILM
[V]
V
CC
[V]
3
V
IHM
V
ILM
VIHM VCC and VILM VCC
TA 25C
MB95630H Series
Document Number: 002-04627 Rev. *A Page 95 of 102
• Output voltage characteristics
0.0
0.2
0.4
0.8
1.4
1.2
1.0
0−2−1−3−5−7−9−4−6−8−10 −11 −12 −13 −14 −15
VCC − VOH2[V]
IOH[mA]
0.6
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
(VCC VOH2) IOH
TA 25C
VOL1 IOL
TA 25C
0.0
0.2
0.4
0.8
1.4
1.2
1.0
0−2−1−3−5−7−9−4−6−8−10 −11 −12 −13 −14 −15
VCC − VOH1[V]
IOH[mA]
0.6
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
(VCC VOH1) IOH
TA 25C
0.0
0.2
0.4
0.8
1.0
02135794 6 8 101112131415
VOL2[V]
IOL[mA]
0.6
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VOL2 IOL
TA 25C
0.0
0.2
0.4
0.8
1.4
1.2
1.0
02135794 6 8 101112131415
VOL1[V]
IOL[mA]
0.6
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.5 V
VCC = 4.0 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
MB95630H Series
Document Number: 002-04627 Rev. *A Page 96 of 102
• Pull-up charac teristics
0
50
100
150
200
123456
RPULL[kΩ]
VCC[V]
RPULL VCC
TA 25C
MB95630H Series
Document Number: 002-04627 Rev. *A Page 97 of 102
20. Mask Options
21. Ordering Information
No. Part number
MB95F632H
MB95F633H
MB95F634H
MB95F636H
MB95F632K
MB95F633K
MB95F634K
MB95F636K
Selectable/Fixed Fixed
1Low-voltage detection
reset Without low-voltage detection
reset With low-voltage detection reset
2Reset With dedicated res et inp u t Without dedicat ed res et input
Part number Package
MB95F632HPMC-G-SNE2
MB95F632KPMC-G-SNE2
MB95F633HPMC-G-SNE2
MB95F633KPMC-G-SNE2
MB95F634HPMC-G-SNE2
MB95F634KPMC-G-SNE2
MB95F636HPMC-G-SNE2
MB95F636KPMC-G-SNE2
MB95F636KPMC-G-UNE2
32-pin plastic LQFP
(FPT-32P-M30)
MB95F632HP-G-SH-SNE2
MB95F632KP-G-SH-SNE2
MB95F633HP-G-SH-SNE2
MB95F633KP-G-SH-SNE2
MB95F634HP-G-SH-SNE2
MB95F634KP-G-SH-SNE2
MB95F636HP-G-SH-SNE2
MB95F636KP-G-SH-SNE2
32-pin plastic SH-DIP
(DIP-32P-M06)
MB95F632HWQN-G-SNE1
MB95F632KWQN-G-SNE1
MB95F633HWQN-G-SNE1
MB95F633KWQN-G-SNE1
MB95F634HWQN-G-SNE1
MB95F634KWQN-G-SNE1
MB95F636HWQN-G-SNE1
MB95F636KWQN-G-SNE1
32-pin plastic QFN
(LCC-32P-M19)
MB95630H Series
Document Number: 002-04627 Rev. *A Page 98 of 102
22. Package Dimension
32-pin plastic LQFP Lead pitch 0.80 mm
Package width ×
package length 7.00 mm × 7.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 1.60 mm MAX
32-pin plastic LQFP
(FPT-32P-M30)
(FPT-32P-M30)
C
7.00±0.10(.276±.004)SQ
0.80(.031)
"A"
0.10(.004)
9.00±0.20(.354±.008)SQ
18
1724
9
16
25
32
INDEX
0~7°
0.60±0.15
(.024±.006)
0.25(.010)
0.10±0.05
(.004±.002)
Details of "A" part
0.10(.004)
*
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F32051S-c-1-2
0.20(.008) M
0.35+0.08
–0.03
+.003
–.001
.014
0.13 +0.05
–0.00
+.002
–.000
.005
(.063) MAX
1.60 MAX (Mounting height)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
MB95630H Series
Document Number: 002-04627 Rev. *A Page 99 of 102
32-pin plastic SDIP Lead pitch 1.778 mm
Low space 10.16 mm
Sealing method
Plastic mold
32-pin plastic SDIP
(DIP-32P-M06)
(DIP-32P-M06)
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED D32018S-c-1-3
(.350±.010)
*8.89±0.25
1.778(.070)
1.27(.050)
10.16(.400)
INDEX
*28.00
1.102
+0.20
–
0.30
–
.012
+.008
4.70
.185
+0.70
–
0.20
–
.008
+.028
3.30
.130
+0.20
–
0.30
–
.012
+.008
MAX.
1.02
.040
–
0.20
–
.008
+.012
+0.30
MIN.
0.51(.020)
0~15°
M
0.25(.010)
.019
0.48
+0.08
+.003
–
.005
–
0.12
0.27
.011–
.003
–
0.07
+.001
+0.03
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
MB95630H Series
Document Number: 002-04627 Rev. *A Page 100 of 102
32-pin plastic QFN Lead pitch 0.50 mm
Package width ×
package length 5.00 mm × 5.00 mm
Sealing method Plastic mold
Mounting height 0.80 mm MAX
Weight 0.06 g
32-pin plastic QFN
(LCC-32P-M19)
(LCC-32P-M19)
(.010 )
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED C32071S-c-1-2
(.197±.004)
5.00±0.10
5.00±0.10
(.197±.004)
(3-R0.20)
((3-R.008))
0.50(.020) 1PIN CORNER
(C0.30(C.012))
0.75±0.05
(0.20(.008))
INDEX AREA
0.40±0.05
(.016±.002)
+0.03
–0.02
–.001
+.001
0.02
(.001 )
(.138±.004)
3.50±0.10
3.50±0.10
(.138±.004)
(TYP)
(.030±.002)
+0.05
–0.07
–.003
+.002
0.25
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB95630H Series
Document Number: 002-04627 Rev. *A Page 101 of 102
23. Major Changes In This Edition
Spansion Publication Number: DS702-00009-3v0-E
NOTE: Please see “Document History” about later revised information.
Document History Page
Page Section Details
22 ■PIN CONNECTION
•C pin Corrected the following statement.
The bypass capacitor for the VCC pin must have a
capacitance larger than CS.
The decoupling capacitor for the VCC pin must have a
capacitance equal to or larger than the capacitance of CS.
66 ■ELECTRICAL CHARACTERISTICS
2. Recommended Operating Conditions Corrected the following statement in remark *2.
The bypass capacitor for the VCC pin must have a
capacitance larger than CS.
The decoupling capacitor for the VCC pin must have a
capacitance equal to or larger than the capacitance of CS.
71 4. AC Characteristics
(1) Clock Timing Corrected the pin names of the parameter “Input clock
rising time and falling time”.
X0 X0, X0A
X0, X1 X0, X1, X0A, X1A
Document Title: MB95630H Series, New 8FX 8-bit Microcontrollers
Document Number: 002-04627
Revision ECN Orig. of
Change Submission
Date Description of Change
** - AKIH 06/07/2013 Migrated to Cypress and assigned document number 002-04627.
No change to document contents or format.
*A 5193921 AKIH 03/29/2016 Updated to Cypress template
Added “MB95F636KPMC-G-UNE2” in “Ordering Information”
Document Number: 002-04627 Rev. *A Revi sed March 29, 2016 Page 102 of 102
MB95630H Series
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