Dual Channel, 128-/256-Position, SPI, Nonvolatile Digital Potentiometer AD5122/AD5142 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VLOGIC 10 k and 100 k resistance options Resistor tolerance: 8% maximum Wiper current: 6 mA Low temperature coefficient: 35 ppm/C Wide bandwidth: 3 MHz Fast start-up time < 75 s Linear gain setting mode Single- and dual-supply operation Independent logic supply: 1.8 V to 5.5 V Wide operating temperature: -40C to +125C 3 mm x 3 mm package option 4 kV ESD protection VDD POWER-ON RESET RDAC1 INPUT REGISTER 1 SCLK SDI INPUT REGISTER 2 A2 W2 B2 EEPROM MEMORY 10880-001 SDO VSS Figure 1. GENERAL DESCRIPTION Table 1. Family Models The AD5122/AD5142 potentiometers provides a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of 8% and up to 6 mA current density in the Ax, Bx, and Wx pins. Model AD5123 1 AD5124 AD5124 AD51431 AD5144 AD5144 AD5144A AD5122 AD5122A AD5142 AD5142A AD5121 AD5141 The low wiper resistance of only 40 at the ends of the resistor array allows for pin-to-pin connection. RDAC2 7/8 SYNC Portable electronics level adjustment LCD panel brightness and contrast controls Programmable filters, delays, and time constants Programmable power supplies The high bandwidth and low total harmonic distortion (THD) ensure optimal performance for ac signals, making these devices suitable for filter design. A1 W1 B1 SERIAL INTERFACE GND The linear gain setting mode allows independent programming of the resistance between the digital potentiometer terminals, through the RAW and RWB string resistors, allowing very accurate resistor matching. AD5122/ AD5142 RESET APPLICATIONS The low resistor tolerance and low nominal temperature coefficient simplify open-loop applications as well as applications requiring tolerance matching. INDEP 1 Channel Quad Quad Quad Quad Quad Quad Quad Dual Dual Dual Dual Single Single Position 128 128 128 256 256 256 256 128 128 256 256 128 256 Interface I2 C SPI/I2C SPI I2 C SPI/I2C SPI I2 C SPI I2 C SPI I2 C SPI/I2C SPI/I2C Package LFCSP LFCSP TSSOP LFCSP LFCSP TSSOP TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP LFCSP Two potentiometers and two rheostats. The wiper values can be set through an SPI-compatible digital interface that is also used to read back the wiper register and EEPROM contents. The AD5122/AD5142 is available in a compact, 16-lead, 3 mm x 3 mm LFCSP and a 16-lead TSSOP. The parts are guaranteed to operate over the extended industrial temperature range of -40C to +125C. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5122/AD5142 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 20 Applications ....................................................................................... 1 RDAC Register and EEPROM .................................................. 20 Functional Block Diagram .............................................................. 1 Input Shift Register .................................................................... 20 General Description ......................................................................... 1 SPI Serial Data Interface ............................................................ 20 Revision History ............................................................................... 2 Advanced Control Modes ......................................................... 23 Specifications..................................................................................... 3 EEPROM or RDAC Register Protection ................................. 24 Electrical Characteristics--AD5122 .......................................... 3 INDEP Pin................................................................................... 24 Electrical Characteristics--AD5142 .......................................... 6 RDAC Architecture .................................................................... 27 Interface Timing Specifications .................................................. 9 Programming the Variable Resistor ......................................... 27 Shift Register and Timing Diagrams ....................................... 10 Programming the Potentiometer Divider ............................... 28 Absolute Maximum Ratings .......................................................... 11 Terminal Voltage Operating Range ......................................... 28 Thermal Resistance .................................................................... 11 Power-Up Sequence ................................................................... 28 ESD Caution ................................................................................ 11 Layout and Power Supply Biasing ............................................ 28 Pin Configurations and Function Descriptions ......................... 12 Outline Dimensions ....................................................................... 29 Typical Performance Characteristics ........................................... 14 Ordering Guide .......................................................................... 30 Test Circuits ..................................................................................... 19 REVISION HISTORY 10/12--Revision 0: Initial Version Rev. 0 | Page 2 of 32 Data Sheet AD5122/AD5142 SPECIFICATIONS ELECTRICAL CHARACTERISTICS--AD5122 VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = -2.25 V to -2.75 V; VLOGIC = 1.8 V to 5.5 V, -40C < TA < +125C, unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS--RHEOSTAT MODE (ALL RDACs) Resolution Resistor Integral Nonlinearity 2 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance3 Bottom Scale or Top Scale Nominal Resistance Match DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity 4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 Symbol Test Conditions/Comments N R-INL Min Typ 1 Max 7 RAB = 10 k VDD 2.7 V VDD < 2.7 V RAB = 100 k VDD 2.7 V VDD < 2.7 V R-DNL RAB/RAB (RAB/RAB)/T x 106 RW Unit Bits -1 -2.5 0.1 1 +1 +2.5 LSB LSB -0.5 -1 -0.5 -8 +0.5 +1 +0.5 +8 Code = full scale Code = zero scale RAB = 10 k RAB = 100 k 0.1 0.25 0.1 1 35 LSB LSB LSB % ppm/C 55 130 125 400 RAB = 10 k RAB = 100 k Code = 0xFF -1 40 60 0.2 80 230 +1 % RAB = 10 k RAB = 100 k -0.5 -0.25 -0.25 0.1 0.1 0.1 +0.5 +0.25 +0.25 LSB LSB LSB RAB = 10 k RAB = 100 k -1.5 -0.5 -0.1 0.1 +0.5 LSB LSB RBS or RTS RAB1/RAB2 INL DNL VWFSE VWZSE (VW/VW)/T x 106 RAB = 10 k RAB = 100 k Code = half scale Rev. 0 | Page 3 of 32 1 0.25 5 1.5 0.5 LSB LSB ppm/C AD5122/AD5142 Parameter RESISTOR TERMINALS Maximum Continuous Current Terminal Voltage Range 5 Capacitance A, Capacitance B3 Capacitance W3 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUTS Output High Voltage3 Output Low Voltage3 Data Sheet Symbol Negative Supply Current EEPROM Store Current3, 6 EEPROM Read Current3, 7 Logic Supply Current Power Dissipation 8 Power Supply Rejection Ratio Min RAB = 10 k RAB = 100 k -6 -1.5 VSS Typ 1 Max Unit +6 +1.5 VDD mA mA V IA, IB, and IW CA, CB CW VINH f = 1 MHz, measured to GND, code = half scale RAB = 10 k RAB = 100 k f = 1 MHz, measured to GND, code = half scale RAB = 10 k RAB = 100 k VA = V W = V B -500 VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V 0.8 x VLOGIC 0.7 x VLOGIC VINL VHYST IIN CIN VOH VOL Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Logic Supply Range Positive Supply Current Test Conditions/Comments 25 12 pF pF 12 5 15 pF pF nA +500 0.2 x VLOGIC 0.1 x VLOGIC 1 5 RPULL-UP = 2.2 k to VLOGIC ISINK = 3 mA ISINK = 6 mA, VLOGIC > 2.3 V VLOGIC -1 0.4 0.6 +1 V V V A pF 5.5 2.75 VDD VDD V V V V 5.5 A nA A mA A nA W dB 2 VSS = GND IDD ISS IDD_EEPROM_STORE IDD_EEPROM_READ ILOGIC PDISS PSRR Single supply, VSS = GND Dual supply, VSS < GND VIH = VLOGIC or VIL = GND VDD = 5.5 V VDD = 2.3 V VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VDD/VSS = VDD 10%, code = full scale Rev. 0 | Page 4 of 32 2.3 2.25 1.8 2.25 -5.5 0.7 400 -0.7 2 320 1 3.5 -66 V V V V A pF 120 -60 Data Sheet Parameter DYNAMIC CHARACTERISTICS 9 Bandwidth Total Harmonic Distortion Resistor Noise Density VW Settling Time AD5122/AD5142 Symbol Test Conditions/Comments BW -3 dB RAB = 10 k RAB = 100 k VDD/VSS = 2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 k RAB = 100 k Code = half scale, TA = 25C, f = 10 kHz RAB = 10 k RAB = 100 k VA = 5 V, VB = 0 V, from zero scale to full scale, 0.5 LSB error band RAB = 10 k RAB = 100 k RAB = 10 k RAB = 100 k THD eN_WB tS Crosstalk (CW1/CW2) CT Analog Crosstalk Endurance 10 CTA Min TA = 25C Typ 1 MHz MHz -80 -90 dB dB 7 20 nV/Hz nV/Hz 2 12 10 25 -90 1 s s nV-sec nV-sec dB Mcycles kcycles Years 50 1 Unit 3 0.43 100 Data Retention 11 Max Typical values represent average readings at 25C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 x VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 s. 8 PDISS is calculated from (IDD x VDD) + (ILOGIC x VLOGIC). 9 All dynamic characteristics use VDD/VSS = 2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at -40C to +125C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 2 Rev. 0 | Page 5 of 32 AD5122/AD5142 Data Sheet ELECTRICAL CHARACTERISTICS--AD5142 VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = -2.25 V to -2.75 V; VLOGIC = 1.8 V to 5.5 V, -40C < TA < +125C, unless otherwise noted. Table 3. Parameter DC CHARACTERISTICS--RHEOSTAT MODE (ALL RDACs) Resolution Resistor Integral Nonlinearity 2 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance3 Bottom Scale or Top Scale Nominal Resistance Match DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity 4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 Symbol Test Conditions/Comments N R-INL Min Typ 1 Max 8 RAB = 10 k VDD 2.7 V VDD < 2.7 V RAB = 100 k VDD 2.7 V VDD < 2.7 V R-DNL RAB/RAB (RAB/RAB)/T x 106 RW Unit Bits -2 -5 0.2 1.5 +2 +5 LSB LSB -1 -2 -0.5 -8 0.1 0.5 0.2 1 35 +1 +2 +0.5 +8 LSB LSB LSB % ppm/C 55 130 125 400 -1 40 60 0.2 80 230 +1 % RAB = 10 k RAB = 100 k -1 -0.5 -0.5 0.2 0.1 0.2 +1 +0.5 +0.5 LSB LSB LSB RAB = 10 k RAB = 100 k -2.5 -1 -0.1 0.2 +1 LSB LSB Code = full scale Code = zero scale RAB = 10 k RAB = 100 k RBS or RTS RAB = 10 k RAB = 100 k Code = 0xFF RAB1/RAB2 INL DNL VWFSE VWZSE (VW/VW)/T x 106 RAB = 10 k RAB = 100 k Code = half scale Rev. 0 | Page 6 of 32 1.2 0.5 5 3 1 LSB LSB ppm/C Data Sheet Parameter RESISTOR TERMINALS Maximum Continuous Current Terminal Voltage Range 5 Capacitance A, Capacitance B3 Capacitance W3 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUTS Output High Voltage3 Output Low Voltage3 AD5122/AD5142 Symbol Negative Supply Current EEPROM Store Current3, 6 EEPROM Read Current3, 7 Logic Supply Current Power Dissipation 8 Power Supply Rejection Ratio Min RAB = 10 k RAB = 100 k -6 -1.5 VSS Typ 1 Max Unit +6 +1.5 VDD mA mA V IA, IB, and IW CA, CB CW VINH f = 1 MHz, measured to GND, code = half scale RAB = 10 k RAB = 100 k f = 1 MHz, measured to GND, code = half scale RAB = 10 k RAB = 100 k VA = V W = V B -500 VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V 0.8 x VLOGIC 0.7 x VLOGIC VINL VHYST IIN CIN VOH VOL Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Logic Supply Range Positive Supply Current Test Conditions/Comments 25 12 pF pF 12 5 15 pF pF nA +500 0.2 x VLOGIC 0.1 x VLOGIC 1 5 RPULL-UP = 2.2 k to VLOGIC ISINK = 3 mA ISINK = 6 mA, VLOGIC > 2.3 V VLOGIC -1 0.4 0.6 +1 V V V A pF 5.5 2.75 VDD VDD V V V V 5.5 A nA A mA A nA W dB 2 VSS = GND IDD ISS IDD_EEPROM_STORE IDD_EEPROM_READ ILOGIC PDISS PSRR Single supply, VSS = GND Dual supply, VSS < GND VIH = VLOGIC or VIL = GND VDD = 5.5 V VDD = 2.3 V VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VDD/VSS = VDD 10%, code = full scale Rev. 0 | Page 7 of 32 2.3 2.25 1.8 2.25 -5.5 0.7 400 -0.7 2 320 1 3.5 -66 V V V V A pF 120 -60 AD5122/AD5142 Parameter DYNAMIC CHARACTERISTICS 9 Bandwidth Total Harmonic Distortion Resistor Noise Density VW Settling Time Data Sheet Symbol Test Conditions/Comments BW -3 dB RAB = 10 k RAB = 100 k VDD/VSS = 2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 k RAB = 100 k Code = half scale, TA = 25C, f = 10 kHz RAB = 10 k RAB = 100 k VA = 5 V, VB = 0 V, from zero scale to full scale, 0.5 LSB error band RAB = 10 k RAB = 100 k RAB = 10 k RAB = 100 k THD eN_WB tS Crosstalk (CW1/CW2) CT Analog Crosstalk Endurance 10 CTA Min TA = 25C Typ 1 MHz MHz -80 -90 dB dB 7 20 nV/Hz nV/Hz 2 12 10 25 -90 1 s s nV-sec nV-sec dB Mcycles kcycles Years 50 1 Unit 3 0.43 100 Data Retention 11 Max Typical values represent average readings at 25C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 x VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 s. 8 PDISS is calculated from (IDD x VDD) + (ILOGIC x VLOGIC). 9 All dynamic characteristics use VDD/VSS = 2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at -40C to +125C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 2 Rev. 0 | Page 8 of 32 Data Sheet AD5122/AD5142 INTERFACE TIMING SPECIFICATIONS VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. SPI Interface Parameter 1 t1 t2 t3 Test Conditions/Comments VLOGIC > 1.8 V VLOGIC = 1.8 V VLOGIC > 1.8 V VLOGIC = 1.8 V VLOGIC > 1.8 V VLOGIC = 1.8 V t4 t5 t6 t7 t8 2 t9 3 t10 Min 20 30 10 15 10 15 10 5 5 10 20 Typ Max 50 500 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Description SCLK cycle time SCLK high time SCLK low time SYNC-to-SCLK falling edge setup time Data setup time Data hold time SYNC rising edge to next SCLK fall ignored Minimum SYNC high time SCLK rising edge to SDO valid SYNC rising edge to SDO pin disable 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Refer to tEEPROM_PROGRAM and tEEPROM_READBACK for memory commands operations (see Table 5). 3 RPULL_UP = 2.2 k to VDD with a capacitance load of 168 pF. 2 Table 5. Control Pins Parameter t1 tEEPROM_PROGRAM 1 tEEPROM_READBACK tPOWER_UP 2 tRESET 1 2 Min 0.1 Typ 15 7 30 Max 10 50 30 75 Unit s ms s s s Description RESET low time Memory program time (not shown in Figure 5) Memory readback time (not shown in Figure 5) Start-up time (not shown in Figure 5) Reset EEPROM restore time (not shown in Figure 5) EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles. Maximum time after VDD - VSS is equal to 2.3 V. Rev. 0 | Page 9 of 32 AD5122/AD5142 Data Sheet SHIFT REGISTER AND TIMING DIAGRAMS C3 C2 C1 C0 A2 A3 A1 DB8 DB7 A0 D7 DB0 (LSB) D6 D5 D4 D3 D2 D0 D1 10880-002 DB15 (MSB) DATA BITS ADDRESS BITS CONTROL BITS Figure 2. Input Shift Register Contents t4 t1 t2 t7 SCLK t3 t8 SYNC t5 t6 SDI C3 C2 C1 C0 D7 D6 D5 SDO C3* C2* C1* C0* D7* D6* D5* D2 D1 D0 D2* D1* D0* t9 10880-003 t10 *PREVIOUS COMMAND RECEIVED. Figure 3. SPI Serial Interface Timing Diagram, CPOL = 0, CPHA = 1 t4 t1 t2 t7 SCLK t3 t8 SYNC t5 t6 C3 C2 C1 C0 D7 D6 D5 SDO C3* C2* C1* C0* D7* D6* D5* D2 D1 D0 D2* D1* D0* t9 t10 10880-004 SDI *PREVIOUS COMMAND RECEIVED. Figure 4. SPI Serial Interface Timing Diagram, CPOL = 1, CPHA = 0 SCLK t1 RESET Figure 5. Control Pins Timing Diagram Rev. 0 | Page 10 of 32 10880-005 SYNC Data Sheet AD5122/AD5142 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 6. Parameter VDD to GND VSS to GND VDD to VSS VLOGIC to GND VA, VW, VB to GND IA, IW, IB Pulsed 1 Frequency > 10 kHz RAW = 10 k RAW = 100 k Frequency 10 kHz RAW = 10 k RAW = 100 k Digital Inputs Operating Temperature Range, TA 3 Maximum Junction Temperature, TJ Maximum Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation ESD 4 FICDM Rating -0.3 V to +7.0 V +0.3 V to -7.0 V 7V -0.3 V to VDD + 0.3 V or +7.0 V (whichever is less) VSS - 0.3 V, VDD + 0.3 V or +7.0 V (whichever is less) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE JA is defined by the JEDEC JESD51 standard, and the value is dependent on the test board and test environment. Table 7. Thermal Resistance Package Type 16-Lead LFCSP 16-Lead TSSOP 6 mA/d 2 1.5 mA/d2 1 6 mA/d2 1.5 mA/d2 -0.3 V to VLOGIC + 0.3 V or +7 V (whichever is less) -40C to +125C 150C JA 89.51 150.41 JEDEC 2S2P test board, still air (0 m/sec airflow). ESD CAUTION -65C to +150C 260C 20 sec to 40 sec (TJ max - TA)/JA 4 kV 1.5 kV 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 d = pulse duty factor. 3 Includes programming of EEPROM memory. 4 Human body model (HBM) classification. Rev. 0 | Page 11 of 32 JC 3 27.6 Unit C/W C/W AD5122/AD5142 Data Sheet 14 SYNC PIN 1 INDICATOR VSS 5 12 SDI 11 SCLK 10 VLOGIC 9 VDD B2 8 TOP VIEW (Not to Scale) W2 7 B1 4 A2 6 W1 3 AD5122/ AD5142 A1 2 NOTES 1. INTERNALLY CONNECT THE EXPOSED PAD TO VSS. 10880-006 GND 1 13 SDO 16 RESET 15 INDEP PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 6. 16-Lead LFCSP Pin Configuration Table 8. 16-Lead LFCSP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mnemonic GND A1 W1 B1 VSS A2 W2 B2 VDD VLOGIC SCLK SDI SDO SYNC INDEP 16 RESET EPAD Description Ground Pin, Logic Ground Reference. Terminal A of RDAC1. VSS VA VDD. Wiper Terminal of RDAC1. VSS VW VDD. Terminal B of RDAC1. VSS VB VDD. Negative Power Supply. Decouple this pin with 0.1 F ceramic capacitors and 10 F capacitors. Terminal A of RDAC2. VSS VA VDD. Wiper Terminal of RDAC2. VSS VW VDD. Terminal B of RDAC2. VSS VB VDD. Positive Power Supply. Decouple this pin with 0.1 F ceramic capacitors and 10 F capacitors. Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 F ceramic capacitors and 10 F capacitors. Serial Clock Line. Data is clocked in at the logic low transition. Serial Data Input. Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor. Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register. Linear Gain Setting Mode at Power-Up. Each string resistor is loaded independently from its associated memory location. If INDEP is enabled, it cannot be disabled by software. Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is not used, tie RESET to VLOGIC. Internally Connect the Exposed Pad to VSS. Rev. 0 | Page 12 of 32 Data Sheet AD5122/AD5142 INDEP 1 16 SYNC RESET 2 15 SDO 14 SDI 13 SCLK 3 A1 4 W1 5 B1 6 AD5122/ AD5142 12 VLOGIC TOP VIEW (Not to Scale) 11 VDD VSS 7 10 B2 A2 8 9 W2 10880-007 GND Figure 7. 16-Lead TSSOP, SPI Interface Pin Configuration Table 9. 16-Lead TSSOP, SPI Interface Pin Function Descriptions Pin No. 1 Mnemonic INDEP 2 RESET 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND A1 W1 B1 VSS A2 W2 B2 VDD VLOGIC SCLK SDI SDO SYNC Description Linear Gain Setting Mode at Power-Up. Each string resistor is loaded independently from its associated memory location. If INDEP is enabled, it cannot be disabled by software. Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is not used, tie RESET to VLOGIC. Ground Pin, Logic Ground Reference. Terminal A of RDAC1. VSS VA VDD. Wiper Terminal of RDAC1. VSS VW VDD. Terminal B of RDAC1. VSS VB VDD. Negative Power Supply. Decouple this pin with 0.1 F ceramic capacitors and 10 F capacitors. Terminal A of RDAC2. VSS VA VDD. Wiper Terminal of RDAC2. VSS VW VDD. Terminal B of RDAC2. VSS VB VDD. Positive Power Supply. Decouple this pin with 0.1 F ceramic capacitors and 10 F capacitors. Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 F ceramic capacitors and 10 F capacitors. Serial Clock Line. Data is clocked in at the logic low transition. Serial Data Input. Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor. Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register. Rev. 0 | Page 13 of 32 AD5122/AD5142 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.2 10k, +125C 10k, +25C 10k, -40C 100k, +125C 100k, +25C 100k, -40C 0.4 0.3 0.1 0 R-DNL (LSB) R-INL (LSB) 0.2 0.1 0 -0.1 -0.1 -0.2 -0.3 -0.2 -0.4 -0.3 100 0 200 CODE (Decimal) -0.6 10880-008 -0.5 10k, +125C 10k, +25C 10k, -40C 100k, +125C 100k, +25C 100k, -40C 100 0 200 CODE (Decimal) Figure 8. R-INL vs. Code (AD5142) 10880-011 -0.5 -0.4 Figure 11. R-DNL vs. Code (AD5142) 0.20 0.10 0.15 0.05 0.10 0 R-DNL (LSB) R-INL (LSB) 0.05 0 -0.05 -0.05 -0.10 -0.15 -0.10 10k, +125C 10k, +25C 10k, -40C 100k, +125C 100k, +25C 100k, -40C -0.25 0 -0.25 50 100 -0.30 CODE (Decimal) 10k, +125C 10k, +25C 10k, -40C 0 100 Figure 12. R-DNL vs. Code (AD5122) 0.10 10k, -40C 10k, +25C 10k, +125C 100k, -40C 100k, +25C 100k, +125C 0.2 50 CODE (Decimal) Figure 9. R-INL vs. Code (AD5122) 0.3 100k, +125C 100k, +25C 100k, -40C 10880-012 -0.20 -0.20 10880-009 -0.15 0.05 0 DNL (LSB) 0 -0.05 -0.10 -0.15 -0.1 -0.20 -0.2 -0.3 0 100 CODE (Decimal) 200 -0.30 10k, -40C 10k, +25C 10k, +125C 0 100 CODE (Decimal) Figure 13. DNL vs. Code (AD5142) Figure 10. INL vs. Code (AD5142) Rev. 0 | Page 14 of 32 100k, -40C 100k, +25C 100k, +125C 200 10880-013 -0.25 10880-010 INL (LSB) 0.1 Data Sheet AD5122/AD5142 0.15 0.06 10k, -40C 10k, +25C 10k, +125C 100k, -40C 100k, +25C 100k, +125C 0.10 100k, -40C 100k, +25C 100k, +125C 0.02 0 0.05 -0.02 DNL (LSB) INL (LSB) 10k, -40C 10k, +25C 10k, +125C 0.04 0 -0.04 -0.06 -0.05 -0.08 -0.10 -0.10 -0.14 10880-014 50 0 100 CODE (Decimal) 50 0 450 10k 100k 400 RHEOSTAT MODE TEMPERATURE COEFFICIENT (ppm/C) 350 300 250 200 150 100 50 350 300 250 200 150 100 50 0 0 -50 100 150 200 255 AD5142 50 75 CODE (Decimal) 100 127 AD5122 -50 Figure 15. Potentiometer Mode Temperature Coefficient ((VW/VW)/T x 106) vs. Code 0 50 100 150 200 255 AD5142 0 25 50 75 CODE (Decimal) 100 127 AD5122 Figure 18. Rheostat Mode Temperature Coefficient ((RWB/RWB)/T x 106) vs. Code 800 1200 VLOGIC = 1.8V VLOGIC = 2.3V VLOGIC = 3.3V VLOGIC = 5V VLOGIC = 5.5V 700 1000 ILOGIC CURRENT (A) 500 400 IDD, VDD = 2.3V IDD, VDD = 3.3V IDD, VDD = 5V ILOGIC, VLOGIC = 2.3V ILOGIC, VLOGIC = 3.3V ILOGIC, VLOGIC = 5V 300 200 0 -40 10 60 TEMPERATURE (C) 110 125 800 600 400 200 VDD = VLOGIC VSS = GND 100 10880-016 CURRENT (nA) 600 Figure 16. Supply Current vs. Temperature 0 0 1 2 3 4 5 INPUT VOLTAGE (V) Figure 19. ILOGIC Current vs. Digital Input Voltage Rev. 0 | Page 15 of 32 10880-018 50 25 10880-015 0 0 10880-019 POTENTIOMETER MODE TEMPERATURE COEFFICIENT (ppm/C) Figure 17. DNL vs. Code (AD5122) 100k 10k 400 100 CODE (Decimal) Figure 14. INL vs. Code (AD5122) 450 10880-017 -0.12 -0.15 AD5122/AD5142 Data Sheet 10 0 0x80 (0x40) 0 -10 0x40 (0x20) 0x20 (0x10) 0x20 (0x10) -20 0x10 (0x08) 0x10 (0x08) 0x8 (0x04) 0x8 (0x04) -30 -30 0x4 (0x02) GAIN (dB) GAIN (dB) -20 0x80 (0x40) -10 0x40 (0x20) 0x4 (0x02) 0x2 (0x01) -40 -50 -40 0x1 (0x00) 0x2 (0x01) 0x1 (0x00) 0x00 -60 0x00 -70 -50 -80 1k 10k 100k 1M 10M FREQUENCY (Hz) -90 10 10880-020 100 100 -50 0 1M 10M 10k 100k -10 -20 -60 -30 THD + N (dB) THD + N (dB) 100k Figure 23. 100 k Gain vs. Frequency vs. Code 10k 100k VDD/VSS = 2.5V VA = 1V rms VB = GND CODE = HALF SCALE NOISE FILTER = 22kHz 10k FREQUENCY (Hz) Figure 20. 10 k Gain vs. Frequency vs. Code -40 1k 10880-023 AD5142 (AD5122) AD5142 (AD5122) -60 10 -70 -80 -40 -50 -60 -70 -80 200 2k 20k 200k FREQUENCY (Hz) -90 0.001 10880-021 -100 20 Figure 21. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency 0.1 1 Figure 24. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude 10 VDD/VSS = 2.5V RAB = 10k 0 0 -10 -20 PHASE (Degrees) -20 -40 -60 -30 -40 -50 -60 -70 QUARTER SCALE MIDSCALE FULL-SCALE 100 1k -80 10k 100k 1M 10M FREQUENCY (Hz) -90 10 QUARTER SCALE MIDSCALE FULL-SCALE 100 VDD/VSS = 2.5V RAB = 100k 1k 10k 100k 1M FREQUENCY (Hz) Figure 25. Normalized Phase Flatness vs. Frequency, RAB = 100 k Figure 22. Normalized Phase Flatness vs. Frequency, RAB = 10 k Rev. 0 | Page 16 of 32 10880-025 -80 10880-022 PHASE (Degrees) 0.01 VOLTAGE (V rms) 20 -100 10 VDD/VSS = 2.5V fIN = 1kHz CODE = HALF SCALE NOISE FILTER = 22kHz 10880-024 -90 Data Sheet AD5122/AD5142 300 1.0 200 0.8 0.0015 0.6 0.0010 0.4 0.0005 0.2 100 0 2 1 4 3 5 VOLTAGE (V) 0 0 10880-026 0 -600 -500 -400 -300 -200 -100 0 10k + 0pF 10k + 75pF 10k + 150pF 10k + 250pF 100k + 0pF 100k + 75pF 100k + 150pF 100k + 250pF 200 300 400 500 600 VDD = 5V 10% AC VSS = GND, VA = 4V, VB = GND CODE = MIDSCALE -20 -30 6 5 4 -40 -50 -60 3 -70 2 -90 10 0 0 20 10 40 20 60 80 30 40 CODE (Decimal) 100 50 120 AD5142 60 AD5122 10880-027 0 100k 1M 10M 0.020 0.015 RELATIVE VOLTAGE (V) 0.6 0.5 0.4 0.3 0.2 0.1 0.010 0.005 0 -0.005 -0.010 5 10 TIME (s) 15 10880-028 0 Figure 28. Maximum Transition Glitch -0.020 0 500 1000 1500 TIME (ns) Figure 31. Digital Feedthrough Rev. 0 | Page 17 of 32 2000 10880-031 -0.015 0 -0.1 10k Figure 30. Power Supply Rejection Ratio (PSRR) vs. Frequency 0x80 TO 0x7F 100k 0x80 TO 0x7F 10k 0.7 1k FREQUENCY (Hz) Figure 27. Maximum Bandwidth vs. Code vs. Net Capacitance 0.8 100 10880-030 -80 1 RELATIVE VOLTAGE (V) 10k, RDAC1 100k, RDAC1 -10 PSRR (dB) BANDWIDTH (MHz) 7 100 Figure 29. Resistor Lifetime Drift 10 8 0 RESISTOR DRIFT (ppm) Figure 26. Incremental Wiper On Resistance vs. Positive Power Supply (VDD) 9 CUMULATIVE PROBABILITY 400 1.2 0.0020 PROBABILITY DENSITY 500 WIPER ON RESISTANCE () 0.0025 100k, V DD = 2.3V 100k, V DD = 2.7V 100k, V DD = 3V 100k, V DD = 3.6V 100k, V DD = 5V 100k, V DD = 5.5V 10k, VDD = 2.3V 10k, VDD = 2.7V 10k, VDD = 3V 10k, VDD = 3.6V 10k, VDD = 5V 10k, VDD = 5.5V 10880-029 600 AD5122/AD5142 7 10k 100k 6 THEORETICAL IMAX (mA) -20 -60 -80 -100 5 4 3 2 1 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 10880-032 GAIN (dB) -40 -120 10 10k 100k SHUTDOWN MODE ENABLED 0 0 50 100 0 25 50 75 CODE (Decimal) 150 200 250 AD5142 100 125 AD5122 Figure 33. Theoretical Maximum Current vs. Code Figure 32. Shutdown Isolation vs. Frequency Rev. 0 | Page 18 of 32 10880-033 0 Data Sheet Data Sheet AD5122/AD5142 TEST CIRCUITS Figure 34 to Figure 38 define the test conditions used in the Specifications section. NC VA IW V+ = VDD 10% VDD B V+ VMS ~ Figure 34. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) PSRR (dB) = 20 LOG W B 10880-034 NC = NO CONNECT A VMS PSS (%/%) = RSW = VDD% 0.1V ISW CODE = 0x00 W V+ B VMS B A = NC Figure 35. Potentiometer Divider Nonlinearity Error (INL, DNL) IW = VDD/RNOMINAL DUT W VW B RW = VMS1/IW NC = NO CONNECT 10880-036 VMS1 - VSS TO VDD Figure 38. Incremental On Resistance NC A 0.1V ISW 10880-038 W + V+ = VDD 1LSB = V+/2N 10880-035 DUT A Figure 36. Wiper Resistance Rev. 0 | Page 19 of 32 VMS VDD ) VMS% Figure 37. Power Supply Sensitivity and Power Supply Rejection Ratio (PSS, PSRR) DUT ( 10880-037 DUT A W AD5122/AD5142 Data Sheet THEORY OF OPERATION The AD5122/AD5142 digital programmable potentiometers are designed to operate as true variable resistors for analog signals within the terminal voltage range of VSS < VTERM < VDD. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register that allows unlimited changes of resistance settings. A secondary register (the input register) can be used to preload the RDAC register data. The RDAC register can be programmed with any position setting using the SPI interface (depending on the model). When a desirable wiper position is found, this value can be stored in the EEPROM memory. Thereafter, the wiper position is always restored to that position for subsequent power-ups. The storing of EEPROM data takes approximately 15 ms; during this time, the device is locked and does not acknowledge any new command, preventing any changes from taking place. RDAC REGISTER AND EEPROM The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with 0x80 (AD5142, 256 taps), the wiper is connected to half scale of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. It is possible to both write to and read from the RDAC register using the digital interface (see Table 10). The contents of the RDAC register can be stored to the EEPROM using Command 9 (see Table 16). Thereafter, the RDAC register always sets at that position for any future on-off-on power supply sequence. It is possible to read back data saved into the EEPROM with Command 3 (see Table 10). SPI SERIAL DATA INTERFACE The AD5122/AD5142 contain a 4-wire, SPI-compatible digital interface (SDI, SYNC, SDO, and SCLK). The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the SDI pin. Data is loaded in at the SCLK falling edge transition, as shown in Figure 3 and Figure 4. When SYNC returns high, the serial data-word is decoded according to the instructions in Table 16. To minimize power consumption in the digital input buffers when the part is enabled, operate all serial interface pins close to the VLOGIC supply rails. SYNC Interruption In a standalone write sequence for the AD5122/AD5142, the SYNC line is kept low for 16 falling edges of SCLK, and the instruction is decoded when SYNC is pulled high. However, if the SYNC line is kept low for less than 16 falling edges of SCLK, the input shift register content is ignored, and the write sequence is considered invalid. SDO Pin The serial data output pin (SDO) serves two purposes: to read back the contents of the control, EEPROM, RDAC, and input registers using Command 3 (see Table 10 and Table 16), and to connect the AD5122/AD5142 to daisy-chain mode. The SDO pin contains an internal open-drain output that needs an external pull-up resistor. The SDO pin is enabled when SYNC is pulled low, and the data is clocked out of SDO on the rising edge of SCLK, as shown in Figure 3 and Figure 4. Alternatively, the EEPROM can be written to independently using Command 11 (see Table 16). INPUT SHIFT REGISTER For the AD5122/AD5142, the input shift register is 16 bits wide, as shown in Figure 2. The 16-bit word consists of four control bits, followed by four address bits and by eight data bits. If the AD5122 RDAC or EEPROM registers are read from or written to, the lowest data bit (Bit 0) is ignored. Data is loaded MSB first (Bit 15). The four control bits determine the function of the software command as listed in Table 10 and Table 16. Rev. 0 | Page 20 of 32 Data Sheet AD5122/AD5142 Daisy-Chain Connection To prevent data from mislocking (for example, due to noise) the part includes an internal counter, if the clock falling edges count is not a multiple of 8, the part ignores the command. A valid clock count is 16, 24, or 32. The counter resets when SYNC returns high. Daisy chaining minimizes the number of port pins required from the controlling IC. As shown in Figure 39, the SDO pin of one package must be tied to the SDI pin of the next package. The clock period may need to be increased because of the propagation delay of the line between subsequent devices. When two AD5122/ AD5142 devices are daisy chained, 32 bits of data are required. The first 16 bits assigned to U2, and the second 16 bits assigned to U1, as shown in Figure 40. Keep the SYNC pin low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation. A typical connection is shown in Figure 39. VLOGIC VLOGIC AD5122/ AD5142 MOSI SDI SDI SDO U1 AD5122/ AD5142 RP 2.2k RP 2.2k U2 SDO SCLK SYNC SCLK DAISY-CHAIN SYNC 10880-039 MICROCONTROLLER MISO SCLK SS Figure 39. Daisy-Chain Configuration SCLK 1 2 16 17 18 32 SYNC DB15 DB0 INPUT WORD FOR U1 INPUT WORD FOR U2 SDO_U1 DB0 DB15 DB0 DB15 DB15 UNDEFINED DB0 INPUT WORD FOR U2 Figure 40. Daisy-Chain Diagram Rev. 0 | Page 21 of 32 10880-040 MOSI AD5122/AD5142 Data Sheet Table 10. Reduced Commands Operation Truth Table Command Number 0 1 Control Bits[DB15:DB12] C3 C2 C1 C0 0 0 0 0 0 0 0 1 Address Bits[DB11:DB8]1 A3 A2 A1 A0 X X X X 0 0 0 A0 2 0 0 1 0 0 0 0 3 0 0 1 1 X 0 9 10 14 15 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 X A3 0 0 X 0 1 D7 X D7 Data Bits[DB7:DB0]1 D6 D5 D4 D3 D2 D1 X X X X X X D6 D5 D4 D3 D2 D1 D0 X D0 A0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 X X X X X X D1 D0 0 0 X 0 A0 A0 X A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 X D0 Operation NOP: do nothing. Write contents of serial register data to RDAC Write contents of serial register data to input register Read back contents D1 D0 Data 0 1 EEPROM 1 1 RDAC Copy RDAC register to EEPROM Copy EEPROM into RDAC Software reset Software shutdown D0 Condition 0 Normal mode 1 Shutdown mode X = don't care. Table 11. Reduced Address Bits Table A3 1 0 0 0 1 A2 X1 0 0 0 A1 X1 0 0 1 A0 X1 0 1 0 Channel All channels RDAC1 RDAC2 Not applicable X = don't care. Rev. 0 | Page 22 of 32 Stored Channel Memory Not applicable RDAC1 Not applicable RDAC2 Data Sheet AD5122/AD5142 ADVANCED CONTROL MODES Low Wiper Resistance Feature The AD5122/AD5142 digital potentiometers include a set of user programming features to address the wide number of applications for these universal adjustment devices (see Table 16 and Table 18). The AD5122/AD5142 include two commands to reduce the wiper resistance between the terminals when the devices achieve full scale or zero scale. These extra positions are called bottom scale, BS, and top scale, TS. The resistance between Terminal A and Terminal W at top scale is specified as RTS. Similarly, the bottom scale resistance between Terminal B and Terminal W is specified as RBS. Key programming features include the following: * * * * * * * Input register Linear gain setting mode Low wiper resistance feature Lineal increment and decrement instructions 6 dB increment and decrement instructions Reset Shutdown mode The contents of the RDAC registers are unchanged by entering in these positions. There are three ways to exit from top scale and bottom scale: by using Command 12 or Command 13 (see Table 16); by loading new data in an RDAC register, which includes increment/decrement operations; or by entering shutdown mode, Command 15 (see Table 16). Input Register The AD5122/AD5142 include one input register per RDAC register. These registers allow preloading of the value for the associated RDAC register. These registers can be written to using Command 2 and read back from using Command 3 (see Table 16). This feature allows a synchronous update of one or all the RDAC registers at the same time. The transfer from the input register to the RDAC register is done synchronously by Command 8 (see Table 16). Table 12 and Table 13 show the truth tables for the top scale position and the bottom scale position, respectively, when the potentiometer or linear gain setting mode is enabled. Table 12. Top Scale Truth Table Linear Gain Setting Mode RAW RWB RAB RAB RAW RTS Potentiometer Mode RWB RAB Table 13. Bottom Scale Truth Table If new data is loaded into an RDAC register, this RDAC register automatically overwrites the associated input register. Linear Gain Setting Mode The patented architecture of the AD5122/AD5142 allows the independent control of each string resistor, RAW, and RWB. To enable this feature, use Command 16 (see Table 16) to set Bit D2 of the control register (see Table 18). This mode of operation can control the potentiometer as two independent rheostats connected at a single point, W terminal, as opposed to potentiometer mode where each resistor is complementary, RAW = RAB - RWB. This feature enables a second input and an RDAC register per channel, as shown in Table 17; however, the actual RDAC contents remain unchanged. The same operations are valid for potentiometer mode and linear gain setting mode. Linear Gain Setting Mode RAW RWB RTS RBS RAW RAB Potentiometer Mode RWB RBS Linear Increment and Decrement Instructions The increment and decrement commands (Command 4 and Command 5 in Table 16) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to send an increment or decrement command to the device. The adjustment can be individual or in a ganged potentiometer arrangement, where all wiper positions are changed at the same time. For an increment command, executing Command 4 automatically moves the wiper to the next RDAC position. This command can be executed in a single channel or multiple channels. If the INDEP pin is pulled high, the device powers up in linear gain setting mode and loads the values stored in the associated memory locations for each channel (see Table 17). The INDEP pin and D2 bit are connected internally to a logic OR gate, if any or both are 1, the parts cannot operate in potentiometer mode. Rev. 0 | Page 23 of 32 AD5122/AD5142 Data Sheet 6 dB Increment and Decrement Instructions Shutdown Mode Two programming instructions produce logarithmic taper increment or decrement of the wiper position control by an individual potentiometer or by a ganged potentiometer arrangement where all RDAC register positions are changed simultaneously. The +6 dB increment is activated by Command 6, and the -6 dB decrement is activated by Command 7 (see Table 16). For example, starting with the zero-scale position and executing Command 6 ten times moves the wiper in 6 dB steps to the fullscale position. When the wiper position is near the maximum setting, the last 6 dB increment instruction causes the wiper to go to the full-scale position (see Table 14). The AD5122/AD5142 can be placed in shutdown mode by executing the software shutdown command, Command 15 (see Table 16); and by setting the LSB (D0) to 1. This feature places the RDAC in a special state. The contents of the RDAC register are unchanged by entering shutdown mode. However, all commands listed in Table 16 are supported while in shutdown mode. Execute Command 15 (see Table 16) and set the LSB (D0) to 0 to exit shutdown mode. Incrementing the wiper position by +6 dB essentially doubles the RDAC register value, whereas decrementing the wiper position by -6 dB halves the register value. Internally, the AD5122/AD5142 use shift registers to shift the bits left and right to achieve a 6 dB increment or decrement. These functions are useful for various audio/video level adjustments, especially for white LED brightness settings in which human visual responses are more sensitive to large adjustments than to small adjustments. Table 14. Detailed Left Shift and Right Shift Functions for the 6 dB Step Increment and Decrement Left Shift (+6 dB/Step) 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 1111 1111 Table 15. Truth Table for Shutdown Mode A2 0 1 1 Linear Gain Setting Mode AW WB N/A1 Open Open N/A1 Potentiometer Mode AW WB Open RBS N/A1 N/A1 N/A = not applicable. EEPROM OR RDAC REGISTER PROTECTION The EEPROM and RDAC registers can be protected by disabling any update to these registers. This can be done by using software or by using hardware. If these registers are protected by software, set Bit D0 and/or Bit D1 (see Table 18), which protects the EEPROM and RDAC registers independently. When RDAC is protected, the only operation allowed is to copy the EEPROM into the RDAC register. Right Shift (-6 dB/Step) 1111 1111 0111 1111 0011 1111 0001 1111 0000 1111 0000 0111 0000 0011 0000 0001 0000 0000 0000 0000 INDEP PIN If the INDEP pin is pulled high at power-up, the part operates in linear gain setting mode, loading each string resistor, RAWx and RWBx, with the value stored into the EEPROM (see Table 17). If the pin is pulled low, the part powers up in potentiometer mode. The INDEP pin and the D2 bit are connected internally to a logic OR gate, if any or both are 1, the part cannot operate in potentiometer mode (see Table 18). Reset The AD5122/AD5142 can be reset through software by executing Command 14 (see Table 16) or through hardware on the low pulse of the RESET pin. The reset command loads the RDAC registers with the contents of the EEPROM and takes approximately 30 s. The EEPROM is preloaded to midscale at the factory, and initial power-up is, accordingly, at midscale. Tie RESET to VLOGIC if the RESET pin is not used. Rev. 0 | Page 24 of 32 Data Sheet AD5122/AD5142 Table 16. Advance Command Operation Truth Table Command Number 0 1 Control Bits[DB15:DB12] C3 C2 C1 C0 0 0 0 0 0 0 0 1 Address Bits[DB11:DB8]1 A3 A2 A1 A0 X X X X 0 A2 0 A0 D7 X D7 2 0 0 1 0 0 A2 0 A0 3 0 0 1 1 0 A2 A1 4 5 6 7 8 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 9 0 1 1 1 0 10 11 0 1 1 0 1 0 1 0 12 1 0 0 13 1 0 14 15 1 1 16 1 1 D6 X D6 Data Bits[DB7:DB0]1 D5 D4 D3 D2 D1 X X X X X D5 D4 D3 D2 D1 D0 X D0 D7 D6 D5 D4 D3 D2 D1 D0 A0 X X X X X X D1 D0 0 0 0 0 0 A0 A0 A0 A0 A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 X A2 0 A0 X X X X X X X 1 0 0 A2 0 0 A1 A0 A0 X D7 X D6 X D5 X D4 X D3 X D2 X D1 0 D0 1 A3 A2 0 A0 1 0 0 0 0 0 0 D0 0 1 A3 A2 0 A0 0 0 0 0 0 0 0 D0 0 1 1 0 1 0 X A3 X A2 X 0 X A0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 X D0 1 0 1 X X X X X X X X X D2 D1 D0 X = don't care. Rev. 0 | Page 25 of 32 Operation NOP: do nothing Write contents of serial register data to RDAC Write contents of serial register data to input register Read back contents D1 D0 Data 0 0 Input register 0 1 EEPROM 1 0 Control register 1 1 RDAC Linear RDAC increment Linear RDAC decrement +6 dB RDAC increment -6 dB RDAC decrement Copy input register to RDAC (software LRDAC) Copy RDAC register to EEPROM Copy EEPROM into RDAC Write contents of serial register data to EEPROM Top scale D0 = 0; normal mode D0 = 1; shutdown mode Bottom scale D0 = 1; enter D0 = 0; exit Software reset Software shutdown D0 = 0; normal mode D0 = 1; device placed in shutdown mode Copy serial register data to control register AD5122/AD5142 Data Sheet Table 17. Address Bits A3 1 0 0 0 0 0 0 1 A2 X1 0 1 0 1 0 0 A1 X1 0 0 0 0 1 1 A0 X1 0 0 1 1 0 1 Potentiometer Mode Input Register RDAC Register All channels All channels RDAC1 RDAC1 Not applicable Not applicable RDAC2 RDAC2 Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Linear Gain Setting Mode Input Register RDAC Register All channels All channels RWB1 RWB1 RAW1 RAW1 RWB2 RWB2 RAW2 RAW2 Not applicable Not applicable Not applicable Not applicable X = don't care. Table 18. Control Register Bit Descriptions Bit Name D0 D1 D2 Description RDAC register write protect 0 = wiper position frozen to value in EEPROM memory 1 = allows update of wiper position through digital interface (default) EEPROM program enable 0 = EEPROM program disabled 1 = enables device for EEPROM program (default) Lineal setting mode/potentiometer mode 0 = potentiometer mode (default) 1 = linear gain setting mode Rev. 0 | Page 26 of 32 Stored Channel Memory Not applicable RDAC1/RWB1 Not applicable RAW1 Not applicable RDAC2/RWB2 RAW2 Data Sheet AD5122/AD5142 RDAC ARCHITECTURE To achieve optimum performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5122/AD5142 employ a three-stage segmentation approach, as shown in Figure 41. The AD5122/AD5142 wiper switch is designed with the transmission gate CMOS topology and with the gate voltage derived from VDD and VSS. A The nominal resistance between Terminal A and Terminal B, RAB, is 10 k or 100 k, and has 128/256 tap points accessed by the wiper terminal. The 7-bit/8-bit data in the RDAC latch is decoded to select one of the 128/256 possible wiper settings. The general equations for determining the digitally programmed output resistance between Terminal W and Terminal B are AD5122: RWB (D) = STS D x R AB + RW 128 From 0x00 to 0x7F (1) D x R AB + RW 256 From 0x00 to 0xFF (2) AD5142: RH RWB (D) = RM RH where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. RM RL W In potentiometer mode, similar to the mechanical potentiometer, the resistance between Terminal W and Terminal A also produces a digitally controlled complementary resistance, RWA. RWA also gives a maximum of 8% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equations for this operation are RL 7-BIT/8-BIT ADDRESS DECODER RM RH RM RH SBS AD5122: 10880-041 B Figure 41. AD5122/AD5142 Simplified RDAC Circuit RAW (D) = RAW (D) = PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation--8% Resistor Tolerance The AD5122/AD5142 operate in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be floating, or it can be tied to Terminal W, as shown in Figure 42. A W B A W B B Figure 42. Rheostat Mode Configuration 256 - D x RAB + RW 256 From 0x00 to 0xFF (4) (3) where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. If the part is configured in linear gain setting mode, the resistance between Terminal W and Terminal A is directly proportional to the code loaded in the associate RDAC register. The general equations for this operation are AD5122: R AW (D) = D x R AB + RW 128 From 0x00 to 0x7F (5) D x R AB + RW 256 From 0x00 to 0xFF (6) AD5142: W 10880-042 A From 0x00 to 0x7F AD5142: Top Scale/Bottom Scale Architecture In addition, the AD5122/AD5142 include new positions to reduce the resistance between terminals. These positions are called bottom scale and top scale. At bottom scale, the typical wiper resistance decreases from 130 to 60 (RAB = 100 k). At top scale, the resistance between Terminal A and Terminal W is decreased by 1 LSB, and the total resistance is reduced to 60 (RAB = 100 k). 128 - D x RAB + RW 128 R AW (D) = where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. Rev. 0 | Page 27 of 32 AD5122/AD5142 Data Sheet In the bottom scale condition or top scale condition, a finite total wiper resistance of 40 is present. Regardless of which setting the part is operating in, limit the current between Terminal A to Terminal B, Terminal W to Terminal A, and Terminal W to Terminal B, to the maximum continuous current of 6 mA or to the pulse current specified in Table 6. Otherwise, degradation or possible destruction of the internal switch contact can occur. VDD A W VSS PROGRAMMING THE POTENTIOMETER DIVIDER Figure 44. Maximum Terminal Voltages Set by VDD and VSS Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A that is proportional to the input voltage at A to B, as shown in Figure 43. A VB VOUT B Figure 43. Potentiometer Mode Configuration Connecting Terminal A to 5 V and Terminal B to ground produces an output voltage at the Wiper W to Terminal B ranging from 0 V to 5 V. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B is VW (D ) = R (D ) RWB (D ) x VA + AW x VB RAB RAB POWER-UP SEQUENCE Because there are diodes to limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 44), it is important to power up VDD first before applying any voltage to Terminal A, Terminal B, and Terminal W. Otherwise, the diode is forward-biased such that VDD is powered unintentionally. The ideal power-up sequence is VSS, VDD, VLOGIC, digital inputs, and VA, VB, and VW. The order of powering VA, VB, VW, and digital inputs is not important as long as they are powered after VSS, VDD, and VLOGIC. Regardless of the power-up sequence and the ramp rates of the power supplies, once VLOGIC is powered, the power-on preset activates, which restores EEPROM values to the RDAC registers. LAYOUT AND POWER SUPPLY BIASING (7) where: RWB(D) can be obtained from Equation 1 and Equation 2. RAW(D) can be obtained from Equation 3 and Equation 4. Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RAW and RWB, and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/C. It is always a good practice to use a compact, minimum lead length layout design. Ensure that the leads to the input are as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. It is also good practice to bypass the power supplies with quality capacitors. Apply low equivalent series resistance (ESR) 1 F to 10 F tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance and to filter low frequency ripple. Figure 45 illustrates the basic supply bypassing configuration for the AD5122/AD5142. VDD TERMINAL VOLTAGE OPERATING RANGE The AD5122/AD5142 are designed with internal ESD diodes for protection. These diodes also set the voltage boundary of the terminal operating voltages. Positive signals present on Terminal A, Terminal B, or Terminal W that exceed VDD are clamped by the forward-biased diode. There is no polarity constraint between VA, VW, and VB, but they cannot be higher than VDD or lower than VSS. VSS Rev. 0 | Page 28 of 32 + C3 10F C1 0.1F + C4 10F C2 0.1F VDD VLOGIC AD5122/ AD5142 C5 0.1F C6 10F + VLOGIC VSS GND 10880-045 W 10880-043 VA 10880-044 B Figure 45. Power Supply Bypassing Data Sheet AD5122/AD5142 OUTLINE DIMENSIONS 3.10 3.00 SQ 2.90 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.75 1.60 SQ 1.45 9 TOP VIEW 0.80 0.75 0.70 4 5 8 0.50 0.40 0.30 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN BOTTOM VIEW 08-16-2010-E PIN 1 INDICATOR 0.30 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. Figure 46. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm x 3 mm Body, Very Very Thin Quad (CP-16-22) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. 0 | Page 29 of 32 0.75 0.60 0.45 AD5122/AD5142 Data Sheet ORDERING GUIDE Model 1, 2 AD5122BCPZ10-RL7 AD5122BCPZ100-RL7 AD5122BRUZ10 AD5122BRUZ100 AD5122BRUZ10-RL7 AD5122BRUZ100-RL7 AD5142BCPZ10-RL7 AD5142BCPZ100-RL7 AD5142BRUZ10 AD5142BRUZ100 AD5142BRUZ10-RL7 AD5142BRUZ100-RL7 EVAL-AD5142DBZ 1 2 RAB (k) 10 100 10 100 10 100 10 100 10 100 10 100 Resolution 128 128 128 128 128 128 256 256 256 256 256 256 Interface SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI SPI Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP Evaluation Board Package Option CP-16-22 CP-16-22 RU-16 RU-16 RU-16 RU-16 CP-16-22 CP-16-22 RU-16 RU-16 RU-16 RU-16 Z = RoHS Compliant Part. The evaluation board is shipped with the 10 k RAB resistor option; however, the board is compatible with all of the available resistor value options. Rev. 0 | Page 30 of 32 Branding DH8 DH9 DH5 DH6 Data Sheet AD5122/AD5142 NOTES Rev. 0 | Page 31 of 32 AD5122/AD5142 Data Sheet NOTES (c)2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10880-0-10/12(0) Rev. 0 | Page 32 of 32 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: AD5122BRUZ100 AD5142BRUZ100 EVAL-AD5142DBZ AD5122BCPZ100-RL7 AD5142BCPZ100-RL7 AD5142BRUZ10 AD5122BRUZ10 AD5142BCPZ10-RL7 AD5122BCPZ10-RL7 AD5142BRUZ100-RL7 AD5142BRUZ10-RL7