KH29LV320CBTC-90G - Macronix International Co., Ltd.

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE

3V ONLY FLASH MEMORY

FEATURES

GENERAL FEA TURES

• 4,194,304 x 8 / 2,097,152 x 16 switchable

• Sector Structure

- 8K-Byte x 8 and 64K-Byte x 63

• Extra 64K-Byte sector for security

- Features factory locked and identifiable, and cus-

tomer lockable

• Twenty-Fo ur Sector Gro ups

- Provides sector group protect function to prevent pro-

gram or erase operation in the protected sector group

- Provides chip unprotect function to allow code chang-

ing

- Provides temporary sector group unprotect function

for code changing in previously protected sector groups

• Single P ower Supply Operatio n

- 2.7 to 3.6 volt for read, erase, and program opera-

tions

• Latch-up protected to 250mA from -1V to Vcc + 1V

• Low Vcc write inhibit is equal to o r less than 1.4V

• Compatible with JEDEC standard

- Pinout and software compatible to single power sup-

ply Flash

•Fully compatible with KH29LV320A T/B device

PERFORMANCE

• High Performance

- Fast access time: 70/90ns

- Fast pro gram time: 7us/word typical utilizing acceler-

ate function

- F ast er ase time: 0.9s/sector , 35s/chip (typical)

• Low Power Consumption

- Low active read current: 10mA (typical) at 5MHz

- Low standby current: 200nA (typical)

• Minimum 100,000 erase/program cycle

• 10 years data retentio n

SOFTWARE FEA TURES

• Erase Suspend/ Erase Resume

- Suspends sector erase operation to read data from

or program data to another sector which is not being

erased

• Status Reply

- Data# P olling & To ggle bits provide detectio n of pro-

gram and erase operation completion

• Suppo rt Co mmo n Flash Interf ace (CFI)

HARDWARE FEATURES

• Ready/Busy# (RY/BY#) Output

- Provides a hardware method of detecting program

and erase operation completion

• Hardware Reset (RESET#) Input

- Provides a hardware method to reset the internal state

machine to read mode

• WP#/ACC input pin

- Provides accelerated program capability

PACKAGE

• 48-Pin TSOP

•All Pb-free devices are RoHS Compliant

GENERAL DESCRIPTION

The KH29LV320C T/B is a 32-mega bit Flash memory

organized as 4M bytes of 8 bits and 2M words of 16 bits.

MXIC's Flash memories offer the most cost-effective and

reliable read/write no n-v o latile random access memo ry.

The KH29LV320C T/B is pac kaged in 48-pin TSOP. It is

designed to be repro grammed and erased in system o r in

standard EPROM programmers.

The standard KH29LV320C T/B offers access time as

fast as 70ns, allowing operation of high-speed micropro-

cessors without wait states. To eliminate bus conten-

tion, the KH29L V320C T/B has separate chip enable (CE#)

and o utput enable (OE#) co ntrols.

MXIC's Flash memo ries augment EPROM functio nality

with in-circuit electrical erasure and pro gramming. The

KH29LV320C T/B uses a co mmand register to manage

this functio nality.

MXIC Flash techno logy reliably sto res memo ry contents

even after 100,000 erase and program cycles. The MXIC

cell is designed to optimize the erase and program

mechanisms. In additio n, the co mbination o f adv anced

tunnel oxide processing and low internal electr ic fields

for erase and pro gramming o peratio ns produces reliable

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

cycling. The KH29LV320C T/B uses a 2.7V to 3.6V VCC

supply to perform the High Reliability Erase and auto

Pro gram/Erase algo rithms.

The highest degree o f latch-up protection is achieved with

MXIC's pro prietary non-epi process. Latch-up protection

is pro ved for stresses up to 100 milliamperes o n address

and data pin fro m -1V to VCC + 1V.

AUTOMA TIC PROGRAMMING

The KH29LV320C T/B is byte/wo rd programmable using

the Automatic Programming algor ithm. The Automatic

Programming algorithm makes the exter nal system do

not need to have time out sequence nor to verify the

data pro grammed. The typical chip programming time at

room temperature of the KH29LV320C T/B is less than

36 seco nds.

AUTOMA TIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm require the user

to o nly write pro gram set-up co mmands (including 2 un-

lo ck write cycle and A0H) and a program co mmand (pro-

gram data and address). The device auto matically times

the pro gramming pulse width, pro vides the program veri-

ficatio n, and co unts the number of sequences. A status

bit similar to Data# Polling and a status bit toggling be-

tween co nsecutiv e read cycles, pro vide f eedback to the

user as to the status o f the pro gramming o peratio n.

A UTOMATIC CHIP ERASE

The entire chip is bulk erased using 50 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at ro o m temperature is acco mplished in

less than 35 seconds. The Automatic Erase algor ithm

auto matically programs the entire array prio r to electrical

erase. The timing and verificatio n o f electrical erase are

co ntro lled internally within the device.

AUTOMA TIC SECTOR ERASE

The KH29LV320C T/B is sector(s) erasable using

MXIC's Auto Sector Erase algorithm. Sector erase

modes allow sectors of the array to be erased in one

erase cycle. The Automatic Sector Erase algorithm

automatically programs the specified sector(s) prior to

electrical erase. The timing and verification of electri-

cal erase are controlled internally within the device.

AUTOMA TIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stand-

ard microprocessor write timings. The device will auto-

matically pre-program and verify the entire arra y. Then

the device automatically times the erase pulse width,

pro vides the erase verificatio n, and counts the number of

sequences. A status bit toggling between consecutive

read cycles pro vides f eedback to the user as to the sta-

tus o f the programming o peratio n.

machine which co ntro ls the erase and pro gramming cir-

cuitry. During write cycles, the co mmand register inter-

nally latches address and data needed f o r the pro gram-

ming and erase o perations. During a system write cycle,

addresses are latched o n the falling edge, and data are

latched o n the rising edge o f WE# .

MXIC's Flash technology combines years of EPROM

experience to pro duce the highest levels of quality , relia-

bility , and co st effectiveness. The KH29LV320C T/B elec-

trically erases all bits simultaneo usly using Fowler-Nord-

heim tunneling. The bytes/words are programmed by

using the EPROM pro gramming mechanism of hot elec-

tro n injection.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend co mmand. After Erase Suspend is co mpleted,

the de vice sta ys in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full co mmand set.

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

PIN CONFIGURATION

48 TSOP

SYMBOL PIN NAME

A0~A20 Address Input

Q0~Q14 15 Data Inputs/Outputs

Q15/A-1 Q15(Data Input/Output, word mode)

A-1(LSB Address Input, byte mo de)

CE# Chip Enable Input

WE# Write Enable Input

OE# Output Enable Input

BYTE# Word/Byte Selectio n Input

RESET# Hardware Reset Pin, Active Low

R Y/BY# Read/Busy Output

VC C 3.0 volt-only single power supply

WP#/ACC Hardware Write Protect/Acceleration

GND Device Ground

N C Pin Not Connected Internally

PIN DESCRIPTION LOGIC SYMBOL

16 or 8

Q0-Q15

(A-1)

RY/BY#

A0-A20

CE#

OE#

WE#

RESET#

WP#/ACC

BYTE#

A15

A14

A13

A12

A11

A10

A19

A20

WE#

RESET#

WP#/ACC

RY/BY#

A18

A17

A16

BYTE#

GND

Q15/A-1

Q14

Q13

Q12

VCC

Q11

Q10

OE#

GND

CE#

KH29LV320C T/B

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

BLOCK DIAGRAM

CONTROL

INPUT

LOGIC

PROGRAM/ERASE

HIGH V OLTAGE

WRITE

STATE

MACHINE

(WSM)

STATE

FLASH

ARRAY

X-DECODER

ADDRESS

LATCH

AND

BUFFER Y-PASS GATE

Y-DECODER

ARRAY

SOURCE

HV COMMAND

DATA

DECODER

COMMAND

DATA LATCH

I/O BUFFER

PGM

DATA

PROGRAM

DATA LATCH

SENSE

AMPLIFIER

Q0-Q15/A-1

A0-A20

CE#

OE#

WE#

RESET#

BYTE#

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Sector Sector Sector Address Sector Size (x8) (x16)

Group A20-A12 (Kbytes/Kwords) Address Range Address Range

1 SA0 000000xxx 64/32 000000h-00FFFFh 000000h-07FFFh

1 SA1 000001xxx 64/32 010000h-01FFFFh 008000h-0FFFFh

1 SA2 000010xxx 64/32 020000h-02FFFFh 010000h-17FFFh

1 SA3 000011xxx 64/32 030000h-03FFFFh 018000h-01FFFFh

2 SA4 000100xxx 64/32 040000h-04FFFFh 020000h-027FFFh

2 SA5 000101xxx 64/32 050000h-05FFFFh 028000h-02FFFFh

2 SA6 000110xxx 64/32 060000h-06FFFFh 030000h-037FFFh

2 SA7 000111xxx 64/32 070000h-07FFFFh 038000h-03FFFFh

3 SA8 001000xxx 64/32 080000h-08FFFFh 040000h-047FFFh

3 SA9 001001xxx 64/32 090000h-09FFFFh 048000h-04FFFFh

3 SA10 001010xxx 64/32 0A0000h-0AFFFFh 050000h-057FFFh

3 SA11 001011xxx 64/32 0B0000h-0BFFFFh 058000h-05FFFFh

4 SA12 001100xxx 64/32 0C0000h-0CFFFFh 060000h-067FFFh

4 SA13 001101xxx 64/32 0D0000h-0DFFFFh 068000h-06FFFFh

4 SA14 001110xxx 64/32 0E0000h-0EFFFFh 070000h-077FFFh

4 SA15 001111xxx 64/32 0F0000h-0FFFFFh 078000h-07FFFFh

5 SA16 010000xxx 64/32 100000h-10FFFFh 080000h-087FFFh

5 SA17 010001xxx 64/32 110000h-11FFFFh 088000h-08FFFFh

5 SA18 010010xxx 64/32 120000h-12FFFFh 090000h-097FFFh

5 SA19 010011xxx 64/32 130000h-13FFFFh 098000h-09FFFFh

6 SA20 010100xxx 64/32 140000h-14FFFFh 0A0000h-0A7FFFh

6 SA21 010101xxx 64/32 150000h-15FFFFh 0A8000h-0AFFFFh

6 SA22 010110xxx 64/32 160000h-16FFFFh 0B0000h-0B7FFFh

6 SA23 010111xxx 64/32 170000h-17FFFFh 0B8000h-0BFFFFh

7 SA24 011000xxx 64/32 180000h-18FFFFh 0C0000h-0C7FFFh

7 SA25 011001xxx 64/32 190000h-19FFFFh 0C8000h-0CFFFFh

7 SA26 011010xxx 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh

7 SA27 011011xxx 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh

8 SA28 011100xxx 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh

8 SA29 011101xxx 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh

8 SA30 011110xxx 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh

8 SA31 011111xxx 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh

9 SA32 100000xxx 64/32 200000h-20FFFFh 100000h-107FFFh

9 SA33 100001xxx 64/32 210000h-21FFFFh 108000h-10FFFFh

9 SA34 100010xxx 64/32 220000h-22FFFFh 110000h-117FFFh

9 SA35 100011xxx 64/32 230000h-23FFFFh 118000h-11FFFFh

10 SA36 100100xxx 64/32 240000h-24FFFFh 120000h-127FFFh

10 SA37 100101xxx 64/32 250000h-25FFFFh 128000h-12FFFFh

10 SA38 100110xxx 64/32 260000h-26FFFFh 130000h-137FFFh

10 SA39 100111xxx 64/32 270000h-27FFFFh 138000h-13FFFFh

T able 1.a: KH29L V320CT SECTOR GROUP ARCHITECTURE

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Sector Sector Sector Address Sector Size (x8) (x16)

Group A20-A12 (Kbytes/Kwords) Address Range Address Range

11 SA40 101000xxx 64/32 280000h-28FFFFh 140000h-147FFFh

11 SA41 101001xxx 64/32 290000h-29FFFFh 148000h-14FFFFh

11 SA42 101010xxx 64/32 2A0000h-2AFFFFh 150000h-157FFFh

11 SA43 101011xxx 64/32 2B0000h-2BFFFFh 158000h-15FFFFh

12 SA44 101100xxx 64/32 2C0000h-2CFFFFh 160000h-147FFFh

12 SA45 101101xxx 64/32 2D0000h-2DFFFFh 168000h-14FFFFh

12 SA46 101110xxx 64/32 2E0000h-2EFFFFh 170000h-177FFFh

12 SA47 101111xxx 64/32 2F0000h-2FFFFFh 178000h-17FFFFh

13 SA48 110000xxx 64/32 300000h-30FFFFh 180000h-187FFFh

13 SA49 110001xxx 64/32 310000h-31FFFFh 188000h-18FFFFh

13 SA50 110010xxx 64/32 320000h-32FFFFh 190000h-197FFFh

13 SA51 110011xxx 64/32 330000h-33FFFFh 198000h-19FFFFh

14 SA52 110100xxx 64/32 340000h-34FFFFh 1A0000h-1A7FFFh

14 SA53 110101xxx 64/32 350000h-35FFFFh 1A8000h-1AFFFFh

14 SA54 110110xxx 64/32 360000h-36FFFFh 1B0000h-1B7FFFh

14 SA55 110111xxx 64/32 370000h-37FFFFh 1B8000h-1BFFFFh

15 SA56 111000xxx 64/32 380000h-38FFFFh 1C0000h-1C7FFFh

15 SA57 111001xxx 64/32 390000h-39FFFFh 1C8000h-1CFFFFh

15 SA58 111010xxx 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh

15 SA59 111011xxx 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh

16 SA60 111100xxx 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh

16 SA61 111101xxx 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh

16 SA62 111110xxx 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh

17 SA63 111111000 8/4 3F0000h-3F1FFFh 1F8000h-1F8FFFh

18 SA64 111111001 8/4 3F2000h-3F3FFFh 1F9000h-1F9FFFh

19 SA65 111111010 8/4 3F4000h-3F5FFFh 1FA000h-1FAFFFh

20 SA66 111111011 8/4 3F6000h-3F7FFFh 1FB000h-1FBFFFh

21 SA67 111111100 8/4 3F8000h-3F9FFFh 1FC000h-1FCFFFh

22 SA68 111111101 8/4 3FA000h-3FBFFFh 1FD000h-1FDFFFh

23 SA69 111111110 8/4 3FC000h-3FDFFFh 1FE000h-1FEFFFh

24 SA70 111111111 8/4 3FE000h-3FFFFFh 1FF000h-1FFFFFh

T op Boot Security Sector Addresses

Sector Address Sector Size (x8) (x16)

A20~A12 (Kbytes/Kwords) Address Range Address Range

111111xxx 64/32 3F0000h-3FFFFFh 1F8000h-1FFFFFh

No te:The address range is A20:A-1 in byte mo de (BYTE#=VIL) o r A20:A0 in wo rd mo de (BYTE#=VIH)

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Sector Sector Sector Address Sector Size (x8) (x16)

Group A20-A12 (Kbytes/Kwords) Address Range Address Range

1 SA0 000000000 8/4 000000h-001FFFh 000000h-000FFFh

2 SA1 000000001 8/4 002000h-003FFFh 001000h-001FFFh

3 SA2 000000010 8/4 004000h-005FFFh 002000h-002FFFh

4 SA3 000000011 8/4 006000h-007FFFh 003000h-003FFFh

5 SA4 000000100 8/4 008000h-009FFFh 004000h-004FFFh

6 SA5 000000101 8/4 00A000h-00BFFFh 005000h-005FFFh

7 SA6 000000110 8/4 00C000h-00DFFFh 006000h-006FFFh

8 SA7 000000111 8/4 00E000h-00FFFFh 007000h-007FFFh

9 SA8 000001xxx 64/32 010000h-01FFFFh 008000h-00FFFFh

9 SA9 000010xxx 64/32 020000h-02FFFFh 010000h-017FFFh

9 SA10 000011xxx 64/32 030000h-03FFFFh 018000h-01FFFFh

10 SA11 000100xxx 64/32 040000h-04FFFFh 020000h-027FFFh

10 SA12 000101xxx 64/32 050000h-05FFFFh 028000h-02FFFFh

10 SA13 000110xxx 64/32 060000h-06FFFFh 030000h-037FFFh

10 SA14 000111xxx 64/32 070000h-07FFFFh 038000h-03FFFFh

11 SA15 001000xxx 64/32 080000h-08FFFFh 040000h-047FFFh

11 SA16 001001xxx 64/32 090000h-09FFFFh 048000h-04FFFFh

11 SA17 001010xxx 64/32 0A0000h-0AFFFFh 050000h-057FFFh

11 SA18 001011xxx 64/32 0B0000h-0BFFFFh 058000h-05FFFFh

12 SA19 001100xxx 64/32 0C0000h-0CFFFFh 060000h-067FFFh

12 SA20 001101xxx 64/32 0D0000h-0DFFFFh 068000h-06FFFFh

12 SA21 001110xxx 64/32 0E0000h-0EFFFFh 070000h-077FFFh

12 SA22 001111xxx 64/32 0F0000h-0FFFFFh 078000h-07FFFFh

13 SA23 010000xxx 64/32 100000h-10FFFFh 080000h-087FFFh

13 SA24 010001xxx 64/32 110000h-11FFFFh 088000h-08FFFFh

13 SA25 010010xxx 64/32 120000h-12FFFFh 090000h-097FFFh

13 SA26 010011xxx 64/32 130000h-13FFFFh 098000h-09FFFFh

14 SA27 010100xxx 64/32 140000h-14FFFFh 0A0000h-0A7FFFh

14 SA28 010101xxx 64/32 150000h-15FFFFh 0A8000h-0AFFFFh

14 SA29 010110xxx 64/32 160000h-16FFFFh 0B0000h-0B7FFFh

14 SA30 010111xxx 64/32 170000h-17FFFFh 0B8000h-0BFFFFh

15 SA31 011000xxx 64/32 180000h-18FFFFh 0C0000h-0C7FFFh

15 SA32 011001xxx 64/32 190000h-19FFFFh 0C8000h-0CFFFFh

15 SA33 011010xxx 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh

15 SA34 011011xxx 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh

16 SA35 011100xxx 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh

16 SA36 011101xxx 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh

16 SA37 011110xxx 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh

16 SA38 011111xxx 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh

T able 1.b: KH29L V320CB SECTOR GROUP ARCHITECTURE

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Sector Sector Sector Address Sector Size (x8) (x16)

Group A20-A12 (Kbytes/Kwords) Address Range Address Range

17 SA39 100000xxx 64/32 200000h-20FFFFh 100000h-107FFFh

17 SA40 100001xxx 64/32 210000h-21FFFFh 108000h-10FFFFh

17 SA41 100010xxx 64/32 220000h-22FFFFh 110000h-117FFFh

17 SA42 100011xxx 64/32 230000h-23FFFFh 118000h-11FFFFh

18 SA43 100100xxx 64/32 240000h-24FFFFh 120000h-127FFFh

18 SA44 100101xxx 64/32 250000h-25FFFFh 128000h-12FFFFh

18 SA45 100110xxx 64/32 260000h-26FFFFh 130000h-137FFFh

18 SA46 100111xxx 64/32 270000h-27FFFFh 138000h-13FFFFh

19 SA47 101000xxx 64/32 280000h-28FFFFh 140000h-147FFFh

19 SA48 101001xxx 64/32 290000h-29FFFFh 148000h-14FFFFh

19 SA49 101010xxx 64/32 2A0000h-2AFFFFh 150000h-157FFFh

19 SA50 101011xxx 64/32 2B0000h-2BFFFFh 158000h-15FFFFh

20 SA51 101100xxx 64/32 2C0000h-2CFFFFh 160000h-167FFFh

20 SA52 101101xxx 64/32 2D0000h-2DFFFFh 168000h-16FFFFh

20 SA53 101110xxx 64/32 2E0000h-2EFFFFh 170000h-177FFFh

20 SA54 101111xxx 64/32 2F0000h-2FFFFFh 178000h-17FFFFh

21 SA55 110000xxx 64/32 300000h-30FFFFh 180000h-187FFFh

21 SA56 110001xxx 64/32 310000h-31FFFFh 188000h-18FFFFh

21 SA57 110010xxx 64/32 320000h-32FFFFh 190000h-197FFFh

21 SA58 110011xxx 64/32 330000h-33FFFFh 198000h-19FFFFh

22 SA59 110100xxx 64/32 340000h-34FFFFh 1A0000h-1A7FFFh

22 SA60 110101xxx 64/32 350000h-35FFFFh 1A8000h-1AFFFFh

22 SA61 110110xxx 64/32 360000h-36FFFFh 1B0000h-1B7FFFh

22 SA62 110111xxx 64/32 370000h-37FFFFh 1B8000h-1BFFFFh

23 SA63 111000xxx 64/32 380000h-38FFFFh 1C0000h-1C7FFFh

23 SA64 111001xxx 64/32 390000h-39FFFFh 1C8000h-1CFFFFh

23 SA65 111010xxx 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh

23 SA66 111011xxx 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh

24 SA67 111100xxx 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh

24 SA68 111101xxx 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh

24 SA69 111110xxx 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh

24 SA70 111111xxx 64/32 3F0000h-3FFFFFh 1F8000h-1FFFFFh

Bottom Boot Security Sector Addresses

Sector Address Sector Size (x8) (x16)

A20~A12 (Kbytes/Kwords) Address Range Address Range

111111xxx 64/32 000000h-00FFFFh 00000h-07FFFh

No te:The address range is A20:A-1 in byte mode (BYTE#=VIL) o r A20:A0 in wo rd mo de (BYTE#=VIH)

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Operation CE# OE# WE# RE- WP#/ Addresses Q0~Q7 Q 8 ~ Q15

SET# A C C (Note 2) Byte#=VIH Byte#=VIL

Read L L H H L/H AIN DOUT DOUT Q8-A14

Write (No te 1) L H L H No te 3 AIN DIN DIN =High-Z

Accelerate L H L H VHH AIN DIN DIN Q15=A-1

Program

Standby VCC±X X VCC±H X High-Z High-Z High-Z

0.3V 0.3V

Output Disable L H H H L/H X High-Z High-Z High-Z

Reset X X X L L/H X High-Z High-Z High-Z

Sector Group L H L VID L/H Sector Addresses, DIN, DOUT X X

Protect (Note 2) A6=L, A1=H, A0=L

Chip Unprotect L H L VID No te 3 Secto r Addresses, DIN, DOUT XX

(N ote 2) A6=H, A1=H, A0=L

Temporary Sector X X X VID Note 3 AIN DIN DIN High-Z

Group Unprotect

Legend:

L=Lo gic LO W=VIL, H=Lo gic High=VIH, VID=12.0±0.5V, VHH=11.5-12.5V, X=Do n't Care, AIN=Address IN, DIN=Data IN,

DOUT=Data OUT

Notes:

1. When the WP#/ACC pin is at VHH, the device enters the accelerated program mode. See "Accelerated Program

Operatio ns" fo r more info rmatio n.

2. The secto r gro up protect and chip unpro tect functio ns may also be implemented via pro gramming equipment. See

the "Secto r Group Pro tection and Chip Unpro tection" section.

3. If WP#/ACC=VIL, the two o utermo st bo ot secto rs remain pro tected. If WP#/A CC=VIH, the two o utermost bo o t sector

protection depends on whether they were last pro tected o r unprotected using the method described in "Sector/Sector

Blo ck Protectio n and Unpro tectio n". If WP#/ACC=VHH, all sectors will be unpro tected.

4. DIN o r Do ut as required by co mmand sequence, data po lling, or sector protectio n algorithm.

5. Address are A20:A0 in wo rd mo de (BYTE#=VIH), A20:A-1 in b yte mo de (BYTE#=VIL).

T able 2. BUS OPERA TION--1

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

A20 A11 A8 A5

Operation CE# OE# WE# t o t o A 9 to A 6 t o A 1 A0 Q0 -Q 7 Q8-Q15

A12 A10 A7 A2

Read Silico n ID L L H X X VID X L X L L C2H X

Manufacturer Code

Read Silico n ID L L H X X VID X L X L H A7H 22h(word)

KH29LV320CT X (byte)

Read Silico n ID L L H X X VID X L X L H A8H 22h(word)

KH29LV320CB X (byte)

Secto r Pro tect L L H SA X VID X L X H L 01h(1), X

Verification or 00h

Security Sector L L H X X VID X L X H H 99h(2), X

Indicater Bit (Q7) o r 19h

BUS OPERA TION--2

Notes:

1.Code=00h means unprotected, o r code=01h pro tected.

2.Co de=99 means facto ry lo cked, o r co de=19h no t facto ry lo cked.

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KH29LV320C T/B

REQUIREMENTS FOR READING ARRAY DA T A

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

co ntrol and selects the device . OE# is the o utput co ntro l

and gates arra y data to the o utput pins . WE# should re-

main at VIH.

The internal state machine is set for reading arra y data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory co n-

tent occurs during the power transition. No co mmand is

necessary in this mode to obtain array data. Standard

micro processor read cycles that assert valid address on

the device address inputs produce valid data o n the de-

vice data outputs. The de vice remains enabled for read

access until the co mmand register co ntents are altered.

WRITE COMMANDS/COMMAND SEQUENCES

To program data to the device or erase secto rs of memory

, the system must driv e WE# and CE# to VIL, and OE#

to VIH.

An erase operation can erase one sector, multiple sec-

tors , o r the entire de vice . Tab le 1 indicates the address

space that each sector occupies. A "sector address"

co nsists o f the address bits required to uniquely select a

sector . Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 3 defines the valid register command

sequences. Writing incorrect address and data values o r

writing them in the improper sequence resets the device

to reading array data. Section has details on erasing a

sector or the entire chip, o r suspending/resuming the erase

operation.

After the system writes the Automatic Select command

sequence, the device enters the Automatic Select mode.

The system can then read A uto matic Select co des from

the internal register (which is separate from the memory

array) on Q7-Q0. Standard read cycle timings apply in

this mode. Ref er to the Auto matic Select Mode and A u-

to matic Select Command Sequence sectio n for mo re in-

formation.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The "AC

Characteristics" section contains timing specification table

and timing diagrams fo r write o perations.

ACCELERATED PROGRAM OPERA TION

The device offers accelerated pro gram operations through

the ACC function. If the system asserts VHH on WP#/

ACC pin, the device will provide the fast programming

time to user. This function is primarily intended to allow

f aster manuf acturing throughput during productio n. Re-

moving VHH fro m the WP#/ACC pin returns the device to

normal operation. Note that the WP#/ACC pin must not

be at VHH fo r o peratio ns o ther than accelerated pro gram-

ming, o r de vice damage ma y result.

ST ANDBY MODE

KH29LV320C T/B can be set into Standby mode with

two different approaches. One is using both CE# and

RESET# pins and the other one is using RESET pin only .

When using both pins of CE# and RESET#, a CMOS

Standby mode is achie ved with both pins held at VCC ±

0.3V. Under this conditio n, the current co nsumed is less

than 0.2uA (typ.). If both of the CE# and RESET# are

held at VIH, but not within the range of VCC ± 0.3V, the

de vice will still be in the standb y mode, but the standby

current will be larger. During Auto Algor ithm operation,

Vcc active current (ICC2) is required even CE# = "H"

until the o peratio n is co mpleted. The device can be read

with standard access time (tCE) from either of these

standby mo des.

When using only RESET#, a CMOS standby mode is

achieved with RESET# input held at Vss ± 0.3V, Under

this condition the current is consumed less than 1uA

(typ.). Once the RESET# pin is taken high, the device is

back to active without recovery delay.

In the standby mode the outputs are in the high imped-

ance state, independent o f the OE# input.

KH29LV320C T/B is capable to provide the Automatic

Standby Mode to restrain power consumption during read-

out of data. This mode can be used effectively with an

application requested low power consumption such as

handy terminals.

To active this mode, KH29LV320C T/B automatically

switch themselves to low power mode when KH29L V320C

T/B addresses remain stable during access time of

tACC+30ns. It is not necessary to control CE#, WE#,

and OE# o n the mode. Under the mo de, the current co n-

sumed is typically 0.2uA (CMOS level).

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KH29LV320C T/B

OUTPUT DISABLE

With the OE# input at a logic high level (VIH), output

fro m the devices are disabled. This will cause the o utput

pins to be in a high impedance state.

RESET# OPERA TION

The RESET# pin provides a hardware metho d of reset-

ting the device to reading array data. When the RESET#

pin is driven low for at least a period of tRP, the device

immediately terminates any operation in progress,

tristates all output pins, and ignores all read/write com-

mands for the duration o f the RESET# pulse. The device

also resets the internal state machine to reading array

data. The operation that was interrupted should be

reinitiated once the device is ready to accept another

co mmand sequence, to ensure data integrity

Current is reduced fo r the duration o f the RESET# pulse.

When RESET# is held at VSS±0.3V, the device draws

CMOS standby current (ICC4). If RESET# is held at VIL

but not within VSS±0.3V, the standby current will be

greater.

The RESET# pin may be tied to system reset circuitr y.

A system reset wo uld that also reset the Flash memo ry ,

enabling the system to read the boo t-up firm-ware fro m

the Flash memo ry .

If RESET# is asserted during a pro gram o r erase o pera-

tio n, the R Y/BY# pin remains a "0" (busy) until the inter-

nal reset o peratio n is co mplete, which requires a time o f

tREAD Y (during Embedded Algorithms). The system can

thus mo nitor R Y/BY# to determine whether the reset o p-

eration is complete . If RESET# is asserted when a pro-

gram or erase operatio n is no t e x ecuting (R Y/BY# pin is

"1"), the reset operation is completed within a time of

tREAD Y (no t during Embedded Algo rithms). The system

can read data tRH after the RESET# pin returns to VIH.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 14 f o r the timing diagram.

SECTOR GROUP PROTECT OPERA TION

The KH29LV320C T/B features hardware sector group

protection. This feature will disable both program and

erase operations for these sector group protected. Sec-

to r pro tection can be implemented via two metho ds.

The primary metho d requires VID on the RESET# o nly.

This metho d can be implemented either in-system or via

pro gramming equipment. This method uses standard mi-

cro processo r bus cycle timing. Refer to Figure 13 f or tim-

ing diagram and Figure 14 illustrates the algorithm for the

sector group protection operatio n.

The alternate method intended only for programming

equipment, must fo rce VID o n address pin A9 and con-

trol pin OE#, (suggest VID = 12V) A6 = VIL and CE# =

VIL(see T able 2). Programming o f the pro tection circuitry

begins o n the falling edge o f the WE# pulse and is termi-

nated on the rising edge. Contact MXIC for details.

To verify pro gramming o f the protectio n circuitry , the pro-

gramming equipment must fo rce VID o n address pin A9 (

with CE# and OE# at VIL and WE# at VIH). When A1=1,

it will pro duce a logical "1" co de at device o utput Q0 for a

pro tected sector . Otherwise the device will produce 00H

f o r the unpro tected secto r . In this mo de, the addresses ,

except for A1, are don't care. Address locations with

A1= VIL are reserved to read manufacturer and device

codes.(Read Silicon ID)

It is also possible to determine if the group is protected

in the system by writing a Read Silicon ID command.

P erfo rming a read o peration with A1=VIH, it will produce

a lo gical "1" at Q0 f or the protected secto r.

CHIP UNPRO TECT OPERA TION

The KH29LV320C T/B also features the chip unpro tect

mode, so that all sectors are unprotected after chip

unprotect is completed to incorporate any changes in

the code. It is recommended to protect all sectors before

activating chip unprotect mode.

The primary metho d requires VID on the RESET# o nly.

This method can be implemented either in-system or via

programming equipment. This method uses standard

microprocessor bus cycle timing. Refer to Figure 13 for

timing diagram and Figure 14 illustrates the algorithm for

the sector group protection operation.

The alternate method intended only for programming

equipment, must fo rce VID o n address pin A9 and con-

trol pin OE#, (suggest VID = 12V) A6 = VIL and CE# =

VIL(see T able 2). Programming o f the pro tection circuitry

begins o n the falling edge o f the WE# pulse and is termi-

nated o n the rising edge. Co ntact MXIC f o r details.

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

It is also po ssible to determine if the chip is unpro tected

in the system by writing the Read Silicon ID command.

P erfo rming a read o peration with A1=VIH, it will pro duce

00H at data o utputs(Q0-Q7) fo r an unprotected secto r. It

is noted that all sectors are unprotected after the chip

unpro tect algo rithm is completed.

TEMPORARY SECTOR GROUP UNPROTECT OPERA-

TION

This feature allows tempo rary unpro tection o f previo usly

pro tected secto r to change data in-system. The Tempo-

rary Sector Unprotect mode is activated by setting the

RESET# pin to VID(11.5V -12.5V). During this mo de, fo r-

merly protected sectors can be programmed or erased

as un-protected secto r. Once VID is remove from the

RESET# pin, all the previously protected sectors are pro-

tected again.

WRITE PROTECT (WP#)

The write protect functio n provides a hardware method to

pro tect bo ot secto rs without using VID.

If the system asserts VIL on the WP#/ACC pin, the de-

vice disables pro gram and erase functions in the two "out-

ermost" 8 Kbyte boot sectors independently of whether

those sectors were protected or unprotected using the

metho d described in Secto r/Sector Gro up Protection and

Chip Unpro tection". The two o utermost 8 Kbyte boot sec-

to rs are the two sectors containing the lowest addresses

in a bottom-boot-configured device, or the two sectors

co ntaining the highest addresses in a top-boot-configured

device.

If the system asserts VIH on the WP#/A CC pin, the de-

vice re v e rts to whether the two outermo st 8K Byte boo t

secto rs were last set to be pro tected or unprotected. That

is, secto r pro tectio n or unpro tectio n fo r these two secto rs

depends on whether they w ere last protected or unpro-

tected using the method described in "Sector/Sector Group

Protection and Chip Unprotection".

Note that the WP#/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may

result.

AUTOMA TIC SELECT OPERA TION

Flash memories are intended for use in applications where

the lo cal CPU alters memo ry co ntents. As such, man u-

f acturer and device co des m ust be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high voltage. How e ver , m ultiplexing high v o ltage onto

address lines is not generally desired system design prac-

tice.

KH29LV320C T/B pro vides hardw are method to access

the Automatic Select operatio n. This method requires VID

on A9 pin, VIL on CE#, OE#, A6, and A1 pins. When

applying VIL on A0 pin, the device will output MXIC's

manufacture code of C2H. When applying VIH o n A0 pin,

the device will output KH29LV320C T/B device code of

22A7h and 22A8h.

VERIFY SECTOR GROUP PROTECT ST A TUS OPERA-

TION

KH29LV320C T/B provides hardware method for sector

group protect status verify. This method requires VID on

A9 pin, VIH o n WE# and A1 pins , VIL o n CE#, OE#, A6,

and A0 pins, and sector address on A12 to A20 pins.

When the identified sector is protected, the device will

o utput 01H. When the identified secto r is no t protect, the

de vice will o utput 00H.

SECURITY SECTOR FLASH MEMOR Y REGION

The Security Sector (Security Sector) feature provides a

Flash memo ry region that enables permanent part iden-

tification through an Electronic Serial Number (ESN). The

Security Sector is 64 Kbytes (32 Kwords) in length, and

uses a Security Sector Indicator Bit (Q7) to indicate

whether or not the Security Sector is locked when shipped

from the factor y. This bit is per-manently set at the fac-

tory and cannot be changed, which prevents cloning of a

facto ry lo cked part. This ensures the security of the ESN

once the product is shipped to the field.

MXIC offers the device with the Security Sector either

factor y locked or customer lockable. The factory-locked

version is always protected when shipped from the fac-

tory, and has the Security on Silicon Sector (Security

Sector) Indicato r Bit permanently set to a "1". The cus-

to mer-lockable v ersion is shipped with the unpro tected,

allowing custo mers to utiliz e the that secto r in any man-

ner they cho o se. The customer-lo ckable v ersion has the

Security on Silico n Sector (Security Sector) Indicato r Bit

permanently set to a "0". Thus, the Security Secto r Indi-

cato r Bit prev ents customer-lockable de vices from being

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

used to replace de vices that are f actory lo c k ed.

The system accesses the Security Secto r through a com-

mand sequence (see "Enter Security Secto r/Exit Secu-

rity Secto r Command Sequence"). After the system has

written the Enter Security Secto r co mmand se-quence ,

it ma y read the Security Secto r by using the ad-dresses

normally o ccupied b y the bo o t sectors. This mo de of o p-

eratio n co ntinues until the system issues the Exit Secu-

rity Sector command sequence, o r until power is remo ved

from the device. On power-up, or following a hardware

reset, the device rever ts to sending commands to the

bo o t sectors.

Factory Locked: Security Sector Programmed and

Protected at the Factory

In a factory locked device, the Security Sector is pro-

tected when the device is shipped from the factory. The

Security Secto r cannot be modified in any w a y. The de-

vice is available preprogrammed with one of the follow-

ing:

A random, secure ESN o nly.

In devices that have an ESN, a Bottom Boot device will

have the 16-byte (8-word) ESN in the lowest address-

able memory area starting at 00000h and ending at

0000Fh (00007h). In the Top Boot device the starting

address of the ESN will be at the bottom of the lowest 8

Kbyte (4 Kword) boot sector starting at 3F0000h

(1F8000h) and ending at 3F000Fh (1F8007h).

Customer Lockable: Security Sector NOT Pro-

grammed or Protected at the Factory

If the security feature is not required, the Security Sec-

tor can be treated as an additional Flash memory space,

expanding the size of the available Flash array by 64

Kbytes (32 Kwords). The Security Sector can be read,

pro gr ammed, and erased as o ften as required. The Se-

curity Sector area can be protected using one of the

following procedures:

Write the three-cycle Enter Security Region command

sequence, and then follow the in-system sector group

protect algorithm as shown in Figure 14, except that

RESET# ma y be at either VIH o r VID. This allows in-sys-

tem protection o f the without raising an y de vice pin to a

high v oltage. No te that this method is only applicable to

the Security Secto r .

Write the three-cycle Enter Secur ity Region command

sequence, and then use the alternate method of sector

protection described in the "Sector/Sector Block Protec-

tion and Unprotection section.

Once the Security Sector is locked and verified, the sys-

tem must write the Exit Security Sector Region com-

mand sequence to return to reading and writing the re-

mainder o f the arr a y.

The Security Sector protection must be used with cau-

tion since, once protected, there is no procedure avail-

able for unprotecting the Security Sector area and none

of the bits in the Security Sector memory space can be

modified in any way.

DA T A PROTECTION

The KH29LV320C T/B is designed to offer protection

against accidental erasure or programming caused by

spurious system level signals that may exist during power

transition. During power up the device automatically re-

sets the state machine in the Read mode. In addition,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specific command sequences. The device also

inco rpo rates several features to prevent inadvertent write

cycles resulting from VCC power-up and power-down tran-

sition or system no ise .

LOW VCC WRITE INHIBIT

When VCC is less than VLKO the device does not ac-

cept any write cycles. This protects data during VCC

pow er-up and power-do wn. The command register and

all internal program/erase circuits are disabled, and the

de vice resets. Subsequent writes are igno red until VCC

is greater than VLKO. The system must pro vide the proper

signals to the control pins to prevent unintentional write

when VCC is greater than VLK O.

WRITE PULSE "GLITCH" PRO TECTION

Noise pulses of less than 5ns (typical) on OE#, CE# or

WE# will not initiate a write cycle.

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KH29LV320C T/B

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# = VIL, CE#

= VIH or WE# = VIH. To initiate a write cycle CE# and

WE# must be a logical zero while OE# is a lo gical one.

POWER-UP SEQUENCE

The KH29LV320C T/B powers up in the Read o nly mode.

In addition, the memory contents may only be altered

after successful co mpletio n o f the predefined co mmand

sequences.

POWER-UP WRITE INHIBIT

If WE#=CE#=VIL and OE#=VIH during power up, the

device do es no t accept co mmands o n the rising edge o f

WE#. The internal state machine is automatically reset

to the read mo de on power-up .

PO WER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween its VCC and GND .

SOFTW ARE COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing them

in the improper sequence will reset the device to the

read mo de . Table 3 defines the v alid register co mmand

sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the

Sector Erase operation is in progress. Either of the two

reset command sequences will reset the device (when

applicable).

All addresses are latched on the falling edge of WE# o r

CE#, whichever happens later. All data are latched on

rising edge of WE# o r CE#, whichever happens first.

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KH29LV320C T/B

First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus

Command Bus Cycle Cycle Cycle Cycle Cycle Cycle

Cycles Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read(Note 5) 1 RA RD

Reset(Note 4) 1 XXX F0

Automatic Select(Note 5)

Manufacturer ID Word 4 555 AA 2AA 55 555 90 X00 C2H

Byte 4 AAA AA 555 55 AAA 90 X00 C2H

Device ID Word 4 555 AA 2AA 55 555 90 X01 ID

Byte 4 AAA AA 555 55 AAA 90 X02

Security Sector Factory Word 4 555 AA 2AA 55 555 90 X03 99/19

Protect Verify (Note 6) Byte 4 AAA AA 555 55 AAA 90 X06

Sector Protect Verify Word 4 555 AA 2AA 55 555 90 (SA)X02 00/01

(Note 7) Byte 4 AAA AA 555 55 AAA 90 (SA)X04

Enter Security Sector Word 3 5 5 5 AA 2A A 5 5 555 88

Region Byte 3 AAA AA 555 55 AAA 88

Exit Security Sector Word 4 5 55 AA 2 A A 55 555 90 XXX 00

Byte 4 AAA AA 555 55 AAA 90 XXX 00

Program Word 4 555 AA 2AA 55 555 A0 PA PD

Byte 4 AAA AA 555 55 AAA A0 PA PD

Chip Erase Word 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Byte 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Sector Erase Word 6 5 55 AA 2A A 5 5 5 55 8 0 5 5 5 AA 2A A 5 5 SA 3 0

Byte 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30

CFI Query (Note 8) Word 1 55 98

Byte 1 AA 98

Erase Suspend(Note 9) 1 SA B0

Erase Resume(Note 10) 1 SA 30

T ABLE 3. KH29L V320C T/B COMMAND DEFINITIONS

Legend:

X=Don't care

RA=Address of the memory location to be read.

RD=Data read from location RA dur ing read operation.

PA=Address of the memor y location to be programmed.

Addresses are latched on the falling edge of the WE# or CE#

pulse.

PD=Data to be pro grammed at location PA. Data is latched o n

the rising edge of WE# or CE# pulse.

SA=Address of the sector to be erased or verified. Address

bits A20-A12 uniquely select any sector.

ID=22A7h(Top), 22A8h(Bottom)

Notes:

1. See Table 1 for descriptions of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or Automatic Select data, all bus cycles are write operation.

4. The Reset command is required to return to the read mode when the device is in the Automatic Select mode or if Q5 goes

high.

5. The four th cycle of the Automatic Select command sequence is a read cycle.

6. The data is 99h for factory locked and 19h for not factor y locked.

7. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. In the third cycle of the

command sequence, address bit A20=0 to verify sectors 0~31, A20=1 to verify sectors 32~70 for Top Boot device.

8. Command is valid when device is ready to read array data or when device is in Automatic Select mode.

9. The system may read and program functions in non-erasing secto r s , or enter the Automatic Select mode, when in the erase

Suspend mode. The Erase Suspend command is valid only during a sector erase operation.

10.The Erase Resume command is valid only during the Erase Suspend mode.

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

READING ARRAY DA T A

The de vice is auto matically set to reading array data af-

ter device power-up. No commands are required to re-

trieve data. The device is also ready to read arr ay data

after completing an Automatic Program or Automatic

Erase algo rithm.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data. After

completing a programming operation in the Erase

Suspend mode, the system may once again read array

data with the same exception. See Erase Suspend/Erase

Resume Commands” for more information on this mode.

The system must issue the reset command to re-en-

able the device for reading array data if Q5 goes high

during an active program or erase operation, or while in

the Automatic Select mode. See the "Reset Command"

section, next.

RESET COMMAND

Writing the reset co mmand to the de vice resets the de-

vice to reading array data. Address bits are don't care fo r

this co mmand.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device igno res

reset co mmands until the o peratio n is co mplete.

The reset command may be written between the se-

quence cycles in a pro gram co mmand sequence befo re

programming begins. This resets the device to reading

array data (also applies to programming in Erase Sus-

pend mode). Once programming begins, however, the

device ignores reset commands until the operation is

complete.

The reset command may be written between the se-

quence cycles in an Automatic Select command se-

quence. Once in the Automatic Select mode, the reset

co mmand must be written to return to reading array data

(also applies to Automatic Select during Erase Suspend).

If Q5 go es high during a program o r erase operation, writ-

ing the reset co mmand returns the device to reading ar-

ray data (also applies during Erase Suspend).

AUTOMA TIC SELECT COMMAND SEQUENCE

The Automatic Select co mmand sequence allows the ho st

system to access the manufacturer and device codes,

and determine whether o r not a sector is pro-tected. Tab le

2 shows the address and data requirements.

This method is an alternative to that shown in Table 3,

which is intended for EPROM programmers and requires

VID on address bit A9.

The Automatic Select command sequence is initiated

by writ-ing two unlock cycles, followed by the Automatic

Select command. The device then enters the Automatic

Select mode, and the system may read at any address

any number of times, without initiating another command

sequence. A read cycle at address XX00h retrieves the

manufacturer code. A read cycle at address XX01h in

word mode (or xx02h in byte mode) returns the device

code. A read cycle containing a sector address (SA) and

the address 02h on A7-A0 in word mode (or the address

04h on A6-A-1 in byte mode) returns 01h if that sector is

protected, or 00h if it is unprotected. Refer to Table 1 for

valid sector addresses.

The system must write the reset command to exit the

Automatic Select mode and return to reading array data.

ENTER SECURITY SECTOR & EXIT SECURITY SEC-

TOR COMMAND SEQUENCE

The Security Sector provides a secured area which con-

tains a random, sixteen-byte electronic serial

number.(ESN)

The system can access the Security Sector area by is-

suing the three-cycle "Enter Security Sector command

sequence. The device continues to access the security

section area until the system issues the four-cycle Exit

Security Sector command sequence. The Exit Security

Sector command sequence returns the device to normal

operation.

BYTE/WORD PROGRAM COMMAND SEQUENCE

The device programs one byte/word of data for each

program operation. The command sequence requires four

bus cycles, and is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in turn

initiate the Embedded Program algorithm. The system is

not required to provide further controls or timings. The

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

device automatically generates the program pulses and

verifies the programmed cell margin. Table 3 shows the

address and data requirements f or the byte/word program

command sequence.

When the Embedded Program algorithm is complete, the

device then returns to reading array data and addresses

are no longer latched. The system can determine the

status of the program operation by using Q7, Q6, or RY/

BY#. See "Write Operatio n Status" fo r info rmatio n on these

status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the programming

operation. The Byte/Word Program command sequence

should be reinitiated once the device has reset to reading

array data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed from a

"0" back to a "1". Attempting to do so may cause the

device to set Q5 to "1", or cause the Data# Polling

Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code (Hex)

Manufacture code VIL VIL 1 1 0 0 0 0 1 0 C2H

Device code for KH29LV320CT VIH VIL 1 0 1 0 0 1 1 1 22A7H

Device code for KH29LV320CB VIH VIL 1 0 1 0 1 0 0 0 22A8H

TABLE 4. SILICON ID CODE

AUTOMATIC CHIP/SECTOR ERASE COMMAND

The device does not require the system to preprogram

prio r to erase. The Automatic Erase algo rithm auto mati-

cally preprograms and verifies the entire memory for an

all zero data pattern prior to electrical erase. The system

is not required to provide any controls or timings during

these operations. Table 3 shows the address and data

requirements for the chip erase command sequence.

Any commands written to the chip during the Automatic

Erase algorithm are ignored. Note that a hard-ware reset

during the chip erase operation immediately terminates

the operation. The Chip Erase co mmand sequence should

algorithm to indicate the operation was successful.

However, a succeeding read will show that the data is

still "0". Only erase operations can convert a "0" to a

"1".

SETUP AUTOMA TIC CHIP/SECT OR ERASE

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are f ollowed b y writing the

"set-up" co mmand 80H. Two mo re "unlo ck" write cycles

are then followed by the chip erase command 10H, or

the sector erase command 30H.

The KH29LV320C T/B contains a Silicon-ID-Read opera-

tion to supplement traditional PROM pro gramming meth-

o dolo gy . The operation is initiated by writing the read sili-

co n ID co mmand sequence into the co mmand register .

Following the command write, a read cycle with

A1=VIL,A0=VIL retrieves the manufacturer code of C2H.

A read cycle with A1=VIL, A0=VIH returns the device

co de of A7H/A8H fo r KH29L V320C T/B.

be reinitiated once the device has returned to reading

arra y data, to ensure data integrity.

The system can determine the status of the erase op-

eratio n by using Q7, Q6, Q2, or R Y/BY#. See "Write Op-

eratio n Status" fo r info rmatio n o n these status bits. When

the Automatic Erase algorithm is complete, the device

returns to reading array data and addresses are no longer

latched.

Figure 5 illustrates the algorithm for the erase opera-tion.

See the Erase/Program Operations tables in "AC Char-

acteristics" for parameters, and to Figure 4 for timing

diagrams.

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KH29LV320C T/B

SECTOR ERASE COMMANDS

The device does not require the system to entirely

pre-program prior to executing the Automatic Set-up

Sector Erase command and Automatic Sector Erase

command. Upon executing the Automatic Sector

Erase command, the device will automatically

program and verify the sector(s) memory for an all-

zero data pattern. The system is not required to

provide any control or timing during these operations.

When the sector(s) is automatically verified to

contain an all-zero pattern, a self-timed sector erase

and verify begin. The erase and verify operations are

complete when the data on Q7 is "1" and the data on

Q6 stops toggling for two consecutive read cycles, at

which time the device returns to the Read mode. The

system is not required to provide any control or timing

during these operations.

When using the Automatic Sector Erase algorithm,

note that the erase automatically terminates when

adequate erase margin has been achieved for the

memory array (no erase verification command is

required). Sector erase is a six-bus cycle operation.

There are two "unlock" write cycles. These are

followed by writing the set-up command 80H. Two

more "unlock" write cycles are then followed by the

sector erase command 30H. The sector address is

latched on the falling edge of WE# or CE#, whichever

happens later , while the command(data) is latched on

the rising edge of WE# or CE#, whichever happens

first. Sector addresses selected are loaded into

internal register on the sixth falling edge of WE# or

CE#, whichever happens later. Each successive

sector load cycle started by the falling edge of WE#

or CE#, whichever happens later must begin within

50us from the rising edge of the preceding WE# or

CE#, whichever happens first. Otherwise, the loading

period ends and internal auto sector erase cycle

starts. (Monitor Q3 to determine if the sector erase

timer window is still open, see section Q3, Sector

Erase Timer.) Any command other than Sector

Erase(30H) or Erase Suspend(B0H) during the time-

out period resets the device to read mode.

ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation,

and therefore will only be responded dur ing Automatic

Secto r Erase operatio n. When the Erase Suspend co m-

mand is issued during the sector erase operation, the

de vice requires a maximum 20us to suspend the secto r

erase operation. However, When the Erase Suspend com-

mand is written during the secto r erase time-o ut, the de-

vice immediately terminates the time-out perio d and sus-

pends the erase o peratio n. After this co mmand has been

executed, the command register will initiate erase sus-

pend mo de. The state machine will return to read mo de

automatically after suspend is ready. At this time , state

machine o nly allows the co mmand register to respo nd to

the Erase Resume, program data to, or read data from

any secto r no t selected fo r erasure. The system can use

Q7, or Q6 and Q2 together, to deter mine if a sector is

actively erasing or is erase-suspended.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within no n-suspended blo cks.

ERASE RESUME

This co mmand will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing.

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

T able 5. Write Operation Status

Notes:

1. P erf orming successive read operatio ns from the erase-suspended secto r will cause Q2 to toggle.

2. Performing successive read operations from any address will cause Q6 to toggle.

3. Reading the byte/word address being programmed while in the erase-suspend program mode will indicate logic "1"

at the Q2 bit.

How ever, successive reads from the erase-suspended secto r will cause Q2 to toggle.

WRITE OPERATION STATUS

The device provides several bits to deter mine the sta-

tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY /

BY#. Table 5 and the fo llowing subsectio ns describe the

functio ns of these bits. Q7, RY/BY#, and Q6 each o ffer a

metho d f o r determining whether a pro gram o r er ase o p-

eration is complete or in progress. These three bits are

discussed first.

Status Q7 Q6 Q5 Q3 Q2 RY/

Note1 Note2 BY#

Byte/Word Program in Auto Program Algorithm Q7 # Toggle 0 N/A No 0

Toggle

Auto Erase Algorithm 0 Toggle 0 1 Toggle 0

Erase Suspend Read 1 No 0 N/A Toggle 1

(Erase Suspended Sector) Toggle

In Progress Erase Suspended Mode Erase Suspend Read Data Data Data Data Data 1

(Non-Erase Suspended Sector)

Erase Suspend Program Q7# Toggle 0 N/A N/A 0

Byte/Word Program in Auto Program Algorithm Q7 # Toggle 1 N/A No 0

Toggle

Exceeded

Time Limits Auto Erase Algorithm 0 Toggle 1 1 Toggle 0

Erase Suspend Program Q7# Toggle 1 N/A N/A 0

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KH29LV320C T/B

Q7: Data# P olling

The Data# Polling bit, Q7, indicates to the host system

whether an Automatic Algorithm is in progress or com-

pleted, or whether the device is in Erase Suspend. Data#

P olling is valid after the rising edge o f the final WE# pulse

in the program or erase command sequence.

During the Automatic Program algorithm, the device out-

puts on Q7 the complement of the datum programmed

to Q7. This Q7 status also applies to programming dur-

ing Erase Suspend. When the Auto matic Pro gram algo-

rithm is complete, the device outputs the datum pro-

gr ammed to Q7. The system must provide the pro g ram

address to read valid status information on Q7. If a pro-

gram address falls within a pro tected secto r , Data# Po ll-

ing on Q7 is activ e for appro ximately 1 us , then the de-

vice returns to reading array data.

During the Auto matic Erase algorithm, Data# Polling pro-

duces a "0" o n Q7. When the Auto matic Erase algo rithm

is complete, or if the device enters the Erase Suspend

mo de, Data# Po lling produces a "1" on Q7. This is analo-

gous to the complement/true datum out-put described

for the Automatic Program algorithm: the erase function

changes all the bits in a sector to "1" prior to this, the

device outputs the "complement," or "0". The system must

pro vide an address within any o f the sectors selected fo r

erasure to read v alid status info rmation o n Q7.

After an erase command sequence is written, if all sec-

to rs selected f o r erasing are pro tected, Data# P olling o n

Q7 is active for approximately 100 us, then the device

returns to reading array data. If not all selected sectors

are protected, the Automatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

When the system detects Q7 has changed from the

complement to true data, it can read valid data at Q7-Q0

on the following read cycles. This is because Q7 may

change asynchronously with Q0-Q6 while Output Enable

(OE#) is asserted low.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid

after the rising edge o f the final WE# or CE#, whichev er

happens first pulse in the command sequence (prior to

the program or erase operation), and during the sector

time-out.

During an Automatic Program or Erase algorithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE# or CE# to

co ntro l the read cycles. When the operatio n is co mplete,

Q6 sto ps to ggling.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Q6 toggles for

100us and returns to reading array data. If not all se-

lected sectors are protected, the Automatic Erase algo-

rithm erases the unprotected sectors, and ignores the

selected sectors that are protected.

The system can use Q6 and Q2 together to determine

whether a sector is actively erasing or is erase suspended.

When the device is actively erasing (that is, the Auto-

matic Erase algo rithm is in progress), Q6 to ggling. When

the device enters the Erase Suspend mode, Q6 stops

toggling. Howev er, the system must also use Q2 to de-

termine which sectors are erasing or erase-suspended.

Alternatively, the system can use Q7.

If a program address falls within a protected sector, Q6

toggles for approximately 2us after the program com-

mand sequence is written, then returns to reading array

data.

Q6 also toggles during the erase-suspend-program mode,

and stops toggling once the Automatic Program algo-

rithm is complete.

Table 5 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "To ggle Bit II" o n Q2, when used with Q6, indicates

whether a par ticular sector is actively erasing (that is,

the Automatic Erase algorithm is in process), or whether

that sector is erase-suspended. Toggle Bit II is valid

after the rising edge o f the final WE# o r CE#, whiche ver

happens first pulse in the command sequence.

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE# or CE# to control the read

cycles.) But Q2 canno t distinguish whether the secto r is

actively erasing o r is erase-suspended. Q6, by co mpari-

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

so n, indicates whether the device is actively er asing, o r

is in Erase Suspend, but cannot distinguish which sec-

to rs are selected fo r er asure. Thus, both status bits are

required for sectors and mo de info rmation. Refer to Table

5 to co mpare o utputs f o r Q2 and Q6.

Reading T oggle Bits Q6/ Q2

Whenev er the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a toggle bit is to ggling. Typically , the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

co mpleted the program o r erase operatio n. The system

can read array data on Q7-Q0 on the following read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase opera-

tion. If it is still toggling, the device did not complete the

operation successfully, and the system must write the

reset command to return to reading array data.

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previo us paragraph. Alternatively ,

it may choose to perform other system tasks. In this

case, the system must start at the beginning of the al-

gorithm when it returns to determine the status of the

operation.

Q5:Program/Erase Timing

Q5 will indicate if the program o r erase time has exceeded

the specified limits(internal pulse count). Under these

co nditio ns Q5 will pro duce a "1". This time-o ut conditio n

indicates that the program or erase cycle was not suc-

cessfully completed. Data# Polling and Toggle Bit are

the o nly operating functio ns o f the device under this co n-

dition.

If this time-out condition occurs during sector erase op-

eration, it specifies that a particular secto r is bad and it

may not be reused. Howe ver , other secto rs are still func-

tional and may be used f or the program o r er ase opera-

tio n. The device must be reset to use o ther sectors. Write

the Reset command sequence to the device, and then

execute pro gram o r erase co mmand sequence. This al-

lows the system to co ntin ue to use the o ther active sec-

tors in the device.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

If this time-out condition occurs during the byte/word pro-

gramming operation, it specifies that the entire sector

containing that byte/word is bad and this sector maynot

be reused, (other sectors are still functional and can be

reused).

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the Au-

tomatic Algorithm operation. Hence, the system never

reads a valid data on Q7 bit and Q6 never stops toggling.

Once the Device has exceeded timing limits, the Q5 bit

will indicate a "1". Please note that this is not a device

failure condition since the device was incorrectly used.

The Q5 failure condition may appear if the system tries

to program a "1" to a location that is previously pro-

grammed to "0". Only an erase operation can change a

"0" back to a "1". Under this condition, the device halts

the operation, and when the operation has exceeded the

timing limits, Q5 produces a "1".

Q3:Sector Erase Timer

After the co mpletio n o f the initial secto r erase co mmand

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is co mplete. Data# P o lling

and T o ggle Bit are valid after the initial secto r erase com-

mand sequence.

If Data# Po lling or the Toggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is

still o pen. If Q3 is high ("1") the internally contro lled erase

cycle has begun; attempts to write subsequent commands

to the de vice will be ignored until the erase operatio n is

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

co mpleted as indicated by Data# P o lling o r Toggle Bit. If

Q3 is low ("0"), the device will accept additional sector

erase co mmands. To insure the command has been ac-

cepted, the system software should check the status of

Q3 prio r to and f o llowing each subsequent sector erase

co mmand. If Q3 w ere high o n the seco nd status check,

the co mmand ma y no t hav e been accepted.

If the time between additional erase commands from the

system can be less than 50us, the system need not to

mo nitor Q3.

RY/BY#:READY/BUSY# OUTPUT

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in progress

or complete. The RY/BY# status is valid after the rising

edge o f the final WE# pulse in the co mmand sequence.

Since RY/BY# is an o pen-dr ain o utput, se v eral RY/BY#

pins can be tied to gether in parallel with a pull-up resistor

to VCC .

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the Erase

Suspend mode.) If the output is high (Ready), the device

is ready to read array data (includ-ing during the Erase

Suspend mode), or is in the standby mode.

QUERY COMMAND AND COMMON FLASH INTER-

F ACE (CFI) MODE

KH29L V320C T/B is capable o f operating in the CFI mode.

This mode all the host system to deter mine the manu-

facturer o f the device such as o perating parameters and

co nfiguratio n. Two commands are required in CFI mo de.

Query command of CFI mode is placed first, then the

Reset co mmand exits CFI mo de. These are described in

Table 3.

The single cycle Query command is valid only when the

device is in the Read mode, including Erase Suspend,

Standby mode, and Automatic Select mo de; howe v er , it

is ignored otherwise.

The Reset command exits from the CFI mode to the

Read mode, or Erase Suspend mode, or Automatic Se-

lect mo de. The command is valid o nly when the device is

in the CFI mo d e.

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

T able 6-1. CFI mode: Identification Data Values

(All values in these tables are in hexadecimal)

Description Address (h) Address (h) Data (h)

(Word Mode) (Byte Mode)

Query-unique ASCII string "QRY" 1 0 2 0 0051

11 22 0052

12 24 0059

Primary vendor command set and control interface ID code 1 3 2 6 0002

14 28 0000

Address for primary algorithm extended query table 1 5 2A 0040

16 2C 0000

Alternate vendor command set and control interface ID code (none) 1 7 2E 0000

18 30 0000

Address for secondary algorithm extended query table (none) 1 9 32 0000

1A 34 0000

T able 6-2. CFI Mode: System Interface Data V alues

Description Address (h) Address (h) Data (h)

(Word Mode) (Byte Mode)

VCC supply, minimum (2.7V) 1B 3 6 0027

VCC supply, maximum (3.6V) 1 C 3 8 0036

VPP supply, minimum (none) 1 D 3A 0000

VPP supply, maximum (none) 1E 3C 0000

Typical timeout for single word/byte write (2N us) 1F 3E 0004

Typical timeout for maximum size buffer write (2N us) (not supported) 2 0 4 0 0000

Typical timeout for individual sector erase (2N ms) 2 1 4 2 000A

Typical timeout for full chip erase (2N ms) 2 2 44 0000

Maximum timeout for single word/byte write times (2N X Typ) 23 4 6 0005

Maximum timeout for maximum size buffer write times (2N X Typ) 24 4 8 0000

Maximum timeout for individual sector erase times (2N X Typ) 2 5 4 A 0004

Maximum timeout for full chip erase times (not supported) 2 6 4C 0000

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KH29LV320C T/B

T able 6-3. CFI Mode: Device Geometry Data V alues

Description Address (h) Address (h) Data (h)

(Word Mode) (Byte Mode)

Device size (2N bytes) 27 4E 0016

Flash device interface code (02=asynchronous x8/x16) 2 8 5 0 0002

29 52 0000

Maximum number of bytes in multi-byte write (not supported) 2A 5 4 0000

2B 56 0000

Number of erase sector regions 2 C 5 8 0002

Erase Sector Region 1 Information 2 D 5A 0007

[2E,2D] = # of same-size sectors in region 1-1 2E 5C 0000

[30, 2F] = sector size in multiples of 256-bytes 2F 5E 0020

30 60 0000

Erase Sector Region 2 Information 3 1 6 2 003E

32 64 0000

33 66 0000

34 68 0001

Erase Sector Region 3 Information 3 5 6A 0000

36 6C 0000

37 6E 0000

38 70 0000

Erase Sector Region 4 Information 3 9 7 2 0000

3A 74 0000

3B 76 0000

3C 78 0000

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KH29LV320C T/B

T able 6-4. CFI Mode: Primary V endor-Specific Extended Query Data V alues

Description Address (h) Address (h) Data (h)

(Word Mode) (Byte Mode)

Query-unique ASCII string "PRI" 4 0 8 0 0050

41 82 0052

42 84 0049

Major version number, ASCII 4 3 8 6 0031

Minor version number, ASCII 4 4 8 8 0031

Address sensitive unlock (0=required, 1= not required) 4 5 8A 0000

Erase suspend (2= to read and write) 4 6 8 C 0002

Sector protect (N= # of sectors/group) 4 7 8E 0004

Temporary sector unprotect (1=supported) 48 90 0001

Sector protect/Chip unprotect scheme 49 92 0004

Simultaneous R/W operation (0=not supported) 4A 94 0000

Burst mode type (0=not supported) 4B 9 6 0000

Page mode type (0=not supported) 4 C 98 0000

ACC (Acceleration) Supply Minimum 4D 9A 00B5

(0=not supported, D7-D4:Volt, D3-D0:100mV

ACC (Acceleration) Supply Maximum 4E 9 C 00C5

(0=not supported, D7-D4:Volt, D3-D0:100mV

Top/Bottom Boot Sector Flag 4 F 9E 000X

02h=Bottom Boot Device, 03h=Top Boot Device

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KH29LV320C T/B

ABSOLUTE MAXIMUM RATINGS

Storage T emperature

Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC

Ambient T emperature

with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC

Vo ltage with Respect to Gro und

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE#, and

RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC v oltage o n input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-

shoot VSS to -2.0 V for periods of up to 20ns. Maxi-

mum DC voltage on input or I/O pins is VCC +0.5 V.

During voltage transitions, input or I/O pins may over-

shoot to VCC +2.0 V for periods up to 20 ns.

2. Minimum DC input v o ltage o n pins A9, OE#, and RE-

SET# is -0.5 V. Dur ing voltage transitions, A9, OE#,

and RESET# may o versho o t VSS to -2.0 V fo r perio ds

of up to 20 ns. Maximum DC input voltage on pin A9

is +12.5 V which may overshoo t to 14.0 V for perio ds

up to 20 ns.

3. No more than o ne output may be sho rted to ground at

a time. Duration of the short circuit should not be

greater than one second.

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device at these or any other conditions above those in-

dicated in the operational sections of this data sheet is

not implied. Exposure of the device to absolute maxi-

mum rating conditions for extended periods may affect

device reliability.

OPERA TING RATINGS

Commercial (C) Devices

Ambient Temperature (TA ). . . . . . . . . . . . 0 °C to +70°C

Industrial (I) Devices

Ambient Temperature (TA ). . . . . . . . . . -4 0°C to +85°C

VCC Supply Voltages

VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V

Operating ranges define tho se limits between which the

functio nality o f the de vice is guaranteed.

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Notes:

1. On the WP#/ACC pin only, the maximum input load current when WP#/ACC = VIL is ± 5.0uA / VIH is ± 3.0uA.

2. Maxim um ICC specificatio ns are tested with VCC = VCC max.

3. The ICC current listed is typically is less than 2 mA/MHz, with OE# at VIH. Typical specifications are for VCC = 3.0V.

4. ICC active while Embedded Erase o r Embedded Pro gram is in pro gress.

5. A uto matic sleep mo de enab les the low power mode when addresses remain stable f o r tACC + 30 ns. Typical sleep

mo de current is 200 nA.

6. Not 100% tested.

DC CHARACTERISTICS VCC=2.7V~3.6V

Para- Description T est Conditions T A=0°°

°°

°C to 70°°

°°

°C T A=-40°°

°°

°C to 85°°

°°

°C

meter Min Typ Max Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC, ±1.0 ±1.0 uA

(Note 1) VCC = VCC max

ILIT A9 Input Load Current VCC = VCC max, 3 5 4 5 uA

A9=12.5V

ILO Output Leakage Current VOUT = VSS to VCC , ±1.0 ±1.0 uA

VCC = VCC max

ICC1 VCC Active Read Current CE#=VIL, 5 MHz 1 0 1 6 1 0 1 6 mA

(No tes 2, 3) OE#=VIH 1 MHz 2 4 2 4 mA

ICC2 VCC Active Write Current CE#=VIL , OE# = VIH, 15 30 15 30 mA

(No tes 2, 4, 6) WE#=VIL

ICC3 VCC Standby Current CE#, RESET#, 0.2 15 0.2 1 5 uA

(No te 2) WP#/ACC = VCC±0.3V

ICC4 VCC Reset Current (No te 2) RESET# = VSS ± 0.3V, 0.2 15 0.2 15 uA

WP#/ACC= VCC ± 0.3V

ICC5 Automatic Sleep Mode VIH = VCC ± 0.3V; 0.2 15 0.2 15 uA

(Notes 2,5) VIL = VSS ± 0.3V,

WP#/ACC=VCC±0.3V

IACC WP#/ACC Accelerated CE#=VIL, WP#/ACC pin 5 1 0 5 10 mA

Pro gram Current, Wo rd or Byte OE#=VIH VCC pin 1 5 3 0 15 3 0 mA

VIL Input Low V oltage -0.5 0.8 -0.5 0.8 V

VIH Input High V o ltage 0.7xVcc Vcc+0.3 0.7xVcc Vcc+0.3 V

VHH Voltage for WP#/ACC Sector VCC = 3.0 V ± 10% 11.5 12.5 11.5 12.5 V

Protect/Unprotect and

Program Acceleration

VID Voltage for Automatic Select VCC = 3.0 V ± 1 0% 11.5 12.5 11.5 12.5 V

and T emporary Sector

Unprotect

V OL Output Low V o ltage IOL=4.0mA, 0.45 0.45 V

VCC=VCC min

V OH1 Output High V o ltage IOH=-2.0mA, 0.85Vcc 0.85Vcc V

VCC=VCC min

VOH2 IOH=-100uA, Vcc-0.4 Vcc-0.4 V

VCC = VCC min

VLKO Low VCC Lock-Out V oltage 1.4 2.1 1.4 2.1 V

(Note 6)

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

SWITCHING TEST CIRCUITS TEST SPECIFICA TIONS

Test Condition 7 0 9 0 Unit

Output Load 1 TTL gate

Output Load Capacitance,CL 30 100 pF

(including jig capacitance)

Input Rise and F all Times 5 ns

Input Pulse Levels 0.0-3.0 V

Input timing measurement 1.5 V

reference levels

Output timing measurement 1.5 V

reference levels

1.5V 1.5V

Measurement Level

3.0V

0.0V OUTPUT

INPUT

SWITCHING TEST WAVEFORMS

DEVICE UNDER

TEST

DIODES=IN3064

OR EQUIVALENT

CL 6.2K ohm

1.6K ohm +3.3V

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Do n't Care, Any Change P ermitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State(High Z)

KEY TO SWITCHING WAVEFORMS

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Symbol DESCRIPTION CONDITION 70 90 Unit

tACC Address to o utput dela y CE#=VIL MAX 70 90 ns

OE#=VIL

tCE Chip enable to o utput delay OE#=VIL MAX 70 9 0 ns

tOE Output enable to output delay MAX 40 4 0 ns

tDF OE# High to output flo at(Note1) MAX 30 3 0 ns

t OH Output hold time of from the rising edge of MI N 0 0 ns

Address, CE# o r OE# whiche ver happens first

t R C Read cycle time (Note 1) MI N 70 9 0 n s

t W C Write cycle time (Note 1) MIN 70 90 ns

tCWC Command write cycle time(Note 1) MIN 70 9 0 ns

tAS Address setup time MI N 0 0 ns

tAH Address hold time MIN 45 4 5 ns

tDS Data setup time MI N 45 4 5 ns

tDH Data hold time MIN 0 0 ns

tVCS VCC setup time(Note 1) MIN 50 5 0 ns

tCS Chip enable setup time MIN 0 0 ns

tCH Chip enable hold time MIN 0 0 ns

tOES Output enable setup time (Note 1) MIN 0 0 ns

tOEH Output enable hold time (Note 1) Read M IN 0 0 ns

Toggle & MIN 10 10 ns

Data# Polling

tWES WE# setup time MI N 0 0 ns

tWEH WE# ho ld time MIN 0 0 ns

tCEP CE# pulse width MIN 45 4 5 ns

tCEPH CE# pulse width high MIN 30 30 ns

tWP WE# pulse width MIN 35 3 5 ns

tWPH WE# pulse width high MI N 30 3 0 ns

tBUSY Pro gram/Erase v alid to R Y/BY# delay MAX 9 0 9 0 ns

tGHWL Read recovery time before write MIN 0 0 ns

tGHEL Read recovery time before write MIN 0 0 ns

tWHWH1 Programming operation BYTE TYP 9 9 us

WORD TYP 11 11 us

Accelerated programming operation word or TYP 7 7 us

byte

tWHWH2 Sector erase operation TYP 0.9 0.9 sec

tBAL Sector address hold time MAX 5 0 5 0 us

No tes: 1.Not 100% Tested

AC CHARACTERISTICS T A=-40° C to 85° C, VCC=2.7V~3.6V

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 1. COMMAND WRITE OPERA TION

Addresses

CE#

OE#

WE#

DIN

tDS

tAH

Data

tDH

tCS tCH

tCWC

tWPH

tWP

tOES

tAS

VCC 3V

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

ADD V alid

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

READ/RESET OPERATION

Figure 2. READ TIMING W A VEFORMS

Addresses

CE#

OE#

tACC

WE#

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH

VOL

HIGH Z HIGH Z

D ATA V alid

tOE

tOEH tDF

tCE

tRC

Outputs

tOH

ADD V alid

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 3. RESET# TIMING W AVEFORM

AC CHARACTERISTICS

Parameter Description Test Setup All Speed Options Unit

tREAD Y1 RESET# PIN Low (During Auto matic Algorithms) MAX 2 0 us

to Read o r Write (See No te)

tREAD Y2 RESET# PIN Low (NOT During Automatic MAX 500 ns

Algo rithms) to Read o r Write (See No te)

tRP1 RESET# Pulse Width (During Auto matic Algorithms) MIN 1 0 us

tRP2 RESET# Pulse Width (NOT During Automatic Algorithms) MIN 500 ns

tRH RESET# High Time Befo re Read(See No te) MIN 7 0 ns

tRB1 RY/BY# Reco very Time(to CE#, OE# go low) MIN 0 ns

tRB2 RY/BY# Recovery Time(to WE# go low) MIN 50 ns

Note:Not 100% tested

tRH

tRB1

tREADY1

tRP2

tRP1

tREADY2

RY/BY#

CE#, OE#

RESET#

Reset Timing NOT during Automatic Algorithms

Reset Timing during Automatic Algorithms

RY/BY#

CE#, OE#

tRB2

WE#

RESET#

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

ERASE/PROGRAM OPERATION

Figure 4. AUTOMA TIC CHIP ERASE TIMING W A VEFORM

tWC

Address

OE#

CE#

55h

2AAh SA

10h

Progress Complete

VA VA

Note:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

tAS

tAH

555h for chip erase

tGHWL

tCH

tWP

tDS tDH

tWHWH2

Read Status Data Erase Command Sequence(last two cycle)

tBUSY tRB

tCS tWPH

tVCS

WE#

Data

RY/BY#

VCC

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 5. AUTOMA TIC CHIP ERASE ALGORITHM FLO WCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

YES

Write Data 10H Address 555H

Write Data 55H Address 2AAH

DATA = FFh ?

YES

Auto Erase Completed

Data Poll

from system

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 6. A UTOMATIC SECTOR ERASE TIMING WA VEFORM

tWC

Address

OE#

CE#

55h

2AAh Sector

Address 1

Sector

Address 0

30h In

Progress Complete

VA VA

30h

Note:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

Sector

Address n

tAS

tAH

tBAL

tGHWL

tCH

tWP

tDS tDH

tWHWH2

Read Status Data Erase Command Sequence(last two cycle)

tBUSY tRB

tCS tWPH

tVCS

WE#

Data

RY/BY#

VCC

30h

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 7. A UTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data AAH Address 555H

Write Data 80H Address 555H

Write Data 30H Sector Address

Write Data 55H Address 2AAH

Auto Sector Erase Completed

Data Poll from System

YES

Data=FFh?

Last Sector

to Erase ?

YES

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 8. ERASE SUSPEND/RESUME FLOWCHART

START

Write Data B0H

Toggle Bit checking Q6

not toggled

ERASE SUSPEND

YES

Write Data 30H

Continue Erase

Reading or

Programming End

Read Array or

Program

Another

Erase Suspend ? NO

YES

ERASE RESUME

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 9. AUTOMA TIC PROGRAM TIMING W A VEFORMS

Figure 10. Accelerated Program Timing Diagram

tWC

Address

OE#

CE#

A0h

555h PA

PD Status DOUT

PA PA

Note:

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

tAS

tAH

tGHWL

tCH

tWP

tDS tDH

tWHWH1

Read Status Data (last two cycle)Program Command Sequence(last two cycle)

tBUSY tRB

tCS tWPH

tVCS

WE#

Data

RY/BY#

VCC

WP#/ACC

tVHH

VHH (11.5V ~ 12.5V)

VIL or VIH VIL or VIH

tVHH

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 11. CE# CONTROLLED WRITE TIMING WA VEFORM

tWC

tWH

tGHEL

tWHWH1 or 2

tCP

Address

WE#

OE#

CE#

Data Q7

Data# Polling

DOUT

RESET#

RY/BY#

Notes:

1. PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.

2. Figure indicates the last two bus cycles of the command sequence.

tAH

tAS

PA for program

SA for sector erase

555 for chip erase

tRH

tDH

tDS

tWS

A0 for program

55 for erase

tCPH

tBUSY

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 12. A UTOMA TIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Program Data/Address

Write Data A0H Address 555H

YES

Verify Data OK ?

YES

Auto Program Completed

Data Poll

from system

Increment

Address

Last Address ?

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

SECTOR GROUP PROTECT/CHIP UNPROTECT

Figure 13. Sector Group Protect/Chip Unprotect Waveform (RESET# Control)

Note:

1. For sector group protect A6=0, A1=1, A0=0 ; for chip unprotect A6=1, A1=1, A0=0

Sector Group Protect: 150us

Chip Unprotect: 15ms

1us

VID

VIH

Data

SA, A6

A1, A0

CE#

WE#

OE#

Valid (note2)Valid (note2) Valid (note2)

Status

Sector Group Protect or Chip Unprotect

40h60h60h

Verify

RESET#

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 14. IN-SYSTEM SECTOR GROUP PRO TECT/CHIP UNPROTECT ALGORITHMS WITH RESET#=VID

START

PLSCNT=1

RESET#=VID

Wait 1us

Set up sector address

Sector Protect:

Write 60h to sector

address with

A6=0, A1=1, A0=0

Wait 150us

Verify Sector Protect:

Write 40h to sector

address with

A6=0, A1=1, A0=0

Read from

sector address

with

A6=0, A1=1, A0=0

Reset

PLSCNT=1

Remove VID from RESET#

Write reset command

Sector Protect

Algorithm

Chip Unprotect

Algorithm

Sector Protect complete Remove VID from RESET#

Write reset command

Chip Unprotect complete

Device failed

Temporary Sector

Unprotect Mode

Increment PLSCNT

First Write

Cycle=60h?

Set up first sector address

Protect all sectors:

The indicated portion of

the sector protect algorithm

must be performed

for all unprotected sectors

prior to issuing the first

sector unprotect address

Chip Unprotect:

Write 60h to sector

address with

A6=1, A1=1, A0=0

Time Out Timing (note 1)

Verify Sector Unprotect:

Write 40h to sector

address with

A6=1, A1=1, A0=0

Read from

sector address

with

A6=1, A1=1, A0=0

Data=01h?

PLSCNT=25?

Device failed

START

PLSCNT=1

RESET#=VID

Wait 1us

First Write

Cycle=60h?

All sectors

protected?

Data=00h?

PLSCNT=1000?

Last sector

verified?

Yes

YesYes

Yes

Protect another

sector?

Reset

PLSCNT=1

Temporary Sector

Unprotect Mode

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 15. TEMPORAR Y SECTOR GROUP UNPROTECT WA VEFORMS

T able 7. TEMPORARY SECT OR GROUP UNPROTECT

Parameter Std. Description Test Setup All Speed Options Unit

tVI DR VID Rise and F all Time (See No te) Mi n 5 0 0 ns

tRSP RESET# Setup Time for T emporary Sector Unprotect Min 4 us

Note:

Not 100% tested

RESET#

CE#

WE#

RY/BY#

tVIDR

12V

0 or 3V VIL or VIH

tRSP

tVIDR

Program or Erase Command Sequence

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 16. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART

Start

RESET# = VID (Note 1)

Perform Erase or Program Operation

RESET# = VIH

Temporary Sector Unprotect Completed(Note 2)

Operation Completed

2. All previously protected sectors are protected again.

Notes : 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V.

(if WP#/ACC=VIL, outermost boot sectors will remain protected)

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 17. SILICON ID READ TIMING W A VEFORM

tACC

tCE

tACC

tOE

tOH tOH

tDF

DATA OUT

C2H A7H (TOP boot)

A8H (Bottom boot)

VID

VIH

VIL

ADD

CE#

OE#

WE#

ADD

DATA OUT

DATA

Q0-Q7

VCC 3V

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

WRITE OPERATION STATUS

Figure 18. D A T A# POLLING TIMING WA VEFORMS (DURING AUTOMA TIC ALGORITHMS)

Note:

VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.

tDF

tCE

tCH

tOE

tOEH

tACC

tRC

tOH

Address

CE#

OE#

WE#

Q0-Q6

RY/BY#

tBUSY

Status Data Status Data

Status Data Complement True Valid Data

VAVA

High Z

Valid DataTrue

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 19. Data# P olling Algorithm

START

Read Q7~Q0

Add. = VA (1)

Yes

Q7 = Data ?

Q5 = 1 ?

Read Q7~Q0

Add. = VA

PASS

FAIL

(2)

Notes:

1. VA=valid address f o r pro g ramming o r er asure.

2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 20. TOGGLE BIT TIMING WA VEFORMS (DURING AUTOMA TIC ALGORITHMS)

Note:

VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and

array data read cycle.

tDF

tCE

tCH

tOE

tOEH

tACC

tRC

tOH

Address

CE#

OE#

WE#

Q6/Q2

RY/BY#

tBUSY

Valid Status

(first read)

Valid Status

(second read) (stops toggling)

Valid Data

VA VA

Valid Data

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

START

Read Q7~Q0

YES

Toggle Bit Q6

=Toggle?

Q5=1?

YES

(Note 1)

Read Q7~Q0 Twice (Note 1,2)

Toggle Bit Q6=

Toggle?

Program/Erase Operation Not

Complete, Write Reset Command

YES

Program/Erase Operation Complete

Figure 21. Toggle Bit Algorithm

Notes:

1. Read toggle bit twice to determine whether or not it is toggling.

2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 22. Q6 versus Q2

Note:

The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended

WE#

Enter Embedded

Erasing Erase

Suspend Enter Erase

Suspend Program

Erase

Suspend

Program

Erase Suspend

Read

Erase Suspend

Read Erase

Erase

Resume

Erase

Complete

Erase

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

Figure 23. BYTE# TIMING W AVEFORM FOR READ OPERATIONS (BYTE# switching fr om byte mode to wor d

mode)

AC CHARACTERISTICS

WORD/BYTE CONFIGURA TION (BYTE#)

Parameter Description Speed Options Unit

JEDEC Std -70 -90

tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 2 5 30 ns

tFHQV BYTE# Switching High to Output Active Mi n 70 90 ns

tFHQV

tELFH

DOUT

(Q0-Q7) DOUT

(Q0-Q14)

VA DOUT

(Q15)

CE#

OE#

BYTE#

Q0~Q14

Q15/A-1

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

RECOMMENDED OPERATING CONDITIONS

At Device Power-Up

AC timing illustrated in Figure A is reco mmended fo r the supply v o ltages and the co ntro l signals at device po wer-up.

If the timing in the figure is igno red, the device may not o perate correctly.

Figure A. AC Timing at Device P ower-Up

Notes :

1. Sampled, no t 100% tested.

2. This specificatio n is applied f o r no t o nly the device po wer-up but also the no rmal o peratio ns.

Symbol Parameter Notes Min. Max. Unit

tVR VCC Rise Time 1 2 0 500000 us/V

tR Input Signal Rise Time 1, 2 2 0 us/V

tF Input Signal F all Time 1, 2 2 0 us/V

VCC

ADDRESS

CE#

WE#

OE#

DATA

tVR

tACC

tR or tF

tCE

VCC(min)

GND

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VOH High Z

VOL

WP#/ACC VIH

VIL

Valid

Ouput

Valid

Address

tR or tF

tOE

tF tR

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

MIN. MAX.

Input Voltage with respect to GND on all pins except I/O pins -1.0V 12.5V

Input Voltage with respect to GND on all I/O pins -1.0V VCC + 1.0V

VCC Current -100mA +100mA

Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.

LIMITS

PARAMETER MIN. TYP.(2) MAX. UNITS

Sector Erase Time 0. 9 1 5 sec

Chip Erase Time 3 5 5 0 sec

Byte Programming Time 9 300 us

Word Program Time 1 1 360 us

Chip Programming Time Byte Mode 3 6 10 8 sec

Word Mode 24 72 sec

Accelerated Byte/Word Program Time 7 210 us

Erase/Program Cycles 100,000 Cycles

LATCH-UP CHARACTERISTICS

ERASE AND PROGRAMMING PERFORMANCE(1)

Note: 1.Not 100% Tested, Excludes external system le v el over head.

2.Typical values measured at 25°C,3.3V.

Parameter Symbol Parameter Description Test Set TYP MAX UNIT

CIN Input Capacitance VIN=0 6 7.5 pF

COUT Output Capacitance VOUT=0 8.5 1 2 pF

CIN2 Control Pin Capacitance VIN=0 7.5 9 pF

TSOP PIN CAPACITANCE

Notes:

1. Sampled, no t 100% tested.

2. T est conditions T A=25°C , f=1.0MHz

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

P ART NO. A CCESS OPERA TING ST ANDBY PA CKA GE Remark

TIME (ns) Current MAX. (mA) Current MAX. (uA)

KH29LV320CTTC-70 7 0 3 0 5 48 Pin TSOP

(Normal Type)

KH29LV320CBTC-70 7 0 3 0 5 48 Pin TSOP

(Normal Type)

KH29LV320CTTC-90 9 0 3 0 5 48 Pin TSOP

(Normal Type)

KH29LV320CBTC-90 9 0 3 0 5 48 Pin TSOP

(Normal Type)

KH29LV320CTTC-70G 70 30 5 48 Pin TSOP PB free

(Normal Type)

KH29LV320CBTC-70G 70 30 5 48 Pin TSOP PB free

(Normal Type)

KH29LV320CTTC-90G 90 30 5 48 Pin TSOP PB free

(Normal Type)

KH29LV320CBTC-90G 90 30 5 48 Pin TSOP PB free

(Normal Type)

ORDERING INFORMATION

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

PART NAME DESCRIPTION

KH 29 LV 70C T T C G

OPTION:

G: Lead-free package

blank: normal

SPEED:

70: 70ns

90: 90ns

TEMPERATURE RANGE:

C: Commercial (0˚C to 70˚C)

PACKAGE:

T: TSOP

BOOT BLOCK TYPE:

T: Top Boot

B: Bottom Boot

REVISION:

DENSITY & MODE:

320: 32Mb, x8/x16 Boot Block

TYPE:

LV: 3V

DEVICE:

29:Flash

320

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

PACKAGE INFORMATION

P/N:PM1251 REV. 1.1, DEC. 09, 2005

KH29LV320C T/B

REVISION HISTORY

Revision No. Description Page Date

1.1 1. Mo dified content error P33,53 DEC/09/2005

MACRONIX INTERNATIONAL CO., LTD .

Headquarters:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

Europe Office :

TEL:+32-2-456-8020

FAX:+32-2-456-8021

Hong Kong Office :

TEL:+86-755-834-335-79

FAX:+86-755-834-380-78

Japan Office :

Kawasaki Office :

TEL:+81-44-246-9100

FAX:+81-44-246-9105

Osaka Office :

TEL:+81-6-4807-5460

FAX:+81-6-4807-5461

Singapore Office :

TEL:+65-6346-5505

FAX:+65-6348-8096

Taipei Office :

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-262-8887

FAX:+1-408-262-8810

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

KH29LV320C T/B