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Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
October 2012
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FT3001 • Rev. 1.0.4
FT3001 — Reset Timer with Configurable Delay
FT3001
Reset Timer with Configurable Delay
Features
Delay Times: 3.0, 3.75, 4.5, 6.0 Seconds
≤ 1 µA ICC Current Consumption in Standby
Primary and Secondary Input Reset Pins
Push-Pull and Open-Drain Output Pins
1.65 V to 5.0 V Operation at TA = 0C to +85C
1.7 V to 5.0 V Operation at TA = 0C to +85C
1.8 V to 5.0 V Operation at TA = -40C to +85C
Available in 8-Lead MLP and 10-Lead UMLP
Packages
ESD Protection Exceeds:
- 4 kV HBM
(per JESD22-A114 & Mil Std 883e 3015.7)
- 2 kV CDM (per ESD STM 5.3)
Description
The FT3001 is a timer for resetting a mobile device
where long reset times are needed. The long delay
helps avoid unintended resets caused by accidental key
presses. Four timer values can be selected by hard-
wiring the DSR0 and DSR1 pins.
The FT3001 has two inputs for single- or dual-button
resetting capability. The device has two outputs: a push-
pull output with 0.5 mA drive and an open-drain output
with 0.5 mA pull-down drive.
The FT3001 draws minimal supply current when
inactive and functions over a power supply range of
1.65 V to 5.0 V.
Figure 1. Block Diagram
Ordering Information
Part Number Operating
Temperature Range Package Packing Method
FT3001UMX -40C to +85C 10-Lead, Ultrathin MLP, 1.4 x 1.8 x 0.55mm
Package, 0.40 mm Pitch
5000 Units
Tape and Reel
FT3001MPX -40C to +85C 8-Lead, Molded Leadless Package (MLP),
Dual JEDEC, MO-229 2.0 x 2.0 mm
3000 Units
Tape and Reel
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FT3001 • Rev. 1.0.4 2
FT3001 — Reset Timer with Configurable Delay
Pin Configurations
10
4
8
3
9
5
2 6
7
1
RST2 DSR1 VCC
GND
/SR1
/RST1 NC DSR0
/SR0
TRIG
Figure 2. UMLP (Top Through View ) Figure 3. MLP (Top Through View )
Pin Definitions
UMLP
Pin# MLP
Pin# Name Description
1 2 GND Ground
2 3 /SR1 Secondary Reset Input, Active LOW
3 4 /RST1 Open-Drain Output, Active LOW
4 NC No Connect
5 5 DSR0 Delay Selection Input (Must be tied directly to GND or VCC; do not use pull-up or
pull-down resistors.)
6 6 TRIG Test Pin; tied to ground in normal use
7 7 /SR0 Primary Reset Input, Active LOW
8 8 VCC Power Supply
9 DSR1 Delay Selection Input (Must be tied directly to GND or VCC; do not use pull-up or
pull-down resistors.)
10 1 RST2 Push-Pull Output, Active HIGH
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FT3001 • Rev. 1.0.4 3
FT3001 — Reset Timer with Configurable Delay
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Condition Min. Max. Unit
VCC Supply Voltage -0.5 7.0 V
VIN DC Input Voltage /SR0, /SR1, TRIG, DSR0 -0.5 7.0 V
VOUT Output Voltage(1) /RST1, RST2 HIGH or LOW -0.5 VCC+0.5 V
/RST1, RST2, VCC=0 V -0.5 7.0
IIK DC Input Diode Current VIN < 0 V -50 mA
IOK DC Output Diode Current VOUT < 0 V -50 mA
VOUT > VCC +50
IOH/IOL DC Output Source/Sink Current -50 +50 mA
ICC DC VCC or Ground Current per Supply Pin 100 mA
TSTG Storage Temperature Range -65 +150 C
VCC Junction Temperature Under Bias +150 C
VIN Junction Lead Temperature, Soldering 10 Seconds +260 C
PD Power Dissipation 5 mW
ESD Electrostatic Discharge Capability Human Body Model, JESD22-A114 4 kV
Charged Device Model, JESD22-C101 2
Note:
1. IO absolute maximum rating must be observed.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FT3001 • Rev. 1.0.4 4
FT3001 — Reset Timer with Configurable Delay
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter Conditions Min. Max. Unit
VCC Supply Voltage
TA = 0C to +85C 1.65 5.00
V
TA = -25C to +85C 1.7 5.0
TA = -40C to +85C 1.8 5.0
tVCC_REC Vcc Recovery Time After Power
Down
Vcc = 0 V after power down, then rising to
0.5 V 5 ms
VIN Input Voltage(2) /SR0, /SR1 0 5.0 V
VOUT Output Voltage /RST1, RST2 High or Low 0 VCC V
/RST1, RST2, VCC = 0 V 0 5.0
IOH DC Output Source Current
RST2, 1.8 V ≤ VCC ≤ 3.0 V -100
µA
RST2, 3.0 V ≤ VCC ≤ 5.0 V -500
IOL DC Output Sink Current /RST1, RST2, VCC = 1.8V to 5.0 V +500
TA Free Air Operating Temperature -40 +85 C
JA Thermal Resistance MLP-8 245
°C/W
UMLP-10 200
Notes:
2. All unused inputs must be held at VCC or GND.
DC Electrical Characteristics
Unless otherwise specified, conditions of TA=-40 to 80C with VCC=1.8 - 5.0V OR TA=-25 to 85C with VCC=1.7 – 5V OR
TA=0 to 85C with VCC=1.65 – 5V produce the performance characteristics below.
Symbol Parameter Condition Min. Max. Unit
VIH Input High Voltage(3) /SR0, /SR1 0.8 x VCC V
VIL Input Low Voltage /SR0, /SR1 0.2 x VCC V
VIH Input High Voltage DSR0, DSR1 0.8 x VCC V
VIL Input Low Voltage DSR0, DSR1 0.2 x VCC V
VOH High Level Output Voltage
RST2, IOH=-100 µA 0.8 x VCC
V
RST2, IOH=-500 µA, VCC=3.0
to 5.0V 0.8 x VCC
VOL Low Level Output Voltage RST2, IOL=500 µA 0.3 V
/RST1, IOL=500 µA 0.3
IIN Input Leakage Current VIN =0.0 V or 5.0 V 1 µA
ICC Quiescent Supply Current (Timer
Inactive) /SR0 or /SR1=VCC 1 µA
ICC Dynamic Supply Current (Timer Active) /SR0 and /SR1=0 V 100 µA
Note:
3. /SR0 and /SR1 HIGH levels should be referenced to the same VCC rail supplying the FT3001.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FT3001 • Rev. 1.0.4 5
FT3001 — Reset Timer with Configurable Delay
AC Electrical Characteristics
Unless otherwise specified, conditions of TA=-40 to 80°C with VCC=1.8 - 5.0 V OR TA=-25 to 85°C with VCC=1.7 – 5 V OR
TA=0 to 85°C with VCC=1.65 – 5 V produce the performance characteristics below.
Symbol Parameter Condition Min. Typ. Max. Unit
tPHL1,
tPLH1
Timer Delay, /SRn to /RST1
(DSR0=0, DSR1=0)
CL=5 pF, RL=5 k,
Figure 9, Figure 4, Figure 5 2.40 3.00 3.60
s
Timer Delay, /SRn to /RST1
(DSR0=0, DSR1=1)
CL=5 pF, RL=5 k, Figure 9, Figure
4, Figure 5 3.00 3.75 4.50
Timer Delay, /SRn to RST2
(DSR0=1, DSR1=0)
CL=5 pF, RL=10 k, Figure 6, Figure
7 3.60 4.50 5.40
Timer Delay, /SRn to RST2
(DSR0=1, DSR1=1),
CL=5 pF, RL=10 k, Figure 6, Figure
7 4.80 6.00 7.20
tREC Reset Timeout Delay, /RST1 and
RST2 Figure 4, Figure 5, Figure 6, Figure 7 400 ms
Capacitance Specifications
TA = +25C.
Symbol Parameter Condition Typical Unit
CIN Input Capacitance VCC=GND 4.0 pF
COUT Output capacitance VCC=5.0 V 5.0 pF
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FT3001 • Rev. 1.0.4 6
FT3001 — Reset Timer with Configurable Delay
AC Test Circuits and Waveforms
Figure 4. AC Test Circuit, RST1 Output Figure 5. RST1 Output Waveform
Figure 6. AC Test Circuit, RST2 Output Figure 7. RST2 Output Waveform
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FT3001 • Rev. 1.0.4 7
FT3001 — Reset Timer with Configurable Delay
Functional Description
The reset timer uses an internal oscillator and a two-
stage 21-bit counter to determine when the output pins
switch. The time, n, is set by the hard-wired logic level
of the DSR0 and DSR1 pins. See Table 1 & 2.
Table 1. F T3001UMX Truth Table
DSR0 DSR1 Reset Time (20%)
in Seconds
0 0 3.00
0 1 3.75
1 0 4.50
1 1 6.00
Table 2. F T3001MPX Truth Table
DSR0 Reset Time (20%)
in Seconds
0 3.0
1 4.5
The two CMOS input pins, /SR0 and /SR1, control the
reset function. A low input signal on both /SR0 and /SR1
starts the oscillator. Both /SR0 and /SR1 pins must be
held LOW for time n before the /RST1 and RST2
outputs are activated. The TRIG pin should be tied LOW
during normal operation. The TRIG pin is used for
SCAN testing.
Application Information
IMPORTANT: The DSR0 and DSR1 pins must be tied
directly to VCC or GND to provide a HIGH or LOW
voltage level. The voltage level on the DSR pin
determines the length of the configurable delay. The
voltage level on the DSR pins must not change during
normal operation. Do not use pull-up or pull-down
resistors on DSR pins.
Short Duration (Button Press Time < n)
In this case, both input /SR0 and /SR1 are LOW for a
duration (tW) that is shorter than time n. When an input
goes LOW, the internal timer starts counting. If the input
goes HIGH before time n, the timer stops counting and
resets and no changes occur on the outputs.
Long Duration (tW > n)
In this case, both input /SR0 and /SR1 are LOW for a
duration (tW) that is longer than time n. When an input
goes LOW, the internal timer starts counting.
After time n, the outputs switch and the timer stops
counting. After time tREC, the outputs return to their
original states.
Table 3. Short Duration
/SR0 /SR1 /RST1 RST2 Description
L H L
The timer starts counting when both inputs go LOW. The timer stops
counting and resets when either input goes high. No changes occur on the
outputs. Both /SR0 and /SR1 need to be LOW to activate (start) the timer.
Figure 8. Short Duration Figure 9. Long Duration
Table 4. Long Duration
/SR0 /SR1 /RST1 RST2 Description
L The timer starts counting when both inputs go LOW. After time n, the
outputs switch. After time tREC, the outputs return to their original states.
Both /SR0 and /SR1 need to be LOW to activate (start) the timer.
L
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FT3001 • Rev. 1.0.4 8
FT3001 — Reset Timer with Configurable Delay
Physical Dimensions
AB
C
SEATING
PLANE
DETAIL A
PIN#1 IDENT
RECOMMENDED
LAND PATTERN
NOTES:
A. PACKAGE DOES NOT FULLY CONFORM TO
JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY.
E. DRAWING FILENAME: MKT-UMLP10Arev3.
TOP VIEW
BOTTOM VIEW
0.15 C
0.08 C
0.15 C
2X
2X
SIDE VIEW
0.10 C
0.05
3
6
1
0.10 C A B
0.05 C
0.55 MAX.
10
1.40
1.80
0.40
0.15
0.25(10X)
0.35
0.45(9X)
1.70
2.10
0.40
0.663 0.563
(9X)
0.225
(10X)
1
0.152
0.10
0.10
0.55
0.45
0.10
DETAIL A
SCALE : 2X
1.85
1.45
0.55
0.40
0.225
(10X)
9X
0.45
PIN#1 IDENT
OPTIONAL MINIMIAL
TOE LAND PATTERN
SCALE : 2X
LEAD
OPTION 1
SCALE : 2X
LEAD
OPTION 2
PACKAGE
EDGE
Figure 10. 10-Lead, Ultrathin MLP, 1.4 x 1.8 x 0.55 mm Package, 0.40 mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’ s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FT3001 • Rev. 1.0.4 9
FT3001 — Reset Timer with Configurable Delay
Physical Dimensions (Continued)
BOTTOM VIEW
SIDE VIEW
TOP VIEW
NOTES:
A. PACKAGE CONFORMS TO JEDEC MO-229,
VARIATION W2020D EXCEPT WHERE NOTED.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
D. LAND PATTERN RECOMMENDATION BASED
ON PCB MATRIX CALCULATOR V2009.
E. IF CENTER PAD IS NOT SOLDERED TO, NO
EXPOSED METAL IS ALLOWED IN THE TOP
LAYER OF THE BOARD IN THE AREA SHOWN.
F. DRAWING FILENAME: MKT-MLP08Rrev2.
0.05
0.00
0.80 MAX
0.10 C
0.08 C
(0.20)
C
SEATING
PLANE
PIN1
IDENT
2.00
2.00
A
B
2X
2X
0.10 C
0.10 C
85
14
0.10 CAB
0.05 C
PIN 1
IDENT
0.50
0.65
0.45
0.25
0.15 8X
8X
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
OPTION #1: NO CENTER PAD
(0.25)
(0.90)
1.80
0.50 8X
8X
OPTION #2: WITH CENTER PAD
E
TOP LAYER
CU KEEP
OUT AREA
0.90
(1.35)
A
(0.25)
(0.90)
1.80
0.50 8X
8X
0.90
(0.35)
1.35 MAX
0.40 MAX
Figure 11. 8-Lead, Molded Lead less Package (ML P), Du al JEDEC, MO-229 2.0 x 2.0 mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the m ost recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com
FT3001 • Rev. 1.0.4 10
FT3001 — Reset Timer with Configurable Delay
www.onsemi.com
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ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
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literature is subject to all applicable copyright laws and is not for resale in any manner.
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