SY87721L
1
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
3.3V 28Mbps-2.7Gbps AnyRate®
CLOCK AND DATA RECOVERY WITH
INTEGRATED CLOCK MULTIPLIER UNIT
DESCRIPTION
FEATURES
SY87721L
■Recovers any data and clock from 28Mbps to
2.7Gbps
• OC-1, OC-3, OC-12, OC-48, ATM
• Gigabit Ethernet, Fast Ethernet
• Fibre Channel, 2x Fibre Channel
• P1394, Infiniband
• SMPTE-259, SMPTE-292
• Proprietary optical transport
■Integrated clock multiplier unit with low jitter
generation
■Complies with Bellcore, ITU/CCITT and ANSI
specifications
■Selectable mux for pass through; avoids jitter
accumulation when switching through backplanes
■Available in 64-Pin EPAD-TQFP package
The SY87721L is a complete Clock Recovery and Data
retiming integrated circuit for data rates from 28Mbps up to
2.7Gbps NRZ including SONET FEC data rates. Included
in the device, is a fully integrated Clock Multiplier Unit (CMU)
that is capable of generating frequencies that cover the
same data rate range as the CDR. The device is ideally
suited for SONET/SDH/ATM, Fibre Channel, and Gigabit
Ethernet applications, as well as other high-speed data
transmission applications.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming data
stream. The VCO center frequency is controlled by the
reference clock frequency and the selected divide ratio.
On-chip clock generation is performed through the use of a
frequency multiplier PLL with a byte rate or code group rate
source as reference.
Rev.: D Amendment: /0
Issue Date: January 2008
SIMPLIFIED BLOCK DIAGRAM
SY87721L
AnyRate
Data In
Reference
Clock
2
2
2
2
AnyRate
Data Out
Transmit
Clock
2
CDR
Recovered
Clock
CMU
APPLICATIONS
■SONET/SDH/ATM-based transmission systems,
modules, and test equipment
■Transponders and section repeaters
■Multiplexers: access, add drop (ADM), and terminal (TM)
■Terabit routers and broadband cross-connects
■Fiber optic test equipment
AnyRate is a registered trademark of Micrel, Inc.
SY87721L
2
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
BRD+
VCOSEL2
FREQSEL1
FREQSEL2
FREQSEL3
CD
GND
VCC
GND
BRDMX
VCC
VCCO
BRD—
LFIN
RDIN—
RDIN+
VCOSEL1
PLLRN+
PLLRN—
NC
PLLRW+
PLLRW—
NC
VCCA
GNDA
PLLSW—
PLLSW+
NC
PLLSN—
PLLSN+
NC
NC
GND
ENPECL
RDOUTE+
RDOUTE
—
RDOUTC+
RDOUTC
—
VCCO
RCLKE+
RCLKE—
RCLKC+
RCLKC—
VCCO
TCLKE+
TCLKE—
TCLKC+
TCLKC—
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64-Pin
EPAD-TQFP
DIVSEL3
GND
REFCLK+
REFCLK—
VCC
GND
GND
GND
GND
VCC
GND
CLKSEL
ALRSEL
DIVSEL2
DIVSEL1
NC
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY87721LHI H64-1 Industrial SY87721LHI Sn-Pb
SY87721LHITR(2) H64-1 Industrial SY87721LHI Sn-Pb
SY87721LHY(3) H64-1 Industrial SY87721LHY with Pb-Free
Pb-Free bar-line indicator Matte-Sn
SY87721LHYTR(2, 3) H64-1 Industrial SY87721LHY with Pb-Free
Pb-Free bar-line indicator Matte-Sn
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and Reel.
3. Recommended for new designs.
SY87721L
3
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
SYSTEM BLOCK DIAGRAM
DEMUX
TCLK 4, 5, 8, 10 bits
4, 5, 8, 10 bits
LOCK
RCLK
RDATA SY87724L
POST AMPTIAPIN DIODE
FIBER
LASER
DIODE
FIBER
SY889x3
CMU
CDR
SY87721L
AnyRate®
REF_CLK
SEL
27MHz
SY87729L
SY889x2
AnyClock™
LASER
DIODE
DRIVER
Fractional
Synthesizer
MUX
OC-48 EYE DIAGRAM
Time (100ps/div)
SY87721L
4
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL BLOCK DIAGRAM
RCLKE+
RCLKE—
RCLKC+
RCLKC—
LFIN
Link Fault
Detector
TCLKE+
TCLKE—
TCLKC+
TCLKC—
VCO
N/W1/W2/W3
Phase
Detector/
Data Recovery
Phase/
Frequency
Detector
VCO
N/W1/W2/W3
Phase/
Frequency
Detector
Charge
Pump
N/W
Divide by 1, 2,
4, 8, 10, 16,
20, 32
FREQSEL1
FREQSEL2
FREQSEL3
ENPECL
CD
RDIN+
RDIN—
Charge
Pump
N/W
Mux
DIVSEL3
DIVSEL2
DIVSEL1
VCOSEL2
VCOSEL1
PLLSN+
PLLSN—
PLLSW+
PLLSW—
Mux
CLKSEL
RDOUTC+
RDOUTC
—
RDOUTE+
RDOUTE
—
REFCLK+
REFCLK—
BRD Mux
BRD+
BRD—
PLLRW
—
PLLRW+
PLLRN
—
PLLRN+
ALRSEL
BRDMX
SY87721L
5
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
DIVSEL1, ..., DIVSEL3 [Divider Select] – TTL Inputs
These inputs select the ratio between the output clock
frequency (RCLK/TCLK) and the REFCLK input frequency
as shown in Table 4. Please note that the divide by 32
selection, “011”, is only available for use when FREQSEL
are set to “000.”
REFCLK
DIVSEL1 DIVSEL2 DIVSEL3 Multiplier
0001
0012
0104
01132
1008
10110
11016
11120
Table 2(1). Reference Clock Multiplier Truth Table
Note:
1. Some combinations of FREQSEL and DIVSEL result in undefined behavior.
Refer to Table 3 for more details.
CLKSEL [Clock Select] – TTL Input
This input is used to select either the recovered clock of
the receiver PLL (CLKSEL = HIGH) or the clock of the
frequency synthesizer (CLKSEL = LOW) to the TCLK
outputs. Do not use for skew matching.
ENPECL [Enable ECL] – TTL Input
This input, when HIGH (ENPECL = 1), enables the
differential PECL outputs TCLKE±, RDOUTE±, and RCLKE±.
It also disables the CML outputs, by setting TCLKC+,
RDOUTC+, and RCLKC+ logic HIGH and setting TCLKC–,
RDOUTC–, and RCLKC– logic LOW.
When set LOW (ENPECL = 0), this signal enables the
differential CML outputs TCLKC±, RDOUTC±, and RCLKC±.
It also disables the PECL outputs by setting TCLKE+,
RDOUTE+, and RCLKE+ logic HIGH and setting TCLKE–,
RDOUTE– and RCLKE– logic LOW.
ALRSEL [Auto Lock Range Select] – TTL Input
This pin defines the frequency difference, and the
frequency difference hysteresis at which ‘in-lock’ and ‘out of
lock’ conditions are declared. Please refer to the “AC
Characteristics” for more details.
PIN NAMES
INPUTS
BRDMX [BRD Mux] – PECL Input
This signal indicates what data appears at the BRD±
output. When logic HIGH, BRD± is a direct copy of what
appears at RDOUTC±. When logic low, BRD± is a copy of
what appears at RDIN±. Unlike RDOUTC±, BRD± conveys
valid data even when ENPECL is logic LOW. Please refer
to Table 1.
BRDMX (Input) BRD± (Output)
0 RDIN±
1 RDOUTC±
Table 1. BRDMX Truth Table
RDIN± [Serial Data Input] – Differential PECL Input
This differential input accepts the receive serial data
stream. An internal receive PLL recovers the embedded
clock (RCLK) and data (RDOUT) information. The incoming
data rate can be within one of ten frequency ranges, or can
be one of five specific frequencies, depending on the state
of the FREQSEL and VCOSEL pins. The RDIN– pin has an
internal 75KΩ resistor tied to VCC.
REFCLK± [Reference Clock] – Differential PECL Input
This input is used as the reference for the internal
frequency synthesizer and the “training” frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN input. The input frequency to
REFCLK is limited to 340MHz or less, depending on the
setting on the DIVSEL signals. The REFCLK– pin has an
internal 75KΩ resistor tied to VCC.
CD [Carrier Detect] – PECL Input
This input controls the recovery function of the Receive
PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH, the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW, the
data on the RDOUT output will be internally forced to a
constant LOW, the Link Fault Indicator output LFIN forced
LOW, and the clock recovery PLL forced to lock onto the
synthesized clock frequency generated from REFCLK.
VCOSEL1, VCOSEL2 [VCO Select] – TTL Inputs
These inputs select the output clock frequency range via
either one of three PLLs, or a SONET/SDH specific PLL.
Only the selected PLL is enabled. All other PLLs are
disabled. Refer to Table 3 for more details.
FREQSEL1, ..., FREQSEL3 [Frequency Select] – TTL Inputs
These inputs select the post divide ratio of the VCO.
Refer to Table 3 for more details.
SY87721L
6
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
OUTPUTS
BRD± [Buffered Recovered Data] – Differential CML Output
The signal is either a buffered RDIN± or RDOUTC±,
depending on the state of the BRDMX input. This allows a
user to selectively bypass the CDR or not, as warranted by
architecture. This CML output has a voltage swing of 400mV
loaded.
LFIN [Link Fault Indicate] – O.C. TTL Output
This output indicates the status of the input data stream
RDIN. Active HIGH indicates that the internal clock recovery
PLL has locked onto the incoming data stream. LFIN will go
HIGH if CD is HIGH and RDIN is within the frequency range
of the Receive PLL (as per ALRSEL). LFIN is an
asynchronous output.
RDOUTE± [Receive Data Out] – Differential PECL Output
These ECL 100K outputs (+3.3V referenced) represent
the recovered data from the input data stream (RDIN). It is
specified on the rising edge of RCLK.
RDOUTC± [Receive Data Out] – Differential CML Output
This is the CML version of RDOUTE±.
RCLKE± [Receive Clock Out] – Differential PECL Output
These ECL 100K outputs (+3.3V referenced) represent
the recovered clock used to sample the recovered data
(RDOUT).
RCLKC± [Receive Clock Out] – Differential CML Output
This is the CML version of RCLKE±.
TCLKE± [Transmit Clock Out] – Differential PECL Output
These ECL 100K outputs (+3.3V referenced) represent
either the recovered clock (CLKSEL = HIGH) used to sample
the recovered data (RDOUT) or the transmit clock of the
frequency synthesizer (CLKSEL = LOW).
TCLKC± [Transmit Clock Out] – Differential CML Output
This is the CML version of TCLKE±.
PLLSN+, PLLSN– [Clock Synthesis Loop Filter]
External loop filter pins for the clock synthesis narrow
band PLL.
PLLSW+, PLLSW– [Clock Synthesis Loop Filter]
External loop filter pins for the clock synthesis wide band
PLL.
PLLRN+, PLLRN– [Clock Recovery Loop Filter]
External loop filter pins for the clock recovery narrow
band PLL.
PLLRW+, PLLRW– [Clock Recovery Loop Filter]
External loop filter pins for the clock recovery wide band
PLL.
OTHERS
VCC Supply Voltage
VCCO Output Supply Voltage
VCCA Analog Supply Voltage
GND Ground
GNDA Analog Ground
NC These pins are for factory test, and are to be
left unconnected during normal use.
SY87721L
7
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
General
The SY87721L is a complete clock and data recovery
circuit, capable of handling NRZ data rates from 28MHz
through to 2.7GHz. A reference PLL is used as a frequency
synthesizer, both to multiply a reference clock to the desired
transmit rate, and to train the recovery PLL in preparation
for actual data recovery.
Link Fault Algorithm
The SY87721L includes a Link Fault Detection circuit.
This circuit provides the following functions: Under Loss-of-
Lock (LOL) conditions, which can occur when the Carrier
Detect (CD) input is active HIGH, the output of the RCLK
approximates the output of the TCLK, within a lock range
as specified by the state of ALRSEL.
Under Loss-of-Signal (LOS) conditions, enabled by driving
the Carrier Detect (CD) input to inactive logic LOW, the
output of the RCLK becomes an exact copy of the TCLK
output. This is the result of forcing the recovery PLL to lock
to the synthesized reference.
Under LOL and LOS conditions, the LFIN output is an
inactive logic LOW.
SY87721L follows a prescribed procedure, to acquire and
recover the clock of the incoming data stream. This
procedure is triggered either by a falling edge on CD, or by
the recovered clock PLL indicating a frequency error,
compared to the synthesized reference, of greater than
500ppm or 4,500ppm, as selected by ALRSEL. With the
CD input set active HIGH, the algorithm begins by phase
and frequency training the recovery PLL to the synthesized
reference. Once the recovery PLL is within the specified
lock range, determined by the state of ALRSEL, the
SY87721L will switch from a phase-frequency comparison
with the synthesized reference, to a phase-only comparison
with the incoming data stream. When the recovery PLL is
locked to this incoming data stream (that is, after phase
step recovery), then data recovery may proceed and LFIN
asserts. Once locked and accepting data, the LFIN signal
may de-assert should the data input frequency deviate too
far from the synthesized reference frequency.
VCO Selection
SY87721L sports four complete VCO circuits. Depending
on the application and the frequency range, any one of
these four perform data recovery.
As indicated by the VCO selection table, there are three
general purpose VCOs each covering one of three frequency
ranges. However, to extend the range of the device, the
output of the VCO may be divided down.
In the case of the two highest frequency general purpose
VCOs (VCOSEL = 1, 0 or 0,1 ), this divisor is always set to
1. For the lowest frequency VCO, the FREQSEL pins select
which divisor, and hence, which range of frequencies the
VCO will work over.
In addition, for SONET/SDH applications, there is a
narrow band, extremely low jitter PLL. It also uses the
FREQSEL divisor to choose the correct SONET/SDH
frequency.
The valid modes of operation are shown in Table 3.
Notes:
1. REFCLK multiplier of 1 or 2 is not allowed in this range.
2. REFCLK multiplier of 1 is not allowed in this range.
3. Combinations of VCOSEL and FREQSEL other then those in this table result in undefined behavior, and should not be used.
VCOSEL1 VCOSEL2 FREQSEL1 FREQSEL2 FREQSEL3 Range (MHz)
000002488 (OC48)–2700
000011244-1350
00010622(OC12)–675
00100311–337
00110155(OC3)–168
010001800–2700
100001250–1800
11000650–1300(1)
11001325–650(2)
11010163–325
11011109–216
1110082–162
1110155–108
11110 41–81
11111 28–54
Table 3 (3). Frequency Range Selection Truth Table
SY87721L
8
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
LOOP FILTER COMPONENTS CML OUTPUT DIAGRAM(1)
50Ω50Ω
100Ω
SY87721L
VCC
16mA
Figure 3. 50Ω Load CML Output
PLLSN+
or
PLLSW+
PLLSN–
or
PLLSW
–
RC
Figure 1. Narrow Band and Wide Band
Synthesizer Loop Filter
PLLRN+
or
PLLRW+
PLLRN–
or
PLLRW–
RC
Figure 2. Narrow Band and Wide Band
CDR Loop Filter
NOTE:
1. VOSW is defined as |VOH–VOL| on any one pin (either the true or the
complement pin). As opposed to the single-ended swing, differential
swing, VOSW (true pin) + VOSW (complement pin) is double the VOSW
value.
OC-48 JITTER TRANSFER AND TOLERANCE
OC-48 Jitter Tolerance
.1
1
10
100
1000 10000 100000 1.E+6 1.E+7
Modulation Frequency (Hz)
Amplitude UI
OC-48 Jitter Transfer
-20
-10
0
10
1000 10000 100000 1.E+6 1.E+7
Modulation Frequency (Hz)
Jitter Ratio (dB)
PLL R C
PLLSN+, PLLSN–1.2kΩ1µF
PLLRN+, PLLRN–390Ω1µF
PLLSW+, PLLSW–845Ω1µF
PLLRW+, PLLRW–455Ω1µF
Table 4. Synthesizer and Clock Recovery Loop Filter Values
SY87721L
9
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
Symbol Parameter Min. Typ. Max. Unit Condition
VIH Input HIGH Voltage VCC – 1.165 —VCC – 0.880 V
VIL Input LOW Voltage VCC – 1.810 —VCC – 1.475 V
IIL Input LOW Current –0.5 ——µAV
IN = VIL(Min)
VOH Output HIGH Voltage VCC – 1.075 —VCC – 0.830 V 50Ω to VCC –2V
VOL Output LOW Voltage VCC – 1.860 —VCC – 1.570 V 50Ω to VCC –2V
VCC =VCCO = VCCA = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C
100K PECL DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Min. Typ. Max. Unit Condition
VCC Power Supply Voltage 3.15 3.3 3.45 V
ICC Power Supply Current —360 450 mA
VCC =VCCO = VCCA = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C
DC ELECTRICAL CHARACTERISTICS
CML DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Min. Typ. Max. Unit Condition
VOH Output HIGH Voltage VCC – 0.050 —VCC V No Load
VOL Output LOW Voltage ——VCC – 0.65 V No Load
VOSW Output Voltage Swing —0.4 —V50Ω to VCC
VCC =VCCO = VCCA = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C
Symbol Parameter Rating Unit
VCC Power Supply Voltage –0.5 to +5.0 V
VIN Input Voltage –0.5 to VCC V
IOUT ECL Output Current –Continuous 50 mA
–Surge 100
ICMLOUT CML Output Current 30 mA
Lead Temperature (soldering, 20 sec.) +260 °C
Tstore Storage Temperature Range –65 to +150 °C
TAOperating Temperature Range –40 to +85 °C
θJA Package Thermal Resistance(2) –0lfpm 22.3 °C/W
(Junction-to-Ambient) –200lfpm 17.2 °C/W
–500lfpm 15.1 °C/W
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at
conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
2. Jedec standard test boards with die attach pad soldered to pcb. Tested at 1W.
ABSOLUTE MAXIMUM RATINGS(1)
Note:
1. All PECL inputs have an internal 75kΩ resistor to VEE. In addition, the complement inputs of all differential PECL inputs have a 75kΩ resistor to VCC. Thus,
unconnected PECL inputs behave like static logic LOW.
Note:
1. VOSW is defined as |VOH–VOL| on any one pin (either the true or the complement pin). As opposed to the single-ended swing, differential swing, VOSW
(true pin) + VOSW (complement pin) is double the VOSW value.
SY87721L
10
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
Symbol Parameter Min. Typ. Max. Unit Condition
VIH Input HIGH Voltage 2.0 ——V
VIL Input LOW Voltage ——0.8 V
IIH Input HIGH Current ——+20 µAV
IN = 2.7V, VCC = 3.45V
——+100 µAV
IN = VCC, VCC = 3.45V
IIL Input LOW Current –300 ——µAV
IN = 0.5V, VCC = Max.
IOLK Output Leakage Current ——500 µAV
OUT = VCC
VOL Output LOW Voltage ——0.5 V IOL = 4mA
VCC =VCCO = VCCA = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C
TTL DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Min. Typ. Max. Unit Condition
TCLK Output Jitter ——0.01 UI rms REFCLK Multiplier ≤16
VCOSEL = 0, 0
Frequency Difference, 500 1500 —ppm ALRSEL High
LFIN shows Out of Lock
Frequency Difference, 4500 6500 —ppm ALRSEL Low
LFIN shows Out of Lock
RDIN Maximum Data Rate 2.7 ——Gbps
REFCLK Maximum Frequency ——340 MHz
tCPWH REFCLK Pulse Width High 1.2 ——ns
tCPWL REFCLK Pulse Width Low 1.2 ——ns
tIRF REFCLK Input Rise/Fall Time ——1.0 ns
(20% to 80%)
tODC Output Duty Cycle (RCLK/TCLK) 45 —55 % of UI
tRE ECL Output Rise/Fall Time ——600 ps 50Ω to VCC–2V
tFE (20% to 80%)
tRC CML Output Rise/Fall Time ——120 ps 50Ω Load
tFC (20% to 80%)
tDV Data Valid 100 ——ps
tDH Data Hold 100 ——ps
VCC =VCCO = VCCA = 3.3V ±5%; GND = GNDA = 0V; TA = –40°C to +85°C
AC ELECTRICAL CHARACTERISTICS
SY87721L
11
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
TIMING WAVEFORMS
CML VOSW DIAGRAM
t
CPWL
REFCLK–
t
CPWH
RDOUT
t
DV
t
ODC
t
ODC
t
DH
RCLK
V
OL
V
OH
V
OSW
(Single-Ended Swing)
CML Pin
(True or Complement)
SY87721L
12
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
EVALUATION BOARD SCHEMATIC
SY87721L
2
3
4
5
6
7
8
9
10
11
12
13
17
48
47
46
45
44
43
42
41
40
39
38
37
36
61
60
59
58
57
56
55
54
53
52
51
50
14
15
16
35
34
33
62
63
64
RDIN+
GND
VCC
REFCLK—
REFCLK+
GND
VCC
GND
GND
GND
DIVSEL3
ALRSEL
CLKSEL
GND
DIVSEL1
DIVSEL2
NC
RDIN—
LFIN
BRD+
BRD—
VCCO
VCC
BRDMX
GND
VCC
GND
CD
FREQSEL3
FREQSEL2
FREQSEL1
VCOSEL2
TCLKC—
TCLKC+
TCLKE—
TCLKE+
VCCO
RCLKC—
RCLKC+
RCLKE—
RCLKE+
VCCO
RDOUTC—
RDOUTC+
RDOUTE—
RDOUTE+
ENPECL
GND
VCOSEL1
PLLRN+
PLLRN—
NC
PLLRW+
PLLRW—
NC
VCCA
GNDA
PLLSW—
PLLSW+
NC
PLLSN—
PLLSN+
NC
NC
1
49
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
67
8
9
10
11
12
VEE VCCO: PIN 37
VCCO: PIN 42
RDOUTE+
RDOUTE—
RDOUTC+
RDOUTC—
RCLKE+
RCLKE—
RCLKC+
RCLKC—
TCLKE+
TCLKE—
TCLKC+
TCLKC—
VEE: PIN 48
VCC
VEE
VEE:PIN 32
VEE:PIN 26
VEE:PIN 25
REFCLK+: FORCE
REFCLK+: SENSE
VCC
L4
C11 C12
VEE
VCCA L3
C10C9
VEE:PIN 23
REFCLK—: FORCE
REFCLK—: SENSE
SW DIP-6
S3
1
3
5
7
9
11 12
10
8
6
4
2
HEADER
6X2 JP1
VCC
1
2
3
4
56
7
8
9
10
VEE SW DIP-5
S1
R5, 5kΩ
VCC
C5
R7
C6
R8
C7
R9
C8
R10
RDIN+: FORCE
RDIN+: SENSE
RDIN—: FORCE
RDIN—: SENSE
BRD+: PIN 52
BRD—: PIN 53
VEE: PIN 57
VCC: PIN 58
VCC L2
C3 C4
1
3
56
4
2
HEADER
3X2 JP4
LED
VCC
D3 R17,
1.7kΩ
VCCO
L1
C2 C1
1
2
3
4
56
7
8
9
10
VCC SW DIP-8
S2
VCC
R47,
130Ω
VEE
VCC
R48,
20Ω
VEE L7
C18 C17
VEE: PIN 59
R4, 5kΩ
R3, 5kΩ
R2, 5kΩ
R1, 5kΩ
R23, 5kΩ
R22, 5kΩ
R21, 5kΩ
R20, 5kΩ
R19, 5kΩ
R18, 5kΩ
R11, 1.2kΩ
R12, 1.2kΩ
R13, 1.2kΩ
R14, 1.2kΩ
R15, 1.2kΩ
VCC:PIN 24
R16,
5kΩJP2
D1
D2
VEE
VCC
5kΩ
VEE: PIN 56
Notes:
1. C11, C17, C10, C4, C2 = 0.1µF
2. C18, C12, C9, C3, C1 = 1µF
3. C2, C4, C10, C11, and C17 need to be located right at device pin. If vias
to power GND used—use overlapping multiple vias to lower inductance.
SY87721L
13
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
EVALUATION BOARD I/O TERMINATION SCHEMES
TCLKC–C19
12
J14
RCLKC–C23
12
J10 RDOUTC–C27
12
J6
V
CC
R37,
185.2Ω
C31
12
J1
R36,
68.5Ω
RDIN+:FORCE
V
EE
TCLKC+ C20
12
J13
RCLKC+ C24
12
J9 RDOUTC+ C28
12
J5
RDIN+: SENSE C32
12
J2
TCLKE–
R30,
330Ω
C21
12
J12
V
EE
RCLKE–
R32,
330Ω
C25
12
J8
VEE
RDOUTE+
R34,
330Ω
C29
12
J4
VEE
V
CC
R39,
185.2Ω
C33
12
J17
R38,
68.5Ω
RDIN–:FORCE
V
EE
TCLKE+
R31,
330Ω
C22
12
J11
V
EE
RCLKE+
R33,
330Ω
C26
12
J7
VEE
RDOUTE+
R35,
330Ω
C30
12
J3
VEE
RDIN–: SENSE C34
12
J18
TCLK RCLK RDOUT RDIN
OUTPUTS OUTPUTS OUTPUTS INPUTS
Notes:
1. For AC coupling, include capacitors C19 thru C31, C33, C35 and C37.
2. If DC coupling, remove resistors R36 thru R43.
SY87721L
14
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
V
CC
R41,
185.2Ω
C35
12
J15
R40,
68.5Ω
REFCLK+:FORCE
V
EE
BRD+: PIN 52 C39
12
J21
REFCLK+: SENSE C36
12
J16
BRD—: PIN 53 C40
12
J22
V
CC
R43,
185.2Ω
C37
12
J19
R42,
68.5Ω
REFCLK–:FORCE
V
EE
REFCLK–: SENSE C38
12
J20
VEE: PIN 59 C45
0.01 F
VCC: PIN 58 C46
0.01 F
VEE: PIN 57 C47
0.01 F
VEE: PIN 48 C49
0.01 F
VCCO: PIN 42 C50
0.01 F
VCCO: PIN 37 C51
0.01 F
VEE: PIN 32 C52
0.01 F
VEE: PIN 26 C53
0.01 F
VEE: PIN 25 C54
0.01 F
VCC: PIN 24 C55
0.01 F
VEE: PIN 23 C56
0.01 F
REFCLK BRD
INPUTS OUTPUTS
SY87721L
15
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
64 LEAD EPAD-TQFP (DIE UP) (H64-1)
Rev. 02
+0.05
–0.05
+0.002
–0.002
+0.006
–0.006
+0.012
–0.012
+0.002
–0.002
+0.15
–0.15
+0.03
–0.03
+0.05
–0.05
+0.012
–0.012
+0.05
–0.05
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heavy Copper Plane
Heavy Copper Plane
V
EE
V
EE
Heat Dissipation
PCB Thermal Consideration for 64-Pin EPAD-TQFP Package
SY87721L
16
Micrel, Inc.
M9999-012508
hbwhelp@micrel.com or (408) 955-1690
APPENDIX A
Layout and General Suggestions
1. Establish controlled impedance stripline, microstrip, or co-planar construction techniques.
2. Signal paths should have, approximately, the same width as the device pads.
3. All differential paths are critical timing paths, where skew should be matched to within ±10ps.
4. Signal trace impedance should not vary more than ±5%. If in doubt, perform TDR analysis of all high-speed signal
traces.
5. Maintain compact filter networks as close to filter pins as possible. Provide ground plane relief under filter path to
reduce stray capacitance. Be careful of crosstalk coupling into the filter network.
6. Maintain low jitter on the REFCLK input. Isolate the XTAL oscillator from power supply noise by adequately
decoupling. Keep XTAL oscillator close to device, and minimize capacitive coupling from adjacent signals.
7. Higher speed operation may require use of fundamental-tone (third-overtone typically have more jitter) crystal based
oscillator for optimum performance. Evaluate and compare candidates by measuring TXCLK jitter.
8. Evaluate ASIC AND FPGA REFIN source clocks with suitable jitter analysis equipment, such as TDS11801 tektronix
DSO oscilloscope, or Wavecrest DTS2077 Time Interval Analyzer.
9. All unused outputs require termination. NC, however, should be unconnected.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2005 Micrel, Incorporated.
