L99DZ100G, L99DZ100GP Automotive door module with LIN and HS-CAN (L99DZ100G) or HS-CAN supporting selective wake up (L99DZ100GP) Datasheet - production data All the embedded outputs come with protection and supervision features: - Current Monitor (high-side only) - Open-load - Overcurrent - Thermal warning - Thermal shutdown Fully protected driver for external MOSFETs in H-bridge configuration or dual Half bridge configuration Features AEC Q100 compliant qualified 1 half bridge for 7.5 A load (RON = 100 m) 1 half bridge for 7.5 A load (RON = 150 m) 2 half bridges for 0.5 A load (RON = 2000 m) 2 half bridges for 3 A load (RON = 300 m) 1 configurable high-side driver for up to 1.5 A (RON = 500 m) or 0.35 A (RON = 1600 m) load 1 configurable high-side driver for 0.8 A (RON = 800 m) or 0.35 A (RON = 1600 m) load 3 configurable high-side drivers for 0.15 A/0.35 A (RON =2 ) 1 configurable high-side driver for 0.25 A/0.5 A (RON = 2 ) to supply EC Glass MOSFET Fully protected driver for external high-side MOSFET Control block for electro-chromic element Two 5 V voltage regulators for microcontroller and peripheral supply Programmable reset generator for power-on and undervoltage Configurable window watchdog LIN 2.2a compliant (SAEJ2602 compatible) transceiver Advanced high speed CAN transceiver (ISO 11898-2:2003 /-5:2007 and SAE J2284 compliant) with local failure and bus failure diagnosis and selective wake-up functionality according to ISO 11898-6:2013 4 configurable high-side drivers for 0.15 A/0.25 A (RON = 5 ) Separated (Isolated) fail-safe block with 2 LS (RON = 1 ) to pull down the gates of the external HS MOSFETs Internal 10bit PWM timer for each stand-alone high-side driver Thermal clusters Buffered supply for voltage regulators and 2 high-side drivers (OUT15 & OUT_HS / both P-channel) to supply e.g. external contacts Programmable soft-start function to drive loads with higher inrush currents as current limitation value (for OUT1-6, OUT7, OUT8 and OUT_HS) with thermal expiration feature March 2019 This is information on a product in full production. A/D conversion of supply voltages and internal temperature sensors Embedded and programmable VS duty cycle adjustment for LED driver outputs Applications Door zone applications. DS11546 Rev 5 1/197 www.st.com L99DZ100G, L99DZ100GP Table 1. Device summary Order codes Package Variant LQFP-64 epad High Speed CAN Transceiver with partial networking (ISO 11898-6:2013) LQFP-64 epad High Speed CAN Transceiver (ISO 11898-2:2003 and 11898-5:2007) Product label 2/197 DS11546 Rev 5 Tray Tape and reel L99DZ100GP L99DZ100GPTR L99DZ100G L99DZ100GTR L99DZ100G, L99DZ100GP Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 Block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.1 3.4 LQFP64 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.1 Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.3 Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.4 Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4.5 Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.6 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.4.7 Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4.8 Current monitor output (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4.9 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.4.10 Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR . . . . . . . . . . . . . . . . . . 38 3.4.11 Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.12 Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.4.13 Heater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.4.14 H-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.4.15 Gate drivers for the external Power-MOS switching times . . . . . . . . . . 45 3.4.16 Drain source monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . 48 3.4.17 Drain source monitoring external heater MOSFET . . . . . . . . . . . . . . . . 49 3.4.18 Open-load monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . . . 49 3.4.19 Open-load monitoring external heater MOSFET . . . . . . . . . . . . . . . . . . 50 3.4.20 Electro-chrome mirror driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.4.21 Fail safe low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.4.22 Wake up input WU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.23 High speed CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.4.24 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DS11546 Rev 5 3/197 7 Contents 4 L99DZ100G, L99DZ100GP 3.4.25 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.4.26 Inputs TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . . 63 3.4.27 Inputs DIRH, PWMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.4.28 Debug input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.4.29 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.4.30 Temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.4.31 Interrupt outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.4.32 Timer1 and Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.4.33 SGND loss comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.1 Supply VS, VSREG 4.2 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3 4.4 4.2.1 Voltage regulator: V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.2.2 Voltage regulator: V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2.3 Voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2.4 Short to ground detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2.5 Voltage regulator behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3.1 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3.2 Flash modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.3.3 SW-debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.3.4 V1_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.3.5 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.3.6 CAN wake-up signalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3.7 VBAT_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Wake-up from Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.4.1 Wake up input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.5 Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.6 Configurable window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.6.1 4.7 4/197 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Change watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.7.1 Temporary failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.7.2 Non-recoverable failures - forced Vbat_standby mode . . . . . . . . . . . . . 83 4.8 Reset output (NReset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.9 LIN Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DS11546 Rev 5 L99DZ100G, L99DZ100GP 4.10 Contents 4.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.9.2 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.9.3 Wake up from Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.9.4 Receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 High-speed CAN bus transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.10.1 Features: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.10.2 CAN transceiver operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.10.3 Automatic voltage biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.10.4 Wake-up by CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.10.5 CAN looping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.10.6 Pretended networking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.10.7 CAN error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.11 Serial Peripheral Interface (ST SPI Standard) . . . . . . . . . . . . . . . . . . . . . 93 4.12 Power supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.12.1 VS supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.12.2 VSREG supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.13 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 97 4.14 Power outputs OUT1..15 and OUT_HS . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.15 Auto-recovery alert and thermal expiration . . . . . . . . . . . . . . . . . . . . . . . 99 4.16 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.17 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.18 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.19 Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.20 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.21 PWM mode of the power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.22 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.23 Programmable soft-start function to drive loads with higher inrush current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.24 H-bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.25 H-bridge driver slew-rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.26 Resistive low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.27 Short circuit detection / drain source monitoring . . . . . . . . . . . . . . . . . . 108 4.28 H-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.29 Programmable cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . 111 DS11546 Rev 5 5/197 7 Contents 5 L99DZ100G, L99DZ100GP 4.30 Power window H-bridge safety switch off block . . . . . . . . . . . . . . . . . . . . 111 4.31 Heater MOSFET Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 4.32 Controller of electro-chromic glass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 4.33 Temperature warning and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 4.34 Thermal clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 4.35 VS compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . . .117 4.36 Analog digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.1 ST SPI 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.1.1 5.2 Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.2.1 Clock and Data Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.2.2 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.2.3 Address definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.2.4 Protocol failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 7 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6/197 7.1 Global Status Byte GSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.2 Control register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7.3 Status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.4 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 7.4.1 Control Register CR1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 7.4.2 Control Register CR2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 7.4.3 Control Register CR3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 7.4.4 Control Register CR4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 7.4.5 Control Register CR5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 7.4.6 Control Register CR6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 7.4.7 Control Register CR7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 7.4.8 Control Register CR8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 7.4.9 Control Register CR9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 7.4.10 Control Register CR10 (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.4.11 Control Register CR11 (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 7.4.12 Control Register CR12 (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 DS11546 Rev 5 L99DZ100G, L99DZ100GP Contents 7.4.13 Control Register CR13 (0x0D) to CR17 (0x11) . . . . . . . . . . . . . . . . . . 167 7.4.14 Control Register CR18 (0x12) to CR22 (0x16) . . . . . . . . . . . . . . . . . . 168 7.4.15 Control Register CR23 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 7.4.16 Control Register CR24 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 7.4.17 Control Register CR25 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.4.18 Control Register CR26 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.4.19 Control Register CR27 (0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 7.4.20 Control Register CR28 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 7.4.21 Control Register CR29 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 7.4.22 Control Register CR34 (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 7.4.23 Configuration Register (0x3F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 7.5 8 9 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.5.1 Status Register SR1 (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.5.2 Status Register SR2 (0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 7.5.3 Status Register SR3 (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.5.4 Status Register SR4 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.5.5 Status Register SR5 (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7.5.6 Status Register SR6 (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 7.5.7 Status Register SR7 (0x37) to SR9 (0x39) . . . . . . . . . . . . . . . . . . . . . 188 7.5.8 Status Register SR10 (0x3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 7.5.9 Status Register SR11 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 7.5.10 Status Register SR12 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 8.1 LQFP-64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 8.2 LQFP-64 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 DS11546 Rev 5 7/197 7 List of tables L99DZ100G, L99DZ100GP List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. 8/197 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Current monitor output (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Charge pump electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Heater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 H-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Gate drivers for the external Power-MOS switching times . . . . . . . . . . . . . . . . . . . . . . . . . 45 Drain source monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Drain source monitoring external heater MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Open-load monitoring external H-bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Open-load monitoring external heater MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Electro-chrome mirror driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Fail safe low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Wake-up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 CAN communication operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 CAN transmit data input: pin TxDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 CAN receive data output: Pin RxDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 CAN transmitter dominant output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 CAN transmitter recessive output characteristics, CAN normal mode . . . . . . . . . . . . . . . . 54 CAN transmitter recessive output characteristics, CAN low-power mode, biasing active . 54 CAN transmitter recessive output characteristics, CAN low-power mode, biasing inactive 55 CAN receiver input characteristics during CAN normal mode . . . . . . . . . . . . . . . . . . . . . . 55 CAN receiver input characteristics during CAN low power mode, biasing active . . . . . . . . 55 CAN Receiver input characteristics during CAN Low power mode, biasing inactive . . . . . 56 CAN receiver input resistance biasing active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 CAN transceiver delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Maximum leakage currents on CAN_H and CAN_L, unpowered . . . . . . . . . . . . . . . . . . . . 57 Biasing control timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 LIN transmit data input: pin TxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 LIN receive data output: pin RxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 LIN transmitter and receiver: pin LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 LIN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Inputs: CLK, DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DS11546 Rev 5 L99DZ100G, L99DZ100GP Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. List of tables DI, CLK and CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Output: DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Inputs: TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Inputs DIRH, PWMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Debug input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Interrupt outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Timer1 and Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SGND loss comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 CAN wake-up signalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Wake-up events description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Status of different functions/features vs operating modes . . . . . . . . . . . . . . . . . . . . . . . . . 77 Temporary failures description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Non-recoverable failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Power output settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 H-bridge control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 H-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Heater MOSFET control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Thermal cluster definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Operation codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Global Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Device application access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Device information read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 RAM address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 ROM address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Information Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Burst Read Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 SPI Data Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Data Consistency Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 WD Type/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 WD bit position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Global Status Byte (GSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 GSB signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Control register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Control Register CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 CR1 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Wake-up input1 filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 CAN transceiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Voltage regulator V2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Standby transition configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Control Register CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 CR2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Configuration of Timer x on-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Control Register CR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 CR3 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Control Register CR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 CR4 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 DS11546 Rev 5 9/197 11 List of tables Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. Table 149. Table 150. Table 151. Table 152. 10/197 L99DZ100G, L99DZ100GP Control Register CR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 CR5 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 OUTx Configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Control Register CR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 CR6 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Control Register CR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 CR7 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Half-bridge minimum ON time and related overcurrent recovery frequency. . . . . . . . . . . 160 High-side minimum ON time and related overcurrent recovery frequency . . . . . . . . . . . . 160 Control Register CR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 CR8 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Control Register CR9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 CR9 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Control Register CR10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 CR10 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Control Register CR11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 CR11 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Control Register CR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 CR12 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Control Register CR13 to CR17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 CR13 to CR17 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Control Register CR18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 CR18 to CR22 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Control Register CR23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 CR23 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Control Register CR24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 CR24 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Control Register CR25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 CR25 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Control Register CR26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 CR26 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Control Register CR27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 CR27 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Control Register CR28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 CR28 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Control Register CR29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 CR29 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Control Register CR34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 CR34 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 CR signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Status Register SR1 (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 SR1 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Status Register SR2 (0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 SR2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Status Register SR3 (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 SR3 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Status Register SR4 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 SR4 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Status Register SR5 (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 SR5 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Status Register SR6 (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 DS11546 Rev 5 L99DZ100G, L99DZ100GP Table 153. Table 154. Table 155. Table 156. Table 157. Table 158. Table 159. Table 160. Table 161. Table 162. Table 163. List of tables SR6 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Status Register SR7 (0x37) to SR9 (0x39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 SR7 to SR9 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Status Register SR10 (0x3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 SR10 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Status Register SR11 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 SR11 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Status Register SR12 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 SR12 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 LQFP-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 DS11546 Rev 5 11/197 11 List of figures L99DZ100G, L99DZ100GP List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. 12/197 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Activation profile 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Activation profile 1 (first cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Activation profile 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Activation profile 2 (first cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LQFP64 package and PCB thermal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Voltage regulator V1 characteristics (quiescent current and accuracy) . . . . . . . . . . . . . . . 31 Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 H-driver delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 IGHxr ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 IGHxf ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 SPI input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 SPI output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 SPI CSN - output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 SPI - CSN high to low transition and global status bit access . . . . . . . . . . . . . . . . . . . . . . 69 Voltage regulator behaviour and diagnosis during supply voltage . . . . . . . . . . . . . . . . . . . 72 Sequence to disable/enable the watchdog in CAN Flash mode . . . . . . . . . . . . . . . . . . . . . 73 NINT pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Watchdog in Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 NReset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 RxDL pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Wake-up behavior according to LIN 2.2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 RxDC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 CAN transceiver state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 CAN wake up capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Example of long auto-recovery on OUT7. Temperature acquisition starts after tAR, thermal expiration occurs after a T = 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Block diagram of physical realization of AR alert and thermal expiration . . . . . . . . . . . . . 101 Charge pump low filtering and start up implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Software strategy for half bridges before applying auto-recovery mode. . . . . . . . . . . . . . 104 Overcurrent recovery mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 H-bridge GSHx slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 H-bridge diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 H-bridge open-load-detection (no open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . 109 H-bridge open-load-detection (open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 H-bridge open-load-detection (short to ground detected) . . . . . . . . . . . . . . . . . . . . . . . . . 110 H-bridge open-load detection (short to VS detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 PWMH cross current protection time implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 LSx_FSO: low-side driver "passively" turned on, taking supply from output pin (if main supply fails), can guarantee VLSx_FSO < VOUT_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 DS11546 Rev 5 L99DZ100G, L99DZ100GP Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. List of figures Safety concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Heater MOSFET open-load and short-circuit to GND detection . . . . . . . . . . . . . . . . . . . . 113 Electro-chrome control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Thermal clusters identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Block diagram VS compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . . . 118 Sequential ADC Read Out for VSREG, VS, WU and THCL1 ..THCL6 . . . . . . . . . . . . . . . . 119 SPI pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 SDO pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 SDI Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 SDO frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Window watchdog operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Timer_x controlled by DIR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Extended ID and extended ID mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 LQFP-64 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 LQFP-64 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 LQFP-64 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 DS11546 Rev 5 13/197 13 Description 1 L99DZ100G, L99DZ100GP Description The L99DZ100G and L99DZ100GP are door zone systems IC providing electronic control modules with enhanced power management power supply functionality, including various standby modes, as well as LIN and HS CAN physical communication layers. The two low-drop voltage regulators of the devices supply the system microcontroller and external peripheral loads such as sensors and provide enhanced system standby functionality with programmable local and remote wake-up capability. In addition 8 high-side drivers to supply LEDs, 2 high-side drivers to supply bulbs increase the system integration level. Up to 5 DC motors and 4 external MOS transistors in H-bridge configuration can be driven. An additional gate drive can control an external MOSFET in high-side configuration to supply a resistive load connected to GND (e.g. mirror heater). An electro-chromic mirror glass can be controlled using the integrated SPI-driven module in conjunction with an external MOS transistor. All outputs are SC protected and implement an open-load diagnosis. The ST standard SPI interface (4.0) allows control and diagnosis of the device and enables generic software development. 14/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Block diagram and pin descriptions Figure 1. Block diagram &33 &3 96 287P $ &30 &KDUJH 3XPS &33 &30 $ 287P 287P $ *+ $ 287P 6+ */ $ 287P [ 'ULYHU,QWHUIDFH/RJLF'LDJQRVWLF $ 287P ',5+ 3:0+ /6B)62 /6B)62 )DLO6DIH [ 965(* 9B 15(6(7 95(* 9B 95(* &$16XSSO\ 5['B&1,17 7['B& &$1B+ &$1B/ 5['B/1,17 7['B/ /,1 'HEXJ /,1 287P $UHVS $ :DWW%XOE +6 287P $UHVS $ :DWW%XOE +6 287 $$ +6 287 $ !7RGULYH(&026)(7DVZHOO +6 287 P$ +6 287 P$ +6 287 P$ +6 P$ 287 *+KHDWHU 6+KHDWHU +6 3&KDQQHO 1,17 :8 +6 965(* [7M &O 3&KDQQHO 96 [7M &O &61 &/. ', '2 &0 +6 %XI IHUHG 96 +6&$1 ZLWK31 P$ 287 287B+6 P$ ',5 ',5 %LW $'&6$5 63,,QW HUI DF H :LQG RZ :DW FKG RJ 2 Block diagram and pin descriptions (&*ODVV &RQWURO%ORFN %,763,FRQWUROOHG *1' 6*1' (&'5 (&9 3*1' *$3*&)7 Table 2. Pin definitions and functions Pin Symbol Function 1 WU Wake-up Input: Input pin for static or cyclic monitoring of external contacts 2 CP2M Charge pump pin for capacitor 2, negative side 3 CP2P Charge pump pin for capacitor 2, positive side 4 CP 5 CP1P Charge pump pin for capacitor 1, positive side 6 CP1M Charge pump pin for capacitor 1, negative side Charge pump output DS11546 Rev 5 15/197 196 Block diagram and pin descriptions L99DZ100G, L99DZ100GP Table 2. Pin definitions and functions (continued) Pin Symbol 7 GHheater Gate driver for external power N-Channel MOSFET in high-side configuration to control the heater 8 SHheater Source of high-side MOSFET to control the heater 9 OUT14 High-side-driver output to drive LEDs 10 OUT13 High-side-driver output to drive LEDs 11 OUT12 High-side-driver output to drive LEDs 12 OUT9 High-side-driver output to drive LEDs 13 OUT10 High-side-driver-output; Important: Beside the bits OUT10_x (CR 5) this output can be switched on setting the ECON bit for electro-chrome control mode with higher priority. 14 OUT11 High-side-driver output to drive LEDs 15 LS1_FSO Fail Safe low-side switch (Active low) 16 LS2_FSO Fail Safe low-side switch (Active low) Power supply voltage for power stage outputs (external reverse battery protection required), for this input a ceramic capacitor as close as possible to GND is recommended. Important: For the capability of driving, the full current at the outputs all pins of VS must be connected externally! 17 VS 18 VS; 2nd pin 19 OUT7 High-side-driver output to drive LEDs or a 10 Watt bulb (programmable Rdson) OUT6 Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output) OUT1 Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output) OUT2 Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output) 23 OUT5 Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output) 24 OUT5; 2nd pin 20 21 22 16/197 Function Current capability (pin description see above) Current capability (pin description see above) DS11546 Rev 5 L99DZ100G, L99DZ100GP Block diagram and pin descriptions Table 2. Pin definitions and functions (continued) Pin Symbol Function 25 VSREG Power supply voltage to supply the internal voltage regulators, OUT15 and the OUT_HS (external reverse battery protection required / Diode) for this input a ceramic capacitor as close as possible to GND and an electrolytic back up capacitor is recommended. 26 OUT_HS 27 OUT4 28 OUT4; 2nd pin High-side-driver output to drive LEDs or to supply contacts Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output) Current capability (pin description see above) Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output) 29 OUT3 30 VS; 3rd pin 31 OUT15 High-side-driver output to drive LEDs 32 PGND Power GND 33 OUT8 High-side-driver output to drive LEDs or a 5 Watt bulb (programmable Rdson) 34 ECDR ECDR: using the device in EC control mode this pin is used to control the gate of an external N-Channel MOSFET 35 SGND Signal Ground Current capability (for the pin description see above) 36 CM Current monitor output: depending on the selected multiplexer bits CM_SEL_x (CR 7) of the; Control Register this output sources an image of the instant current; through the corresponding high-side driver with a fixed ratio 37 ECV ECV: using the device in EC control mode this pin is used as voltage monitor input. For fast discharge an additional low-side-switch is implemented 38 CLK SPI: serial clock input 39 DO SPI: serial data output (push pull output stage) 40 DI SPI: serial data input 41 CSN 42 TxD_L 43 RxD_L/NINT 44 TxD_C 45 RxD_C/NINT 46 DIR1 SPI: chip select not input LIN Transmit data input RxDL -> LIN receive data output; NINT -> indicates local/remote wake-up events (push pull output stage) CAN transmit data input CAN receive data output NINT -> indicates local/remote wake-up events (push pull output stage) Direct Drive Input 1 DS11546 Rev 5 17/197 196 Block diagram and pin descriptions L99DZ100G, L99DZ100GP Table 2. Pin definitions and functions (continued) 18/197 Pin Symbol Function 47 PWMH PWMH input: this input signal can be used to control the H-bridge Gate Drivers. 48 DIRH Direction Input: this input controls the H-bridge Drivers for the external MOSFETs 49 DIR2 Direct Drive Input 2 50 NRESET 51 5V_1 52 CAN Supply 53 NINT 54 CAN_L CAN low level voltage I/O 55 CAN_H CAN high level voltage I/O 56 Debug Debug input to deactivate the window watchdog (high active) 57 LIN 58 5V_2 Voltage regulator 2 output: 5 V supply for external loads (potentiometer, sensors) or CAN Transceiver. V2 is protected against reverse supply 59 GL1 Gate driver for PowerMOS low-side switch in half-bridge 1 60 SH1 Source of high-side switch in half-bridge 1 61 GH1 Gate driver for PowerMOS high-side switch in half-bridge 1 62 GH2 Gate driver for PowerMOS high-side switch in half-bridge 2 63 SH2 Source of high-side switch in half-bridge 2 64 GL2 Gate driver for PowerMOS low-side switch in half-bridge 2 NReset output to micro controller; (reset state = LOW) (Low-side switch with drain connected to the output pin and internal pull up resistance to 5V_1) Voltage regulator 1 output: 5 V supply e.g. micro controller, CAN transceiver CAN supply input; to allow external CAN supply from V1 or V2 regulator Interrupt output (low active; push-pull output stage) to indicate VSREG early warning (Active mode); indicates wake-up events from V1_standby mode LIN bus line DS11546 Rev 5 L99DZ100G, L99DZ100GP Block diagram and pin descriptions ',5 9B 15(6(7 &$16XSSO\ &$1B/ 1,17 &$1B+ 'HEXJ 9B /,1 6+ */ *+ 6+ *+ */ Figure 2. Pin connection (top view) :8 ',5+ &30 3:0+ &33 ',5 &3 5['B&1,17 &33 7['B& &30 5['B/1,17 *+KHDWHU 7['B/ 6+KHDWHU &61 287 ', 287 '2 287 &/. 287 (&9 287 3*1' 287 96 287 287 965(* 287B+6 287 287 287 287 287 287 287 287 (&'5 /6B)62 96 /6B)62 96 287 &0 6*1' *$3*&)7 DS11546 Rev 5 19/197 196 Electrical specifications L99DZ100G, L99DZ100GP 3 Electrical specifications 3.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability Table 3. Absolute maximum ratings Symbol Value [DC voltage] Unit DC supply voltage / "jump start" -0.3 to +28 V Load dump -0.3 to +40 V Stabilized supply voltage, logic supply -0.3 to 6.5 V1 < VSREG V Stabilized supply voltage -0.3 to +28(2) V -0.3 to V1+0.3 V Multi Level Inputs -0.3 to 40 V Debug input pin voltage range -0.3 to 40 V Output voltage range of Fail-Safe Low-side Switches -0.3 to 35 V DC Wake up input voltage / "jump start" -0.3 to +28 V Load dump -0.3 to +40 V LIN bus I/O voltage range -20 to +40 V Current injection into VS related input pins 20 mA IOUT_INJ(3) Current injection into VS related outputs 20 mA VCANSUP CAN supply -0.3 to +5.25 V VS, VSREG 5V_1 5V_2(1) Parameter / test condition VDI, VCLK VCSN VDO, VRXDL/NINT, VRXDC, VNRESET, VCM, VDIR, Logic input / output voltage range VDIR2, VPWMH, VDIRH, VINT VTXDC, VTXDL VDebug VLS1_FSO, VLS2_FSO VWU VLIN IInput(3) VCANH, VCANL CAN bus I/O voltage range -27 to +40 V VCANH - VCANL Differential CAN-Bus Voltage -5 to +10 V -0.3 to VS+0.3 V VOUTn, VECDR, VECV, Output voltage (n = 1 to 15) Vout_HS 20/197 VGH1, VGH2 (VGxy) High Voltage Signal Pins VSxy-0.3 to VSxy+13; VCP+0.3 V VGL1, VGL2, (VGxy) High Voltage Signal Pins VSxy-0.3 to VSxy+13; VCP-0.3V to +12V; Vcp+0.3V V DS11546 Rev 5 L99DZ100G, L99DZ100GP Electrical specifications Table 3. Absolute maximum ratings (continued) Symbol VSH1, VSH2 (VSxy) Parameter / test condition Value [DC voltage] Unit High Voltage Signal Pins -1 to 40 V High Voltage Signal Pins; single pulse with tmax = 200ns -5 to 40 V VCP1P High Voltage Signal Pins VS-0.3 to VS+14 V VCP2P High Voltage Signal Pins VS-0.6 to VS+14 V VCP1M, VCP2M High Voltage Signal Pins -0.3 to VS+0.3 V High Voltage Signal Pin VS 26 V VS-0.3 to VS+14 V High Voltage Signal Pin VS > 26 V VS-0.3 to +40 V VGH_heater VSheater -0.3 to VSheater+13; VCP+0.3 V VSH_heater -0.3 to 40V Or -0.3 to Vs+0.3 V ISH_Heater +/-10 mA IECV, IOUT2, IOUT3, IOUT9, IOUT10, IOUT11, IOUT12, IOUT13, IOUT14, IOUT15, IOUT_HS 1.25 A 2.5 A IOUT7 5 A IOUT1,6 5 A IOUT4,5 10 A VCP IOUT8 Output current(2) IVScum Maximum cumulated current at VS drawn by OUT1 & OUT2(2) 7.5 A IVScum Maximum cumulated current at VS drawn by OUT3, OUT8 & OUT10(2) 2.5 A IVScum Maximum cumulated current at VS drawn by OUT4(2) 10 A IVScum Maximum cumulated current at VS drawn by OUT5(2) 10 A IVScum Maximum cumulated current at VS drawn by OUT6 & OUT7(2) 7.5 A IVScum Maximum cumulated current at VS drawn by OUT9, OUT11, OUT12, OUT13, OUT14, OUT15 and CP 2.5 A IVSREG Maximum current at VSREG pin (2) (5V_1. 5V_2 and OUT_HS) 2.5 A Maximum cumulated current at PGND drawn by OUT1 & OUT6(2) 7.5 A IPGNDcum DS11546 Rev 5 21/197 196 Electrical specifications L99DZ100G, L99DZ100GP Table 3. Absolute maximum ratings (continued) Symbol Parameter / test condition Value [DC voltage] Unit IPGNDcum Maximum cumulated current at PGND drawn by OUT2 & OUT5(2) 12.5 A IPGNDcum Maximum cumulated current at PGND drawn by OUT3, OUT4 & ECV(2) 12.5 A Maximum current at SGND(2) 1.25 A -0.3 to 0.3 V ISGND GND pins PGND versus SGND 1. 5V_2 is robust against SC to 28 V only in case VSREG is supplied. 2. Values for the absolute maximum DC current through the bond wires. This value does not consider maximum power dissipation or other limits. 3. Guaranteed by design. Note: All maximum ratings are absolute ratings. Leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit! Note: Loss of ground or ground shift with externally grounded loads: ESD structures are configured for nominal currents only. If external loads are connected to different grounds, the current load must be limited to this nominal current. 3.2 ESD protection Table 4. ESD protection Parameter All pins(1) All power output pins (2): OUT1 - OUT15, OUT_HS, ECV Value Unit +/-2 kV +/-4 kV +/-8(2) +/-9(3) (4) +/-6(5) LIN kV +/-8(2) +/-6(5) (4) kV All pins(6) +/-500 V Corner pins(6) +/-750 V pins(7) +/- 200 V CAN_H, CAN_L All 1. HBM (human body model, 100 pF, 1.5 k) according to MIL 883C, Method 3015.7 or EIA/JESD22A114-A. 2. HBM with all none zapped pins grounded. 3. Indirect ESD Test according to IEC 61000-4-2 (150 pF, 330 ) and `Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive Applications' (version 1.3, 2012-05-04). 4. Value has been verified by an external test house; the result was equal or better than minimum requirement. 5. Direct ESD Test according to IEC 61000-4-2 (150 pF, 330 ) and `Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive Applications' (version 1.3, 2012-05-04). 6. Charged device model. 7. Machine model; C = 220 pF, R = 0 . 22/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP 3.3 Electrical specifications Thermal data Table 5. Operating junction temperature Symbol Tj Parameter Operating junction temperature Value Unit -40 to 175 C All parameters are guaranteed in the junction temperature range -40 to 150C (unless otherwise specified); the device is still operative and functional at higher temperatures (up to 175C). Note: Parameters limits at higher junction temperatures than 150C may change respect to what is specified as per the standard temperature range. Note: Device functionality at high junction temperature is guaranteed by characterization. Table 6. Temperature warning and thermal shutdown Symbol TW Parameter Thermal overtemperature warning threshold Min. Typ. Max. Unit 140 150 160 C Cluster 1-4 Cluster 5-6 165 165 175 175 185 190 C Tj(1) 175 185 195 C Tj(1) Tj(1) TSD1 TSD2 TSD12hys Tjtft Thermal shutdown junction temperature 1 Thermal shutdown junction temperature 2 Thermal warning / shutdown filter time Hysteresis 5 C 32 s 1. Non-overlapping. 3.3.1 LQFP64 thermal data Devices belonging to L99DZxxx family embed a multitude of junctions (i.e. Outputs based on a PowerMOSFET stage) housed in a relatively small piece of silicon. The devices contain, among all the described features, 6 Half-bridges (12 N-Channel PowerMOS), 10 high-sides and two voltage regulators; all the other derivatives, even if smaller than the family super set device, still contain a significant number of junctions. For this reason, using the Thermal Impedance of a single junction (i.e. voltage regulator or major power dissipation contributor) does not allow to predict thermal behavior of the whole device and therefore it is not possible to assess if a device is thermally suitable for a given activation profile and loads characteristics. Thermal information is provided as temperature reading by different clusters placed close to the most dissipative junctions. Some representative and realistic worst-case thermal profiles are described in the below paragraph. Following measurement methods can be easily implemented, by final user, for a specific activation profile. DS11546 Rev 5 23/197 196 Electrical specifications L99DZ100G, L99DZ100GP L99DZ100G and L99DZ100GP thermal profiles Profile 1 Battery Voltage: 16V, Ambient temperature start: 85C DC activation V1 charged with 70 mA (DC activation) V2 charged with 30 mA (DC activation) OUT7: 1 x10W bulb (DC activation) OUT8: 1 x 5W bulb (DC activation) OUT11: 300 resistor (DC activation) OUT12: 300 resistor (DC activation) OUT13: 300 resistor (DC activation) OUT14: 300 resistor (DC activation) Cyclic activation OUT4 - OUT5: 3,3 resistor placed across those outputs - 10 activations of Lock/Un-lock (250 ms ON Lock; 500 ms wait; 250 ms ON Unlock unlock; 500 ms wait) OUT5 - OUT6: 10 resistor placed across those outputs - (250 ms ON Safe Lock; 500 ms wait; 250 ms ON Safe unlock; 500 ms wait) Test execution: Once thermal equilibrium is reached with all DC load active, the "Cyclic Activation" sequence is applied. Temperature reading is logged just at the end of the whole sequence. Figure 3. Activation profile 1 d d ("1($'5 24/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Electrical specifications Figure 4. Activation profile 1 (first cycle) d Khd Note: d ("1($'5 All curves are plotted interpolating measured samples with 15 ms of period. Profile 2 Battery Voltage: 16V, Ambient temperature start: 85C DC activation V1 charged with 70 mA (DC activation) V2 charged with 30 mA (DC activation) OUT7: 1 x10W bulb (DC activation) OUT8: 1 x 5W bulb (DC activation) OUT11: 300 resistor (DC activation) OUT12: 300 resistor (DC activation) OUT13: 300 resistor (DC activation OUT14: 300 resistor (DC activation) Cyclic activation OUT1 - OUT6: 6,8 resistor placed across those outputs - 2 activations of Fold/Unfold. (3s ON; 1s OFF; 2x) Test execution: Once thermal equilibrium is reached with all DC load active, the "Cyclic Activation" sequence is applied. DS11546 Rev 5 25/197 196 Electrical specifications L99DZ100G, L99DZ100GP Figure 5. Activation profile 2 d d ("1($'5 Figure 6. Activation profile 2 (first cycle) d Khd Note: 26/197 d All curves are plotted interpolating measured samples with 15 ms of period. DS11546 Rev 5 ("1($'5 L99DZ100G, L99DZ100GP Electrical specifications Figure 7. LQFP64 package and PCB thermal configuration Note: Layout condition for Thermal Characterization (board finishing thickness 1.5 mm +/- 10%, board four layers, board dimension 77 mm x 114 mm, board material FR4, Cu thickness 0,070 mm for outer layers, 0.0035 mm for inner layers, thermal vias separation 1.2 mm. 3.4 Electrical characteristics 3.4.1 Supply and supply monitoring All SPI communication, logic and oscillator parameter are working down to VSREG = 3.5 V and parameter are as specified in the according chapters (guaranteed by design). SPI thresholds Oscillator frequency (delay times correctly elapsed) Internal register status correctly kept (reset at default values for VSREG< VPOR) Reset threshold correctly detected The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28 V; 6 V VSREG 28 V; Tj = -40 C to 150 C, unless otherwise specified. DS11546 Rev 5 27/197 196 Electrical specifications L99DZ100G, L99DZ100GP Table 7. Supply and supply monitoring Symbol Parameter VSUV VS undervoltage threshold Vhyst_UV VS undervoltage hysteresis VSOV VS overvoltage threshold Vhyst_OV VS overvoltage hysteresis VSREG_UV VSREG undervoltage threshold Vhyst_UV VSREG undervoltage hysteresis VSREG_OV VSREG overvoltage threshold Vhyst_OV VSREG overvoltage hysteresis tovuv_filt VS/VSREG over/undervoltage filter time Test condition VS increasing / decreasing V 0.2 V VS decreasing 18.5 22.5 0.5 VSREG increasing / decreasing 1 4.2 0.04 0.1 V 4.9 V 0.2 V 20 22.5 VSREG decreasing 18.5 22.5 0.5 1 1.5 64 Current consumption in Vbat_standby mode with cyclic sense enabled (1) IV(BAT)CW V 1.5 VSREG increasing IV(BAT)CS 28/197 5.4 22.5 Current consumption in Vbat_standby mode (1) IV(SW) Unit 20 VS = 12 V; Both voltage regulators deactivated; HS/LS Driver OFF; No CAN communication; CAN automatic voltage biasing enabled IV(V1stby) 0.1 Max. VS increasing Current consumption in Active mode IV(BAT) Typ. 4.7 0.04 VS = VSREG = 12 V; TxD CAN = high; TxD LIN = high; V1 = ON; V2 = ON; HS/LS Driver OFF; CP = ON IV(act) Min. V V s 11 15 mA 8 21 35 A VS = 12 V; Both voltage regulators deactivated; T = 50 ms, tON = 100 s 40 100 143 A Current consumption in Vbat_standby mode with cyclic wake enabled (1) VS = 12 V; Both voltage regulators deactivated during standby phase 40 100 143 A Current consumption in V1_standby mode (1) VS = 12 V; Voltage regulator V1 active; (IV1 = 0); HS/LS Driver OFF 16 56 76 A Current consumption in V1_standby mode (1) (2) VS = 12 V; Voltage regulator V1 active; (IV1 = ICMP); HS/LS Driver OFF 196 A Current consumption in V1_standby mode (1) VS = 12V; Voltage regulator V1 active; (IV1 = IPEAK); HS/LS Driver OFF 436 A Current consumption adder in standby mode if Selective Wakeup enabled and CAN communication on the bus TRX_BIAS mode (1) VS = 12 V 2000 A DS11546 Rev 5 1570 L99DZ100G, L99DZ100GP Electrical specifications Table 7. Supply and supply monitoring (continued) Symbol Parameter IqCAN Quiescent current adder for CAN wake up activated Guaranteed by design 0 A IqLIN Quiescent current adder for LIN wake up activated Guaranteed by design 0 A IOUT_HS Test condition Min. Additional bias quiescent current for switched on OUT_HS or Guaranteed by design OUT15 by DIR or Timer; value for 1 output Typ. Max. Unit 620 1100 A IOUTHS_DIR Quiescent current adder if OUT_HS and/or OUT15 are configured for Direct Drive; value during output off Guaranteed by design 0 5 A Itimer Quiescent current adder if timer1 and/or timer 2 are active to provide interrupt on NINT upon timer expiration Guaranteed by design 65 110 A 1. Conditions for specified current consumption: -- VLIN > (VS-1.5 V) -- (VCAN_H - VCAN_L) < 0.4 V or (VCAN_H - VCAN_L) > 1.2 V -- VWU < 1 V or VWU > (VS - 1.5 V) 2. Iq = Iq0 + 2% * ILOAD (see also Figure 8: Voltage regulator V1 characteristics (quiescent current and accuracy) 3.4.2 Oscillator The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28 V; 6 V VSREG 28 V; Tj = -40 C to 150 C, unless otherwise specified. Table 8. Oscillator Symbol Parameter Test condition Min. Typ. Max. Unit fCLK1(1) Oscillation frequency OSC1 1.66 2.0 2.34 MHz (1) Oscillation frequency OSC2 30.4 32.0 33.6 MHz Typ. Max. Unit 3.45 4.5 V 3.5 V fCLK2 1. OSC1: charge pump, SPI, output drivers, watchdog OSC2: ADC, CAN-PN 3.4.3 Power-on reset (VSREG) All outputs open; Tj = -40 C to 150 C, unless otherwise specified. Table 9. Power-on reset (VSREG) Symbol VPOR_R VPOR_F Parameter VPOR threshold VPOR threshold Test condition Min. VSREG rising VSREG falling(1) 2.45 1. This threshold is valid if VSREG had already reached VPOR_R(max) previously. DS11546 Rev 5 29/197 196 Electrical specifications 3.4.4 L99DZ100G, L99DZ100GP Voltage regulator V1 The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V VS 28 V; 4.5 V VSREG 28 V; Tj = -40 C to 150 C, unless otherwise specified. Table 10. Voltage regulator V1 Symbol V1 VSREG_absmin Parameter Test condition Output voltage VSREG = 13.5V VSREG absolute minimum value for controlling NRESET output VSREG rising/falling Min. Typ. Max. 5.0 Unit V 2 V V1_low_acc Output voltage ILOAD = 0 mA to ICMP; (Active tolerance Low accuracy mode) or ILOAD = 0 mA to IPEAK (V1stdby); VSREG = 13.5 V mode -3 3 % V1_hi_acc ILOAD = ICMP to 100 mA; (Active Output voltage mode) or ILOAD = IPEAK to tolerance High accuracy 100 mA (V1stdby); mode VSREG = 13.5 V -2 2 % V1_250mA Output voltage tolerance (100 to 250mA) -3 3 % VDP1 ICC1 ICCmax1 Cload1 tTSD Drop-out Voltage ILOAD = 250 mA; VSREG = 13.5 V ILOAD = 50 mA; VSREG = 5 V 0.2 0.4 V ILOAD = 100 mA; VSREG = 5 V 0.3 0.5 V ILOAD = 150 mA; VSREG = 5 V 0.45 0.6 V 250 mA 900 mA Output current in Active Max. continuous load current mode Short circuit output current Current limitation Load capacitor1 Ceramic (+/- 20%) 340 600 0.22(1) V1 deactivation time after thermal shut-down F 1 sec ICMP_ris Current comp. rising thresh Rising current 2 4 6 mA ICMP_fal Current comp. falling threshold Falling current 1.4 2.8 4.2 mA ICMP_hys Current comp. Hysteresis 1.2 mA IPeak_ris(2) Current comp. rising thresh. Rising current 6 12 18 mA IPeak_fal(2) Current comp. falling threshold Falling current 5 10 15 mA IPeak_hys(2) Current comp. Hysteresis 30/197 2 DS11546 Rev 5 mA L99DZ100G, L99DZ100GP Electrical specifications Table 10. Voltage regulator V1 (continued) Symbol Parameter V1fail V1 fail threshold tV1fail Test condition Min. Max. Unit 2 V V1 fail filter time 2 s V1 short filter time 4 ms tV1FS V1 Fail-Safe Filter Time 2 ms tV1off V1 deactivation time after 8 consecutive WD failures tV1short V1 forced Typ. Tested by scan 150 200 250 ms 1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20%). Capacitor must be located close to the regulator output pin. A 2.2 F capacitor is recommended to minimize the DPI stress in the application. 2. In Active mode, V1 regulator is switched to high accuracy mode, dropping below the ICMP threshold regulator switches to low accuracy mode. Figure 8. Voltage regulator V1 characteristics (quiescent current and accuracy) $FWLYH9VWGE\PRGH +LJKDFFXUDF\9 9 :'RQ GH PR 9 ,T LYH $FWFXUDF\9RQ KDF +LJ :' GH PR9 \ E WG 9 9DVFFXUDF:\ 'RQ /RZ 6ORSH ,/RDG ,T DF\ FXU DF I /RZ 9 'RI RQ : 9 GE\ :' W H 9V PRG H Y L W $F ,&03 3.4.5 ,3HDN ,/RDG ("1($'5 Voltage regulator V2 The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V VS 28 V; 4.5 V VSREG 28 V; Tj = -40 C to 150 C, unless otherwise specified. Table 11. Voltage regulator V2 Symbol V2 V2_1mA Parameter Test condition Output voltage VSREG = 13.5 V Output voltage tolerance (0 to 1 mA) ILOAD = 1 mA; VSREG = 13.5 V DS11546 Rev 5 Min. Typ. Max. 5.0 -6.5 Unit V 6.5 % 31/197 196 Electrical specifications L99DZ100G, L99DZ100GP Table 11. Voltage regulator V2 (continued) Symbol Parameter Test condition Min. Typ. Max. Unit V2_25mA Output voltage tolerance (1 to 25 mA) ILOAD = 25 mA; VSREG = 13.5 V -3 3 % V2_50mA Output voltage tolerance (25 to 50 mA) ILOAD = 50 mA; VSREG = 13.5 V -4 4 % V2_100mA Output voltage tolerance (50 to 100 mA) ILOAD = 100 mA; VSREG = 13.5 V -4 4 % VDP2 Drop-out voltage ILOAD = 25 mA; VSREG = 5.25 V 0.3 0.4 V ILOAD = 50 mA; VSREG = 5.25 V 0.4 0.8 V ILOAD = 100 mA; VSREG = 13.5 V 1 1.6 V 50 mA 250 mA Output current in Active mode Max. continuous load current Short circuit output current Current limitation Cload Load capacitor Ceramic (+/- 20%) V2fail V2 fail threshold V2 forced tV2fail ICC2 ICCmax2 tV2short 100 150 0.22 (1) F 2 V V2 fail filter time 2 s V2 short filter time 4 ms 1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20%). Capacitor must be located close to the regulator output pin. A 2.2 F capacitor is recommended to minimize the DPI stress in the application. 3.4.6 Reset output The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4V VSREG 28V; Tj = -40 C to 150 C, unless otherwise specified. Table 12. Reset output 32/197 Symbol Parameter VRT1falling Reset threshold voltage1 VRT2falling Test condition Min. Typ. Max. Unit VV1 decreasing 3.25 3.5 3.7 V Reset threshold voltage2 VV1 decreasing 3.55 3.8 4 V VRT3falling Reset threshold voltage3 VV1 decreasing 3.75 4.0 4.2 V VRT4falling Reset threshold voltage4 VV1 decreasing 4.1 4.3 4.5 V VRTrising Reset threshold voltage4 VV1 increasing 4.67 4.8 4.87 V VRESET Reset Pin low output V1 > 1 V; IRESET = 5 mA voltage 0.2 0.4 V RRESET Reset pull up int. resistor 20 30 k 10 DS11546 Rev 5 L99DZ100G, L99DZ100GP Electrical specifications Table 12. Reset output (continued) Symbol Parameter Test condition ILOAD = 1 mA Min. Typ. 6 Max. Unit 40 s tRR Reset reaction time tUV1 V1 undervoltage filter time tV1R Reset pulse duration (V1 undervoltage and V1 power on reset) 1.5 2.0 2.5 ms tWDR Reset pulse duration (watchdog failure) 3 4 5 ms 16 DS11546 Rev 5 s 33/197 196 Electrical specifications 3.4.7 L99DZ100G, L99DZ100GP Watchdog timing 4.5 V VSREG 28 V; Tj = -40 C to 150 C, unless otherwise specified. Table 13. Watchdog timing Symbol tLW 34/197 Parameter Test condition Long open window Min. Typ. Max. Unit 160 200 240 ms 4.5 ms TEFW1 Early Failure Window 1 TLFW1 Late Failure Window 1 20 TSW1 Safe Window 1 7.5 TEFW2 Early Failure Window 2 TLFW2 Late Failure Window 2 100 TSW2 Safe Window 2 37.5 TEFW3 Early Failure Window 3 TLFW3 Late Failure Window 3 200 TSW3 Safe Window 3 75 TEFW4 Early Failure Window 4 TLFW4 Late Failure Window 4 400 TSW4 Safe Window 4 150 DS11546 Rev 5 ms 12 ms 22.3 ms ms 60 ms 45 ms ms 120 ms 90 ms ms 240 ms L99DZ100G, L99DZ100GP Electrical specifications Figure 9. Watchdog timing 1RUPDOVWDUWXSRSHUDWLRQDQGWLPHRXWIDLOXUHV 7 /: ORQJRSHQZLQGRZ 7 (): HDUO\IDLOXUHZLQGRZ FRUUHFWWULJJHUWLPLQJ 7 6: VDIHWULJJHUZLQGRZ HDUO\WULJJHUWLPLQJ 7 :'5 ZDWFKGRJUHVHWGXUDWLRQ PLVVLQJWULJJHU 7 ():7 6: 7 (): 7 6: 7 (): 7 /: :' WULJJHU WULJJHUVLJQDO 7 /: 7 /: 15(6 2XW 7 :'5 7:'5 QRUPDORSHUDWLRQ WLPHPV PLVVLQJ WULJJHU HDUO\ ZULWH WLPHPV 0LVVLQJ0LFURFRQWUROOHUWULJJHUVLJQDO :' WULJJHU 7 /: 7/: 7 /: WLPHPV 15(6 2XW 7 :'5 7 :'5 7 :'5 WLPHPV ("1($'5 DS11546 Rev 5 35/197 196 Electrical specifications L99DZ100G, L99DZ100GP Figure 10. Watchdog early, late and safe windows 76:Q 6DIHZLQGRZ 7():Q (DUO\)DLOXUHZLQGRZ 7/):Q /DWHIDLOXUHZLQGRZ 7/):QBPLQ 76:QBPD[ 76:QBPLQ XQGHILQHG 7():QBPD[ (DUO\ :DWFKGRJ IDLOXUH VDIHWULJJHUDUHD /DWH ZDWFKGRJ IDLOXUH XQGHILQHG WLPH ("1($'5 3.4.8 Current monitor output (CM) The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28V; 6 V VSREG 28 V; Tj = -40 C to 150 C, unless otherwise specified Table 14. Current monitor output (CM) Symbol VCM Parameter Test condition Functional voltage range 36/197 ICM/IOUT8 (low on-resistance) Typ. 0 Current monitor output ratio: ICM/IOUT1,4,5,6 and 7 (low onresistance) ICMr Min. 1/10000 0 V VCM (V1 - 1 V) 1/6500 ICM/IOUT 2,3, 7,8 (high onresistance) 1/2000 ICM/IOUT9,10,11,12,13,14,15 and HS 1/1000 DS11546 Rev 5 Max. Unit V1-1V V L99DZ100G, L99DZ100GP Electrical specifications Table 14. Current monitor output (CM) (continued) Symbol ICM acc Parameter Current monitor accuracy accICMOUT1,4,5,6 and 7(low onresistance) 0 V VCM (V1 - 1 V); IOUTmin = 500 mA; IOUT4,5max=7.4 A; IOUT1,6max = 2.9 A; IOUT7max = 1.4 A Current monitor accuracy accICMOUT 8 (low on-resistance) 0 V VCM (V1 - 1 V); IOUTmin = 100 mA; IOUT8max=0.9 A Current monitor accuracy accICMOUT2,3, 9,10,11,12,13,14,15 ,HS and OUT7,8 (high onresistance) 0 V VCM (V1 - 1 V); IOUT.min = 100 mA; IOUT11,12, 15 HS = 0.2 A; IOUT7,8 max = 0.3 A Current monitor accuracy accICMOUT1,4,5,6 and 7 (low onresistance) 0 V VCM (V1 - 1 V); IOUTmin = 2 * IOLD; IOUT4,5max = 7.4 A; IOUT1,6max = 2.9 A; IOUT7max = 1.4 A Current monitor accuracy accICMOUT 8(low on-resistance) 0 V VCM (V1 - 1 V); IOUTmin = 2 * IOLD; IOUT8max = 0.9 A Current monitor accuracy accICMOUT2, 3, 9,11,12,13,14,15, HS and OUT7,8 (high on-resistance) 0 V VCM (V1 - 1 V); IOUT.min = 2 * IOLD; IOUT2,3max = 0.4 A; IOUT9,13,14max = 0.3 A; IOUT11,12,15 HS = 0.2 A; IOUT7,8 max = 0.3 A Current monitor accuracy accICMOUT10 0 V VCM (V1 - 1 V); IOUT.min = 2 * IOLD; IOUT10max = 0.4 A ICM acc_2ol tcmb Test condition Min. Current monitor blanking time Typ. Max. 4% + 1% FS(1) 8% + 2% FS(1) 4% + 1% FS(1) 8% + 2% FS(1) 4% + 1% FS(1) 8% + 4% FS(1) 32 Unit s 1. FS (full scale) = IOUTmax * ICMr 3.4.9 Charge pump The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28V; Tj = -40 C to 150 C, unless otherwise specified. Table 15. Charge pump electrical characteristics Symbol Parameter VCP Charge pump output voltage ICP Charge pump output current(1) Test condition Min. Typ. VS = 6 V, ICP = -15 mA VS+6 VS+7 VS 10 V, ICP = -15 mA VS+11 VS+12 VCP = VS + 10 V; VS = 13.5 V; C1 = C2 = CCP = 100 nF 22.5 DS11546 Rev 5 Max. Unit V VS+13.5 V mA 37/197 196 Electrical specifications L99DZ100G, L99DZ100GP Table 15. Charge pump electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. VCP = VS; VS = 13.5 V; C1 = C2 = CCP = 100 nF Max. Unit 70 mA VS+5.5 V ICPlim Charge pump output current limitation(2) VCP_low Charge pump low threshold voltage TCP Charge pump low filter time 64 s fCP Charge Pump frequency 400 kHz VS+4.5 VS+5 1. ICP is the minimum current the device can provide to an external circuit without VCP going below VS + 10 V. 2. ICPlim is the maximum current, which flows out of the device in case of a short to VS. 3.4.10 Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28 V; 6 V VSREG 28 V, all outputs open; Tj = -40 C to 150 C, unless otherwise specified. Table 16. Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR Symbol Parameter rON OUT1,6 On-resistance to supply or GND rON OUT2,3 rON OUT4 rON OUT5 On-resistance to supply or GND On-resistance to supply or GND On-resistance to supply or GND On-resistance to supply in low resistance mode rON OUT7 On-resistance to supply in high resistance mode 38/197 Test condition VS = 13.5 V; Tj = 25 C; IOUT1,6 = 1.5A Min. Typ. 300 VS = 13.5V; Tj = 130C IOUT1,6 = 1.5 A VS = 13.5 V; Tj = 25 C; IOUT2,3 = 0.25 A 2000 VS = 13.5 V; Tj = 25C; IOUT5 = 3 A 150 VS = 13.5 V; Tj = 25 C; IOUT7 = -0.8 A 100 VS = 13.5 V; Tj = 25C; IOUT7 = -0.2 A VS = 13.5 V; Tj = 130 C; IOUT7 = -0.2 A DS11546 Rev 5 m m 200 500 VS = 13.5 V; Tj = 130 C; IOUT7 = -0.8 A m m 300 VS = 13.5 V; Tj = 130 C; IOUT5 = 3 A m m 4000 VS = 13.5 V; Tj = 130 C; IOUT4 = 3 A Unit m 600 VS = 13.5 V; Tj = 130 C; IOUT2,3 = 0.25 A VS = 13.5V; Tj = 25 C; IOUT4 = 3 A Max. m m 1000 1600 m m 3200 m L99DZ100G, L99DZ100GP Electrical specifications Table 16. Outputs OUT1 - OUT15, OUT_HS, ECV, ECDR (continued) Symbol Parameter On-resistance to supply in low resistance mode rON OUT8 On-resistance to supply in high resistance mode rON OUT9,10,13,14 On-resistance to supply rON OUT11,12,15, HS On-resistance to supply rON ECV On-resistance to GND Test condition VS = 13.5 V; Tj = 25 C; IOUT8 = -0.4 A Typ. Max. 800 VS = 13.5 V; Tj = 130 C; IOUT8 = -0.4 A 1600 VS = 13.5 V; Tj = 130 C; IOUT8 = -0.2 A 2000 VS = 13.5 V; Tj = 130 C; IOUT9,10,13,14 = -75 mA 5 VS = 13.5 V; Tj = 130 C; IOUT11,12,15, HS = -75 mA m m 4000 VS = 13.5 V; Tj = 25 C; IOUT11,12,15, HS = -75 mA m m 3200 VS = 13.5 V; Tj = 25 C; IOUT9,10,13,14 = -75 mA Unit m 1600 VS = 13.5 V; Tj = 25 C; IOUT8 = -0.2 A m 10 VS = 13.5 V; Tj = 25 C; IOUTECV,ECFD = +0.4 A 1600 2200 m VS = 13.5 V; Tj = 130 C; IOUTECV,ECFD = +0.4 A 2500 3400 m IQLH Switched-off output current VOUT = 0 V; standby mode high-side drivers of OUT7VOUT = 0 V; active mode 15, OUT_HS IQLH Switched-off output current VOUT = 0 V; standby mode high-side drivers of OUT1-6 V OUT = 0 V; Active mode VOUT = VS; standby mode Switched-off output current low-side drivers of OUT1-6 VOUT = VS - 0.5 V; active mode IQLL Min. VOUT = VS - 2.5 V with Switched-off output current ECDR = VS; standby mode low-side driver of ECV VOUT = VS - 2.5 V with ECDR = VS; active mode DS11546 Rev 5 -5 A -10 A -5 A -100 A 165 -100 -15 -10 A A 15 A A 39/197 196 Electrical specifications 3.4.11 L99DZ100G, L99DZ100GP Power outputs switching times The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28 V; 6 V VSREG 28 V; Tj = -40 C to 150 C, unless otherwise specified. Table 17. Power outputs switching times Symbol td ON H td OFF H Parameter Output delay time high-side driver on (OUT1,2,3,4,5,6) Output delay time high-side driver on (OUT7,8) Output delay time high-side driver off (OUT1,4,5,6) Output delay time high-side driver off (OUT2,3, 7,8) Test condition VS = 13.5 V; V1 = 5 V; corresponding low-side driver is not active (1)(2)(3) (from CSN 50% to OUT 50%) see Figure 18 VS = 13.5 V; (1)(2)(3) (from V1 = 5 V CSN 50% to OUT 50%) see Figure 18 Min. Typ. Max. Unit 15 40 80 s 20 40 90 s 50 150 300 s 20 70 130 s td ON H Output delay time high-side driver on (OUT9 ...OUT15, OUT_HS) VS/VSREG = 13.5 V; V1 = 5 V; (from CSN 80% to OUT 80%) 30 s td OFF H Output switch off delay time highside driver on (OUT9 ...OUT15, OUT_HS) VS/VSREG = 13.5 V; V1 = 5 V; (from CSN 80% to OUT 20%) 35 s Output delay time low-side driver (OUT1-6, ECV) on VS = 13.5 V; V1 = 5 V; corresponding high-side driver is not active (1)(2)(3) (from CSN 50% to OUT 50%) see Figure 18 td ON L td HL td LH 30 70 s Output delay time low-side driver (OUT1-6) off V1 = 5 V CSN 50% to OUT 50%) see Figure 18 40 150 300 s Output delay time low-side driver (ECV) off VS = 13.5 V; V1 = 5 V (1)(2)(3) (from CSN 50% to OUT 50%) see Figure 18 15 45 110 s 50 200 400 s 0.1 0.2 0.6 V/s td OFF L Cross current protection time (OUT1-6) VS = 13.5 V; (1)(2)(3) (from 15 tcc ONLS_OFFHS - td OFF H(4) tcc ONHS_OFFLS - td OFF L (4) VS = 13.5 V; V1 = 5 V dVOUT/dt Slew rate of OUT1-OUT8, ECV dVmax/dt Maximum external applied slew rate on OUT1-OUT6 without Guaranteed by design switching on the LS and HS (only in Active mode) dVOUT/dt Slew rate of OUT9-OUT15, OUT_HS VS/VSREG = 13.5 V; V1 = 5 V (1)(2)(3) 2 V/s fPWMx(00) PWM switching frequency VS/VSREG = 13.5 V; V1 = 5 V 100 Hz 40/197 (1)(2)(3) DS11546 Rev 5 20 V/s L99DZ100G, L99DZ100GP Electrical specifications Table 17. Power outputs switching times (continued) Symbol Parameter Test condition Min. Typ. Max. Unit fPWMx(01) PWM switching frequency VS/VSREG = 13.5 V; V1 = 5 V 200 Hz fPWMx(10) PWM switching frequency VS/VSREG = 13.5 V; V1 = 5 V 330 Hz fPWMx(11) PWM switching frequency VS/VSREG = 13.5 V; V1 = 5 V 500 Hz 1. RLOAD = 16 at OUT1,6 and OUT7,8 in low on-resistance mode 2. RLOAD = 4 at OUT4,5 3. RLOAD = 128 at OUT2,3,4,9,10,11,12,13,15,15,HS, ECV and OUT7,8 in high on-resistance mode 4. tCC is the switch-on delay time if complement in half bridge has to switch off 3.4.12 Current monitoring The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28 V; 6 V VSREG 28 V; Tj = -40 C to 150 C, unless otherwise specified. Table 18. Current monitoring Symbol Parameter |IOC1|, |IOC6| Test condition VS = 13.5 V; V1 = 5 V; sink and source |IOC2|, |IOC3| Min. Typ. Max. Unit 3 5 A 0.5 1.0 A 7.5 10 A 6 10 A VS = 13.5 V; V1 = 5 V; sink and source; Tj = -40 C to |IOC4| Overcurrent threshold HS & LS 70 C VS = 13.5 V; V1 = 5 V; sink and source; Tj = 130 C |IOC5_1| |IOC5_2| VS = 13.5 V; V1 = 5 V; sink and source |IOC5_3| 3 4 5 A 4.5 6 7.5 A 10 A 7.5 DS11546 Rev 5 41/197 196 Electrical specifications L99DZ100G, L99DZ100GP Table 18. Current monitoring (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Overcurrent threshold HS in low onresistance mode 1.5 2.5 A Overcurrent threshold HS in high on-resistance mode 0.35 0.65 A Overcurrent threshold HS in low onresistance mode 0.7 1.3 A Overcurrent threshold HS in high on-resistance mode 0.35 0.65 A 0.35 0.7 A 0.15 0.3 A Overcurrent threshold HS in high current mode 0.5 1 A Overcurrent threshold HS in low current mode 0.25 0.5 A |IOC11|, |IOC12|, |IOC15|, |IOC_HS| Overcurrent threshold HS in high current mode 0.25 0.5 A Overcurrent threshold HS in low current mode 0.15 0.3 A |IOCECV| output current threshold LS VS = 13.5 V; V1= 5 V; sink 0.5 1.0 A tFOC Filter time of overcurrent signal Duration of overcurrent condition to set the status bit 10 100 s frec0 Recovery frequency for OC; OCR_FREQ (CR 7) = 0 1 4 kHz frec1 Recovery frequency for OC; OCR_FREQ (CR 7) = 1 2 6 kHz tAR Auto recovery time limit |IOC7| |IOC8| |IOC9|, |IOC13|, |IOC14| |IOC10| Overcurrent threshold HS in high current mode Overcurrent threshold to HS in low current mode VS/VSREG = 13.5 V; V1 = 5 V; source OUT1 to OUT6 100 ms OUT7, OUT8, OUT_HS 120 ms |IOLD1|, |IOLD6| |IOLD2|, |IOLD3| Under-current threshold HS & LS VS = 13.5 V; V1 = 5 V; sink and source |IOLD4|, |IOLD5| 42/197 55 DS11546 Rev 5 6 30 80 mA 6 20 30 mA 40 150 300 mA L99DZ100G, L99DZ100GP Electrical specifications Table 18. Current monitoring (continued) Symbol |IOLD7| |IOLD8| IOLD9|, |IOLD13|, |IOLD14| |IOLD10| Parameter Test condition Min. Typ. Max. Unit Under-current threshold HS in low on-resistance mode 15 40 60 mA Under-current threshold HS in high on-resistance mode 5 10 15 mA Under-current threshold HS in low on-resistance mode 10 30 45 mA Under-current threshold HS in high on-resistance mode 5 10 15 mA 6 12 mA 0.5 4 mA Under -current threshold HS in high current mode 10 30 mA Under -current threshold HS in low current mode 0.3 4 mA Under-current threshold HS in high current mode Under-current threshold HS in low current mode VS/VSREG = 13.5 V; V1 = 5 V; source |IOLD11|, |IOLD12|, |IOLD15|, |IOLD_HS| Under -current threshold HS in high current mode 6 12 mA Under -current threshold HS in low current mode 0.85 4 mA |IOLDECV| Under-current threshold LS VS = 13.5 V; V1 = 5 V; sink 6 20 30 mA Filter time of open-load signal Duration of open-load condition to set the status bit 150 200 250 s tOL_out 3.4.13 Heater The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28 V; Tj = -40 C to 150 C, unless otherwise specified. Table 19. Heater Symbol Parameter IGHheater Average charge-current (charge stage) RGLheater On-resistance (dischargestage) VGHheater Test condition Min. Tj = 25 C VSLx = 0 V; IGHx = 50 mA; Tj = 25 C 4 VS = SH= 6 V; ICP = 15 mA VSHheater + 6 VS = SH = 12 V; ICP = 15 mA VSHeahter + 8 DS11546 Rev 5 Max. 0.3 VSLx = 0 V; IGHx = 50 mA; Tj = 130 C Gate-on voltage Typ. Unit A 8 10 11 14 V VSHeater VSHeater + 10 + 11.5 V 43/197 196 Electrical specifications L99DZ100G, L99DZ100GP Table 19. Heater (continued) Symbol Parameter Test condition RGSHeater Passive gate-clamp resistance TG(HL)xHL Propagation delay time high to low (switch mode) Min. Typ. Max. Unit 15 k VS = 13.5 V; VSHx = 0; RG = 0 ; CG = 2.7 nF 1.5 s TG(HL)xLH Propagation delay time low VS = 13.5 V; VSLx = 0; to high (switch mode) RG = 0 ; CG = 2.7 nF 1.5 s t0GHheaterr Rise time (switch mode) VS = 13.5 V; VSheater = 0; RG = 0 ; CG = 2.7 nF 45 ns t0GHheaterf Fall time (switch mode) VS = 13.5 V; VSheater = 0; RG = 0 ; CG = 2.7 nF 85 ns 3.4.14 H-bridge driver The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28 V; 6 V VSREG 28 V; Tj = -40C to 150 C, unless otherwise specified. Table 20. H-bridge driver Symbol Parameter Test condition Min. Typ. Max. Unit Drivers for external high-side PowerMOS IGHx(Ch) RGHx Average charge current (charge stage) Tj = 25 C On-resistance (dischargestage) VGHHx Gate-on voltage RGSHx Passive gate-clamp resistance VSHx = 0 V; IGHx = 50 mA; Tj = 25 C 0.3 6 VSHx = 0 V; IGHx = 50 mA; Tj = 130 C VS = SH = 6 V; ICP = 15 mA VSHx + 6 VS = SH = 12 V; ICP = 15 mA VSHx + 8 VGHx = 0.5 V A 10 14 14 20 V VSHx + 10 VSHx + 11.5 V 15 k 0.3 A Drivers for external low-side Power-MOS IGLx(Ch) RGLx Average charge-current (charge stage) On-resistance (dischargestage) VGHLx Gate-on voltage RGSLx Passive gate-clamp resistance 44/197 Tj = 25 C VSLx = 0 V; IGHx = 50 mA; Tj = 25 C 6 VSLx = 0 V; IGHx = 50 mA; Tj = 130 C VS = 6 V; ICP = 15 mA VSLx + 6 VS = 12 V; ICP = 15 mA VSLx + 8 10 14 14 20 V VSLx + 10 VSLx + 11.5 15 DS11546 Rev 5 V k L99DZ100G, L99DZ100GP 3.4.15 Electrical specifications Gate drivers for the external Power-MOS switching times The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28 V; 6 V VSREG 28 V; Tj = -40 C to 150 C, unless otherwise specified. Table 21. Gate drivers for the external Power-MOS switching times Symbol Parameter Test condition Min. Typ. Max. Unit TG(HL)xHL Propagation delay time high to low (switch mode(1) VS = 13.5 V; VSHx = 0; RG = 0 ; CG = 2.7 nF 1.5 s TG(HL)xLH Propagation delay time low to high (switch mode)(1) VS = 13.5 V; VSLx = 0; RG = 0 ; CG = 2.7 nF 1.5 s IGHxrmax Maximum source current (current mode) VS = 13.5 V; VSHx = 0; VGHx = 1 V; SLEW<4:0> = 1 FH 32 mA IGHxfmax Maximum sink current (current mode) VS = 13.5 V, VSHx = 0; VGHx = 2 V; SLEW<4:0> = 1 FH 32 mA dIIGHxr Source current accuracy VS = 13.5 V; VSHx = 0; VGHx = 1 V See Figure 12: IGHxr ranges dIIGHxf Sink current accuracy VS = 13.5 V; VSHx = 0; VGHx = 2 V See Figure 13: IGHxf ranges Switching voltage (VS-VSH) VDSHxrSW between current mode and switch mode (rising) VS = 13.5 V 2.8 V Switching voltage (VS-VSH) VDSHxfSW between switch mode and current mode (falling) VS = 13.5 V 2.8 V t0GHxr Rise time (switch mode) VS = 13.5 V; VSHx = 0; RG = 0 ; CG = 2.7 nF 45 ns t0GHxf Fall time (switch mode) VS = 13.5 V; VSHx = 0; RG = 0 ; CG = 2.7 nF 85 ns t0GLxr Rise time VS = 13.5 V; VSLx = 0; RG = 0 ; CG = 2.7 nF 45 ns t0GLxf Fall time VS = 13.5 V; VSLx = 0; RG = 0 ; CG = 2.7 nF 85 ns tccp0001 Programmable cross-current protection time 500 ns tccp0010 Programmable cross-current protection time 750 ns tccp0011 Programmable cross-current protection time 1000 ns tccp0100 Programmable cross-current protection time 1250 ns tccp0101 Programmable cross-current protection time 1500 ns DS11546 Rev 5 45/197 196 Electrical specifications L99DZ100G, L99DZ100GP Table 21. Gate drivers for the external Power-MOS switching times (continued) Symbol Parameter Test condition Min. Typ. Max. Unit tccp0110 Programmable cross-current protection time 1750 ns tccp0111 Programmable cross-current protection time 2000 ns tccp1000 Programmable cross-current protection time 2250 ns tccp1001 Programmable cross-current protection time 2500 ns tccp1010 Programmable cross-current protection time 2750 ns tccp1011 Programmable cross-current protection time 3000 ns tccp1100 Programmable cross-current protection time 3250 ns tccp1101 Programmable cross-current protection time 3500 ns tccp1110 Programmable cross-current protection time 3750 ns tccp1111 Programmable cross-current protection time 4000 ns fPWMH PWMH switching frequency(1) VS = 13.5 V; VSLx = 0; RG = 0 ; CG = 2.7 nF; PWMH-Duty-Cycle = 50% 1. Without cross-current protection time tCCP. 46/197 DS11546 Rev 5 50 kHz L99DZ100G, L99DZ100GP Electrical specifications Figure 11. H-driver delay times 7*+/ [/+ 7*+/ [+/ 9 &613:0+',5 W 9&613:0+',5 W 9 *6+/ [ W *$3*&)7 Figure 12. IGHxr ranges ,*+[U DFFXUDF\ ,*+[U0D[ ,*+[U7\S ,*+[U0LQ 'DWDLQSXW ("1($'5 DS11546 Rev 5 47/197 196 Electrical specifications L99DZ100G, L99DZ100GP Figure 13. IGHxf ranges ,*+[I DFFXUDF\ ,*+[I0D[ ,*+[I7\S ,*+[I0LQ 'DWDLQSXW 3.4.16 ("1($'5 Drain source monitoring external H-bridge The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28 V; 6 V VSREG 28 V; Tj = -40C to 150 C, unless otherwise specified. Table 22. Drain source monitoring external H-bridge Symbol Parameter Test condition Min. Typ. Max. Unit VSCd1_HB Drain-source threshold voltage 0.375 0,5 0.625 V VSCd2_HB Drain-source threshold voltage 0.6 0,75 0.9 V VSCd3_HB Drain-source threshold voltage 0,85 1 1,15 V VSCd4_HB Drain-source threshold voltage 1,06 1,25 1,43 V VSCd5_HB Drain-source threshold voltage 1,27 1,5 1,73 V VSCd6_HB Drain-source threshold voltage 1,49 1,75 2,01 V VSCd7_HB Drain-source threshold voltage 1,7 2 2,3 V tSCd_HB Drain-source monitor filter time tscs_HB Drain-source comparator settling time 48/197 6 VS = 13.5 V; VSH = jump from GND to VS DS11546 Rev 5 s 5 s L99DZ100G, L99DZ100GP 3.4.17 Electrical specifications Drain source monitoring external heater MOSFET The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28 V; 6 V VSREG 28 V; Tj = -40 C to 150 C, unless otherwise specified. Table 23. Drain source monitoring external heater MOSFET Symbol Parameter Test condition Min. Typ. Max. Unit VSCd1_HE Drain-source threshold voltage 160 200 250 mV VSCd2_HE Drain-source threshold voltage 200 250 305 mV VSCd3_HE Drain-source threshold voltage 240 300 360 mV VSCd4_HE Drain-source threshold voltage 280 350 420 mV VSCd5_HE Drain-source threshold voltage 320 400 480 mV VSCd6_HE Drain-source threshold voltage 360 450 540 mV VSCd7_HE Drain-source threshold voltage 400 500 600 mV VSCd8_HE Drain-source threshold voltage 440 550 660 mV tSCd_HE Drain-source monitor filter time tscs_HE Drain-source comparator settling time tscbl_HE Drain-source monitoring blanking time 3.4.18 6 VS = 13.5 V; VSH = jump from GND to VS s 5 8 s s Open-load monitoring external H-bridge The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28 V; 6 V VSREG 28 V; Tj = -40 C to 150 C, unless otherwise specified. Table 24. Open-load monitoring external H-bridge Symbol Parameter Test condition Min. Typ. Max. Unit VODSL Low-side drain-source monitor low off-threshold voltage VSLx = 0 V; VS = 13.5 V 0.15 VS V VODSH Low-side drain-source monitor high off-threshold voltage VSLx = 0 V; VS = 13.5 V 0.85 VS V VOLSHx Output voltage of selected SHx in open-load test mode VSLx = 0 V; VS = 13.5 V 0.5 VS V RpdOL Pull-down resistance of the nonVSLx = 0 V; VS = 13.5 V; selected SHx pin in open-load mode VSHX = 4.5 V 20 k tOL_HB Open-load filter time 2 ms DS11546 Rev 5 49/197 196 Electrical specifications 3.4.19 L99DZ100G, L99DZ100GP Open-load monitoring external heater MOSFET The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V VS 28 V; 6 V VSREG 28 V; Tj = -40 C to 150 C, unless otherwise specified. Table 25. Open-load monitoring external heater MOSFET Symbol Parameter Test condition Min. Typ. Max. Unit VOLheater Open-load -threshold voltage VSLx = 0 V; VS = 13.5 V 2 V IOLheater Pull-up current source open-load diagnosis activated VSLx = 0 V; VS = 13.5 V; VSHheater = 4.5 V 1 mA 2 ms tOL_HE 3.4.20 Open-load filter time Electro-chrome mirror driver The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V VS 28V; 6V VSREG 28V; Tj = -40 C to 150 C, unless otherwise specified. Table 26. Electro-chrome mirror driver Symbol Parameter Test condition ECV_HV (Config Reg) = 1 VCTRLmax Maximum EC-control voltage (1) ECV_HV (Config Reg) = 0 (1) Min. Typ. Max. Unit 1.4 1.6 V 1.12 1.28 V -2 2 -5% 1LSB(2) +5% + 1LSB(2) LSB DNLECV Differential Non Linearity IdVECVI Voltage deviation between target and ECV dVECVnr Difference voltage between dVECV = Vtarget(3) - VECV; target and ECV sets flag if toggle bitx = 1; status reg. x VECV is below it 120 mV dVECVhi Difference voltage between dVECV = Vtarget(3) - VECV; target and ECV sets flag if toggle bitx = 1; status reg. x VECV is above it -180 mV tFECVNR ECVNR filter time 32 s tFECVHI ECVHI filter time 32 s VECDRminHIGH VECDRmaxLOW 50/197 Output voltage range dVECV = Vtarget(3) - VECV; IIECDRI < 1 A (2) mV IECDR = -10 A V1 0.3 V V1 V IECDR = 10 A 0 0.7 V DS11546 Rev 5 L99DZ100G, L99DZ100GP Electrical specifications Table 26. Electro-chrome mirror driver (continued) Symbol Parameter Test condition Vtarget(3) > IECDR Recdrdis Current into ECDR Pull-down resistance at ECDR in fast discharge mode and while EC-mode is off Min. Typ. Max. Unit VECV + 500 mV; VECDR = 3.5 V -100 -10 A Vtarget(3) < VECV - 500 mV; VECDR = 1.0 V; Vtarget = 0 V; VECV = 0.5 V 10 100 A 10 k VECDR = 0.7 V; ECON = `1', EC<5:0> = 0 or ECON = `0' 1. Bit ECV_HV (Config Reg) ='1' or `0': ECV voltage, where IIECDR can change sign. 2. 1 LSB (Least Significant Bit) = 23.8 mV typ 3. Vtarget is set by bits EC<5:0> (CR 11) and bit ECV_HV (Config Reg); tested for each individual bit. 3.4.21 Fail safe low-side switch The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V VS 18 V; Tj = 40 C to 150 C, unless otherwise specified. Table 27. Fail safe low-side switch Symbol VOUT_max Parameter Max output voltage in case of missing supply RDSON DC output resistance IOLimit Overcurrent limitation tONHL Test condition Min. IOUT = 1 mA; VS = VSREG = 0 V ILOAD = 250 mA; Tj = 25 C Typ. Max. Unit 2 2.5 V 1.4 ILOAD = 250 mA; Tj = 130 C 2.2 1500 mA Turn on delay time to 10% VOUT 100 s tOFFLH Turn off delay time to 90% VOUT 100 s tSCF Short circuit filter time dVmax/dt 8 V < VS < 16 V 500 64 Maximum external applied slew rate on Guaranteed by design LS1_FSO and LS2_FSO without switching on LS DS11546 Rev 5 60 s V/s 51/197 196 Electrical specifications 3.4.22 L99DZ100G, L99DZ100GP Wake up input WU The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V VSREG 28 V; Tj = 40 C to 150 C, unless otherwise specified. Table 28. Wake-up inputs Symbol Parameter VWUthn Min. Typ. Max. Unit Wake-up negative edge threshold voltage 0.4 VSREG 0.45 VSREG 0.5 VSREG V VWUthp Wake-up positive edge threshold voltage 0.5 VSREG 0.55 VSREG 0.6 VSREG V VHYST Hysteresis 0.05 VSREG 0.1 VSREG 0.15 VSREG V tWU_stat Static wake filter time IWU_stdby Input current in standby mode RWU_act Input resistor to GND in Active mode and in Standby mode during Wake-up input sensing tWU_cyc Cyclic wake filter time 3.4.23 Test condition 64 VWU < 1 V or VWU > (VSREG - 1.5 V) s 5 30 60 A 80 160 300 k 16 s High speed CAN transceiver ISO 11898-2:2003 and ISO 11898-5:2007 compliant. SAE J2284 compliant. Selective wake functionality according to ISO 11898-6:2013. The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 5.5 V VSREG 18 V; VCANSUP = V1; Tjunction = -40 C to 150 C, unless otherwise specified. -12 V (VCANH + VCANL) / 2 12 V Table 29. CAN communication operating range Symbol Parameter Test condition VSREG_COM Supply voltage operating range for CAN communication VCANSUPlow CAN supply low voltage flag VV1 = VCANSUP decreasing VCANHL,CM Common mode Bus voltage 52/197 VV1 = VCANSUP Measured with respect to the ground of each CAN node DS11546 Rev 5 Min. Typ. 5.5 4.5 -12 4.65 Max. Unit 18 V 4.8 V 12 V L99DZ100G, L99DZ100GP Electrical specifications Table 30. CAN transmit data input: pin TxDC Symbol Parameter Test condition Min. Typ. Max. Unit VTXDCLOW Input voltage dominant level 1.0 1.45 2.0 V VTXDCHIGH Input voltage recessive level 1.2 1.85 2.3 V VTXDCHYS VTXDCHIGH-VTXDCLOW 0.2 0.4 0.7 V RTXDCPU TXDC pull up resistor 16 35 60 k TXDC - CANH,L delay td,TXDC(dom-rec) time dominant recessive RL = 60 ; CL = 100 pF; 70 % VRXD - 30% VDIFF; TXDC rise time = 10 ns (10% - 90%)(1) 0 120 ns TXDC - CANH,L delay time recessive dominant RL = 60 ; CL = 100 pF; 30 % VRXD - 70% VDIFF; TXDC fall time = 10 ns (90% - 10%)(1) 0 120 ns 5 ms td,TXDC(rec-diff) tdom(TXDC) TXDC dominant time-out 0.8 2 1. Guaranteed by design. Table 31. CAN receive data output: Pin RxDC Symbol Parameter Test condition Min. Typ. Max. Unit 0 0.2 0.5 V V1 V VRXDCLOW Output voltage dominant level IRXDC = 2 mA VRXDCHIGH Output voltage recessive level IRXDC = -2 mA tr,RXDC RXDC rise time CL = 15 pF; 30% - 70% VRXDC(1) 0 25 ns tf,RXDC RXDC fall time CL = 15 pF; 70% - 30% VRXDC(1) 0 25 ns td,RXDC(dom-rec) CANH,L - RXDC delay time dominant - recessive CL = 15 pF; 30% VDIFF - 70% VRXDC(1) 0 120 ns td,RXDC(rec - dom) CANH,L - RXDC delay time recessive - dominant CL = 15 pF; 70% VDIFF - 30% VRXDC(1) 0 120 ns V1 - 0.5 V1 - 0.2 1. Guaranteed by design. Table 32. CAN transmitter dominant output characteristics Symbol Parameter VCANHdom Single ended CANH voltage level in dominant state VCANLdom VDIFF,dom Test condition Min. Typ. VTXDC = VTXDCLOW; RL = 50 ; 65 2.75 3.5 4.5 V Single ended CANL voltage level in dominant state VTXDC = VTXDCLOW; RL = 50 ; 65 0.5 1.5 2.25 V Differential output voltage in dominant state: VCANHdomVCANLdom VTXDC = VTXDCLOW; RL = 50 ; 65 1.5 2.0 3 V DS11546 Rev 5 Max. Unit 53/197 196 Electrical specifications L99DZ100G, L99DZ100GP Table 32. CAN transmitter dominant output characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit 4.5 5 5.5 V -100 -75 -45 mA 75 100 mA Driver symmetry VSYM = VCANHdom + VCANLdom Measured over one 250 kHz period (4 s) RL = 50 ; 65 ; fTXDC = 250 kHz (square wave, 50% duty cycle); (1) CSPLIT = 4.7 nF (+-5%) IOCANH,dom (0V) CANH output current in dominant state VTXDC = VTXDCLOW; VCANH = 0 V IOCANL,dom (5V) CANL output current in dominant state VTXDC = VTXDCLOW; VCANL = 5 V 45 IOCANH,dom (40V) CANH output current in dominant state VTXDC = VTXDCLOW; VCANH = 40 V; RL = 65 ; VS = 40 V 0 5 mA IOCANL,dom (40V) CANL output current in dominant state VTXDC = VTXDCLOW; VCANL = 40 V; RL = 65 ; VS = 40 V 0 100 mA VSYM 1. Measurement equipment input load <20 pF, >1 M. Table 33. CAN transmitter recessive output characteristics, CAN normal mode Symbol Parameter Test condition Min. Typ. Max. Unit VCANHrec CANH voltage level in recessive state TRX ready state; VTXDC = VTXDCHIGH; No load 2 2.5 3 V VCANLrec CANL voltage level in recessive state TRX Ready state; VTXDC = VTXDCHiGH; No load 2 2.5 3 V 50 mV Differential output TRX Ready state; voltage in recessive state VTXDC = VTXDCHIGH; No load VCANHrec-VCANLrec VDIFF,recOUT Note: -50 CAN normal mode: tested in TRX ready state while the device is in active mode. Table 34. CAN transmitter recessive output characteristics, CAN low-power mode, biasing active Symbol Parameter Test condition Min. Typ. Max. Unit VCANHrecLPbias CANH voltage level in recessive state TRX BIAS state; VTXDC = VTXDCHIGH; No load 2 2.5 3 V VCANLrecLPbias CANL voltage level in recessive state TRX BIAS state; VTXDC = VTXDCHiGH; No load 2 2.5 3 V 50 mV Differential output voltage TRX BIAS state; VDIFF,recOUTLPbias in recessive state VTXDC = VTXDCHIGH; No load VCANHrec-VCANLrec Note: 54/197 -50 CAN low power mode, biasing active: tested in TRX BIAS state while the device is in active mode, V1 Standby mode and Vbat_standby mode DS11546 Rev 5 L99DZ100G, L99DZ100GP Electrical specifications Table 35. CAN transmitter recessive output characteristics, CAN low-power mode, biasing inactive Symbol Parameter Test condition Min. Typ. Max. Unit VCANHrecLP CANH voltage level in recessive state TRX Sleep state; VTXDC = VTXDCHIGH; No load -0.1 0 0.1 V VCANLrecLP CANL voltage level in recessive state TRX Sleep state; VTXDC = VTXDCHIGH; No load -0.1 0 0.1 V Differential output voltage TRX Sleep state; in recessive state VTXDC = VTXDCHIGH; No load VCANHrec -VCANLrec -50 50 mV VDIFF,recOUTLP Note: CAN Low Power mode, biasing inactive: tested in TRX sleep state while the device is in active mode, V1 Standby mode and Vbat_standby mode. Table 36. CAN receiver input characteristics during CAN normal mode Symbol Parameter VTHdom Differential receiver threshold voltage recessive to dominant state VTHrec Differential receiver threshold voltage dominant to recessive state Test condition Min. Typ. Max. Unit TRX ready state; (VCANH + VCANL) / 2 = -12 V, 2.5 V, 12 V (1) 0.5 -- 0.9 V TRX Ready state; (VCANH + VCANL) / 2 = -12 V, 2.5 V, 12 V (1) 0.5 -- 0.9 V 1. Parameter evaluated with specific RL = 60 ; guaranteed by characterization. Note: CAN normal mode: tested in TRX ready state while the device is in active mode. Table 37. CAN receiver input characteristics during CAN low power mode, biasing active Symbol Parameter Test condition Min. Typ. Max. Unit VTHdomLPbias Differential receiver threshold TRX BIAS state; voltage recessive to (VCANH + VCANL) / 2 = -12 V, 2.5 V, 12 V(1) dominant state 0.5 -- 0.9 V VTHrecLPbias Differential receiver threshold TRX BIAS state; voltage dominant to (VCANH + VCANL) / 2 = -12 V, 2.5 V, 12 V(1) recessive state 0.5 -- 0.9 V 1. Parameter evaluated with specific RL = 60 ; guaranteed by characterization. Note: CAN low power mode, biasing active: tested in TRX BIAS state while the device is in active mode, V1 Standby mode and Vbat_standby mode. DS11546 Rev 5 55/197 196 Electrical specifications L99DZ100G, L99DZ100GP Table 38. CAN Receiver input characteristics during CAN Low power mode, biasing inactive Symbol Parameter Test condition Min. Typ. Max. Unit VTHdomLP Differential receiver threshold voltage recessive to dominant state TRX sleep state; (VCANH + VCANL) / 2 = -12 V; 0 V; 12 V(1) 0.5 -- 0.9 V VTHrecLP Differential receiver threshold voltage dominant to recessive state TRX Sleep state; (VCANH + VCANL) / 2 = -12 V; 0 V; 12 V(1) 0.5 -- 0.9 V 1. Parameter evaluated with specific RL = 60 ; guaranteed by characterization. Note: CAN Low Power mode, biasing inactive: Tested in TRX Sleep state while the device is in active mode, V1 Standby mode and Vbat_standby mode. Table 39. CAN receiver input resistance biasing active Symbol Parameter Min. Typ. Max. Unit TRX Ready & TRX BIAS states; VTXDC = VTXDCHIGH; no load 40 60 100 k RCANH, CANL Single ended Internal TRX Ready & TRX BIAS states; resistance VTXDC = VTXDCHIGH; no load 20 30 50 k mR TRX Ready & TRX BIAS states; Internal Resistance VTXDC = VTXDCHIGH; no load; matching RCANH,CANL mR = 2 x (RCAN_H - RCAN_L) / (RCAN_H + RCAN_L) -0.03 Cin Internal capacitance Guaranteed by design 20 35 pF Cin,diff Differential internal capacitance Guaranteed by design 10 20 pF Differential internal resistance Rdiff Note: Test condition 0.03 CAN Normal and Low Power mode, biasing active: Tested in TRX Ready and TRX BIAS state while the device is in active and V1 Standby mode. Table 40. CAN transceiver delay Symbol Parameter Test condition Min. Typ. Max. Unit tTXpd,hl Loop delay TXDC to RXDC (High to Low) RL = 60 ; CL = 100 pF; 30% VTXDC - 30% VRXDC; TXDC fall time = 10 ns (90% - 10%); CRXDC = 15 pF; fTXDC = 250 kHz 255 ns tTXpd,lh Loop delay TXDC to RXDC (Low to High) RL = 60; CL = 100pF; 70% VTXD - 70% VRXD; TXDC rise time = 10 ns (10% - 90%); CRXDC = 15 pF; fTXDC = 250 kHz 255 ns 56/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Electrical specifications Table 40. CAN transceiver delay (continued) Symbol Parameter Recessive Bit symmetry TBitrec Test condition Min. Typ. Max. Unit RL = 60 ; CL = 100 pF; 70% VTXDC (rising) - 30% VRXDC (falling); CRXD = 15 pF; 10 ns (10% 90%, 90% - 10%); Rectangular pulse signal TTXDC = 6000 ns, high pulse 1000 ns, low pulse 5000 ns 765 1000 1255 ns 500 700 1000 s CAN permanent dominant time-out tCAN tWUP-V1(1) Time between WUP(2) Wake-Up according to ISO11898on the CAN bus until 5:2007 (Bit SWEN = 0); V1 goes active 70% VDIFF - 90% V1(min) 0 200 s (1) Time between WUF(3) Wake-Up according to ISO11898on the CAN bus until 6:2013 (Bit SWEN = 1); V1 goes active 30% VDIFF - 90% V1(min) 0 200 s tWUF-V1 1. Guaranteed by characterization. 2. Time starts with the end of last dominant phase of the WUP. 3. Time starts with the end of CRC delimiter of the WUF. Table 41. Maximum leakage currents on CAN_H and CAN_L, unpowered Symbol Parameter Test condition Min. Unpowered device; VCANH = 5 V; VCANL = 5 V; VSREG, VCANSUP connected via 0 to GND; VSREG, VCANSUP Input leakage current ILeakage, CANH connected via 47 k to GND(1) CANH Tj = -40 C to 105 C(2) Tj = 130 C(3) Unpowered device; VCANH = 5 V; VCANL = 5 V; VSREG, VCANSUP connected Input leakage current via 0 to GND; VSREG, VCANSUP connected ILeakage, CANL via 47 k to GND(1) CANL Tj = -40 C to 105 C(2) Tj = 130 C(3) Typ. Max. Unit A -10 -12 10 12 -10 -12 10 12 A 1. Guaranteed by design. 2. 105C is the maximum junction temperature of an unpowered device according to this test condition within the specified ambient temperature range 3. Used for device test only. Table 42. Biasing control timings Symbol Parameter Test condition Min. tfilter CAN activity filter time 0.5 twake Wake-up time out 0.5 DS11546 Rev 5 Typ. 1 Max. Unit 5 s 5 ms 57/197 196 Electrical specifications L99DZ100G, L99DZ100GP Table 42. Biasing control timings (continued) Symbol tSilence tBIAS Parameter Test condition CAN timeout RL = 50 , 65 ; CL = 100 pF; CGND (= CSPLIT) = 100 pF; VTXDC = VTXDCLOW; 50% VDIFF - VCANH = VCANL = VCAN(H,L)rec(min)(1); Transition TRX Sleep to TRX BIAS in Active, V1-Standby and Vbat_standby modes Bias reaction time Min. Typ. Max. Unit 600 700 1200 ms 200 s 0 1. A wake-up-pattern is sent with a bit length of tfilter. TBIAS is measured from the rising edge after having released the bus at the end of the 2nd dominant bit until CANH and CANL reach the minimum recessive output voltage (VCANHrec, VCANHrec). 3.4.24 LIN transceiver LIN 2.2 compliant for bit-rates up to 20 kBit/s SAE J2602 compatible. The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V VSREG 18 V; Tjunction = -40 C to 150C unless otherwise specified. Table 43. LIN transmit data input: pin TxD Symbol Parameter Test condition Min. VTXDLOW Input voltage dominant level Active mode VTXDHIGH Input voltage recessive level Active mode VTXDHYS VTXDHIGH-VTXDLOW Active mode 0.2 RTXDPU TXD pull up resistor Active mode 13 Typ. Max. 1.0 Unit V 2.3 V V 29 46 k Typ. Max. Unit 0.2 0.5 V Table 44. LIN receive data output: pin RxD Symbol Parameter Test condition VRXDLOW Output voltage dominant level Active mode VRXDHIGH Output voltage recessive level Active mode Min. V1-0.5 V1-0.2 V Table 45. LIN transmitter and receiver: pin LIN Symbol Parameter VTHdom Receiver threshold voltage recessive to dominant state VBusdom Receiver dominant state Test condition Min. Typ. Max. Unit 0.4 VSREG 0.45 VSREG 0.5 VSREG V 0.4VSRE G VTHrec Receiver threshold voltage dominant to recessive state 0.5 VSREG VBusrec Receiver recessive state 0.6 VSREG 58/197 DS11546 Rev 5 0.55 VSREG 0.6 VSREG V V V L99DZ100G, L99DZ100GP Electrical specifications Table 45. LIN transmitter and receiver: pin LIN (continued) Symbol Parameter Test condition Min. Typ. Max. Unit VTHhys Receiver threshold hysteresis: VTHrec -VTHdom 0.07 VSREG 0.1 VSREG 0.175 VSREG V VTHcnt Receiver tolerance center value: (VTHrec +VTHdom)/2 0.475 VSREG 0.5 VSREG 0.525 VSREG V VTHwkup Activation threshold for wake-up comparator 1.0 1.5 2 V VTHwkdwn Activation threshold for wake-up comparator VSREG 3.5 VSREG 2.5 VSREG1.5 V tLINBUS LIN Bus Wake-up Dominant Sleep mode; edge: rec-dom Filter time tdom_LIN LIN Bus Wake-up Dominant Sleep mode; edge: rec-domFilter time rec 28 Transmitter input current limit in dominant state 40 ILINDomSC VTXD = VTXDLOW; VLIN = VBATMAX = 18 V Ibus_PAS_dom Input leakage current at the VTXD = VTXDHIGH; VLIN = 0 V; receiver incl. pull-up resistor VBAT = 12 V; Slave mode Ibus_PAS_rec Transmitter input current in recessive state In standby modes; VTXD = VTXDHIGH; VLIN > 8 V; VBAT < 18 V; VLIN VBAT Ibus_NO_GND Input current if loss of GND at device GND = VSREG; 0 V < VLIN < 18 V; VBAT = 12 V Ibus Input current if loss of VBAT at device s s 100 180 mA -1 mA 20 A 1 mA GND = VS; 0 V < VLIN < 18 V Tj=-40 C ....105 C(1) 30 A GND = VS; 0 V < VLIN < 18 V Tj = 130C(2) 35 A 1.2 V VLINdom LIN voltage level in dominant state Active mode; VTXD = VTXDLOW RBus=500 Ohm VLINrec LIN voltage level in recessive state Active mode; VTXD = VTXDHIGH; ILIN = 10 A RLINup LIN output pull up resistor VLIN = 0 V CLIN 64 LIN input capacitance -1 0.8*VS 20 V 40 60 k 30 pF 1. 105C is the maximum junction temperature of an unpowered device according to this test condition within the specified ambient temperature range. 2. Used for device test only. DS11546 Rev 5 59/197 196 Electrical specifications L99DZ100G, L99DZ100GP The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V < VS < 28V; Tj = -40 C to 150 C, unless otherwise specified. Table 46. LIN transceiver timing Symbol tRXpd tRXpd_sym D1 D2 D3 D4 Parameter Test condition Min. Receiver propagation delay time tRXpd = max(tRXpdr, tRXpdf); tRXpdf = t(0.5 VRXD)-t(0.45 VLIN); tRXpdr = t(0.5 VRXD)-t(0.55 VLIN); VSREG = 12 V; CRXD=20 pF; Rbus = 1 k, Cbus = 1 nF; Rbus = 660 , Cbus = 6.8 nF; Rbus = 500 , Cbus = 10 nF Symmetry of receiver propagation delay time (rising vs. falling edge) tRXpd_sym = tRXpdr - tRXpdf; VSRE = 12 V; Rbus = 1 k; Cbus = 1 nF; CRXD = 20 pF -2 Duty Cycle 1 THRec(max) = 0.744 * VSREG; THDom(max) = 0.581 * VSREG; VSREG = 7 to 18 V, tbit = 50 s; D1 = tbus_rec(min) / (2 x tbit); Rbus = 1 k, Cbus = 1 nF; Rbus = 660 , Cbus = 6.8 nF; Rbus = 500 , Cbus = 10 nF 0.396 Duty Cycle 2 THRec(min) = 0.422* VSREG; THDom(min) = 0.284* VSREG; VSREG = 7.6 to 18 V, tbit = 50 s; D2 = tbus_rec(max) / (2 x tbit); Rbus = 1 k, Cbus = 1 nF; Rbus = 660 , Cbus = 6.8 nF; Rbus = 500 , Cbus = 10 nF Duty Cycle 3 THRec(max) = 0.778* VSREG; THDom(max) = 0.616* VSREG; VSREG = 7 to 18 V, tbit = 96 s; D3 = tbus_rec(min) / (2 x tbit); Rbus = 1 k, Cbus = 1 nF; Rbus = 660 , Cbus = 6.8 nF; Rbus = 500 , Cbus = 10 nF Duty Cycle 4 THRec(min) = 0.389* VSREG; THDom(min) = 0.251* VSREG; VSREG = 7.6 to 18 V, tbit = 96 s; D4 = tbus_rec(max) / (2 x tbit); Rbus = 1 k, Cbus = 1 nF; Rbus = 660 , Cbus = 6.8 nF; Rbus = 500 , Cbus = 10 nF Typ. Max. Unit 6 s 2 s 0.581 0.417 0.590 TXDL dominant timeout 12 ms tLIN LIN permanent recessive time-out 40 s tdom(bus) LIN Bus permanent dominant time-out 12 ms tdom(TXDL) 60/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Electrical specifications Figure 14. LIN transmit, receive timing W 7;SGI W 7;SGU 9 7[' WLPH 9 /,1UHF 9 7+UHF 9 /,1 9 7+GRP 9 /,1GRP WLPH 9 5[' WLPH W 5;SGI W 5;SGU *$3*&)7 3.4.25 SPI The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V < VSREG < 18 V; V1 = 5 V; all outputs open; Tj = -40 C to 150 C, unless otherwise specified. Table 47. Input: CSN Symbol Parameter Test condition Min. Typ. VCSNLOW Input voltage low level Normal mode VCSNHIGH Input voltage high level Normal mode VCSNHYS VCSNHIGH - VCSNLOW Normal mode 0.2 ICSNPU CSN Pull up resistor Normal mode 13 29 Min. Typ. Max. 1.0 Unit V 2.3 V V 46 k Max. Unit Table 48. Inputs: CLK, DI Symbol tset Parameter Test condition Delay time from standby Time until SPI, ADC and to Active mode OUT15/OUT_HS are operative 10 Delay time from standby Time until power stages that are to Active mode supplied by the CP are operative 560 Vin_L Input low level 1.0 Vin_H Input high level tset_CP Pull down current at input 960 0.2 Vin = 1.5 V DS11546 Rev 5 5 s V 2.3 Vin_Hyst Input hysteresis Ipdin 750 s V V 30 60 A 61/197 196 Electrical specifications L99DZ100G, L99DZ100GP Table 48. Inputs: CLK, DI (continued) Symbol Parameter Test condition Cin(1) Input capacitance at input CSN, CLK, DI and PWM1,2 fCLK SPI input frequency at CLK Min. Typ. Guaranteed by design Max. Unit 15 pF 4 MHz Max. Unit 1. Value of input capacity is not measured in production test. Parameter guaranteed by design. Table 49. DI, CLK and CSN timing Symbol Note: Parameter Test condition Min. Typ. tCLK Clock period 250 ns tCLKH Clock high time 100 ns tCLKL Clock low time 100 ns tset_CSN CSN setup time, CSN low before rising edge of CLK 150 ns tset_CLK CLK setup time, CLK high before rising edge of CSN 150 ns tset_DI DI setup time 25 ns thold_DI DI hold time 25 ns tr_in Rise time of input signal DI, CLK, CSN 25 ns tf_in Fall time of input signal DI, CLK, CSN 25 ns Max. Unit 0.5 V See Figure 16: SPI input timing. Table 50. Output: DO Symbol Parameter Test condition VDOL Output low level IDO = -4 mA VDOH Output high level IDO = 4 mA IDOLK 3-state leakage current VCSN = V1, 0 V < VDO < V1 CDO 3-state input capacitance Guaranteed by design Min. Typ. V1 - 0.5 V -10 10 A 10 15 pF Typ. Max. Unit Table 51. DO timing Symbol 62/197 Parameter Test condition Min. tr DO DO rise time CL = 50 pF; ILOAD = -1 mA 25 ns tf DO DO fall time CL = 50 pF; ILOAD = -1 mA 25 ns DS11546 Rev 5 L99DZ100G, L99DZ100GP Electrical specifications Table 51. DO timing (continued) Symbol Test condition Min. Typ. Max. Unit ten DO tri L DO enable time from 3-state to low level CL = 50 pF; ILOAD = -1 mA; pull-up load to V1 50 100 ns tdis DO L tri DO disable time from low level to 3-state CL = 50 pF; ILOAD = -1 mA; pull-up load to V1 50 100 ns ten DO tri H DO enable time from 3-state to high level CL = 50 pF; ILOAD = -1 mA; pull-down load to GND 50 100 ns tdis DO H tri DO disable time from high level to 3-state CL = 50 pF; ILOAD = -1 mA; pull-down load to GND 50 100 ns DO delay time VDO < 0.3 V1; VDO > 0.7 V1; CL = 50 pF 30 60 ns Typ. Max. Unit td DO Note: Parameter See Figure 17: SPI output timing. Table 52. CSN timing Symbol Parameter tCSN_HI,min Minimum CSN High time, active mode tCSNfail CSN low timeout Test condition Transfer of SPI-command to Input Register Min. 6 s 20 Note: See Figure 18: SPI CSN - output timing. 3.4.26 Inputs TxD_C and TxD_L for Flash mode 35 50 ms The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V VSREG 18; V1 = 5 V; Tj = -40 C to 150 C. Table 53. Inputs: TxD_C and TxD_L for Flash mode Symbol Parameter Test condition Min. Typ. Max. Unit VflashL Input low level (VTXDC/L for exit from Flash mode) 6.1 7.25 8.4 V VflashH Input high level (VTXDC/L for transition into Flash mode) 7.4 8.4 9.4 V Input voltage hysteresis 0.6 0.8 1.0 V VflashHYS DS11546 Rev 5 63/197 196 Electrical specifications 3.4.27 L99DZ100G, L99DZ100GP Inputs DIRH, PWMH The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V VSREG 18 V; Tj = -40 C to 150 C. Table 54. Inputs DIRH, PWMH Symbol Test condition Min. VIL Input voltage low level VSREG = 13.5 V VIH Input voltage high level VSREG = 13.5 V Input hysteresis VSREG = 13.5 V 0.2 Input pull-down current VSREG = 13.5 V 5 VIHYS Iin 3.4.28 Parameter Typ. Max. 1 Unit V 2.3 V V 30 60 A Debug input The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V VSREG 18 V; Tj = -40 C to 150 C. Table 55. Debug input Symbol Test condition Min. VdIL Input voltage low level VSREG = 13.5 V VdIH Input voltage high level VSREG = 13.5 V Input hysteresis VSREG = 13.5 V 0.2 Pull-down resistor VDEBUG = 6 to 18 V 2.5 VdIHYS Rdin 3.4.29 Parameter Typ. Max. 1 Unit V 2.3 V V 5 7.5 k ADC characteristics The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V VSREG 18 V, Tj = -40 C to 150 C. Table 56. ADC characteristics Symbol Test condition tcon Conversion time fADC Clock frequency (see fclk2) Acc 64/197 Parameter Accuracy Min. Typ. Max. 2.5 s 8 MHz Voltage divider + reference(1) -2 2 Overall accuracy for WU input: VS = 22 V -3 3 Overall accuracy for WU input: VS = 18 V -3.5 3.5 Overall accuracy for WU input: VS = 6 V -4 4 Overall accuracy for WU input: VS = 4.5 V -4.6 4.6 DS11546 Rev 5 Unit % L99DZ100G, L99DZ100GP Electrical specifications Table 56. ADC characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit IEII Integral linearity error 4 LSB IEDI Differential linearity error 2 LSB VAINVS Conversion voltage range (VS, VSREG & WU) 1 22 V VAINTemp Conversion voltage range (TCL1 ...TCL6) 0 2 V 1. Guaranteed by design. 3.4.30 Temperature diode characteristics The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V VSREG 18 V, Tj = -40 C to 150 C Table 57. Temperature diode characteristics Symbol 3.4.31 Parameter Test condition Min. Typ. Max. Unit VTROOM 1-6 TSENSE output voltage at 25 C VS = 12 V; T = 25 C -- 1.4 V VTSENSE1-6 TSENSE output voltage 1 - 8 T = 25 C; T = 130 C; T = -40 C -- -4 mV/K Interrupt outputs The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V VSREG 18 V, Tj = -40 C to 150C Table 58. Interrupt outputs Symbol Parameter Test condition VINTL Output low level IINT = -4 mA VINTH Output high level IINT = 4 mA IINTLK 3-state leakage current 0 V < VINT < V1 tInterrupt Interrupt pulse duration (NINT, RxD_L/NINT, RxD_C/NINT tInt_react Interrupt reaction time Min. Typ. Max. Unit 0.5 V V1 - 0.5 V -10 10 s 56 Tested by scan chain DS11546 Rev 5 6 A 40 s 65/197 196 Electrical specifications 3.4.32 L99DZ100G, L99DZ100GP Timer1 and Timer2 6 V VSREG 18 V; Tj = -40 C to 150 C Table 59. Timer1 and Timer2 Symbol Parameter Test condition Min. Typ. Max. Unit ton 1 Timer on time 0.1 ms ton 2 Timer on time 0.3 ms ton 3 Timer on time 1 ms ton 4 Timer on time 10 ms ton 5 Timer on time 20 ms T1 Timer period 10 ms T2 Timer period 20 ms T3 Timer period 50 ms T4 Timer period 100 ms T5 Timer period 200 ms T6 Timer period 500 ms T7 Timer period 1000 ms T8 Timer period 2000 ms Figure 15. SPI - transfer timing diagram &61KLJKWRORZ'2HQDEOHG &61 WLPH &/. ; ; WLPH ',GDWDZLOOEHDFFHSWHGRQWKHULVLQJHGJHRI&/.VLJQDO ', ; ; &RPPDQG%\WH 'DWD '2GDWDZLOOFKDQJHRQWKHIDOOLQJHGJHRI&/.VLJQDO '2 ; ; WLPH *OREDO6WDWXV%\WH &61ORZWRKLJKDFWXDOGDWDLV WUDQVIHUHGWRRXWSXWSRZHUVZLWFKHV *OREDO(UURU ,QSXW 'DWD 5HJLVWHU ROGGDWD WLPH QHZGDWD WLPH *$3*&)7 The SPI can be driven by a micro controller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. 66/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Electrical specifications Figure 16. SPI input timing 7$$ &61 7$$ WVHW&61 W&/.+ WVHW&/. 7$$ &/. 7$$ WVHW', WKROG', W&/./ 7$$ ', 9DOLG 9DOLG 7$$ *$3*&)7 DS11546 Rev 5 67/197 196 Electrical specifications L99DZ100G, L99DZ100GP Figure 17. SPI output timing 7I&/. 7U&/. 9FF &/. 9FF 9FF 7U'2 9FF '2 ORZWRKLJK 9FF 7G'2 7I '2 9FF '2 KLJKWRORZ 9FF 7I&61 7U&61 9FF &61 9FF 9FF 7HQ'2BWULB/ 7GLV'2B/BWUL 7HQ'2BWULB+ 7GLV'2B+BWUL ("1($'5 68/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Electrical specifications Figure 18. SPI CSN - output timing & 61 ORZ WR KLJK GDWD IURP VKLIW UHJLVWHU LV WUDQVIHUUHG WR RXWSXW SRZHU V ZLWFKHV W U LQ W I LQ W &61B+,PLQ & 61 WG 2)) RXWSXW FXUUHQW RI D GULYHU 2 1 VWDWH 2) ) VWDWH W 2)) WG 21 W 21 RXWSXW FXUUHQW RI D GULYHU 2 )) VWDWH 2 1 VWDWH ("1($'5 Figure 19. SPI - CSN high to low transition and global status bit access &61KLJKWRORZDQG&/.VWD\VORZVWDWXVLQIRUPDWLRQRIGDWDELWIDXOWFRQGLWLRQ LVWUDQVIHUHGWR'2 &61 WLP H &/. WLP H ', WLP H ',GDWDLVQRWDFFHSWHG '2 WLP H '2VWDWXVLQIRUPDWLRQRIGDWDELW*67% IDXOWFRQGLWLRQ ZLOOVWD\DVORQJDV&61LVORZ ("1($'5 3.4.33 SGND loss comparator Tj = -40 C to 150 C, unless otherwise specified. Table 60. SGND loss comparator Symbol Parameter Test condition VSGNDloss VSGND loss threshold (VSGND - VPGND ) tSGNDloss VSGND loss filter time DS11546 Rev 5 Min. Typ. Max. Unit 100 270 500 mV 5 7 9 s 69/197 196 Application information L99DZ100G, L99DZ100GP 4 Application information 4.1 Supply VS, VSREG VSREG supplies voltage regulators V1 and V2, all internal regulated voltages for analog and digital functionality, LIN, CAN, the EC control block and both P-channel high-side switches OUT15 and OUT_HS. All other high-sides, Fail Safe block and the charge pump are supplied by VS. In case the VSREG pin is disconnected, all power outputs connected to VS are automatically switched off. 4.2 Voltage regulators The device contains two independent and fully protected low drop voltage regulators designed for very fast transient response and do not require electrolytic output capacitors for stability. The output voltage is stable with ceramic load capacitors >220 nF. 4.2.1 Voltage regulator: V1 The V1 voltage regulator provides 5 V supply voltage and up to 250 mA continuous load current to supply the system microcontroller and the integrated CAN transceiver. The V1 regulator is embedded in the power management and fail-safe functionality of the device and operates according to the selected operating mode. The V1 voltage regulator is supplied by pin VSREG. In addition, the V1 regulator supplies the devices internal loads. The voltage regulator is protected against overload and overtemperature. An external reverse current protection has to be provided by the application circuitry to prevent the input capacitor from being discharged by negative transients or low input voltage. Current limitation of the regulator ensures fast charge of external bypass capacitors. The output voltage is stable for ceramic load capacitors >220 nF. In case the device temperature exceeds the TSD1 threshold (either cluster or grouped mode) the V1 regulator remains on. The micro controller has the possibility for interaction or error logging. If the chip temperature exceeds the TSD2 threshold (TSD2 > TSD1), V1 will be deactivated and all wakeup sources (CAN, LIN, WU and Timer) are disabled. After tTSD, the voltage regulator will restart automatically. If the restart fails 7 times within one minute the devices enter the Forced Vbat_standby mode. The status bit FORCED_SLEEP_TSD2/V1SC (SR1) is set. 70/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP 4.2.2 Application information Voltage regulator: V2 The voltage regulator V2 is supplied by pin VSREG and can supply additional 5 V loads such as sensors or potentiometers. The maximum continuous load current is 50 mA. The regulator is protected against: 4.2.3 Overload Overtemperature Short-circuit (short to ground and battery supply voltage) Reverse biasing Voltage regulator failure The V1, and V2 regulator output voltages are monitored. In case of a drop below the failure thresholds (V1 < V1fail for t > tV1fail, V2 < V2fail for t > tV2fail), the failure bits V1FAIL, V2FAIL (SR 2) are latched. 4.2.4 Short to ground detection At turn-on of the V1 and V2 regulators, a short-to-GND condition is detected by monitoring the regulator output voltage. If V1 or V2 is below the V1fail (or V2fail) threshold for t > tV1short (t > tV2short) after turn-on, the devices will identify a short circuit condition at the related regulator will be switched off. In case of V1 short-to-GND the device enters Forced Vbat_standby mode automatically. Bits FORCED_SLEEP_TSD2/V1SC and (SR 1) V1FAIL (SR 2) are set. In case of a V2 short-to-GND failure the V2SC (SR 2) and V2FAIL (SR 2) bits are set. Once the output voltage of the corresponding regulator exceeded the V1fail (V2fail) threshold the short-to-ground detection is disabled. In case of a short-to-ground condition, the regulator is switched off due to thermal shutdown. V1 is switched off at TSD2, V2 is switched off at TSD1. DS11546 Rev 5 71/197 196 Application information 4.2.5 L99DZ100G, L99DZ100GP Voltage regulator behavior Figure 20. Voltage regulator behaviour and diagnosis during supply voltage 9VUHJ>9@ 96UHJ89 9325 9VUHJ$%6PLQ 9VUHJXY ELWLVVHW ILOWHUWLPHW2989BILOW 567%ELWLVVHWDQGUHJLVWHUV DUHVHWWRGHIDXOWDW9325B5 9>9@ WW89 XV W!W9IDLO W!W89 &RQWURO 5HJLVWHUV VHWWRGHIDXOW DW9325B) W!W89 9 957+ 9IDLO 1R5HVHWJHQHUDWHG 1UHVHW RXWSXW ,IW!WYVKRUW 9VKRUWGHWHFWHG 9EDWWVWDQGE\ 9IDLOELWLVVHW WYU WYU +LJK WUU WUU /RZ W9)6 VSHFLILF&RQWURO5HJLVWHUVDUHVHWWRGHIDXOWYDOXHV +LJK=*URXQGHG 9VUHJ$%6PLQ PLQLPXP9VUHJWRFRQWURO15HVHW W89 96UHJ89 9VUHJXQGHUYROWDJH W9IDLO 9IDLOILOWHUWLPH 9325B5) 9VUHJSRZHURQUHVHWYROWDJH ULVLQJIDOOLQJ WUU UHVHWSXOVHUHDFWLRQWLPH WYU UHVHWSXOVHGXUDWLRQ 957+ 9UHVHWWKUHVKROGYROWDJH 9)$,/ 9IDLOWKUHVKROGYROWDJH 9XQGHUYROWDJHILOWHUWLPH W9VKRUW 9VKRUWILOWHUWLPH W9)6 9IDLOVDIHILOWHUWLPH W2989BILOW 9VUHJRYHUXQGHUYROWDJHILOWHUWLPH ("1($'5 4.3 Operating modes The devices can be operated in the following operating modes: 4.3.1 Active LIN Flash CAN Flash V1_standby VBAT_standby Debug Active mode All functions are available and the device is controlled by SPI. 72/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP 4.3.2 Application information Flash modes To program the system microcontroller via LIN or HS CAN bus signals, the devices can be operated in LIN Flash mode or CAN Flash mode. The watchdog is disabled in these modes. The Flash modes are entered by applying an external voltage at the respective pin: VTxDL VFlashH (CAN Flash mode) VTxDC VFlashH (LIN Flash mode) In CAN Flash mode the CAN transceiver is set in TRX bias mode (CAN_GO_TO_TRX_RDY = 1) and TRX Normal mode automatically During CAN Flash mode, the watchdog can be deactivated by setting CR34: WDEN = 0. Write access to this bit is only possible during CAN Flash mode in order to prevent accidental deactivation of the watchdog. After setting WDEN (CR 34) the CAN Flash mode can be left (VTxDL < VFlashL) and the Watchdog will remain deactivated (see Figure 21) Figure 21. Sequence to disable/enable the watchdog in CAN Flash mode 2SHUDWLQJ 0RGH $FWLYH )ODVK $FWLYH )ODVK $FWLYH 9 7['/ 9 /,1&RPPXQLFDWLRQ :ULWH&5 :'(1 :ULWH&5 :'(1 63,&61 :'DFWLYH ZLWK:'(1 :'LQDFWLYH ("1($'5 In LIN Flash mode the maximum bitrate is increased to 100 kbit/s automatically (LIN_HS_EN = 1). A transition from Flash modes to V1_standby or Vbat_standby mode is not possible. At exit from Flash modes (VTxDL < VFlashL, VTxDC < VFlashL) no NReset pulse is generated. The watchdog starts with a Long Open Window (tLW). Note: Setting both TxDL and TxDC to high voltage levels (> VFlashH) is not allowed. Communication at the respective TxD pin is not possible. 4.3.3 SW-debug mode To allow software debugging, the watchdog can be deactivated by applying an external voltage to the DEBUG input pin (Vdebug > VdiH). In Debug mode, all device functionality and Operating modes are available. The watchdog is deactivated. At Exit from Debug mode (Vdebug < VdiL) the watchdog starts with a Long Open Window. Note: The device includes a test mode. This mode is activated by a dedicated sequence which includes a high voltage at the Debug Pin. The Debug Pin must be kept at nominal voltage levels in order to avoid accidental activation of the test mode. DS11546 Rev 5 73/197 196 Application information 4.3.4 L99DZ100G, L99DZ100GP V1_standby mode The transition from Active mode to V1_standby mode is controlled by SPI. To supply the micro controller in a low power mode, the V1 voltage regulator remains active. After the V1_standby command (CSN low to high transition), the device enters V1_standby mode immediately and the watchdog starts a Long Open Window (tLW). The watchdog is deactivated as soon as the V1 load current drops below the ICMP threshold (IV1< Icmp_fal). The V1 load current monitoring can be deactivated by setting ICMP = 1. In this configuration the watchdog will be deactivated upon transition into V1_standby mode without monitoring the V1 load current. Writing ICMP (CR 34) = 1 is only possible with the first SPI command after setting ICMP_CONFIG_EN (Config Reg) = 1. The ICMP_CONFIG_EN bit is reset to 0 automatically with the next SPI command. Power outputs (except OUT_HS & OUT15) are switched off in V1_standby mode. OUT_HS & OUT15 remain in the configuration programmed prior to the standby command in order to enable (cyclic) supply of external contacts. The timer signal (Timer1 or Timer2) can be mirrored to the NINT output pin during V1_standby mode. CAN and LIN transmitters (TxDL, TxDC) are off. Wake-up capability by CAN and LIN can be disabled by SPI. The CAN transceiver can be configured in Listen mode (TxDC disabled, RxDC enabled) in order to support pretended networking concepts (for details see Section 4.10.6: Pretended networking) 4.3.5 Interrupt Figure 22. NINT pins 9 (6'SURW 'DWD,Q (QDEOH 'LJLWDO ORJLF 'DWD2XW *1' *1' ("1($'5 RxDL/NINT indicates: a wake-up event from V1_standby mode (except wake-up by CAN) and the programmable timer interrupt RxDL/NINT pin is pulled low for t = tinterrupt. 74/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information RxDC/NINT indicates: Mode transitions of the CAN transceiver according to Figure 31: CAN transceiver state diagram CAN communication timeout (no CAN communication for t > tSilence). The CANTO flag is set. This interrupt can be masked by SPI (CR2: CANTO_IRQ_EN). RxDC/NINT pin is pulled low for t = tinterrupt. See also Section 4.3.6: CAN wake-up signalization NINT indicates: In Active mode: VSREG dropped below the programmed early warning threshold in Control Register 3 (VSREG < VSREG_EW_TH); feature is deactivated if VSREG_EW_TH is set to 0 V. In V1_standby mode - Programmable timer interrupt; An NINT pulse is generated at the beginning of the timer on-time (Timer 1 or Timer2) - CAN communication timeout (no CAN communication for t > tSilence). The CANTO flag is set. This interrupt can be masked by SPI (CR2: CANTO_IRQ_EN). - Wake-up from V1_standby mode by any wake-up source NINT is pulled low for t = tinterrupt In case of increasing V1 load current during V1_standby mode (IV1 > Icmp_ris), the device remains in standby mode and the watchdog starts with a Long Open Window. No Interrupt signal is generated. 4.3.6 CAN wake-up signalization Table 61. CAN wake-up signalization Operating mode Active V1_standby Vbat_standby Event Mode transition Status flag Interrupt pin WUP or WUP/WUF(1) Transition to TRX_Ready WAKE_CAN WUP/WUF(1) RxDC CAN Timeout Transition to TRX_Sleep CANTO RxDC (2) WUP(3) Transition into TRX_Bias WUP RxDC and NINT WUP or WUP/WUF(1) Transition into Active mode; TRX_Ready WAKE_CAN WUP/WUF(1) RxDC and NINT CAN Timeout Transition to TRX_Sleep CANTO RxDC and NINT (2) WUP(3) Transition into TRX_Bias WUP RXDC and NINT WUP or WUP/WUF(1) Transition into Active mode; TRX_Ready WAKE_CAN WUP/WUF(1) none CAN Timeout Transition to TRX_Sleep CANTO 1. SW_EN = 0, PNW_EN = 0: -- wake-up according ISO 11898-5:2007 (on WUP) -- Flags: Wake_CAN, WUP SW_EN = 1: -- wake-up according ISO 11898-6:2013 (on WUP/WUF combination) -- After the reception of a wake-up pattern (WUP) the CAN Enhanced Voltage Biasing is turned on until a CAN timeout is detected -- Flags: Wake_CAN, WUP, WUF DS11546 Rev 5 75/197 196 Application information L99DZ100G, L99DZ100GP 2. Interrupt can be disabled by SPI (CANTO_IRQ_EN). 3. SW_EN = 0, PWN_EN = 1 (Pretended Networking mode) -- no wake-up -- after reception of a wake-up patter (WUP) the transceiver enters TRX Bias mode -- Flags: WUP Note: See also Figure 31: CAN transceiver state diagram. 4.3.7 VBAT_standby mode The transition from Active mode to Vbat_standby mode is initiated by an SPI command. In Vbat_standby mode, the voltage regulators V1 and V2 (depending on configuration in CR 1), the power outputs (except OUT15 and OUT_HS) as well as LIN and CAN transmitters are switched off. An NReset pulse is generated upon wake-up from Vbat_standby mode. At transition into Vbat_standby mode with selective wake-up enabled (SWEN = 1), the CAN transceiver is automatically set to TRX_standby configuration (RXEN = 0). 4.4 Wake-up from Standby modes A wake-up from standby mode will switch the device to Active mode. This can be initiated by one or more of the following events: Table 62. Wake-up events description Wake up source Description LIN bus activity Can be disabled by SPI CAN bus activity Can be disabled by SPI Selective Wake-up can be enabled and configured by SPI Level change of WU IV1 >Icmp_ris Can be configured or disabled by SPI Device remains in V1_standby mode but watchdog is enabled (If ICMP = 0). No interrupt is generated. Programmable by SPI: - V1_standby mode: configurable timer interrupt. NINT and RxDL/NINT Timer Interrupt / Wake up interrupt signals are generated of C by TIMER - Vbat_standby mode: device wakes up after programmable timer expiration, V1 regulator is turned on and NReset signal is generated SPI Access Always active (except in VBAT_STANDBY mode) Wake up event: CSN is low and first rising edge on CLK To prevent the system from a deadlock condition (no wake up from standby possible) a configuration where the wake up by LIN and HS CAN are both disabled is not allowed. All wake-up sources are configured to default values in case of such invalid setting. The SPI Error Bit SPIE (Global Status Byte) is set. 76/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP 4.4.1 Application information Wake up input The WU input can be configured as wake-up source. The wake-up input is sensitive to any level transition (positive and negative edge) and can be configured for static or cyclic monitoring of the input voltage level. For static contact monitoring, a filter time of tWU_STAT is implemented. The filter is started when the input voltage passes the specified threshold VWU_THP or VWU_THN. Cyclic contact monitoring allows periodical activation of the wake-up input to read the status of the external contact. The periodical activation can be configured to Timer 1 or Timer 2. The input signal is filtered with a filter time of tWU_CYC after a delay (80% of the configured Timer on-time. A Wake-up will be processed if the status has changed versus the previous cycle. The buffered output OUT_HS can be used to supply the external contacts with the timer setting according to the cyclic monitoring of the wake-up input. In standby modes, the input WU is configurable with an internal pull-up or pull-down current source according to the setup of the external contact. In Active mode the inputs have an internal pull down resistor (RWU_act) and the input status can be read by SPI. Static sense should be configured before the read operation is started in order to reflect the actual input level. 4.5 Functional overview (truth table) Table 63. Status of different functions/features vs operating modes Operating modes Function Voltage regulator V1 Voltage regulator V2 Comments VOUT = 5 V VOUT = 5 V Reset generator Window watchdog LIN V1-standby static mode (cyclic sense) On On(1) On/ Off(2) On(2) / Off Vbat-standby static mode (cyclic sense) Off On(2) / Off On On Off On Off (on if IV1 > ICMP and ICMP = 0) Off Off Active(3) Active(3) Oscillator time base On / Off On(2) / Off On(2) / Off LIN 2.2a On Off(4) Off(4) On / Off(5) Off(4) Off(4) V1 monitor Wake up HS-cyclic supply Active mode HS_CAN Oscillator OSC1 2 MHz On On/Off(6) On/Off(6) Oscillator OSC2 32 MHz ON ON/Off(7) ON/Off(7) VSREG-Monitor On (8) (8) VS-Monitor On Off Off DS11546 Rev 5 77/197 196 Application information L99DZ100G, L99DZ100GP Table 63. Status of different functions/features vs operating modes (continued) Operating modes Function Comments Active mode V1-standby static mode (cyclic sense) Vbat-standby static mode (cyclic sense) H Bridge Gate Driver, EC control, bridge drivers, heater driver, all high-side drivers (except OUT_HS & OUT15) supplied by VS On/ Off(2) Off Off Fail-safe low-side switches On/ Off(9) On On On On On On/ Off(2) On/ Off (2) On/ Off(2) Charge pump On Off Off ADC (SPI read out and VSREG early warning interrupt) On Off Off Thermal shutdown TSD2 On On Off Thermal shutdown TSD1x for OUT_HS and OUT15 (Pchannel HS) On On/ Off(2) On/ Off(2) Short circuit protection for fail-safe low-side switches (in case LS is switched on) OUT_HS & OUT15 (Pchannel HS) supplied by VSREG 1. Supply the processor in low current mode. 2. According to SPI setting and DIR. 3. Unless disabled by SPI. 4. The bus state is internally stored when going to standby mode. A change of bus state will lead to a wake-up after exceeding of internal filter time (if wake-up by LIN or CAN is not disabled by SPI). Selective Wake functionality if enabled by SPI 5. After power-on, the HS CAN transceiver is in CAN_TRX_SLEEP mode. It is activated by SPI command (CAN_GO_TRX_RDY= 1) 6. ON, if cyclic sense is enabled or during wake-up request. 7. ON if SWEN=1 (CAN partial networking enabled) and ongoing CAN communication on the bus. 8. Cyclic activation = pulsed ON during cyclic sense. 9. ON in Fail-Safe mode; if standby mode is entered with active Fail-safe mode the output remains ON in standby mode. 78/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information Figure 23. Main operating modes )ODVK0RGH/,1&$1 )XQFWLRQDOLW\DVLQ$FWLYH0RGH :DWFKGRJ2)) 9V!9SRU &$1)ODVK0RGH &$175;5'< 5;(1 7;(1 /,1)ODVK0RGH /,1B+6BHQ 9EDWVWDUWXS $OOUHJLVWHUV 6HWWRGHIDXOW &KLS5HVHWELW567% 97;'/!9IODVK 25 97;'&!9IODVK 97;'/9IODVK $1' 97;'&9IODVK 97;'/!9IODVK 25 97;'&!9IODVK $FWLYH 0RGH 63,FRPPDQG 25 [7KHUPDO6KXWGRZQ 25 9VKRUWWR*1' 99IRUPVDIWHUVZLWFK21 25 [:')DLOXUH 97;'/!9IODVK 25 97;'&!9IODVK 921 5HVHW*HQHUDWRUDFWLYH :DWFKGRJDFWLYH :DNHXS (YHQW 63,FRPPDQG :DNHXS (YHQW 96WDQGE\ 0RGH 9EDW6WDQGE\ 0RGH 92)) 5HVHW*HQHUDWRU2))1UHVHW ORZ :DWFKGRJ2)) [7KHUPDO6KXWGRZQ76' 25 [:'IDLO 921 5HVHW*HQHUDWRUDFWLYH :DWFKGRJ 2))LI,Y,FPSRU,&03 ("1($'5 4.6 Configurable window watchdog During normal operation, the watchdog monitors the micro controller within a programmable trigger cycle. After power-on or standby mode, the watchdog is started with a timeout (Long Open Window tLW). The timeout allows the micro controller to run its own setup and then to start the window watchdog by setting TRIG (CR1,ConfigReg) =1 Subsequently, the micro controller has to serve the watchdog by alternating the watchdog trigger bit TRIG (CR1,Config Reg) within the safe trigger area TSWX. The trigger time is configurable by SPI. A correct watchdog trigger signal will immediately start the next cycle. After 8 watchdog failures in sequence, the V1 regulator is switched off for tV1OFF. After 7 additional watchdog failures the V1 regulator is turned off permanently and the device goes into Forced Vbat_standby mode. The status bit FORCED_SLEEP_WD (SR 1) is set. A wake-up is possible by any activated wake-up source. After wake-up from Forced Vbat_standby mode and the watchdog trigger still fails, the device enters Forced Vbat_standby mode again after one Long Open Window. DS11546 Rev 5 79/197 196 Application information L99DZ100G, L99DZ100GP This actually produces an additional watchdog failure but the watchdog fail counter will remain at maximum value of 15 failures. This sequence is repeated until a valid watchdog trigger event is performed by writing TRIG = 1. In case of a Watchdog failure, the power outputs and V2 are switched off and the status bit WDFAIL (SR 1) is set to 1. A reset pulse is generated at NReset output and the device enters Fail-safe mode. Control registers are set to their Fail Safe values and the Fail-safe low-side switches are turned on. Please refer to chapter Section 4.7: Fail-safe mode for more details. The following diagrams illustrate the Watchdog behavior of the devices. The diagrams are split into 3 parts. First diagram shows the functional behavior of the watchdog without any error. The second diagram covers the behavior covering all the error conditions, which can affect the watchdog behavior. Figure 26: Watchdog in Flash mode shows the transition in and out of Flash modes. Figure 24, Figure 25 and Figure 26 can be overlapped to get all the possible state transitions under all circumstances. For a better readability, they were split in normal operating, operating with errors and Flash mode. Figure 24. Watchdog in normal operating mode (no errors) :DNHXS 9!957[ $FWLYHPRGH ORQJ RSHQ ZLQGRZ *R9EDWVWE\ 2U *R9VWE\$1',Y ,FPS :' 2)) 75,* A 9EDWVWDQGE\PRGH 96WDQGE\,9 ,&03 *R9VWE\ SURSSHUWULJJHULQ :LQGRZ 0RGH :LQGRZPRGH JR9EDWVWE\ $FWLYHPRGH ("1($'5 80/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information Figure 25. Watchdog with error conditions )DLO6DIH (YHQW 9!9UWK ORQJ RSHQ ZLQGRZ $FWLYHPRGH IRUFHG9EDWVWE\ 99UWK 75,* A SURSSHUWULJJHULQ :' 2)) )DLO6DIH (YHQW 9EDWVWDQGE\PRGH 99UWK :LQGRZ 0RGH :LQGRZPRGH IRUFHG9%$7[:'IDLO [76' 6KRUW9 $FWLYHPRGH ("1($'5 Figure 26. Watchdog in Flash mode $FWLYHPRGH ORQJ RSHQ ZLQGRZ ([LWIURP )/$6+'HEXJPRGH (QWHU :' 2)) )/$6+'HEXJPRGH $FWLYHPRGH )/$6+'HEXJ PRGH (QWHU :LQGRZ 0RGH )/$6+'HEXJPRGH ("1($'5 Note: Whenever the device is operated without servicing the mandatory watchdog trigger events, a sequence of 15 consecutive reset events is performed and the device enters the Forced_Vbat_Stby mode with bit FORCED_SLEEP_WD in SR1 set. If the device is woken up after such a forced VBAT_Standby condition and the watchdog is still not serviced, the device, after one long open watchdog window will re-enter the same Forced_Vbat_Stby mode until the next wake up event. In this case, an additional watchdog failure is generated, but the fail counter is not cleared, keeping the maximum number of 15 failures. This sequence is repeated until a valid watchdog trigger event is performed by writing TRIG = 1. DS11546 Rev 5 81/197 196 Application information 4.6.1 L99DZ100G, L99DZ100GP Change watchdog timing The watchdog trigger time is configured by setting WD_TIME_x (CR 2). Writing to these bits is possible only using the first SPI command after setting WD_CONFIG_EN = 1 (Config Reg). The WD_CONFIG_EN bit is reset to 0 automatically with the next SPI command. 4.7 Fail-safe mode 4.7.1 Temporary failures The devices enter Fail-safe mode in case of: Watchdog failure V1 turn on failure V1 failure (V1 < VRTxfalling for t > tV1FS) Thermal Shutdown TSD2 - V1 short (V1 < V1fail for t > tV1short) The Fail Safe functionality is also available in V1_Standby mode. During V1_Standby mode the Fail Safe mode is entered in the following cases: V1 failure (V1 < VRTxfalling for t > tV1FS) Watchdog failure (if watchdog still running due to IV1 > Icmp_fal) Thermal Shutdown TSD2 In Fail Safe mode the devices return to a fail safe state. The Fail Safe condition is indicated to the system in the Global Status Byte. The conditions during Fail Safe mode are: All outputs beside LS1_FSO and LS2_FSO are turned off All Control Registers are set to fail safe default values except: 82/197 - SWEN (CR1): selective Wake-up enable - Partial Networking Configuration: CR23-CR29 Write operations to Control Registers are blocked until the Fail Safe condition is cleared. The following bits are not WRITE protected: - TRIG (CR1, Config Register ): watchdog trigger bit - V2_x (CR1): Voltage Regulator V2 control - CAN_GO_TRX_RDY (CR1): activation of CAN transceiver - CR2 (bit <8:23>): Timer1 and Timer2 settings - OUT_HS_x (CR5 ): OUT_HS configuration - OUT15_x (CR6): OUT15 configuration - PWMx_freq_y (CR12): PWM frequency configuration - PWMx_DC_y (CR13 - CR17): PWM duty cycle configuration LIN and HS CAN transmitter and SPI remain on (transmitters are deactivated in case of thermal shutdown TSD1 (TSD1 cluster 5 or 6 in cluster mode) Corresponding Failure Bits in Status Registers are set FS Bit (Global Status Byte) is set LS1_FSO and LS2_FSO will be turned on Charge pump is switched off DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information If the Fail Safe mode was entered it keeps active until the Fail safe condition is removed and the Fail Safe was read by SPI. Depending on the root cause of the Fail Safe operation, the actions to exit Fail safe mode are as shown in the following table. Table 64. Temporary failures description Failure source Failure condition Microcontroller (oscillator) Watchdog early write failure or expired window FS (Global Status Byte) =1; WDFAIL (SR 1) =1; WDFAIL_CNT_x (SR 1) = n+1 TRIG (CR 1) = 1 during long open window Read&Clear SR1 Short at turn-on FS (Global Status Byte) =1; FORCED_SLEEP_TSD2/V1SC (SR 1) =1 Wake-up; Read&Clear SR1 Undervoltage FS (Global Status Byte) = 1; V1UV (SR 1) = 1; V1fail (SR 2) = 1(1) V1 >VRTrising; Read&Clear SR1 Tj > TSD2 FS (Global Status Byte) = 1; TW (SR 2) = 1; TSD1 (SR 1) =1; TSD2 (SR 1) =1 Tj < TSD2; Read&Clear SR1 V1 Temperature Diagnosis Exit from Fail-safe mode 1. If V1 < V1fail (for t > tV1fail). The Fail-safe Bit is located in the Global Status Register. 4.7.2 Non-recoverable failures - forced Vbat_standby mode If the Fail-safe condition persists and all attempts to return to normal system operation fail, the devices enter the Forced Vbat_standby mode in order to prevent damage to the system. The Forced Vbat_standby mode can be terminated by any wake-up source. The root cause of the Forced Vbat_standby mode is indicated in the SPI Status Registers. In forced Vbatstby mode and with Fail Safe conditions still present at wake-up, the Fails safe low side outputs LSx_FSO are switched OFF for 25us after the wake up event. In Forced Vbat_standby mode, all Control Registers are set to power-on default values except: SWEN (CR1) All bits from CR23 to CR29 CP_DITH_DIS (Config. Reg ) The Forced Vbat_standby mode is entered in case of: Multiple watchdog failures: FORCED_SLEEP_WD (SR 1) = 1 (15 x watchdog failure) Multiple thermal shutdown 2: FORCED_SLEEP_TSD2/V1SC (SR 1) = 1 (7 x TSD2) V1 short at turn-on (V1 < V1fail for t > tV1short): FORCED_SLEEP_TSD2/V1SC (SR 1) = 1 DS11546 Rev 5 83/197 196 Application information L99DZ100G, L99DZ100GP Table 65. Non-recoverable failure Failure source Failure condition Temperature 4.8 Exit from Fail-safe mode FS (Global Status Byte) = 1; WDFAIL (SR 1) = 1; FORCED_SLEEP_WD (SR 1) = 1 Wake-up; TRIG (CR 1) = 1 during long open window; Read&Clear SR1 Short at turn-on FS (Global Status Byte) = 1; FORCED_SLEEP_TSD2/V1SC (SR 1) = 1 Wake-up; Read&Clear SR1 7 times TSD2 FS (Global Status Byte) =1; TW (SR 2) = 1; Wake-up; TSD1 (SR 1) = 1; TSD2 (SR 1) = 1; Read&Clear SR1 FORCED_SLEEP_TSD2/V1SC (SR 1) = 1 Microcontroller 15 consecutive (Oscillator) Watchdog Failures V1 Diagnosis Reset output (NReset) Figure 27. NReset pin 9 (6'SURW .2KPV 'DWD2XW 'DWD,Q 'LJLWDO ORJLF *1' *1' ("1($'5 If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output NReset is pulled up to V1 by an internal pull-up resistor after a reset delay time (tV1R). This is necessary for a defined start of the micro controller when the application is switched on. Since the NReset output is realized as an open drain output it is also possible to connect an external NReset open drain NReset source to the output. As soon as the NReset is released by the devices the watchdog starts with a long open window. A reset pulse is generated in case of: 84/197 V1 drops below VRTxfalling (configurable by SPI) for t > tUV1 Watchdog failure Turn-on of the V1 regulator (VSREG Power-on or wake-up from Vbat_standby mode) DS11546 Rev 5 L99DZ100G, L99DZ100GP 4.9 Application information LIN Bus Interface Figure 28. RxDL pin 9 (6'SURW 'DWD,Q (QDEOH 'LJLWDO ORJLF 'DWD2XW *1' *1' ("1($'5 4.9.1 Features LIN 2.2a compliant (SAEJ2602 compatible) transceiver LIN Cell has been designed according to "Hardware requirements for transceivers (version 1.3)" Bitrate up to 20 kbit/s Dedicated LIN Flash mode with bitrate up to 100 kbit/s GND disconnection fail safe at module level Off mode: does not disturb network GND shift operation at system level Micro controller Interface with CMOS-compatible I/O pins Internal pull-up resistor Receive-only mode ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2 Matched output slopes and propagation delay Wake-up behaviour according to LIN2.2a and Hardware Requirements for LIN, CAN and Flexray Interfaces (version 1.3) At VSREG > VPOR (i.e. VSREG power-on reset threshold), the LIN transceiver is enabled. The LIN transmitter is disabled in case of the following errors: Dominant TxDL time out LIN permanent recessive Thermal shutdown 1 VSREG overvoltage/ undervoltage The LIN receiver is not disabled in case of any failure condition. The default bitrate of the transceiver allows communication up to 20 kbit/s. To enable fast flashing via the LIN bus, the transceiver can be operated in high speed mode by setting bit LIN_HS_EN (Config Reg) = 1. This feature is enabled automatically in LIN Flash mode. DS11546 Rev 5 85/197 196 Application information 4.9.2 L99DZ100G, L99DZ100GP Error handling The devices LIN transceiver provides the following 3 error handling features. Dominant TxDL time out If TXD_L is in dominant state (low) for t > tdom(TXDL) the transmitter will be disabled, the status bit LIN_TXD_DOM (SR 2) will be set. The transmitter remains disabled until the status bit is cleared. The TxD dominant timeout detection can be disabled via SPI (LIN_TXD_TOUT_EN = 0). Permanent recessive If TXD_L changes to dominant (low) state but RXD_L signal does not follow within t < tLIN the transmitter will be disabled, the status bit LIN_PERM_REC (SR 2) will be set. The transmitter remains disabled until the status bit is cleared. Permanent dominant If the bus state is dominant (low) for t > tdom(bus) a bus permanent dominant failure will be detected. The status bit LIN_PERM_DOM (SR 2) will be set. The transmitter will not be disabled. 4.9.3 Wake up from Standby modes In low power modes (V1_standby mode and Vbat_standby mode) the devices can receive two types of wake up signals from the LIN bus (configurable by SPI bit LIN_WU_CONFIG (Config Reg)): Recessive-Dominant-recessive pattern with t > tdom_LIN (default, according LIN 2.2a) State Change recessive-to-dominant or dominant-to-recessive (according LIN 2.1) Pattern Wake-up (default) Figure 29. Wake-up behavior according to LIN 2.2a 9ROWDJHDW/,13LQRI/,13K\VLFDO/D\HUGHYLFH /,1UHFHVVLYH WGRP/,1 96XSSO\ 9 6XSSO\ /,1GRPLQDQW VOHHSPRGH VWDQGE\PRGH RUVLPLODUPRGHQDPLQJ *$3*&)7 86/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information Status change wake-up - Recessive-to-dominant Normal wake-up can occur when the LIN transceiver was set in standby mode while LIN was in recessive (high) state. A dominant level at LIN for t > tLINBUS, will switch the devices to Active mode. Status change wake-up - Dominant-to-recessive If the LIN transceiver was set in standby mode while LIN was in dominant (low) state, recessive level at LIN for t > tLINBUS, will switch the devices to Active mode. 4.9.4 Receive-only mode The LIN transmitter can be disabled in Active mode by setting the bit LIN_REC_ONLY (CR2). In this mode it is possible to listen to the bus but not sending to it. 4.10 High-speed CAN bus transceiver Figure 30. RxDC pin 9 (6'SURW 'DWD,Q (QDEOH 'LJLWDO ORJLF 'DWD2XW *1' *1' ("1($'5 DS11546 Rev 5 87/197 196 Application information 4.10.1 88/197 L99DZ100G, L99DZ100GP Features: ISO 11898-2:2003 and ISO 11898-5:2007 compliant ISO 11898-6: 2013 compliant (Selective wake-up functionality up to 500kbps); only L99DZ100GP HS-CAN cell has been designed according to "Requirements for partial networking (version 2.2)" and "Hardware requirements for transceivers (version 1.3)" Supports pretended networking Listen mode (transmitter disabled) Enhanced Voltage Biasing according to ISO 11898-6:2013 SAE J2284 compliant Bitrate up to 1Mbit/s. Function range from -27V to +40V DC at CAN pins. GND disconnection fail safe at module level. GND shift operation at system level. Micro controller Interface with CMOS compatible I/O pins. ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2 Matched output slopes and propagation delay DS11546 Rev 5 L99DZ100G, L99DZ100GP 4.10.2 Application information CAN transceiver operating modes Figure 31. CAN transceiver state diagram 6%& $FWLYH 3RZHU8S5HVHW ,QLWLDO9DOXH )(& 7UDQVLWLRQ 6:(1 ! !)(& 75;6OHHS 6:(1 RU31:(1 :DNHXSSDWWHUQ :83 )ODJ:83 &$1&RPPXQLFDWLRQ ,QWHUUXSW5['&1,17RQO\ 7LPHRXW IRU31:(1 )(& 2U )ODJ&$172 *275;5($'< ,QWHUUXSW5['& 75;%,$6 63,FPG (QDEOH9EDW6WE\0RGH 63,FPG (QDEOH96WE\0RGH :DNHE\63,LI*2 75;5'< 6:(1 $1'31:B(1 :DNHXSSDWWHUQ :83 )ODJV:83:$.(&$1 ,QWHUUXSW5['&1,17 2U :DNHE\63,LI*2 75;5'< 6:(1 :DNHXS)UDPH:8) )ODJV:83:8):$.(&$1 ,QWHUUXSW5['& 6:(1 $1'31:B(1 RU :DNHXSSDWWHUQ:83 )UDPH'HWHFWLRQ(UURU )ODJV:83:$.(&$1 )ODJ)'(UU ,QWHUUXSW5['& ,QWHUUXSW5['& 2U RU *275;5'< *275;5'< *275;5'< 6:(1 :DNHXS)UDPH:8) )ODJV:83:8):$.(&$1 ,QWHUUXSW5['&1,17 RU )UDPH'HWHFWLRQ(UURU )ODJ)'(UU ,QWHUUXSW5['&1,17 2U :DNHE\63,LI*275;5'< 6:(1 RU31:(1 75;%,$6 :DNHXSSDWWHUQ :83 )ODJ:83 ,QWHUUXSW5['&1,17RQO\IRU 31:(1 63,FPG (QDEOH96WE\0RGH 75;5HDG\ 63,FPG (QDEOH9%$7VWE\ 6:(1 :DNHXS)UDPH:8) )ODJV:83:8):$.(&$1 ,QWHUUXSW1RQH RU )UDPH'HWHFWLRQ(UURU )ODJ)'(UU ,QWHUUXSW1RQH &$1&RPPXQLFDWLRQ 7LPHRXW )(& )ODJ&$172 ,QWHUUXSW5['&1,17 75;6OHHS 6%& 96WDQGE\ &$1&RPPXQLFDWLRQ 7LPHRXW )(& )ODJ&$172 75;%,$6 6:(1 :DNHXSSDWWHUQ :83 )ODJV:83:$.(&$1 ,QWHUUXSW1RQH 6:(1 :DNHXSSDWWHUQ :83 )ODJ:83 75;6OHHS 1RWH ,Q3UHWHQGHG1HWZRUNLQJFRQILJXUDWLRQ31:B(1 D:83OHDGVWR x 7UDQVFHLYHUWUDQVLWLRQLQWR75;%,$6PRGHQR6%&PRGHWUDQVLWLRQ x ,QWHUUXSWDW5['&DQG1,17 7KH:DNHXS)UDPHGHFRGHULVWXUQHGRIIPLQLPL]HGFXUUHQWFRQVXPSWLRQ 6%& 9EDW6WDQGE\ 1RWH &$172,QWHUUXSWRQ5['&DQG1,17FDQEHPDVNHGE\63,&5&$172,54(1! *$3*&)7 TRX Ready State In this state the bus-biasing is on. The Frame Decoder is enabled, if selective wake-up is activated (SWEN=1). The transmitter and receiver can be configured by SPI (RXEN, TXEN) as follows: TRX Standby (default): transmitter and receiver disabled TRX Listen: transmitter disabled, receiver enabled TRX Normal: transmitter enabled, receiver enabled DS11546 Rev 5 89/197 196 Application information L99DZ100G, L99DZ100GP TRX BIAS State In this transceiver state the bus biasing is on and the Automatic Voltage Biasing is active (i.e. transceiver enters TRX_Sleep at t > tSilence and turns off the biasing). The Frame Decoder is enabled if selective wake-up is configured (SWEN = 1). The CAN transmitter is disabled. The receiver can be configured by SPI (RXEN) as follows: TRX Standby(default): receiver disabled TRX Listen: receiver enabled The CAN receiver is capable to detect a wake-up pattern (WUP) or a wake-up frame (WUF; if selective wake-up is enabled by SWEN = 1). In V1_standby mode and Active mode, a wake-up is indicated to the micro-controller by an interrupt signal and the transceiver enters TRX_Ready State (receiver and transmitter according to setting of TXEN and RXEN). After serving the interrupt, the micro controller can enable the receiver and transmitter by setting TXEN = 1 and RXEN = 1. In case of a Frame-Detect-Error (FDERR = 1), an automatic wake up is performed and the selective wakeup feature is disabled (SWEN = 0). TRX SLEEP State After Power-on the CAN transceiver enters TRX_Sleep state. In this state, the CAN transceiver is disabled and the biasing is turned off. Transmitter and receiver are disabled (TRX_Standby state). The CAN selective wakeup reference oscillator and the Frame Decoder are off. After the detection of CAN communication (WUP), an interrupt signal is generated and the transceiver enters TRX_Ready state (if SWEN = 0) or TRX_BIAS state (if SWEN = 1). Receiver and transmitter are configured according to setting of TXEN and RXEN. TRX_Sleep state is entered automatically after a CAN communication timeout (see Section 4.10.3: Automatic voltage biasing) 4.10.3 Automatic voltage biasing The Automatic Voltage Biasing is described in ISO 11898-6:2013. This feature is active in all transceiver low-power modes independent of the SBC operating modes and independent if selective wake-up is enabled or not (SWEN (CR 1) = 0 or SWEN = 1). If there has been no activity on the bus for longer than tSilence, the bus lines are biased towards 0V via the receiver input resistors Rin. If wake-up activity on the bus lines is detected (Wake-up pattern, WUP), the bus lines are biased to VCANHrec respectively VCANLrec via the internal receiver input resistors Rin. The biasing is activated not later than tBias. 4.10.4 Wake-up by CAN The devices support 2 wake-up modes. The selective wake-up according to ISO 118986:2013 or the wake-up by any bus activity according to ISO 11898-2:2003/-5:2007 (default configuration). The wake-up behavior can be configured by SPI. Wake-up by CAN pattern (WUP) The default setting for the wake up behavior after Power-on reset is the wake-up by regular communication on the CAN bus according to ISO 11898-5:2007 (SWEN=0). When the CAN 90/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information transceiver is in a low power mode (TRX_BIAS or TRX_Sleep) the device can be woken up by sending 2 consecutive dominant bits separated by a recessive bit. A wake-up can be detected if the CAN transceiver was set in standby mode while the CAN bus was in recessive (high) state or dominant (low) state (see Figure 32: CAN wake up capabilities). Figure 32. CAN wake up capabilities WZDNH WILOWHU W ILOWHU WILOWHU &$15; 67$7( $&7,9( 67$1'%< $&7,9( &$1SDWWHUQZDNHXS WZDNH WILOWHU WILOWHU WILOWHU &$15; 67$7( $&7,9( 67$1'%< $&7,9( &$1SDWWHUQZDNHXSZLWKGRPLQDQWVWDWHEHIRUH6WDQGE\ *$3*&)7 For details, see Figure 31: CAN transceiver state diagram Wakeup by Wake-up Frame (WUF) In this configuration, the wake-up behavior is according to ISO 11898-6:2013. This option is activated by setting SWEN = 1. Upon reception of a valid wake up frame, an interrupt will be generated, the WUF flag will be set and the device enters Active mode. The included frame-error-counter according ISO 11898-6:2013 is reset whenever selective wake-up is set to enable and whenever tSilence has expired in TRX BIAS state (i.e. either on a transition SWEN = 0 -> 1 or on a transition TRX BIAS -> TRX Sleep). To detect a failure of the internal 32 MHz oscillator, the following mechanism is implemented. While selective wake-up is enabled a timer is started with each recessive to dominant edge. After 64 s and with periodic 64 s timer, a check is performed on CAN PN oscillator activity, and if an oscillator fail is detected, the osc_mon bit is set to `1'. Subsequently the device enters wake-up mode according to ISO11898-5 (wake-up pattern wake-up). For details, see Figure 31: CAN transceiver state diagram. Sequence for enabling selective wakeup After Power-On-Reset, the selective wakeup feature is disabled. The PN Configuration Registers have to be read and verified by the microcontroller in order to ensure a valid configuration. A read operation to Registers CR23 to CR29 is required to allow enabling the selective wake-up feature (set SWEN=1). SWRD_CRxx (SR 12) bits will indicate a valid read operation. The SWRD_CRxx bits are reset to 0 with every WRITE operation. DS11546 Rev 5 91/197 196 Application information L99DZ100G, L99DZ100GP When all SWRD_CRxx bits are set, SWEN can be set to enable the Selective Wakeup function. In case SYSERR (SR 12) is set while Selective Wakeup is enabled, the Selective Wakeup will be disabled automatically. In case SYSERR is set, enabling the Selective Wakeup function is blocked. While selective wake-up is enabled (SWEN = 1), writing to CR23 - CR29 is blocked but SWEN is reset to `0'. To re-configure the selective wakeup feature, it is recommended to set SWEN = 0 before writing to CR23 - CR29. Wake up from TRX SLEEP If the CAN Transceiver is in TRX_Sleep state the CAN frame detection logic is disabled. The wake up can be done in two steps. To enable the CAN frame detection logic a wake up pattern must be sent on the bus. With the detection of the wake up pattern an automatic state transition to TRX_BIAS State is done. WUP flag is set. In TRX_BIAS State the CAN frame detection logic is enabled. If there is no bus communication for longer than tSilence an automatic state transition to TRX_Sleep state will be done and the CAN frame detection logic will be disabled. At frame error counter (FECNT_x) overflow, a wake up will be performed and the selective wakeup feature will be disabled. For details, see Figure 31: CAN transceiver state diagram. 4.10.5 CAN looping If CAN_LOOP_EN (CR 2) is set the TxD_C input is mapped directly to the RxD_C pin. This mode can be used in combination with the CAN Receive-only mode, to run diagnosis for the CAN protocol handler of the micro controller. 4.10.6 Pretended networking To support pretended networking concepts, the devices can be configured as follows: V1_standby mode or Active mode (if watchdog is required) Pretended Networking enabled (PNW_EN (CR 2) = 1) In this configuration, the microcontroller is supplied by V1 in low current mode. The CAN Automatic Voltage Biasing is active. Upon incoming CAN messages, the biasing is turned on (TRX_BIAS State) and an interrupt is generated. If the device is in V1_standby mode it remains in this mode. The incoming CAN frames are passed to the microcontroller via the RxD_C signal line for decoding. 4.10.7 CAN error handling The devices provide the following four error handling features. After Power-on Reset (VS > VPOR) the CAN transceiver is disabled. The transceiver is enabled by setting CAN_GO_TRX_RDY(CR 1) = 1. The CAN transmitter will be disabled automatically in case of the following errors: Dominant TxD_C time out CAN permanent recessive RxD_C permanent recessive Thermal Shutdown 1 The CAN receiver is not disabled in case of any failure condition. 92/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information Dominant TxDC time out If TXD_C is in dominant state (low) for t > tdom(TxDC) the transmitter will be disabled, CAN_TXD_DOM (SR 2) will be latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared. CAN Permanent Recessive If TXD_C changes to dominant (low) state but CAN bus does not follow for 4 times, the transmitter will be disabled, CAN_PERM_REC (SR 2) will be latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared. CAN Permanent Dominant If the bus state is dominant (low) for t > tCAN a permanent dominant status will be detected. CAN_PERM_DOM (SR 2) will be latched and can be read and optionally cleared by SPI. The transmitter will not be disabled. RXDC Permanent Recessive If RXD_C pin is clamped to recessive (high) state, the controller is not able to recognize a bus dominant state and could start messages at any time, which results in disturbing the overall bus communication. Therefore, if RXD_C does not follow TXD_C for 4 times the transmitter will be disabled. CAN_RXD_REC (SR 2) will be latched and can be read and optionally cleared by SPI. The transmitter remains disabled until the status register is cleared. 4.11 Serial Peripheral Interface (ST SPI Standard) A 32-bit SPI is used for bi-directional communication with the microcontroller. The SPI is driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible output pins and one input pin is needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-Pin reflects the global error flag (fault condition) of the device. Chip Select Not (CSN) The input Pin is used to select the serial interface of this device. When CSN is high, the output Pin (DO) is in high impedance state. A low signal activates the output driver and a serial communication can be started. The state during CSN = 0 is called a communication frame. If CSN = low for t > tCSNfail the DO output is switched to high impedance in order to not block the signal line for other SPI nodes. Serial Data In (DI) The input Pin is used to transfer data serial into the device. The data applied to the DI is sampled at the rising edge of the CLK signal and shifted into an internal 32-bit shift register. At the rising edge of the CSN signal the content of the shift register is transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 32-bit are transmitted within one communication frame (i.e. CSN DS11546 Rev 5 93/197 196 Application information L99DZ100G, L99DZ100GP low). If more or less clock pulses are counted within one frame the complete frame is ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame. Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected IC's is recommended. Serial Data Out (DO) The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the global error flag (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN Pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out. Serial Clock (CLK) The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up to 4 MHz. 4.12 Power supply failure 4.12.1 VS supply failure VS overvoltage If the supply voltages VS reaches the overvoltage threshold VSOV: LIN remains enabled CAN remains enabled OUT1 to OUT_14 are turned off (default). The shutdown of outputs may be disabled by SPI (VS_OV_SD_EN (CR 3) = 0) Charge pump is disabled (and is switched on automatically in case the supply voltage recovers to normal operating voltage) H-bridge gate driver and heater MOSFET gate driver are switched into sink condition ECV is switched in high impedance state and ECDR is discharged by RECDRDIS (to ensure the gate of the external MOSFET is discharged => EC mode considered as off) Recovery of outputs after overvoltage condition is configurable by SPI: 94/197 - VS_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VS_OV (SR 2). - VS_LOCK_EN (CR 3) = 0: outputs turned on automatically after VS overvoltage condition has recovered. The overvoltage bit VS_OV (SR 2) is set and can be cleared with a `Read&Clear' command. The overvoltage bit is reset automatically if VS_LOCK_EN (CR 3) = 0 and the overvoltage condition has recovered. DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information VS undervoltage If the supply voltage VS drops below the under voltage threshold voltage (VSUV): LIN remains enabled CAN remains enabled OUT1 to OUT14 are turned off (default). The shutdown of outputs may be disabled by SPI (VS_UV_SD_EN (CR 3) = 0) Heater MOSFET gate driver switched into sink condition ECV is switched in high impedance state and ECDR is discharged by RECDRDIS (to ensure the gate of the external MOSFET is discharged => EC mode considered as off) Recovery of outputs after undervoltage condition is configurable by SPI: 4.12.2 - VS_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VS_UV (SR 2). - VS_LOCK_EN (CR 3) = 0: outputs turned on automatically after VS undervoltage condition has recovered. The undervoltage bit VS_UV (SR 2) is set and can be cleared with a `Read&Clear' command. The undervoltage bit is removed automatically if VS_LOCK_EN (CR 3) = 0 and the undervoltage condition has recovered. VSREG supply failure VSREG overvoltage If the supply voltages VSREG reaches the overvoltage threshold VSREG_OV: LIN is switched to high impedance CAN remains enabled OUT15 and OUT_HS are turned off (default). The shutdown of outputs may be disabled by SPI (VSREG_OV_SD_EN (CR 3) = 0) Recovery of outputs after overvoltage condition is configurable by SPI: - VSREG_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VSREG_OV (SR 2). - VSREG_LOCK_EN (CR 3) = 0: outputs turned on automatically after VSREG overvoltage condition has recovered. The overvoltage bit VSREG_OV (SR 2) is set and can be cleared with a `Read&Clear' command. The overvoltage bit is reset automatically if VSREG_LOCK_EN (CR 3) = 0 and the overvoltage condition has recovered. DS11546 Rev 5 95/197 196 Application information L99DZ100G, L99DZ100GP VSREG undervoltage If the supply voltage VSREG drops below the under voltage threshold voltage (VSREG_UV): LIN is switched to high impedance CAN remains enabled OUT15 and OUT_HS are turned off (default). The shutdown of outputs may be disabled by SPI (VSREG_UV_SD_EN (CR 3) = 0) Recovery of outputs after undervoltage condition is configurable by SPI: 96/197 - VSREG_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VSREG_UV (SR 2). - VSREG_LOCK_EN (CR 3) = 0: Outputs turned on automatically after VSREG undervoltage condition has recovered. The undervoltage bit VSREG_UV (SR 2) is set and can be cleared with a `Read&Clear' command. The undervoltage bit is removed automatically if VSREG_LOCK_EN (CR 3) = 0 and the undervoltage condition has recovered. DS11546 Rev 5 L99DZ100G, L99DZ100GP 4.13 Application information Temperature warning and thermal shutdown Figure 33. Thermal shutdown protection and diagnosis 7M!76' 76' 76' $OORXWSXWVDQG9RII 9RIIIRUW W76' W!W76' $OORXWSXWVDQG9RII 9RQ 'LDJQRVLV76' 'LDJQRVLV76' [76' :DNHXSHYHQW )RUFHG 9EDWBVWDQGE\ 0RGH 7M!76' A5HDGDQG&OHDU 25 3RZHURQUHVHW 3RZHURQUHVHW 7HPSHUDWXUH :DUQLQJ 'LDJQRVLV7: A5HDGDQG&OHDU 25 3RZHURQUHVHW 7M!7Z $FWLYH 0RGH 6WDQGE\0RGHV GXULQJF\FOLFVHQVH 9V!9SRU 3RZHU2Q5HVHW $OORXWSXWVLQFO9RII 1RWH ,QWKHUPDOFOXVWHUPRGH76'&RQILJ RQO\WKHFRQFHUQHGRXWSXWFOXVWHUZLOOEHVZLWFKHGRII ("1($'5 Note: The Thermal State machine will recover the same state were it was before entering Standby mode. In case of a TSD2 it will enter TSD1 state. DS11546 Rev 5 97/197 196 Application information 4.14 L99DZ100G, L99DZ100GP Power outputs OUT1..15 and OUT_HS The component provides a total of 6 half bridges outputs OUT1..6 to drive motors and 10 stand alone high-side outputs OUT7..15 and OUT_HS to drive e.g. LED's, bulbs or to supply contacts. All high-side outputs beside OUT_HS and OUT15 are supplied by the pin VS and OUT_HS and OUT15 are supplied by the buffered supply VSREG. OUT_HS is intended to be used as contact supply. Beside OUT15 and OUT_HS the high-side switches can be activated only in case of running charge pump. OUT15 and OUT_HS can be activated also in standby modes. All high-side and low-side outputs switch off in case of: VS (VSREG) overvoltage and undervoltage (depending on configuration, see Section 4.12.2: VSREG supply failure) Overcurrent (depending on configuration, auto recovery mode (see below) Overtemperature (TSD1x/ cluster or single mode) Fail safe event Loss of GND at SGND pin In case of overcurrent or overtemperature (TSD1_CLx (SR 6)) condition, the drivers will switch off. The according status bit will be latched and can be read and optionally cleared by SPI. The drivers remain off until the status is cleared. In case overvoltage/ undervoltage condition, the drivers will be switched off. The according status bit will be latched and can be read and optionally cleared by SPI. If VSREG_LOCK_EN (CR 3) respectively VS_LOCK_EN (CR 3) are set, the drivers remain off until the status is cleared. If the VS_LOCK_EN or VSREG_LOCK_EN) bit is set to 0, the drivers will switch on automatically if the error condition disappears. Undervoltage and overvoltage shutdown can be disabled by SPI. In case of open-load condition, the according status register will be latched. The status can be read and optionally cleared by SPI. The high and low-side outputs are not switched off in case of open-load condition. For OUT1..OUT8 and OUT_HS the auto recovery feature (OUTx_OCR (CR 7)) can be enabled. If these bits are set to 1 the driver will automatically restart from an overload condition. This overload recovery feature is intended for loads which have an initial current higher than the overcurrent limit of the output (e.g. Inrush current of cold light bulbs). The SPI bits OUTx_OCR_ALERT (SR4) indicate that the output reached auto-recovery condition. Note: The maximum voltage and current applied to the High-side Outputs is specified in the `Absolute Maximum Ratings'. Appropriate external protection may be required in order to respect these limits under application conditions. In case of outputs switch off due to loss of ground at SGND pin, the device has to be re-started through a power off on both VS and VSREG. Each of the stand alone high-side driver outputs OUT7 ... OUT15 and OUT_HS can be driven with an internally generated PWM signal, an internal Timer or with DIR1 respectively DIR2. See table below. 98/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information Table 66. Power output settings OUTx_3 OUTx_2 4.15 OUTx_1 OUTx_0 Description 0 0 0 0 OFF 0 0 0 1 ON 0 0 1 0 Timer1 output is controlled by timer1; starting with ON phase after timer restart 0 0 1 1 Timer2 output is controlled by timer2; starting with ON phase after timer restart 0 1 0 0 PWM1 0 1 0 1 PWM2 0 1 1 0 PWM3 0 1 1 1 PWM4 1 0 0 0 PWM5 1 0 0 1 PWM6 1 0 1 0 PWM7 1 0 1 1 PWM8 1 1 0 0 PWM9 1 1 0 1 PWM10 1 1 1 0 DIR1 1 1 1 1 DIR2 Auto-recovery alert and thermal expiration The thermal expiration feature provides a robust protection against possible microcontroller malfunction, switching off a given channel if continuously driven in auto-recovery. If the temperature of the related cluster increases by more than 30 C after reaching the autorecovery time tAR, the channel is switched off. The thermal expiration status bit OUTx_TH_EX (SR 3) is set. During auto-recovery condition, OUTx_OCR_ALERT (SR 4) is set. The Alert bit indicates that an overload condition (load in-rush, short-circuit, etc) is present. The thermal expiration feature is controlled by SPI (OUTx_OCR_THX_EN (CR 8). DS11546 Rev 5 99/197 196 Application information L99DZ100G, L99DZ100GP Figure 34. Example of long auto-recovery on OUT7. Temperature acquisition starts after tAR, thermal expiration occurs after a T = 30 100/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information Figure 35. Block diagram of physical realization of AR alert and thermal expiration #BUU4VQQMZ $VSSFOU 4FOTF (BUF ESJWFS 0/ DPNNBOE $ 1PXFS.04 %JBHOPTUJD 0WFSDVSSFOU DPNQ *UI 5FNQTFOTF "NQ "%$ 5@EBUB )4@&OBC "3MJNJU SFBDIFE %JHJUBM4UBUF .BDIJOF 0$ 04$ -BNQ%SJWFS*$ *$3*&)7 4.16 Charge pump The charge pump uses two external capacitors, which are switched with fCP. The output of the charge pump has a current limitation. In standby mode and after a thermal shutdown has been triggered the charge pump is disabled. If the charge pump output voltage remains too low for longer than TCP, the power-MOS outputs and the EC-control are switched off. The H-bridge MOSFET gate drivers and the Heater MOSFET gate driver are switched to resistive low and CP_LOW (SR 2) is set. This bit has to be cleared to reactivate the drivers. If the bit CP_LOW_CONFIG (Configuration Register 0x3F) is set to `1', CP_LOW (SR2) behaves as a `live' bit and the outputs are re-activated automatically upon recovery of the charge pump output voltage. In case of reaching the overvoltage shutdown threshold VSOV the charge pump is disabled and automatically restarted after VS recovered to normal operating voltage. Figure 36. Charge pump low filtering and start up implementation &3 )LOWHU7LPH7 &3 W\SV 9 & 3ORZ ' &3ORZ &/. 3RZHU6WDJH'LVDEOH 6WDUW8S%ODQ NLQJ 7LPHWVHW B&3 W\SLFDO V $OOSRZHUVWDJH EHVLGH3&KDQQH O GLVDEOHG *DWH'ULYH2XWSXWVGLVDEOHG *$3*&)7 DS11546 Rev 5 101/197 196 Application information 4.17 L99DZ100G, L99DZ100GP Inductive loads Each of the half bridges is built by internally connected high-side and low-side power DMOS transistors. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT6 without external freewheeling diodes. The high-side drivers OUT7 to OUT15 and OUT_HS are intended to drive resistive loads only. Therefore only a limited energy (E < 1 mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For inductive loads (L > 100 H) an external freewheeling diode connected between GND and the corresponding output is required. The low-side driver at ECV does not have a freewheel diode built into the device. 4.18 Open-load detection The open-load detection monitors the load current in each activated output stage. If the load current is below the open-load detection threshold for t > tOL_OUT the corresponding openload bit OUTx_OL (SR 5) is set in the status register. 4.19 Overcurrent detection An overcurrent condition is detected after a filter time of tFOC and is indicated by the status bit OUTx_OC (SR 3). In case of overcurrent, the corresponding driver switches off to reduce the power dissipation and to protect the integrated circuit. If the outputs are not configured in recovery mode, the microcontroller has to clear the according status bits to reactivate the corresponding drivers. 4.20 Current monitor The current monitor sources a current image of the power stage output current at the current monitor pin CM, which has a fixed ratio (ICMr) of the instantaneous current of the selected high-side driver. The signal at output CM is blanked for tcmb after switching on the driver until correct settlement of the circuitry. The bits CM_SELx (CR 7) define which of the outputs is multiplexed to the current monitor output CM. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an openload or overload condition. For example, it can be used to detect the motor state (starting, free running, stalled). The current monitor output is enabled after the current-monitor blanking time, when the selected output is switched on. If this output is off, the current monitor output is in high impedance mode. The current monitor can be deactivated by CM_EN (CR 7). 4.21 PWM mode of the power outputs Description see Section 7.3: Status register overview. 4.22 Cross-current protection The six half-brides of the device are cross-current protected by an internal delay time. If one driver (LS or HS) is turned off, the activation of the other driver of the same half bridge will be automatically delayed by the crosscurrent protection time. After the crosscurrent 102/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information protection time is expired the slew-rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior, it is always guaranteed that the previously activated driver is completely turned off before the opposite driver starts to conduct. 4.23 Programmable soft-start function to drive loads with higher inrush current Loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps, start current of motors) can be driven by using the programmable soft-start function (i.e. overcurrent recovery mode). Each driver has a corresponding overcurrent recovery bit OUTx_OCR (CR 7). If this bit is set, the device automatically switches the outputs on again after a programmable recovery time. The PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. The PWM frequency is defined by CR7<8:12> setting. The device itself cannot distinguish between a real overload (e.g. short-circuit condition) and a load characterized by operation currents exceeding the short-circuit threshold. Examples are non-linear loads like a light bulb used on the HS outputs or a motor used on the half bridge output with inrush and stall currents that shall be limited by the auto recovery feature. For the bulb, a real overload condition can only be qualified by time. For overload detection the microcontroller can switch on the light bulbs by setting the overcurrent recovery bit for the first e.g. 50 ms. After clearing the recovery bit, the output will be switched off automatically if the overload condition remains. For the half bridges the high current can be present during all motor activation and another SW strategy must be applied to identify a SC to GND or Supply. Before running the motor e.g. with a first SPI command all bridge LS are switched on (without auto recovery functionality / cleared overcurrent recovery bit), all HS are switched off and a SC to Battery can be diagnosed. With a next SPI command, all HS are switched on (without auto recovery functionality/ cleared overcurrent recovery bit) and all LS are switched off. In this sequence, a short to GND can be diagnosed. If in both sequences no overload condition is identified, the motor can be run by switching on the according HS and LS each configured in auto recovery mode (see Figure 37: Software strategy for half bridges before applying autorecovery mode). Such sequence can be applied before any motor activation to identify SC just before operating the motor (in case the delay due to the 2 additional SPI commands is not limiting the application) or in case of power up of the system resp. applied on a certain time base. DS11546 Rev 5 103/197 196 Application information L99DZ100G, L99DZ100GP Figure 37. Software strategy for half bridges before applying auto-recovery mode 9EDW 9EDW 96 96 96 287[+6 287\+6 "" 2)) 287[ 0 287[+6 2)) 2)) 287\/6 /'= "" 287\/6 /'= *1' /'= *1' *1' 6:6WHS6KRUWWRJURXQGGHWHFWLRQ 6:6WHS 6:6WHS +62)) /621 2)) 287[/6 6:6WHS6KRUWWREDWWHU\GHWHFWLRQ $52)) 287\ 0 *1' %(*,1 6:5RXWLQH 21 287[ 21 /'= 287\+6 21 287\ 21 287[/6 96 1 6KRUWWR9V" +621 /62)) 6KRUWWR*1'" 1 6HW$521 < < .HHS$52)) 6ZLWFK+62)) .HHS$52)) 6ZLWFK/62)) (1' 6:5RXWLQH ("1($'5 As soon as an output reaches auto-recovery condition, OUTx_OCR_ALERT (SR 4)) is set. The Alert bit indicates that an overload condition (load in-rush, short-circuit, etc) is present. 104/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information Figure 38. Overcurrent recovery mode , /2$' 8QOLPLWHG,QUXVK&XUUHQW /LPLWHG,QUXVK&XUUHQWLQ SURJUDPPDEOHUHFRYHU\PRGH &XUUHQW/LPLWDWLRQ W *$3*&)7 4.24 H-bridge control The PWMH and DIRH inputs control the drivers of the external H-bridge transistors. In single Motor mode the motor direction can be chosen with the direction input (DIRH), the duty cycle and frequency with the PWMH input (single mode). With the SPI bits SD (CR 10) and SDS (CR 10) four different slow-decay modes (via drivers and via diode) can be selected using the high-side or the low-side transistors. Unconnected inputs are defined by internal pull-down current. Alternatively, the bridge can be driven in half bridge mode (dual mode). By setting the dual mode bit DM (Config Reg) = 1, both half-bridges can be controlled independently. DS11546 Rev 5 105/197 196 Application information L99DZ100G, L99DZ100GP Table 67. H-bridge control truth table Output pins VS_OV VS_UV DS TSD1 GH1 x 0 x x x x x x x x RL RL RL RL H-bridge disabled 2 x x 1 x x 0 1 0 0 0 0 RL RL RL RL Charge pump voltage too low 3 x x 1 x x 0 0 x x x 1 RL RL RL RL Thermal shutdown 4 x x 1 x x 0 0 1 0 0 0 L L L L L(1) L(1) L(1) GL2 CP_LOW x GH2 DM 1 GL1 Nb SDS Comment SD Motor config HEN Failure bits PWMH Control bits DIRH Control pins Overvoltage 5 x x 1 x x 0 0 0 0 1 0 L(1) Short-circuit(1) 6 0 1 1 x x 0 0 0 0 0 0 L H H L Bridge H2/L1 on 7 x 0 1 0 0 0 0 0 0 0 0 L H L H Slow-decay mode LS1 and LS2 on 8 0 0 1 0 1 0 0 0 0 0 0 L H L L 9 1 0 1 0 1 0 0 0 0 0 0 L L L H Slow-decay mode LS2 on 10 1 1 1 x x 0 0 0 0 0 0 H L L H Bridge H1/L2 on 11 x 0 1 1 0 0 0 0 0 0 0 H L H L Slow-decay mode HS1 and HS2 on 12 0 0 1 1 1 0 0 0 0 0 0 L L H L Slow-decay mode HS1 on 13 1 0 1 1 1 0 0 0 0 0 0 H L L L Slow-decay mode HS2 on 14 0 0 1 1 0 1 0 0 0 0 0 L L L L 15 0 1 1 1 0 1 0 0 0 0 0 L L L H 16 1 0 1 1 0 1 0 0 0 0 0 L H L L 17 1 1 1 1 0 1 0 0 0 0 0 L H L H 18 0 0 1 0 1 1 0 0 0 0 0 L L L L 19 0 1 1 0 1 1 0 0 0 0 0 L L H L 20 1 0 1 0 1 1 0 0 0 0 0 H L L L 21 1 1 1 0 1 1 0 0 0 0 0 H L H L 22 0 0 1 1 1 1 0 0 0 0 0 H L H L 23 0 1 1 1 1 1 0 0 0 0 0 H L L H 24 1 0 1 1 1 1 0 0 0 0 0 L H H L 25 1 1 1 1 1 1 0 0 0 0 0 L H L H Single Dual Slow-decay mode LS1 on Half bridge mode 1. Only the H-bridge (low-side and high-side), in which one MOSFET is in short-circuit condition is switched off. Both MOSFETs of the other H-bridge remain active and driven by DIRH and PWMH. 106/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information During watchdog long-open window, the H-bridge drivers are forced off until the first valid watchdog trigger in window mode (setting TRIG = 0 during safe window). The Control Registers remain accessible during long open window. 4.25 H-bridge driver slew-rate control The rising and falling slope of the drivers for the external high-side Power-MOS can be slew rate controlled. If this mode is enabled the gate of the external high-side Power-MOS is driven by a current source instead of a low-impedance output driver switch as long as the drain-source voltage over this Power-MOS is below the switch threshold. The current is programmed using the bits SLEW_x<4:0> (CR 10), which represent a binary number. This number is multiplied by the minimum current step. This minimum current step is the maximum source-/sink-current (IGHxrmax / IGHxfmax) divided by 31. Programming SLEW_x <4:0> to 0 disables the slew rate control and the output is driven by the lowimpedance output driver switch. Figure 39. H-bridge GSHx slope 9*6+[ &XUUHQW &RQWUROOHG /RZ5HVLVWLYH 6ZLWFK &RQWUROOHG &XUUHQW &RQWUROOHG W 9'6+[ W *$3*&)7 4.26 Resistive low The resistive output mode protects the devices and the H-bridge in the standby mode and in some failure modes (thermal shutdown TSD1 (SR 1), charge pump low CP_LOW (SR 2) and DI pin stuck at `1' SPI_INV_CMD (SR 2)). When a gate driver changes into the resistive output mode due to a failure a sequence is started. In this sequence the concerning driver is DS11546 Rev 5 107/197 196 Application information L99DZ100G, L99DZ100GP switched into sink condition for 32 s to 64 s to ensure a fast switch-off of the H-bridge transistor. If slew rate control is enabled, the sink condition is slew-rate controlled. Afterwards the driver is switched into the resistive output mode (resistive path to source). 4.27 Short circuit detection / drain source monitoring The Drain - Source voltage of each activated external MOSFET of the H-bridge is monitored by comparators to detect shorts to ground or battery. If the voltage-drop over the external MOSFET exceeds the configurable threshold voltage VSCd_HB (DIAG_x (CR 10) for longer t > tSCd_HB the corresponding gate driver switches off the external MOSFET and the corresponding drain source monitoring flag DS_MON_x (SR 2) is set. The DSMON_x bits have to be cleared through the SPI to reactivate the gate drivers. This monitoring is only active while the corresponding gate driver is activated. If a drain-source monitor event is detected, the corresponding gate-driver remains activated for at maximum the filter time. When the gate driver switches on, the drain-source comparator requires the specified settling time until the drain-source monitoring is valid. During this time, this drain-source monitor event may start the filter time. The threshold voltage VSCd_HB can be programmed using the SPI bits DIAG_x (CR 10). Figure 40. H-bridge diagnosis 9V 96 96 '60RQLWRULQJ+6 *DWH'ULYHU+6 '60RQLWRULQJ+6 97KUHV N N *+ 6+ 97KUHV *DWH'ULYHU+6 *+ 0 6+ *DWH'ULYHU/6 *DWH'ULYHU/6 */ */ '60RQLWRULQJ/6 2/0RQLWRULQJ '60RQLWRULQJ/6 2/0RQLWRULQJ N N 97KUHV 97KUHV ("1($'5 4.28 H-bridge monitoring in off-mode The drain source voltages of the H-bridge driver external transistors can be monitored, while the transistors are switched off. If either bit OL_H1L2 (CR 10) or OL_H2L1 (CR 10) is set to 108/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information 1, while bit HEN (CR 1) = 1, the H-drivers enter resistive low mode and the drain-source voltages can be monitored. Since the pull-up resistance is equal to the pull-down resistance on both sides of the bridge a voltage of 2/3 VS on the pull-up highside and 1/3 VS on the lowside is expected, if they drive a low-resistive inductive load (e.g. motor). If the drain source voltage on each of these Power-MOS is less than 1/6 VS, the drain-source monitor bit of the associated driver is set. The open-load filter time is tOL_HB. Figure 41. H-bridge open-load-detection (no open-load detected) 9V N 9V 9V 0 P '60 N 97 9V N '60 97 9V *$3*&)7 Figure 42. H-bridge open-load-detection (open-load detected) 9V N 0 9V 2SHQ P '60 97 9V N N '60 97 9V *$3*&)7 DS11546 Rev 5 109/197 196 Application information L99DZ100G, L99DZ100GP Figure 43. H-bridge open-load-detection (short to ground detected) 9V N *1' 0 *1' P '60 N 97 9V '60 N 6KRUW 97 9V *$3*&)7 Figure 44. H-bridge open-load detection (short to VS detected) 9V 6KRUW N 9V 9V 0 P '60 '60 N 97 9V N 97 9V *$3*&)7 Table 68. H-bridge monitoring in off-mode Control bits Failure bits Comments Nb OL H1L2 OL H2L1 H OLTH High DSMON LS1 DSMON LS2 110/197 1 0 0 0 0 0 Drain-Source monitor disabled 2 1 0 x 0 0 No open-load detected 3 1 0 0 0 1 Open-load SH2 4 1 0 0 1 1 Short to GND 5 1 0 1 1 1 Short to VS 6 0 1 x 0 0 No open-load detected 7 0 1 0 1 0 Open-load SH1 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information Table 68. H-bridge monitoring in off-mode (continued) Control bits Failure bits Comments Nb OL H1L2 OL H2L1 H OLTH High DSMON LS1 DSMON LS2 4.29 8 0 1 0 1 1 Short to GND 9 0 1 1 1 1 Short to VS Programmable cross current protection The external PowerMOSFETs transistors in H-bridge (two half-bridges) configuration are switched on with an additional delay time tCCP to prevent cross current in the halfbridge. The cross current protection time tCCP can be programmed with the SPI bits COPT_x<3:0> (CR 10). The timer is started when the gate driver is switched on in the device. The PWMH module has 2 timers to configure locking time for high-side and freewheeling low-side. The programmable time tCCP-TIM1 / tCCP-TIM2 is the same. Sequence for switching in PWM mode is the following: HS switch off after locking tCCP-TIM1 LS switch on after 2nd locking tCCP-TIM1 HS switch on after locking tCCP-TIM2 which starts with rising edge on PWM input Figure 45. PWMH cross current protection time implementation WSS W FFS WSS[WFFS WSS![WFFS 3:0 ,QSXW W&&37,0 W&&37,0 W&&37,0 W&&37,0 W&&37,0 W&&37,0 +6/RJLF /6/RJLF W&&37,0 W&&37,0 W&&37,0 $FWLYH )UHH:KHHOLQJ 3DVVLYH )UHH:KHHOLQJ 3DVVLYH )UHH:KHHOLQJ ("1($'5 4.30 Power window H-bridge safety switch off block The two LS Switches LS1_FSO and LS2_FSO are intended to be used to switch off the gates of the external high-side MOSFETs in the power window h-bridge if a fatal error happens. This block must work also in case the MOSFET driver and the according control blocks on the chip are destroyed. Therefore it is necessary to have a complete separated safety block on the device, which has it's own supply and GND connection, separated from the other supplies and GNDs. In the block is implemented an own voltage regulator and oscillator. The safety block is surrounded by a GND isolation ring realized by deep trench isolation. The LS driver must work down to a lower voltage than the other circuits. The block has its DS11546 Rev 5 111/197 196 Application information L99DZ100G, L99DZ100GP own internal supply and an own oscillator for monitoring the failure signals (WWD, V1 fail, SPI fail & Tj) which are Manchester encoded and decoupled by high ohmic resistances. In case of fail-safe event, both LS switches LS1_FSO and LS2_FSO are switched on. In case of entering V1_standby mode or Vbat_standby mode both fail safe low-side switches are switched on to minimize the current drawn by the fail safe block (e.g. oscillator is switched off and Manchester Encoding is deactivated). Short circuit protection to VS is active in both standby modes limiting the current to IOLimit for a filter of tSCF. After this filter time the fail-safe switches are switched off and LSxFSO_OC (SR 3) is set. To reactivate the low-side functionality this bit has to be set back by a read and clear command. In case of VS loss the fail safe switches are biased by their own output voltage to turn on the low-side switches down to VOUT_max. To allow verification of the Fail-Safe path, the low-side switches LS1_FSO and LS2_FSO can be turned on by SPI (Configuration Register 0x3F bit 4: FS_FORCED) Figure 46. LSx_FSO: low-side driver "passively" turned on, taking supply from output pin (if main supply fails), can guarantee VLSx_FSO < VOUT_max &RPSOHWH,& 6XSSO\ )DLO6DIH%ORFN &/($5/6[B)62B2& 9)DLOXUHV 2YHU7HPS 76' 5[6LJQDO 7[0DQFKHVWHU (QFRGHG6LJQDOV 1RUPDOO\6ZLWFKLQJ 7;6LJQDOV :DWFKGRJ)DLO /6B)62B2& )LOWHUV 6WDWH 0DFKLQH /RZ6LGH 'ULYHU /6B)62 /RZ6LGH 'ULYHU /6B)62 /6B)62B2& &ORFN /6B)62B2& /6B)62B2& 95(* (QDEOH *1' ("1($'5 Figure 47. Safety concept 7[6LJQDO 0DQFKHVWHU(QFRGHG 6LJQDOV &ORFN 5[6LJQDO 1RUPDO2SHUDWLRQ )DLO6DIH &ORFN)DLOXUH 'DWD)DLOXUH ("1($'5 112/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP 4.31 Application information Heater MOSFET Driver The Heater MOSFET Driver stage is controlled by control bit GH (CR 5). The driver contains two diagnosis features to indicate short-circuit in active mode (external MOSFET switched on) and open-load in off state (External MOSFET switched off). Short circuit detection in on state is realized by monitoring the drain source voltage of the activated external MOSFET by a comparator to detect a short-circuit of SHheater to ground. If the voltage-drop over the external MOSFET exceeds the programmed threshold voltage VSCd_HE for longer than the drain-source monitor filter time tSCd_HE the gate driver switches off the external MOSFET and the corresponding drain source monitoring flag DSMON_HEAT (SR 4) is set. The drain source-monitoring bit has to be cleared by SPI to reactivate the gate driver. The drain source monitoring is only active while the gate driver is activated. If a drain source monitoring event is detected, the gate-driver remains activated for the maximum filter time. The threshold voltage can be programmed by SPI bits GH_THx (CR 10). Open-load detection in off state is realized by monitoring the voltage difference between SHheater and GND and supplying SHheater by a pull up current source that can be controlled by SPI bit GH_OL_EN (CR 10). When no load is connected to the external MOSFET source, the voltage will be pulled to VS and in case of exceeding the threshold VOLheater for a time longer than the open-load filter time tOL_He the open-load bit GH_OL (SR 5) will be set. Figure 48. Heater MOSFET open-load and short-circuit to GND detection 9V '6021B+($7 &3 63, 97KUHV ,2/KHDWHU *++HDWHU 6++HDWHU *DWH'ULYHU +HDWHU026)(7 *+B2/ 92/KHDWHU ("1($'5 DS11546 Rev 5 113/197 196 Application information L99DZ100G, L99DZ100GP Table 69. Heater MOSFET control truth table Control bit Failure bits Output pin Comment Nb GH ON/OFF 1 x 1 x 2 x 0 3 x 4 CP_LOW VS_OV VS_UV DS TSD1 GHheater x x x RL Charge puump voltage too low x x x 1 RL Thermal shutdown 0 1 x x 0 L Overload 1 0 0 x 1 0 L Short-circuit condition 5 x 0 0 1 0 0 L Undervoltage 6 1 0 0 0 0 0 H Heater MOFET driver enabled 7 0 0 0 0 0 0 L Heater MOFET driver enabled Note: RL = resistive low, L = active low, H = active high. 4.32 Controller of electro-chromic glass The voltage of an electro-chromic element connected at pin ECV can be controlled to a target value, which is set by the bits EC_x <5:0> (CR 11). Setting bit ECON (CR 11) enables this function. An on-chip differential amplifier and an external MOS source follower, with its gate connected to pin ECDR, and which drives the electro-chrome mirror voltage at pin ECV, form the control loop. The drain of the external MOS transistor is supplied by OUT10. A diode from pin ECV (anode) to pin ECDR (cathode) has been placed on the chip to protect the external MOS source follower. A capacitor of at least 5 nF has to be added to pin ECDR for loop-stability. The target voltage is binary coded with a full-scale range of 1.5 V. If bit ECV_HV (Config Reg) is set to 0, the maximum controller output voltage is clamped to 1.2 V without changing the resolution of bits EC_x<5:0> (CR 11). When programming the ECV low-side driver ECV_LS (CR 11) to on-state, the voltage at pin ECV is pulled to ground by a 1.6 low-side switch until the voltage at pin ECV is less than dVECVhi higher than the target voltage (fast discharge). The status of the voltage control loop is reported via SPI. Bit ECV_VHI (SR 6) is set, if the voltage at pin ECV is higher, whereas Bit ECV_VNR (SR 6) is set, if the voltage at pin ECV is lower than the target value. Both status bits are valid, if they are stable for at least the filter time tFEC_VNR and tFEC_VHI. Since OUT10 is the output of a high-side driver, it contains the same diagnose functions as the other high-side drivers (e.g. during an overcurrent detection, the control loop is switched off). In electro-chrome mode, OUT10 cannot be controlled by PWM mode. For EMS reasons, the loop capacitor at pin ECDR as well as the capacitor between ECV and GND has to be placed to the respective pins as close as possible (seeFigure 49: Electro-chrome control block for details). Pin ECDR is pulled resistively (RECDRDIS) to ground while not in electro-chrome mode. EC glass control behavior in case of failure on OUT10: 114/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information ECON (CR11) = 1 (EC glass control enabled) OUT10 is turned ON OUT10 settings in CR5 are ignored (PWM, DIRx, TIMERx) OUT10 settings in CR5 are recovered when ECON is set to 0. In case of a failure on OUT10 while ECON = 1 (overcurrent, VS overvoltage /undervoltage, TSD1) OUT10 is turned OFF (regardless of VS_OV_SD_EN and VS_UV_SD_EN in CR3) DAC is reset: EC_x (CR11) set to `000000' ECDR pin is pulled to GND ECON (CR11) remains `1' ECV_LS (CR11) remains as programmed Re-start of EC control after OUT10 failure Read&Clear or automatic restart (if CR3 Vs_LOCK_EN = 0) Write EC_x (CR11) Figure 49. Electro-chrome control block 96 2YHUFXUUHQW 287 $OOFRPSRQHQWVPXVWEHSODFHGFORVH WRJHWKHUDQGFRQQHFWHGZLWKDYHU\ ORZLPSHGDQFH '$& 63, /RJLF 96FRPSDWLEOH (&'5 9ROWDJHQRWUHDFKHG Q) (&0LUURU (&9 9ROWDJHWRRKLJK 96FRPSDWLEOH Q) *1' ("1($'5 4.33 Temperature warning and shutdown If any of the cluster (see Section 4.34: Thermal clusters) junction temperatures rises above the temperature warning threshold TW, the temperature warning flag TW (SR 2) is set after the temperature warning filter time tjtft and can be read via SPI. If the junction temperature increases above the temperature shutdown threshold (TSD1), the thermal shutdown bit TSD1 (SR 1) is set and the power transistors of all output stages are switched off to protect the device after the thermal shutdown filter time. The gates of the H-bridge and the heater MOSFET are discharged by the `Resistive Low' mode. After these bits have been cleared, the output stages are reactivated. If the temperature is still above the thermal warning threshold, the thermal warning bit is set after tjtft. Once this bit is set and the temperature is above the temperature shutdown threshold, temperature shutdown is detected after tjtft and DS11546 Rev 5 115/197 196 Application information L99DZ100G, L99DZ100GP the outputs are switched off. Therefore the minimum time after which the outputs are switched off after the bits have been cleared in case the temperature is still above the thermal shutdown threshold is twice the thermal warning/ thermal shutdown filter time tjtft. 4.34 Thermal clusters In order to provide an advanced on-chip temperature control, the power outputs are grouped in six clusters with dedicated thermal sensors. The sensors are suitably located on the device (see Figure 50: Thermal clusters identification). In case the temperature of an output cluster reaches the thermal shutdown threshold, the outputs assigned to this cluster are shut down (all other outputs remain active). Each output cluster has a dedicated temperature warning and shutdown flag (SR 6) and the cluster temperature can be read out by SPI. Hence, the thermal cluster concept allows to identify a group of outputs in which one or more channels are in overload condition. If thermal shutdown has occurred within an output cluster, or if temperature is rising within a cluster, it may be desired to identify which of the output (s) is (are) determining the temperature increase. An additional evaluation, based on current monitoring and cluster temperature read-out, supports identification of the outputs mainly contributing to the temperature increase. The cluster temperatures are available in SR 7, SR 8 and SR 9 and can be calculated from the binary coded register value using the following formula: Decimal code = (350 - Temp) / 0.488 Example: T = -40 C => decimal code is 799 (0x31F) T = 25 C => decimal code is 666 (0x29A) Thermal clusters can be configured using bit TSD_CONFIG (Config Reg): Standard mode (default): as soon as any cluster reaches thermal threshold the device is switched off. V1 regulator remains on and is switched off reaching TSD2. Cluster mode: only the cluster which reached shutdown temperature is switched off. If Cluster Th_CL6 (global) or Cluster Th_CL5 (Voltage Regulators) reachTSD1, the whole device is OFF (beside V1). Note: 116/197 Clusters related to power outputs (clusters 1 to 4, see Figure 50: Thermal clusters identification) will be managed digitally only, by mean of the ADC conversion of related thermal sensors, while clusters 5 and 6 will be managed in an analog way (comparators) since ADC can be off, e.g. in V1_standby mode. Temperature reading provided by ADC may differ from real junction temperature of a specific output due to spatial placement of thermal sensor. Such an effect is more visible during fast thermal increases of junction temperature. For some of the Power outputs, located between two different sensors, it may happen that temperature raising also affects the adjacent Cluster. DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information ',5 &$16XSSO\ 9B 15(6(7 &$1B/ 1,17 &$1B+ 'HEXJ 9B /,1 */ 6+ *+ 6+ *+ */ Figure 50. Thermal clusters identification :8 ',5+ &30 3:0+ &33 ',5 &3 5['B& &33 7['B& &30 5['B/1,17 *+KHDWHU 7['B/ &61 6+KHDWHU 287 ', 287 '2 287 &/. 287 (&9 &0 287 6*1' 7KHUPDO&OXVWHU 7KHUPDO&OXVWHU 7KHUPDO&OXVWHU 7KHUPDO&OXVWHU 7KHUPDO&OXVWHU 3*1' 287 96 287 287 965(* 287B+6 287 287 287 287 287 287 287 287 96 (&'5 /6B)62 96 287 /6B)62 *$3*&)7 Table 70. Thermal cluster definition Th_CL1 Th_CL2 5 W Driver + Door Mirror-y+OUT15 lock+OUT_HS Th_CL3 Th_CL4 Th_CL5 Th_CL6 Folder+Mirror-x 10W driver high ohmic channels VREG 1 VREG 2 Global TW digitally managed TSD1 & TSD2 Both analog managed TW digitally managed TSD1 Analog managed TW & TSD1 Both TW & TSD1 Both TW & TSD1 Both TW & TSD1 Both digitally managed digitally managed digitally managed digitally managed 4.35 VS compensation (duty cycle adjustment) module All stand-alone HS outputs can be programmed to calculate some internal duty cycle adjustment to adapt the duty cycle to a changing supply voltage at VS. This feature is aimed to avoid LED brightness flickering in case of alternating supply voltage. The correction of the duty cycle is based on the following formula: Equation 1: Duty cycle correction V th - V LED DutyCycle = --------------------------------- DC nom V Bat - V LED Vth = Duty cycle reference voltage: defined as 10 V DS11546 Rev 5 117/197 196 Application information L99DZ100G, L99DZ100GP VBat = Reference voltage: defined as voltage at pin VS VLED = Voltage drop on the external LED DCnom = Nominal Duty Cycle programmed by SPI< PWMx DCx> To be compatible to different LED load characteristics the value for VLED can be programmed for each output by a dedicated control register OUT7_VLED ... OUT_HS_VLED (CR 18 to CR 22). Auto compensation features can be activated for all HS outputs each by setting OUTx_AUTOCOMP_EN (CR 18 to CR 22). The programmed LED voltage (OUTx_V_LED (CR18 to CR22)) must be lower than Vth (10 V). Figure 51. Block diagram VS compensation (duty cycle adjustment) module $'&96 5HJLVWHU'XW\&\FOH+6 %LWDFFXUDF\ 1RPLQDO 9ROWDJH #9 63, 63, +6$VVLJQPHQWDQG/RDG$GDSWLRQ ,QWHUQDO $GMXVWPHQW 212)) 96&RPSHQVDWLRQ &DOFXODWLRQ %,79/(' YROWDJHOHYHO 99 5HJLVWHUDGMXVWHG 'XW\&\FOH+6 %LWDFFXUDF\ +6 +6 +6 +6 *$3*&)7 4.36 Analog digital converter Voltage signals VS, VSREG, VWU and TH_CL1..6 are read out sequentially. The voltage signals are multiplexed to an ADC. The ADC is realized as a 10 Bit SAR, that is sampled with the main clock fclk2 / fADC. Each channel will be converted with a conversion time tcon, therefore an update of the ADC value is available every tcon * 9. In case of WU is directly connected to Clamp 30, the input must be protected by a series resistance of typical 1k to sustain reverse battery condition. 118/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Application information Figure 52. Sequential ADC Read Out for VSREG, VS, WU and THCL1 ..THCL6 9LQ 9 :8 N 965(* 96 N S) &KDQQHO 0X[ 7+&/ 7+&/ 7+&/ 7+&/ 7+&/ 7+&/ 95() 9 63,5HJLVWHU %LW 6$5 ("1($'5 DS11546 Rev 5 119/197 196 Serial Peripheral Interface (SPI) 5 L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI) A 32-bit SPI is used for bi-directional communication with the microcontroller. The SPI is driven by a microcontroller with its SPI peripheral running in the following mode: CPOL = 0 and CPHA = 0. For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible output Pins and one input Pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-Pin will reflect the global error flag (fault condition) of the device. Chip Select Not (CSN) The input Pin is used to select the serial interface of this device. When CSN is high, the output Pin (DO) is in high impedance state. A low signal activates the output driver and a serial communication can be started. The state during CSN = 0 is called a communication frame. If CSN = low for t > tCSNfail the DO output will be switched to high impedance in order to not block the signal line for other SPI nodes. Serial Data In (DI) The input Pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 32-bit shift register. At the rising edge of the CSN signal the content of the shift register will be transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 32-bit are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame. Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected IC's is recommended. Serial Data Out (DO) The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the global error flag (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN Pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out. Serial Clock (CLK) The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up to 4 MHz. 5.1 ST SPI 4.0 The ST-SPI is a standard used in ST Automotive ASSP devices. 120/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI) This chapter describes the SPI protocol standardization. It defines a common structure of the communication frames and defines specific addresses for product and status information. The ST-SPI allows usage of generic software to operate the devices while maintaining the required flexibility to adapt it to the individual functionality of a particular product. In addition, failsafe mechanisms are implemented to protect the communication from external influences and wrong or unwanted usage. The devices Serial Peripheral Interface are compliant to the ST SPI Standard Rev. 4.0. 5.1.1 Physical layer Figure 53. SPI pin description &61 & 63,0DVWHU 6&. 6', /'=* 6'2 ("1($'5 5.2 Signal description Chip Select Not (CSN) The communication interface is de-selected, when this input signal is logically high. A falling edge on CSN enables and starts the communication while a rising edge finishes the communication and the sent command is executed when a valid frame was sent. During communication start and stop the Serial Clock (SCK) has to be logically low. The Serial Data Out (SDO) is in high impedance when CSN is high or a communication timeout was detected. Serial Clock (SCK) This SCK provides the clock of the SPI. Data present at Serial Data Input (SDI) is latched on the rising edge of Serial Clock (SCK) into the internal shift registers while on the falling edge data from the internal shift registers are shifted out to Serial Data Out (SDO). Serial Data Input (SDI) This input is used to transfer data serially into the device. Data is latched on the rising edge of Serial Clock (SCK). Serial Data Output (SDO) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (SCK). DS11546 Rev 5 121/197 196 Serial Peripheral Interface (SPI) L99DZ100G, L99DZ100GP Figure 54. SDO pin 9 (6'SURW 'DWD,Q 'LJLWDO ORJLF (QDEOH 'DWD2XW *1' *1' ("1($'5 5.2.1 Clock and Data Characteristics The ST-SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 CPHA = 0 Figure 55. SPI signal description 6&. 6', 06% 6'2 06% &61 /6% /6% ("1($'5 The communication frame starts with the falling edge of the CSN (Communication Start). SCK has to be low. The SDI data is then latched at all following rising SCK edges into the internal shift registers. After Communication Start the SDO will leave 3-state mode and present the MSB of the data shifted out to SDO. At all following falling SCK edges data is shifted out through the internal shift registers to SDO. 122/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI) The communication frame is finished with the rising edge of CSN. If a valid communication took place (e.g. correct number of SCK cycles, access to a valid address), the requested operation according to the Operating Code will be performed (Write or Clear operation). 5.2.2 Communication protocol SDI Frame The devices Data-In Frame consist of 32-bit (OpCode (2 bits) + Address (6 bits) + Data Byte 3 + Data Byte 2 + Data Byte 1). The first two transmitted bits (MSB, MSB-1) contain the Operation Code which represents the instruction which will be performed. The following 6 bits (MSB-2 to MSB-7) represent the address on which the operation will be performed. The subsequent bytes contain the payload. Figure 56. SDI Frame 23&2'( 2& 2& $''5(66 $ $ 06% $ $ '$7$%\WH $ $ WLPH WLPH '$7$%\WH WLPH '$7$%\WH WLPH /6% ("1($'5 Operating code The operating code is used to distinguish between different access modes to the registers of the slave device. Table 71. Operation codes OC1 OC0 Description 0 0 Write Operation 0 1 Read Operation 1 0 Read & Clear Operation 1 1 Read Device Information A Write Operation will lead to a modification of the addressed data by the payload if a write access is allowed (e.g. Control Register, valid data). Beside this a shift out of the content (data present at Communication Start) of the registers is performed. A Read Operation shifts out the data present in the addressed register at Communication Start. The payload data will be ignored and internal data will not be modified. In addition a Burst Read can be performed. DS11546 Rev 5 123/197 196 Serial Peripheral Interface (SPI) L99DZ100G, L99DZ100GP A Read & Clear Operation will lead to a clear of addressed status bits. The bits to be cleared are defined first by address, second by payload bits set to `1'. Beside this a shift out of the content (data present at Communication Start) of the registers is performed. Note: Status registers which change status during communication could be cleared by the actual Read & Clear Operation and are neither reported in actual communication nor in the following communications. To avoid a loss of any reported status it is recommended just clear status registers which are already reported in the previous communication (Selective Bitwise Clear). Advanced operation codes To provide beside the separate write of all control registers and the bitwise clear of all status registers, two Advanced Operation Codes can be used to set all control registers to the default value and to clear all status registers. A `set all control registers to default' command is performed when an OpCode `11' at address b'111111 is performed. Note: Please consider that potential device specific write protected registers cannot be cleared with this command as therefore a device Power-on-Reset is needed. A `clear all status registers' command is performed when an OpCode `10' at address b'111111 is performed. Data-in payload The Payload (Data Byte 1 to Data Byte 3) is the data transferred to the devices with every SPI communication. The Payload always follows the OpCode and the Address bits. For Write access the Payload represents the new data written to the addressed register. For Read & Clear operations the Payload defines which bits of the adressed Status Register will be cleared. In case of a `1' at the corresponding bit position the bit will be cleared. For a Read Operation the Payload is not used. For functional safety reasons it is recommended to set unused Payload to `0'. SDO frame The data-out frame consists of 32-bit (GSB + Data Byte 1 to 3). The first eight transmitted bits contain device related status information and are latched into the shift register at the time of the Communication Start. These 8-bit are transmitted at every SPI transaction. The subsequent bytes contain the payload data and are latched into the shift register with the eighth positive SCK edge. This could lead to an inconsistency of data between the GSB and Payload due to different shift register load times. Anyhow, no unwanted Status Register clear should appear, as status information should just be cleared with a dedicated bit clear after. 124/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI) Figure 57. SDO frame *OREDO6WDWXV%\WH*6% *6%1 567% 63,( 3/( )( '( 06% '$7$%\WH *: )6 WLPH WLPH '$7$%\WH WLPH '$7$%\WH /6% WLPH ("1($'5 Global Status Byte (GSB) The bits (Bit0 to Bit4) represent a logical OR combination of bits located in the Status Registers. Therefore no direct Read & Clear can be performed on these bits inside the GSB. Table 72. Global Status Byte Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 GSBN RSTB SPIE PLE FE DE GW FS Global Status Bit Not (GSBN) The GSBN is a logically NOR combination of Bit 24 to Bit 30. This bit can also be used as Global Status Flag without starting a complete communication frame as it is present directly after pulling CSN low. Reset Bit (RSTB) The RSTB indicates a device reset. In case this bit is set, specific internal Control Registers are set to default and kept in that state until the bit is cleared. The RSTB bit is cleared after a Read & Clear of all the specific bits in the Status Registers which caused the reset event. SPI Error (SPIE) The SPIE is a logical OR combination of errors related to a wrong SPI communication. Physical Layer Error (PLE) The PLE is a logical OR combination of errors related to the LIN and HS CAN transceivers. Functional Error (FE) The FE is a logical OR combination of errors coming from functional blocks (e.g. High-side overcurrent). Device Error (DE) The DE is a logical OR combination of errors related to device specific blocks (e.g. VS overvoltage, overtemperature DS11546 Rev 5 125/197 196 Serial Peripheral Interface (SPI) L99DZ100G, L99DZ100GP Global Warning (GW) The GW is a logical OR combination of warning flags (e.g. thermal warning). Fail Safe (FS) The FS bit indicates that the device was forced into a safe state due to mistreatment or fundamental internal errors (e.g. Watchdog failure, Voltage regulator failure). Data-Out Payload The Payload (Data Bytes 1 to 3) is the data transferred from the slave device with every SPI communication to the master device. The Payload always follows the OpCode and the address bits of the actual shifted in data (In-frame-Response). 5.2.3 Address definition Table 73. Device application access Operating Code OC1 OC0 0 0 0 1 1 0 Table 74. Device information read access Operating Code OC1 OC0 1 1 Table 75. RAM address range RAM Address Access 3FH Configuration Register R/W 3CH Status Register 12 R/C ... ... 32H Status Register 2 R/C 31H Status Register 1 R/C ... ... 22H Control Register 34 R/W 1DH Control Register 29 R/W ... 02H 126/197 Description ... Control Register 2 DS11546 Rev 5 R/W L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI) Table 75. RAM address range (continued) RAM Address Description 01H Control Register 1 00H reserved Access R/W Table 76. ROM address range ROM Address Description Access 3FH W 3EH R 20H R 16H R 15H R 14H R 13H R 12H R 11H R 10H R R 06H R 05H R 04H R 03H R 02H R 01H R 00H R ... ... 0AH ... Information registers The Device Information Registers can be read by using OpCode `11'. After shifting out the GSB the 8-bit wide payload will be transmitted. By reading Device Information Registers a communication width which is minimum 16-bit plus a multiple by 8 can be used. After shifting out the GSB followed by the 8-bit wide payload a series of `0' is shifted out at the SDO. DS11546 Rev 5 127/197 196 Serial Peripheral Interface (SPI) L99DZ100G, L99DZ100GP Table 77. Information Registers Map ROM Adress Description Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3FH 3EH R 0 0 0 0 0 0 0 0 20H R 0 1 0 1 0 1 0 1 16H R C0H 15H R 7FH 14H R C0H 13H R 41H 12H R 91H 11H R 28H 10H R B0H ... ... 0AH R ... major revision minor revision L99DZ100G: 01H L99DZ100GP: 00H 06H R 05H R 09H 04H R 46H 03H R 42H 02H R 55H 01H R 01H 00H R 00H Device Identification Registers These registers represent a unique signature to identify the device and silicon version. : 00H (STMicroelectronics) : 01H (BCD Power Management) : 55H : 42H : 46H : 09H : for L99DZ100G: 01H for L99DZ100GP: 00H 128/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI) SPI modes By reading out the register general information of SPI usage of the Device Application Registers can be read. Table 78. SPI Mode Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BR DL2 DL1 DL0 0 0 S1 S0 1 0 1 1 0 0 0 0 : B0H (Burst mode read available, 32-bit, no data consistency check) SPI Burst Read Table 79. Burst Read Bit Bit 7 Description 0 BR not available 1 BR available The SPI Burst Read bit indicates if a burst read operation is implemented. The intention of a Burst Read is e.g. used to perform a device internal memory dump to the SPI Master. The start of the Burst Read is like a normal Read Operation. The difference is, that after the SPI Data Length the CSN is not pulled high and the SCK will be continuously clocked. When the normal SCK max count is reached (SPI Data Length) the consecutive addressed data will be latched into the shift register. This procedure is performed every time when the SCK payload length is reached. In case the automatic incremented address is not used by the device, undefined data is shifted out. An automatic address overflow is implemented when address 3FH is reached. The SPI Burst Read is limited by the CSN low timeout. SPI Data Length The SPI Data Length value indicates the length of the SCK count monitor which is running for all accesses to the Device Application Registers. In case a communication frame with an SCK count not equal to the reported one will lead to a SPI Error and the data will be rejected. DS11546 Rev 5 129/197 196 Serial Peripheral Interface (SPI) L99DZ100G, L99DZ100GP Table 80. SPI Data Length Bit 6 Bit 5 Bit 4 Description DL2 DL1 DL0 0 0 0 invalid 0 0 1 16-bit SPI 0 1 0 24-bit SPI 0 1 1 32-bit SPI ... 1 1 1 64-bit SPI Data Consistency Check (Parity/CRC) N/A Table 81. Data Consistency Check Bit 1 Bit 0 Description S1 S0 0 0 not used 0 1 Parity used 1 0 CRC used 1 1 Invalid Watchdog Definition In case a watchdog is implemented the default settings can be read out via the Device Information Registers. Table 82. WD Type/Timing Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 WD1 WD0 0 0 0 1 WT5 WT4 WT3 1 1 0 1 Bit 2 Bit 1 Bit 0 WT2 WT1 WT0 0 0 0 Register is not used Watchdog Timeout / Long Open Window WT[5:0] * 5ms 1 0 OW2 OW1 OW0 CW2 CW1 CW0 1 0 0 1 0 0 0 1 Open Window OW[2:0] * 5ms 130/197 DS11546 Rev 5 Closed Window CW[2:0] * 5ms L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI) Table 82. WD Type/Timing (continued) Bit 7 Bit 6 1 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Invalid : 28H (Long Open Window: 200ms) : 91H (Open Window. 10ms, Closed Window: 5ms) indicates the Long Open Window (timeout) which is opened at the start of the watchdog. The binary value of WT[5:0] times 5ms indicates the typical value of the Timeout Time. describes the default timing of the window watchdog. The binary value of CW[2:0] times 5ms defines the typical Closed Window time and OW[2:0] times 5ms defines the typical Open Window time. Figure 58. Window watchdog operation FRUUHFWWULJJHUWLPLQJ W/2: ORQJRSHQZLQGRZ HDUO\WULJJHUWLPLQJ W&: FORVHGZLQGRZ PLVVLQJWULJJHU W2: RSHQZLQGRZ W2:) W&:W2: W&: W2: W/2: W&: W&: W2: W&: W2: W/2: RSHQZLQGRZIDLO W2:) W/2: :' 7LJJHU QRUPDO RSHUDWLRQ PLVVLQJ WULJJHU HDUO\ ZULWH WLPH ("1($'5 The watchdog trigger bit location is defined by the registers. Table 83. WD bit position Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 WB1 WB0 0 0 0 1 WBA5 WBA4 WBA3 0 1 0 0 0 1 1 1 Bit 2 Bit 1 Bit 0 WBA2 WBA1 WBA0 0 0 0 1 1 1 1 1 Register is not used Defines the register addresses of the WD trigger bits 1 0 WBA5 DS11546 Rev 5 WBA4 WBA3 WBA2 WBA1 WBA0 131/197 196 Serial Peripheral Interface (SPI) L99DZ100G, L99DZ100GP Table 83. WD bit position (continued) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Defines the stop address of the address range (previous is a WB = `01'). The consecutive has to be a WB = `11' 1 1 0 WBP 4 WBP3 WBP2 WBP1 WBP0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Defines the binary bit position of the WD trigger bit within the register : 41H;watchdog trigger bit located at address 01H (CR1) : C0H; watchdog trigger bit location is bit0 : 7FH;watchdog trigger bit located at address 3FH (Config Register) : C0H; watchdog trigger bit location is bit0 Device Application Registers (RAM) The Device Application Registers are all registers accessible using OpCode `00', `01' and `10'. The functions of these registers are defined in the device specification. 5.2.4 Protocol failure detection To realize a protocol which covers certain failsafe requirements a basic set of failure detection mechanisms are implemented. Clock monitor During communication (CSN low to high phase) a clock monitor counts the valid SCK clock edges. If the SCK edges do not correlate with the SPI Data Length an SPIE is reported with the next command and the actual communication is rejected. By accessing the Device Information Registers (OpCode = `11') the Clock Monitor is set to a minimum of 16 SCK edges plus a multiple by 8 (e.g. 16, 25, 32, ...). Providing no SCK edge during a CSN low to high phase is not recognized as an SPIE. For a SPI Burst Read also the SPI Data Length plus multiple numbers of Payloads SCK edges are assumed as a valid communication. SCK Polarity (CPOL) check To detect the wrong polarity access via SCK the internal Clock monitor is used. Providing first a negative edge on SCK during communication (CSN low to high phase) or a positive edge at last will lead to an SPI Error reported in the next communication and the actual data is rejected. SCK Phase (CPHA) check To verify, that the SCK Phase of the SPI master is set correctly a special Device Information Register is implemented. By reading this register the data must be 55H. In case AAH is read 132/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP Serial Peripheral Interface (SPI) the CPHA setting of the SPI master is wrong and a proper communication cannot be guaranteed. CSN timeout By pulling CSN low the SDO is set active and leaves its 3-state condition. To ensure communication between other SPI devices within the same bus even in case of CSN stuck at low a CSN timeout is implemented. By pulling CSN low an internal timer is started. After timer end is reached the actual communication is rejected and the SDO is set to 3-state condition. SDI stuck at GND As a communication with data all-`0' and OpCode `00' on address b'000000 cannot be distinguished between a valid command and a SDI stuck at GND this communication is not allowed. Nevertheless, in case a stuck at GND is detected the communication will be rejected and the SPIE will be set with the next communication. SDI stuck at HIGH As a communication with data all-`1' and OpCode `11' on address b'111111 cannot be distinguished between a valid command and a SDI stuck at HIGH this communication is not allowed. In case a stuck at HIGH is detected the communication will be rejected and the SPIE will be set with the next communication. SDO stuck @ The SDO stuck at GND and stuck at HIGH has to be detected by the SPI master. As the definition of the GSB guarantees at least one toggle, a GSB with all-`0' or all -`1' reports a stuck at error. DS11546 Rev 5 133/197 196 Application 6 L99DZ100G, L99DZ100GP Application Figure 59. Typical application diagram 9%$7 93URWHFWHG N aQ) )DLO6DIH 6ZLWFK2II 6+ 287 */ 287 [ /6B)6 )DLO6DIH /6B)6 [ 965(* 9B &6XSSO\ 15(6(7 95(* &LQSXW Q) 9B 95(* &$16XSSO\ 5['B&1,17 &LQSXW Q) 7HVWSRLQW 'HEXJ0RGH +6&$1 ZLWK31 ,62 7['B& &RXWSXW &$1B+ &$1B/ 5['B/1,17 &LQSXW /,1 &RXWSXW &LQSXW N /,1 7['B/ /,1 'HEXJ 1,17 :8 [7M &O [7M &O &RXWSXW &RXWSXW &RXWSXW &LQSXW &LQSXW 287 +6 6DIH/RFN :[:RU/(' 0 :RU/(' 287 +6 287 +6 287 +6 287 +6 287 +6 93URWHFWHG *+KHDWHU 6+KHDWHU 287 +6 3&KDQQHO 287B+6 +6 3&KDQQHO 96 &RXWSXW ',5 %LW $'&6$5 &RXWSXW ',5 +6 &61 &/. ', '2 0 /RFN 287 +6 965(* 63,,QWHUIDFH :LQGRZ :DWFKGRJ ([W/RDGV 0 287 3:0+ 0 <$GMXVWPHQW 287 *+ ',5+ &RXWSXW &RXWSXW ;$GMXVWPHQW 287 0 287 )ROG 0 &33 &3 96 &30 &33 &KDUJH &30 3XPS %XIIHUHG96 'ULYHU,QWHUIDFH/RJLF'LDJQRVWLF 93URWHFWHG 9%$7 aQ) aQ) (&*ODVV &RQWURO%ORFN %,763,FRQWUROOHG &RQWDFW 6XSSO\ 287 (&'5 (&9 Q) 67'1)/ &0 *1' 6*1' 3*1' Q) (6'3URWHFWLRQ IRU(&8SLQV &DSDFLWDQFHWREHGLPHQVLRQHGDFFRUGLQJORDGFXUUHQWUXOHRIWKXPE)HDFK$ &DSDFLWDQFHWREHGLPHQVLRQHGHJDFFRUGLQJYROWDJHGURSRXWUHTXLUHPHQWV 2(0UHTXLUHPHQWVDQGH[WHUQDOFRPSRQHQWVIRU/,1UHVS&$1WREHIXOOILOOHG )RU(0&RSWLPL]DWLRQSXUSRVHVFDSDFLWDQFHVFRXOGEHUHGLPHQVLRQHG)UHFRPPHQGHG Q) Q)IRU287287B+6 ("1($'5 134/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers 7 SPI Registers 7.1 Global Status Byte GSB Table 84. Global Status Byte (GSB) 31 30 29 28 27 26 25 24 Bit name GSBN RSTB SPIE PLE FE DE GW FS Reset 1 0 0 0 0 0 0 0 Access R Table 85. GSB signals description Bit 31 30 29 Name Description GSBN Global Status Bit Inverted The GSBN is a logically NOR combination of GSB Bits 24 to Bit 30(1). This bit can also be used as Global Status Flag without starting a complete communication frame as it is present at SDO directly after pulling CSN low. 0: error detected (1 or several GSB bits from 24 to 30 are set) 1: no error detected (default after Power-on) Specific failures may be masked in the Configuration Register 0x3F. A masked failure will still be reported in the GSB by the related failure flag, however it is not reflected in the GSBN (bit 31). RSTB Reset The RSTB indicates a device reset and it is set in case of the following events: - VPOR (SR1 - 0x31) - WDFAIL (SR1 - 0x31) - V1UV (SR1 - 0x31) - FORCED_SLEEP_TSD2/V1SC (SR1 - 0x31) 0: no reset signal has been generated (default) 1: Reset signal has been generated RSTB is cleared by a Read & Clear command to all bits in Status Register 1 causing the Reset event. SPIE(2) SPI Error Bit The SPIE indicates errors related to a wrong SPI communication. - SPI_INV_CMD (SR2 - 0x32) - SPI_SCK_CNT (SR2 - 0x32) The bit is also set in case of an SPI CSN Time-out detection 0: no error (default) 1: error detected SPIE is cleared by a valid SPI command. DS11546 Rev 5 135/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 85. GSB signals description (continued) Bit 28 27 136/197 Name PLE(2) FE Description Physical Layer Error The PLE is a logical OR combination of errors related to the LIN and CAN transceivers. - LIN_PERM_DOM (SR2 - 0x32) - LIN_TXD_DOM (SR2 - 0x32) - LIN_PERM_REC (SR2 - 0x32) - CAN_RXD_REC (SR2 - 0x32) - CAN_PERM_REC (SR2 - 0x32) - CAN_PERM_DOM (SR2 - 0x32) - CAN_TXD_DOM (SR2 - 0x32) - SYSERR (SR12 - 0x3C) - OSC_FAIL (SR12 - 0x3C) - FDERR (SR12 - 0x3C) 0: no error (default) 1: error detected PLE is cleared by a Read & Clear command to all related bits in Status Registers 2 and 12. Functional Error Bit The FE is a logical OR combination of errors coming from functional blocks. - V2SC (SR2 - 0x32) - DSMON_HSx (SR2 - 0x32) - DSMON_LSx (SR2 - 0x32) - OUTxHS_OC TH EX (SR3 - 0x33) - OUTxLS_OC TH EX (SR3 - 0x33) - OUTHS_OC TH EX (SR3 - 0x33) - OUTx_OC (SR3 - 0x33) - LSxFS_OC (SR3 - 0x33) - ECV_OC (SR4 - 0x34) - DSMON_HEAT (SR4 - 0x34) - OUTxHS_OL (SR5 - 0x35)(3) - OUTxLS_OL (SR5 - 0x35) - OUTx_OL (SR5 - 0x35) - OUTHS_OL (SR5 - 0x35) - GH_OL (SR5 - 0x35) - ECV_OL (SR5 - 0x35) 0: no error (default) 1: error detected FE is cleared by a Read & Clear command to all related bits in Status Registers 2, 3, 4, 5 DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 85. GSB signals description (continued) Bit 26 25 Name DE GW (2) Description Device Error Bit DE is a logical OR combination of global errors related to the device. - VS_OV (SR2 - 0x32) - VS_UV (SR2 - 0x32) - VSREG_OV (SR2 - 0x32) - VSREG_UV (SR2 - 0x32) - CP_LOW (SR2 - 0x32) - TSD1_CLx (SR6 - 0x36) 0: no error (default) 1: error detected DE is cleared by a Read & Clear command to all related bits in Status Registers 2 and 6 Global Warning Bit GW is a logical OR combination of warning flags. Warning bits do not lead to any device state change or switch off of functions. - VSREG_EW (SR2 - 0x32) - V1_FAIL (SR2 - 0x32) - V2_FAIL (SR2 - 0x32) - CAN_SUP_LOW (SR2 - 0x32) - TW (3) (SR2 - 0x32) - SPI_INV_CMD (SR2 - 0x32) - SPI_SCK_CNT (SR2 - 0x32) 0: no error (default) 1: error detected GW is cleared by a Read & Clear command to all related bits in Status Register 2. DS11546 Rev 5 137/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 85. GSB signals description (continued) Bit 24 Name FS Description Fail Safe The FS bit indicates the device was forced into a safe state due to the following failure conditions: - WDFAIL (SR1 - 0x31) - V1UV (SR1 - 0x31) - TSD2 (SR1 - 0x31) - FORCED_SLEEP_TSD/V1SC (SR1 - 0x31) All Control Registers are set to default except the following bits: - SWEN (CR1 - 0x01) - CR23 (0x17) to CR29 (0x1D); Configuration of CAN Selective Wake-up functionality Control Registers are blocked for WRITE access except the following bits: - TRIG (CR1 - 0x01) - V2_0 (CR1 - 0x01) - V2_1 (CR1 - 0x01) - GoTRXRDY (CR1 - 0x01) - Timer settings (bits 8...23) (CR2 - 0x02) - OUTHS_x (bits 0...3) (CR5 - 0x05) - OUT15_x (bits 0...3) (CR6 - 0x06) - CR12 (0x0C) to CR17 (0x11); PWM frequency and duty cycles 0: Fail Safe inactive (default) 1: Fail Safe active FS is cleared upon exit from Fail-Safe mode (refer to chapter `Fail-Safe mode') 1. Individual failure flags may be masked in the Configuration Register (0x3F). 2. Bit may be masked in the Configuration Register (0x3F), i.e. the bit will not be included in the Global Status Bit (GSBN). 3. Open-load status flags may be masked in the Configuration register (0x3F), i.e. the open-load flag will be included in the FE flag, but will not set the GSBN. TW failure status flags may be masked in the Configuration register (0x3F), i.e. the TW flag will be included in the GW flag, but will not set the GSBN. 138/197 DS11546 Rev 5 OUT9_3 OUT9_2 OUT9_1 OUT9_0 OUT11_3 OUT11_2 OUT11_1 OUT11_0 0x07 CR7 OUT2_OCR OUT3_OCR OUT4_OCR OUT5_OCR OUT6_OCR OUT7_OCR OUT8_OCR DS11546 Rev 5 T2_PER_0 LIN_REC_ONLY VSREG_EWTH_8 VSREG_EWTH_7 OUT13_1 OUT10_1 OUT4_HS OUT13_0 OUT10_0 OUT4_LS OUT14_3 OUT14_2 Reserved HS_TON_0 OCR_FREQ OUT5_OC1 OUT5_OC0 OUT15_3 OUTHS_3 OUT15_2 OUTHS_2 OUT15_1 OUTHS_1 OUT6_HS CM_SEL_3 CM_SEL_2 CM_SEL_1 R/W R/W R/W R/W R/W R/W TRIG GO_STBY Access 0 R/W WD_TIME_0 WD_TIME_1 VSREG_EWTH_1 STBY_SEL 1 VSREG_EWTH_0 V1_RESET_0 VSREG_EWTH_2 PARITY 2 OUT15_0 OUTHS_0 OUT6_LS V1_RESET_1 VSREG_EWTH_3 V2_0 3 CM_SEL_0 PNW_EN VSREG_EWTH_4 V2_1 4 Reserved CAN_LOOP_EN VSREG_EWTH_5 5 OUT5_LS OUT14_0 Reserved OUT5_HS 6 OUT14_1 HEN 7 CM_EN LIN_TXD_TOUT_EN VSREG_EWTH_6 SWEN CAN_Go_TRX_RDY CAN_TXEN CAN_RXEN 8 Reserved T2_PER_2 CANTO_IRQ_EN CAN_WU_EN LIN_WU_EN Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 GH T2_PER_1 VSREG_EWTH_9 OUT13_2 OUT10_2 T2_ON_0 HS_TON_1 Reserved OUT13_3 OUT10_3 T2_ON_1 T2_ON_2 HB_TON_0 OUT3_LS OUT3_HS TIMER_NINT_EN TIMER_NINT_WAKE_SEL T2_RESTART T2_DIR WU_FILT_0 T1_PER_0 Reserved WU_FILT_1 T1_PER_2 VS_UV_SD_EN WU_PU T1_PER_1 T1_ON_0 VS_OV_SD_EN Reserved OUT12_0 Reserved Reserved OUT2_LS OUT2_HS Reserved T1_ON_1 OUT1_LS VSREG_UV_SD_EN Reserved WU_EN Reserved 0x00 HB_TON_1 OUT12_1 OUT12_2 OUT8_0 OUT8_1 OUT8_2 OUT8_3 OUT7_0 VS_LOCK_EN T1_ON_2 T1_DIR VSREG_LOCK_EN OUT1_HS VSREG_OV_SD_EN T1_RESTART 0x03 CR3 OUT7_1 0x02 CR2 Reserved 0x05 CR5 OUT7_2 0x04 CR4 Reserved 0x01 CR1 OUT7_3 7.2 OUTHS_OCR OUT12_3 0x06 CR6 OUT1_OCR L99DZ100G, L99DZ100GP SPI Registers Control register overview Table 86. Control register overview Bit reserved 139/197 196 Reserved 0x0D CR13 140/197 PMW1_FREQ_0 PMW1_FREQ_1 0x0C CR12 Reserved 0x0F CR15 DS11546 Rev 5 Reserved Reserved PMW7_FREQ_0 PMW7_FREQ_1 SLEW_2 SLEW_1 SLEW_0 EC_2 EC_1 EC_0 Reserved R/W R/W R/W Reserved R/W Access 0 R/W OUT9_OC 1 R/W PWM6_DC_0 PWM4_DC_0 PWM2_DC_0 OUT10_OC OUT11_OC 2 PWM6_DC_1 PWM4_DC_1 PWM2_DC_1 PWM6_DC_2 PWM4_DC_2 PWM2_DC_2 OUT12_OC 3 R/W SLEW_3 EC_3 OUT13_OC 4 R/W SLEW_4 EC_4 PWM6_DC_4 PWM4_DC_4 PWM2_DC_4 PMW10_FREQ_0 OUT14_OC 5 PWM6_DC_3 PWM4_DC_3 PWM2_DC_3 OL_H2L1 OUT15_OC OUTHS_OC 6 EC_5 OL_H1L2 H_OLTH_HIGH OUT9_OL OUT10_OL OUTHS_OCR_THX_EN OUT8_OCR_THX_EN OUT7_OCR_THX_EN OUT6_OCR_THX_EN OUT5_OCR_THX_EN OUT4_OCR_THX_EN 7 PWM6_DC_5 PWM4_DC_5 PWM2_DC_5 PMW10_FREQ_1 PWM6_DC_6 PWM4_DC_6 PWM2_DC_6 PMW9_FREQ_0 ECON Reserved COPT_0 Reserved COPT_2 COPT_1 OUT12_OL COPT_3 OUT11_OL OUT13_OL OUT14_OL OUT15_OL OUTHS_OL SDS SD Reserved GH_TH_0 GH_TH_1 GH_TH_2 Reserved GH_OL_EN 8 PWM6_DC_7 PWM4_DC_7 PWM2_DC_7 PMW9_FREQ_1 DIAG_1 Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 PWM6_DC_8 PWM4_DC_8 PWM2_DC_8 PMW8_FREQ_0 PWM6_DC_9 PWM4_DC_9 PWM2_DC_9 PMW8_FREQ_1 Reserved PWM5_DC_0 PWM3_DC_0 PWM1_DC_0 PMW6_FREQ_0 ECV_OCR ECV_LS Reserved PWM5_DC_1 PWM3_DC_1 PWM1_DC_1 PMW6_FREQ_1 PWM5_DC_2 PWM3_DC_2 PWM1_DC_2 PMW5_FREQ_0 OUT8_RDSON DIAG_2 Reserved PWM5_DC_3 PWM3_DC_3 PWM1_DC_3 PMW5_FREQ_1 PWM5_DC_4 PWM3_DC_4 PWM1_DC_4 PMW4_FREQ_0 PWM5_DC_5 PWM3_DC_5 PWM1_DC_5 PMW4_FREQ_1 PWM5_DC_6 PWM3_DC_6 PWM1_DC_6 PMW3_FREQ_0 PWM5_DC_7 PWM3_DC_7 PWM1_DC_7 PMW3_FREQ_1 0x0B CR11 PWM5_DC_8 PWM3_DC_8 PWM1_DC_8 PMW2_FREQ_0 OUT2_OCR_THX_EN OUT7_RDSON 0x0A CR10 OUT3_OCR_THX_EN OUT1_OCR_THX_EN 0x09 CR9 DIAG_0 0x08 CR8 PWM5_DC_9 PWM3_DC_9 PWM1_DC_9 PMW2_FREQ_1 0x0E CR14 Reserved SPI Registers L99DZ100G, L99DZ100GP Table 86. Control register overview (continued) Bit Reserved OUT9_AUTOCOMP_EN OUT9_VLED_9 OUT9_VLED_8 OUT9_VLED_7 OUT9_VLED_6 OUT9_VLED_5 OUT9_VLED_4 OUT9_VLED_3 OUT9_VLED_2 OUT9_VLED_1 OUT9_VLED_0 Reserved 0x14 CR20 OUT11_AUTOCOMP_EN OUT11_VLED_9 OUT11_VLED_8 OUT11_VLED_7 OUT11_VLED_6 OUT11_VLED_5 OUT11_VLED_4 OUT11_VLED_3 OUT11_VLED_2 OUT11_VLED_1 OUT11_VLED_0 Reserved 0x12 CR18 DS11546 Rev 5 PWM9_DC_3 PWM7_DC_3 PWM9_DC_2 PWM7_DC_2 PWM9_DC_1 PWM7_DC_1 PWM9_DC_0 PWM7_DC_0 OUT7_VLED_3 OUT7_VLED_2 OUT7_VLED_1 OUT7_VLED_0 OUT10_VLED_5 OUT10_VLED_4 OUT10_VLED_3 OUT10_VLED_2 OUT10_VLED_1 OUT12_VLED_5 OUT12_VLED_4 OUT12_VLED_3 OUT12_VLED_2 OUT12_VLED_1 R/W R/W Access 0 R/W PWM10_DC_0 PWM8_DC_0 1 OUT8_VLED_0 PWM10_DC_1 PWM8_DC_1 2 OUT8_VLED_1 PWM10_DC_2 PWM8_DC_2 3 OUT8_VLED_2 PWM10_DC_3 PWM8_DC_3 4 OUT8_VLED_3 PWM10_DC_4 PWM8_DC_4 PWM10_DC_5 PWM8_DC_5 PWM10_DC_6 PWM8_DC_6 5 OUT8_VLED_4 OUT8_VLED_5 OUT8_VLED_6 PWM10_DC_7 PWM8_DC_7 6 R/W OUT10_VLED_6 OUT12_VLED_6 OUT8_VLED_7 PWM10_DC_8 PWM8_DC_8 7 R/W OUT10_VLED_7 OUT12_VLED_7 OUT8_VLED_8 PWM10_DC_9 PWM8_DC_9 8 OUT10_VLED_0 OUT10_VLED_8 OUT12_VLED_8 OUT8_VLED_9 Reserved PWM9_DC_4 PWM7_DC_4 OUT7_VLED_4 Reserved PWM9_DC_5 PWM7_DC_5 OUT7_VLED_5 Reserved PWM9_DC_6 PWM7_DC_6 PWM9_DC_7 PWM7_DC_7 PWM9_DC_8 PWM7_DC_8 Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OUT12_VLED_0 OUT10_VLED_9 OUT12_VLED_9 Reserved PWM9_DC_9 PWM7_DC_9 Reserved OUT7_VLED_6 OUT7_VLED_7 OUT7_VLED_8 OUT7_VLED_9 OUT7_AUTOCOMP_EN 0x11 CR17 Reserved 0x10 CR16 OUT12_AUTOCOMP_EN OUT10_AUTOCOMP_EN OUT8_AUTOCOMP_EN 0x13 CR19 Reserved L99DZ100G, L99DZ100GP SPI Registers Table 86. Control register overview (continued) Bit 141/197 196 0x1B CR27 142/197 0x1A CR26 Reserved DS11546 Rev 5 DLC_1 DLC_0 Reserved EXT_ID_MASK_13 EXT_ID_MASK_12 EXT_ID_MASK_11 DATA_BYTE2_5 DATA_BYTE2_4 DATA_BYTE2_3 EXT_ID_MASK_9 EXT_ID_MASK_8 EXT_ID_MASK_7 EXT_ID_MASK_6 EXT_ID_MASK_5 EXT_ID_MASK_4 EXT_ID_MASK_3 EXT_ID_MASK_2 EXT_ID_MASK_1 EXT_ID_MASK_0 R/W ID_MASK_9 ID_MASK_8 ID_MASK_7 ID_MASK_6 ID_MASK_5 ID_MASK_4 ID_MASK_3 ID_MASK_2 ID_MASK_1 ID_MASK_0 R/W DATA_BYTE2_1 DATA_BYTE2_0 DATA_BYTE1_7 DATA_BYTE1_6 DATA_BYTE1_5 DATA_BYTE1_4 DATA_BYTE1_3 DATA_BYTE1_2 DATA_BYTE1_1 DATA_BYTE1_0 R/W DATA_BYTE2_2 ID_MASK_10 EXT_ID_MASK_10 R/W R/W OUTHS_VLED_0 R/W OUT14_VLED_0 OUT14_VLED_1 Access 0 R/W EXT_ID_0 OUTHS_VLED_1 OUT14_VLED_2 1 ID_0 EXT_ID_1 OUTHS_VLED_2 OUT14_VLED_3 2 ID_1 EXT_ID_2 OUTHS_VLED_3 OUT14_VLED_4 3 ID_2 EXT_ID_3 OUTHS_VLED_4 OUT14_VLED_5 4 ID_3 EXT_ID_4 OUTHS_VLED_5 OUT14_VLED_6 OUT14_VLED_7 OUT14_VLED_8 OUT14_VLED_9 5 ID_4 EXT_ID_5 OUTHS_VLED_6 OUTHS_VLED_7 OUTHS_VLED_8 OUTHS_VLED_9 6 ID_5 EXT_ID_6 EXT_ID_7 EXT_ID_8 EXT_ID_9 7 ID_6 Reserved OUT13_VLED_0 OUT13_VLED_1 8 ID_7 Reserved OUT15_VLED_0 OUT15_VLED_1 OUT13_VLED_2 EXT_ID_10 OUTHS_AUTOCOMP_EN OUT14_AUTOCOMP_EN EXT_ID_11 EXT_ID_12 EXT_ID_13 EXT_ID_14 OUT13_VLED_3 OUT13_VLED_4 OUT13_VLED_5 OUT13_VLED_6 OUT13_VLED_7 OUT13_VLED_8 OUT13_VLED_9 Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ID_8 ID_9 ID_10 DLC_2 EXT_ID_MASK_14 DATA_BYTE2_6 OUT15_VLED_2 OUT15_VLED_3 EXT_ID_15 DLC_3 EXT_ID_MASK_15 DATA_BYTE3_0 DATA_BYTE3_1 DATA_BYTE2_7 OUT15_VLED_6 OUT15_VLED_7 OUT15_VLED_8 OUT15_VLED_9 OUT15_VLED_4 Reserved EXT_ID_MASK_16 SAMPLE_0 EXT_ID_16 Reserved OUT15_VLED_5 SAMPLE_2 SAMPLE_3 BR_0 BR_1 Reserved EXT_ID_MASK_17 SAMPLE_1 EXT_ID_17 DATA_BYTE3_2 DATA_BYTE3_3 DATA_BYTE3_4 0x19 CR25 DATA_BYTE3_5 0x17 CR23 OUT15_AUTOCOMP_EN OUT13_AUTOCOMP_EN Reserved 0x16 CR22 CAN_IDE 0x15 CR21 DATA_BYTE3_6 Reserved 0x18 CR24 DATA_BYTE3_7 SPI Registers L99DZ100G, L99DZ100GP Table 86. Control register overview (continued) Bit 0x3F Note: Conf Reg DS11546 Rev 5 DATA_BYTE8_0 DATA_BYTE5_0 DATA_BYTE7_7 DATA_BYTE4_7 DATA_BYTE7_6 DATA_BYTE4_6 DATA_BYTE7_5 DATA_BYTE4_5 DATA_BYTE7_4 DATA_BYTE4_4 DATA_BYTE7_3 DATA_BYTE4_3 MASK_GW CP_OFF_EN CP_LOW_CONFIG CP_DITH_DIS FS_FORCED CAN_SUP_5V2_EN 4 3 2 R/W R/W Access 0 R/W WD_EN DATA_BYTE7_0 DATA_BYTE4_0 1 R/W 5 TRIG 6 DATA_BYTE7_1 DATA_BYTE4_1 7 ICMP 8 CP_OFF DATA_BYTE7_2 DATA_BYTE4_2 DATA_BYTE8_1 DATA_BYTE5_1 MASK_PLE Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Reserved DATA_BYTE8_2 DATA_BYTE5_2 MASK_SPIE DATA_BYTE8_4 DATA_BYTE5_4 DATA_BYTE8_5 DATA_BYTE5_5 DATA_BYTE8_6 DATA_BYTE5_6 DATA_BYTE8_3 DATA_BYTE5_3 Reserved MASK_OL MASK_EC_OL MASK_TW 0x22 CR34 MASK_OL_LS1 DATA_BYTE6_0 DATA_BYTE6_1 DATA_BYTE6_2 DATA_BYTE6_3 DATA_BYTE6_4 DATA_BYTE6_5 DATA_BYTE6_6 DATA_BYTE8_7 DATA_BYTE5_7 Reserved MASK_OL_HS1 WD_CONFIG_EN ICMP_CONFIG_EN DM ECV_HV TSD_CONFIG 0x1D CR29 LIN_HS_EN LIN_WU_CONFIG DATA_BYTE6_7 0x1C CR28 WU_CONFIG L99DZ100G, L99DZ100GP SPI Registers Table 86. Control register overview (continued) Bit All reserved bits (RES) are read-only (R) and will be read as `0'. Writing `1' to a reserved bit is ignored and does not cause an SPI error. 143/197 196 144/197 WU_WAKE WAKE_CAN WAKE_LIN CAN_RXD_REC OUT3_HS_OL OUT3_HS_OCR_ALERT OUT3_HS_OC_TH_EX CAN_PERM_REC OUT3_LS_OL OUT3_LS_OCR_ALERT OUT3_LS_OC_TH_EX CAN_PERM_DOM DS11546 Rev 5 WDFAIL_CNT_1 WDFAIL_CNT_0 DEVICE_STATE_1 DEVICE_STATE_0 TSD2 TSD1 FORCED_SLEEP_TSD2/V1SC CP_LOW TW V2SC V2FAIL V1FAIL VSREG_EW VSREG_OV OUT9_OC OUT10_OC OUT11_OC OUT12_OC OUT13_OC OUT14_OC OUT15_OC FORCED_SLEEP_WD WDFAIL VPOR VSREG_UV VS_OV VS_UV R OUTHS_OC_TH_EX LS2FSO_OC LS1FSO_OC R OUTHS_OCR_ALERT DSMON_HEAT ECV_OC R GH_OL ECV_OL Reserved R OUTHS_OL OUT15_OL OUT14_OL OUT13_OL OUT12_OL OUT11_OL Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OUT10_OL OUT9_OL WDFAIL_CNT_2 SPI_SCK_CNT OUT8_OC_TH_EX OUT8_OCR_ALERT OUT8_OL V1_RESTART_0 DSMON_LS1 OUT6_LS_OL OUT6_LS_OCR_ALERT OUT6_LS_OC_TH_EX WDFAIL_CNT_3 V1_RESTART_1 DSMON_LS2 OUT6_HS_OL OUT6_HS_OCR_ALERT OUT6_HS_OC_TH_EX SPI_INV_CMD V1_RESTART_2 DSMON_HS1 OUT5_LS_OL OUT5_LS_OCR_ALERT OUT5_LS_OC_TH_EX OUT7_OC_TH_EX V1UV DSMON_HS2 OUT5_HS_OL OUT5_HS_OCR_ALERT OUT5_HS_OC_TH_EX OUT7_OCR_ALERT DEBUG_ACTIVE CAN_SUP_LOW OUT4_LS_OL OUT4_LS_OCR_ALERT OUT4_LS_OC_TH_EX OUT7_OL WAKE_TIMER CAN_TXD_DOM OUT4_HS_OL OUT4_HS_OCR_ALERT OUT4_HS_OC_TH_EX OUT2_LS_OL OUT2_LS_OCR_ALERT OUT2_LS_OC_TH_EX Reserved Bit Access 7.3 OUT2_HS_OL OUT2_HS_OCR_ALERT OUT2_HS_OC_TH_EX LIN_PERM_REC WU_STATE LIN_TXD_DOM OUT1_LS_OL OUT1_LS_OCR_ALERT OUT1_LS_OC_TH_EX 0x35 SR5 Reserved 0x34 SR4 0x32 SR2 LIN_PERM_DOM 0x33 SR3 0x31 SR1 OUT1_HS_OL OUT1_HS_OCR_ALERT OUT1_HS_OC_TH_EX SPI Registers L99DZ100G, L99DZ100GP Status register overview Table 87. Status register overview 8 7 6 5 4 3 2 1 0 R 0x3A SR10 0x3B SR11 0x3C SR12 VSREG_2 TEMP_CL6_2 TEMP_CL4_2 TEMP_CL2_2 VSREG_1 TEMP_CL6_1 TEMP_CL4_1 TEMP_CL2_1 VSREG_0 TEMP_CL6_0 TEMP_CL4_0 TEMP_CL2_0 VS_2 VS_1 VS_0 SWRD_CR29 SWRD_CR28 SWRD_CR27 DS11546 Rev 5 VWU_6 OSC_FAIL VWU_4 VWU_3 VWU_2 VWU_1 VWU_0 R TX_SYNC CANTO WUP WUF FDERR 5 4 3 2 1 0 TSD1_CL6 TSD1_CL5 TSD1_CL4 TSD1_CL3 TSD1_CL2 TSD1_CL1 TEMP_CL5_4 TEMP_CL3_4 TEMP_CL1_4 TEMP_CL5_3 TEMP_CL3_3 TEMP_CL1_3 TEMP_CL5_2 TEMP_CL3_2 TEMP_CL1_2 TEMP_CL5_1 TEMP_CL3_1 TEMP_CL1_1 TEMP_CL5_0 TEMP_CL3_0 TEMP_CL1_0 Reserved 6 TEMP_CL5_5 TEMP_CL3_5 TEMP_CL1_5 TEMP_CL5_6 TEMP_CL3_6 TEMP_CL1_6 TEMP_CL5_7 TEMP_CL3_7 TEMP_CL1_7 7 CAN_SILENT VWU_5 VWU_7 TW_CL1 TEMP_CL5_8 TEMP_CL3_8 TEMP_CL1_8 8 SYSERR TW_CL2 TEMP_CL5_9 TEMP_CL3_9 TEMP_CL1_9 TW_CL3 TW_CL4 Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 SWRD_CR23 VWU_8 SWRD_CR24 VWU_9 SWRD_CR25 Reserved VSREG_3 TEMP_CL6_3 TEMP_CL4_3 TEMP_CL2_3 VS_3 Reserved Reserved VSREG_4 TEMP_CL6_4 TEMP_CL4_4 TEMP_CL2_4 VS_4 FECNT_0 Reserved TW_CL5 VSREG_5 TEMP_CL6_5 TEMP_CL4_5 TEMP_CL2_5 VS_5 FECNT_1 Reserved TW_CL6 VSREG_6 TEMP_CL6_6 TEMP_CL4_6 TEMP_CL2_6 VS_6 FECNT_2 SWRD_CR26 ECV_VHI VSREG_7 TEMP_CL6_7 TEMP_CL4_7 TEMP_CL2_7 VS_7 FECNT_3 Reserved Reserved ECV_VNR VSREG_8 TEMP_CL6_8 TEMP_CL4_8 TEMP_CL2_8 VS_8 WD_TIMER_STATE_0 WD_TIMER_STATE_1 FECNT_4 Reserved 0x39 SR9 VSREG_9 TEMP_CL6_9 TEMP_CL4_9 TEMP_CL2_9 Reserved 0x38 SR8 VS_9 Reserved 0x37 SR7 Reserved 0x36 SR6 Reserved Reserved Bit Access L99DZ100G, L99DZ100GP SPI Registers Table 87. Status register overview Reserved R R R R R R 145/197 196 SPI Registers L99DZ100G, L99DZ100GP 7.4 Control registers 7.4.1 Control Register CR1 (0x01) Table 88. Control Register CR1 SWEN HEN V2_1 V2_0 PARITY STBY_SEL GO_STBY TRIG 0 CAN_ Go_TRX_RDY 1 CAN_TXEN 2 CAN_RXEN R/W 3 CANTO_ IRQ_EN R 4 CAN_WU_EN(1) R R/W 5 LIN_WU_EN(1) Access 0 6 TIMER_NINT_EN 0 7 TIMER_NI0NT_WAKE_SEL 0 8 WU_FILT_0 1 9 WU_FILT_1 0 19 18 17 16 15 14 13 12 11 10 Reserved Reset Bit name WU_PU 20 Reserved 21 WU_EN 22 Reserved 23 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 R R/W 1. Either LIN or CAN must be enabled as wake-up source. Setting both bits 12 and 13 to '0' is an invalid setting. In this case, both bits will be set to '1' (wake-up enabled; default) and the SPI Error Bit (SPIE) in the Global Status Byte will be set. Table 89. CR1 signals description Bit Name 23 Reserved 22 WU_EN 21 Reserved 20 19 18 WU_PU Reserved 17 WU_FILT_1 16 WU_FILT_0 15 146/197 Description -- Wake-up Input 1 (WU) enable(1) 0: WU disabled 1: WU enabled (default) -- Wake-up Input1 Pull-up/down configuration: configuration of internal current source(1) 0: pull-down (default) 1: pull-up -- Wake-up Input1 Filter configuration Bits: configuration of input filter(1) See Table 90: Wake-up input1 filter configuration Select Timer for NINT / Wake: select timer for periodic interrupt in standby modes TIMER_NINT_WAKE_SEL 0: Timer 2 (default) 1: Timer 1 DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 89. CR1 signals description (continued) Bit 14 13 12 Name Description TIMER_NINT_EN LIN_WU_EN (2) CAN_WU_EN (2) 11 CANTO_ IRQ_EN 10 CAN_ RXEN 9 CAN_TXEN 8 7 CAN_Go_TRX_RDY SWEN 6 HEN 5 V2_1 4 V2_0 Timer NINT enable: enable timer interrupt in standby modes 0: timer interrupt disabled (default) 1: timer interrupt enabled V1_standby mode: periodic NINT pulse generated by timer (NINT pulse at start of timer on-phase) Vbat_standby mode: device wakes up after timer expiration and generates NReset LIN Wake-up enable: enable wake-up by LIN(3) 0: disabled 1: enabled (default) CAN Wake-up enable: enable wake-up by CAN(4) 0: disabled 1: enabled (default) CANTO Interrupt enable: enables interrupt signal in case of CAN timeout 0: CAN TO interrupt disabled 1: CAN TO interrupt enabled (default) CAN transceiver configuration See Table 91: CAN transceiver mode CAN Transceiver transition into TRX READY mode. 0: CAN transceiver in TRX BIAS mode (default) 1: CAN transceiver is sent into TRX READY mode At Exit from TRX READY mode, this bit is set to '0' automatically. CAN Flash mode: CAN Go TRX RDY is set to '1' automatically After power-on, this bit should be set to '0' and a clear command should be sent to status registers. CAN Selective Wake-up enable: enable selective wake-up for CAN(5) 0: No Selective Wakeup (default) 1: Selective Wakeup enabled Enable H-bridge 0: H-bridge disabled (default) 1: H-bridge enabled Refer to chapter H-bridge Control for details Voltage Regulator V2 Configuration See Table 92: Voltage regulator V2 configuration DS11546 Rev 5 147/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 89. CR1 signals description (continued) Bit Name Description 3 PARITY 2 STBY_SEL 1 GO_STBY PARITY: Standby Command Parity Bit STBY SEL: Select Standby mode GO_STBY: Execute transition into Standby mode The STBY_SEL and GO_STBY bits are protected by a parity check. The bits STBY_SEL, GO_STBY and PARITY must represent an even number of '1', otherwise the command is ignored and the SPI_INV_CMD bit is set. Table 93: Standby transition configuration shows the valid settings. All other settings are invalid; command will be ignored and SPI_INV_CMD will be set. The GO_STBY bit is not cleared automatically after wake-up. 0 TRIG Watchdog Trigger Bit 1. Setting is only valid if input is configured as wake-up input in Configuration Register (0x3F). 2. Either LIN or CAN must be enabled as wake-up source. Setting both bits 12 and 13 to '0' is an invalid setting. All wake-up sources will be configured according to default setting; SPI Error Bit (SPIE) in Global Status Byte will be set. 3. The wake-up behavior is configurable in the Configuration Register (0x3F). 4. Wake-up occurs at a wake -up event according to ISO 11898-5:2007 (default) Wake-up according ISO 11898-6:2013 (selective wake-up) is configurable (refer to chapter High Speed CAN Bus Transceiver). 5. A dedicated procedure must be followed to set SWEN (CR 1) = 1 (refer to chapter High Speed CAN Bus Transceiver). Table 90. Wake-up input1 filter configuration WU_FILT_1 WU_FILT_0 0 0 Wake-up inputs monitored in static mode (filter time twu_stat) (default) 0 1 Wake- up inputs monitored in cyclic mode with Timer2 (filter time: tWU_cyc; blanking time 80% of timer ON time) 1 0 Wake- up inputs monitored in cyclic mode with Timer1 (filter time: tWU_cyc; blanking time 80% of timer ON time) 1 1 Invalid setting; command will be ignored and SPI INV CMD will be set Table 91. CAN transceiver mode CAN_RXEN CAN_TXEN 0 x 0 x 1 0 TRX Listen: Receiver enabled, Transmitter disabled 1 1 TRX Normal(1): Receiver enabled, Transmitter enabled TRX Standby: Receiver disabled, Transmitter disabled 1. CAN Flash mode: TRX Normal Mode functionality is configured automatically but SPI registers are not updated. 148/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 92. Voltage regulator V2 configuration 1. V2_1 V2_0 0 0 V2 OFF in all modes (default) 0 1 V2 ON in Active mode; OFF in Standby modes 1 0 V2 ON in Active and V1_standby mode; OFF in Vbat_standby mode 1 1 V2 ON in all modes(1) This configuration will not be taken into account if CAN_SUP_5V2_EN = 1. Table 93. Standby transition configuration 7.4.2 PARITY STBY_SEL GO_STBY 0 1 1 Go to V1 standby 1 0 1 Go to Vbat_standby 0 0 0 1 1 0 No transition to standby Control Register CR2 (0x02) T2_ON_0 WD_TIME_0 T2_ON_1 0 WD_TIME_1 T2_ON_2 1 V1_RESET_0 T2_DIR 2 V1_RESET_1 T2_RESTART 3 PNW_EN T1_PER_0 4 CAN_LOOP_EN T1_PER_1 5 LIN_TXD_TOUT_EN T1_PER_2 6 LIN_REC_ONLY T1_ON_0 7 T2_PER_0 19 18 17 16 15 14 13 12 11 10 T1_ON_1 8 T2_PER_1 20 0 0 0 0 0 0 0 0 0 0 0 0 0 Access 9 T2_PER_2 21 T1_ON_2 Reset 22 T1_DIR Bit name 23 T1_RESTART Table 94. Control Register CR2 0 0 0 0 1 0 0 0 0 0 0 R/W Table 95. CR2 signals description Bit Name 23 T1_RESTART 22 T1_DIR1 21 T1_ON_2 20 T1_ON_1 19 T1_ON_0 Description Timer 1 Restart: Restart of Timer 1 0: timer is running with period and on-time according to configuration (default) 1: restart of timer at CSN low to high transition; starting with ON phase(1) Bit is automatically reset with next SPI frame. T1_DIR1: Timer 1 Direct Drive by DIR1 T1_ON_x: Timer 1 On-Time Bits Configuration of Timer 1 on-time, for details see Table 96 and Figure 60 DS11546 Rev 5 149/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 95. CR2 signals description (continued) Bit Name 18 T1_PER_2 17 T1_PER_1 16 T1_PER_0 15 T2_RESTART 14 T2_DIR1 13 T2_ON_2 12 T2_ON_1 11 T2_ON_0 10 T2_PER_2 9 T2_PER_1 8 T2_PER_0 7 LIN_REC_ONLY 6 5 150/197 Description Configuration of Timer 1 Period 000: T1 (default) 001: T2 010: T3 011: T4 100: T5 101: T6 110: T7 111: T8 Timer 2 Restart: restart of timer 2 0: timer is running with period and on-time according to configuration (default) 1: restart of timer at CSN low to high transition; starting with ON phase(1) Bit is automatically reset with next SPI frame. T2_DIR1: Timer 2 Direct Drive by DIR1 T2_ON_x: Timer 2 On-Time Bits Configuration of Timer 2 on-time, for details see Table 96 and Figure 60 Configuration of Timer 2 Period 000: T1 (default) 001: T2 010: T3 011: T4 100: T5 101: T6 110: T7 111: T8 LIN Transceiver Receive Only mode 0: LIN receive only mode disabled (default) 1: LIN receive only mode enabled LIN TxD Timeout Enable LIN_TXD_TOUT_EN 0: LIN TxD timeout detection disabled 1: LIN TxD timeout detection enabled (default) CAN_LOOP_EN CAN Loop Enable: CAN Looping of TxDC to RxDC 0: CAN looping disabled (default) 1: CAN looping enabled DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 95. CR2 signals description (continued) Bit Name 4 PNW_EN 3 V1_RESET_1 2 V1_RESET_0 1 WD_TIME_1 0 WD_TIME_0 Description CAN Pretented Networking mode A WUP leads to transition into TRX Bias mode and an interrupt is generated. 0: pretended networking disabled (default) 1: pretended networking enabled This bit can only be set to '1' if: SWEN = 0 (selective wake-up disabled) CAN RXEN = 1 The bit is automatically reset to '0' if selective wake-up is enabled (SWEN = 1) device enters Vbat_standby mode Voltage Regulator V1 Reset Threshold 00: Vrt4 (default) 01: Vrt3 10: Vrt2 11: Vrt1 thresholds are monitored in Active mode and V1_standby mode Watchdog Trigger Time 00: TSW1 (default) 01: TSW2 10: TSW3 11: TSW4 Writing to WD_TIME_x is blocked unless WD CONFIG EN = 1. The modified WD Trigger Time is valid immediately after the Write command (CSN transition low-high). The watchdog timer is reset when the trigger time is modified (restart at CSN transition low-high). 1. Timer restart behavior: Write to CR2 when Tx_ON_x and Tx_PERx remain unchanged: Tx_RESTART = 1: timers restart at end of SPI frame, starting with ON time Tx_RESTART = 0: write operation to CR2 has no effect on timers Write to CR2 when Tx_ON_x and Tx_PERx are modified Tx_RESTART = 1: timers restart at end of SPI frame, starting with ON time and according to new setting (ON time and period) Tx_RESTART = 0: behavior is not defined; if a predictable behavior is needed, it is recommended to set Tx_RESTART = 1 Table 96. Configuration of Timer x on-time Tx_DIR1 Tx_ON_2 Tx_ON_1 Tx_ON_0 0 0 0 0 ton1 (default) 0 0 0 1 ton2 0 0 1 0 ton3 0 0 1 1 ton4 0 1 0 0 ton5 0 1 0 1 0 1 1 0 0 1 1 1 Invalid setting; command will be ignored and SPI INV CMD will be set DS11546 Rev 5 151/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 96. Configuration of Timer x on-time (continued) Tx_DIR1 Tx_ON_2 Tx_ON_1 Tx_ON_0 (1) 1 0 0 0 ton1 controlled by DIR1 input signal (logical AND) 1(1) 0 0 1 ton2 controlled by DIR1 input signal (logical AND) (1) 0 1 0 ton3 controlled by DIR1 input signal (logical AND) (1) 1 0 1 1 ton4 controlled by DIR1 input signal (logical AND) 1(1) 1 0 0 ton5 controlled by DIR1 input signal (logical AND) 1(1) 1 0 1 (1) 1 1 1 0 1(1) 1 1 1 1 Invalid setting; command will be ignored and SPI INV CMD will be set 1. Tx_DIR1 = 1 is only valid for OUT7-OUT15 and OUT_HS control; the DIR1 signal has no influence for WU monitoring if WU is monitored by timer. Figure 60. Timer_x controlled by DIR1 7[',5 7[ WRQ[ 7LPHU; ',5 287[ ("1($'5 7.4.3 Control Register CR3 (0x03) 0 0 0 0 0 Access R/W 152/197 DS11546 Rev 5 0 0 2 1 0 VSREG_EWTH_0 0 3 VSREG_EWTH_1 1 4 VSREG_EWTH_2 1 5 VSREG_EWTH_3 1 6 VSREG_EWTH_4 VS_UV_SD_EN 1 7 VSREG_EWTH_5 VS_OV_SD_EN 1 8 VSREG_EWTH_6 VSREG_UV_SD_EN 1 Reserved 9 VSREG_EWTH_7 19 18 17 16 15 14 13 12 11 10 VSREG_EWTH_8 20 VSREG_EWTH_9 21 VSREG_OV_SD_EN Reset 22 VS_LOCK_EN Bit name 23 VSREG_LOCK_EN Table 97. Control Register CR3 0 0 0 0 0 0 0 0 0 0 L99DZ100G, L99DZ100GP SPI Registers Table 98. CR3 signals description Bit 23 22 21 20 Name Description VSREG_LOCK_EN VSREG lockout enable: Lockout of VSREG related outputs after VSREG overvoltage/ undervoltage shutdown 0: VSREG related Outputs are turned on automatically and status bits (VSREG_UV, VSREG_OV) are cleared 1: VSREG related Outputs remain turned off until status bits (VSREG_UV, VSREG_OV) are cleared (default) Lockout is always disabled in standby modes in order to ensure supply of external contacts and detect wake-up conditions VS_LOCK_EN VS lockout enable: Lockout of VS related outputs after VS over/undervoltage shutdown 0: VS related Outputs are turned on automatically and status bits (VS_UV, VS_OV) are cleared 1: VS related Outputs remain turned off until status bits (VS_UV, VS_OV) are cleared (default) Lockout is always disabled in standby modes in order to ensure supply of external contacts and detect wake-up conditions VSREG_OV_SD_EN VSREG overvoltage shutdown enable: shutdown of VSREG related outputs in case of VSREG overvoltage 0: no shutdown of VSREG related outputs in case of VSREG overvoltage 1: shutdown of VSREG related outputs in case of VSREG overvoltage (default) VSREG_UV_SD_EN VSREG undervoltage shutdown enable: shutdown of VSREG related outputs in case of VSREG undervoltage 0: no shutdown of VSREG related outputs in case of VSREG undervoltage 1: shutdown of VSREG related outputs in case of VSREG undervoltage (default) In case of V1 undervoltage due to VSREG_UV, the device enters Fail-Safe mode and the outputs are turned off VS_OV_SD_EN VS overvoltage shutdown enable: shutdown of VS related outputs in case of VS overvoltage 0: no shutdown of VS related outputs in case of VS overvoltage if charge pump output voltage is still sufficient (until CPLOW threshold is reached) 1: shutdown of VS related outputs in case of VS overvoltage (default) 18 VS_UV_SD_EN VS undervoltage shutdown enable: shutdown of VS related outputs in case of VS undervoltage 0: no shutdown VS related of outputs in case of VS undervoltage 1: shutdown of VS related outputs in case of VS undervoltage (default) In case of V1 undervoltage due to VS_UV, the device enters Fail-Safe mode and the outputs are turned off 17:10 Reserved 19 Reserved DS11546 Rev 5 153/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 98. CR3 signals description (continued) Bit Name 9 VSREG_EW_TH_9 8 VSREG_EW_TH_8 7 VSREG_EW_TH_7 6 VSREG_EW_TH_6 5 VSREG_EW_TH_5 4 VSREG_EW_TH_4 3 VSREG_EW_TH_3 2 VSREG_EW_TH_2 1 VSREG_EW_TH_1 0 VSREG_EW_TH_0 7.4.4 Description VSREG early warning threshold. At VSREG < VSREG_EW_TH, an interrupt is generated at NINT and status bit VSREG_EW in SR2 is set (in Active mode) 0000000000: 0 V (default) feature deactivated ... 1111111111: VAINVS Control Register CR4 (0x04) Access 0 0 0 0 0 2 Reserved 0 3 0 0 1 0 OUT6_LS 0 4 OUT6_HS 0 5 OUT5_LS 0 6 Reserved 0 7 OUT5_HS 0 8 OUT4_LS 0 9 OUT4_HS 0 Reserved 0 OUT3_LS 0 OUT3_HS 0 Reserved 0 Reserved 0 19 18 17 16 15 14 13 12 11 10 OUT2_LS 0 20 OUT2_HS 0 21 OUT1_LS Bit name Reset 22 Reserved 23 OUT1_HS Table 99. Control Register CR4 0 0 R/W Table 100. CR4 signals description Bit Name 23:22 Reserved Reserved OUT1_HS OUT1 High-Side Driver control 0: OUT1_HS is turned off (default) 1: OUT1_HS is turned on An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT1 are switched on simultaneously. 20 OUT1_LS OUT1 Low-Side Driver control 0: OUT1_LS is turned off (default) 1: OUT1_LS is turned on An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT1 are switched on simultaneously. 19:18 Reserved Reserved 21 154/197 Description DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 100. CR4 signals description (continued) Bit Name Description OUT2_HS OUT2 High-Side Driver control 0: OUT2_HS is turned off (default) 1: OUT2_HS is turned on An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT2 are switched on simultaneously. 16 OUT2_LS OUT2 Low-Side Driver control 0: OUT2_LS is turned off (default) 1: OUT2_LS is turned on An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT2 are switched on simultaneously. 15:14 Reserved Reserved OUT3_HS OUT3 High-Side Driver control 0: OUT3_HS is turned off (default) 1: OUT3_HS is turned on An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT3 are switched on simultaneously. 12 OUT3_LS OUT3 Low-Side Driver control 0: OUT3_LS is turned off (default) 1: OUT3_LS is turned on An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT3 are switched on simultaneously. 11:10 Resrved 17 13 Reserved OUT4_HS OUT4 High-Side Driver control 0: OUT4_HS is turned off (default) 1: OUT4_HS is turned on An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT4 are switched on simultaneously. 8 OUT4_LS OUT4 Low-Side Driver control 0: OUT4_LS is turned off (default) 1: OUT4_LS is turned on An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT4 are switched on simultaneously. 7:6 Reserved Reserved OUT5_HS OUT5 High-Side Driver control 0: OUT5_HS is turned off (default) 1: OUT5_HS is turned on An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT5 are switched on simultaneously. OUT5_LS OUT5 Low-side Driver control 0: OUT5_LS is turned off (default) 1: OUT5_LS is turned on An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT5 are switched on simultaneously. 9 5 4 DS11546 Rev 5 155/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 100. CR4 signals description (continued) Bit Name 3:2 Reserved Reserved OUT6_HS OUT6 High-side Driver control 0: OUT6_HS is turned off (default) 1: OUT6_HS is turned on An internal cross-current protection prevents, that both the low-side and high-side drivers of the half-bridge OUT6 are switched on simultaneously. OUT6_LS OUT6 Low-side Driver control 0: OUT6_LS is turned off (default) 1: OUT6_LS is turned on An internal cross-current protection prevents, that both the low-side and high-side drivers of the half-bridge OUT6 are switched on simultaneously. 1 0 7.4.5 Description Control Register CR5 (0x05) Access 0 0 0 0 0 0 0 0 0 0 0 2 1 0 OUTHS_0 0 3 OUTHS_1 0 4 OUTHS_2 0 5 OUTHS_3 OUT8_0 0 6 GH OUT8_1 0 7 Reserved OUT8_2 0 OUT10_0 OUT8_3 0 8 OUT10_1 OUT7_0 0 9 OUT10_2 19 18 17 16 15 14 13 12 11 10 OUT10_3 20 Reserved 21 OUT7_1 Reset 22 OUT7_2 Bit name 23 OUT7_3 Table 101. Control Register CR5 0 0 0 0 0 R/W Table 102. CR5 signals description Bit Name 23 OUT7_3 22 OUT7_2 21 OUT7_1 20 OUT7_0 19 OUT8_3 18 OUT8_2 17 OUT8_1 16 OUT8_0 15:12 Reserved 11 OUT10_3 10 OUT10_2 9 OUT10_1 8 OUT10_0 156/197 Description OUT7 Configuration Bits: High-Side Driver OUT7 Configuration For OUT7 bits configuration see Table 103: OUTx Configuration bits OUT8 Configuration Bits: High-Side Driver OUT8 Configuration For OUT8 bits configuration see Table 103: OUTx Configuration bits -- OUT10 Configuration Bits: High-Side Driver OUT10 Configuration For OUT10 bits configuration see Table 103: OUTx Configuration bits DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 102. CR5 signals description (continued) Bit Name 7:5 Reserved 4 GH 3 OUTHS_3 2 OUTHS_2 1 OUTHS_1 0 OUTHS_0 Description -- Gate Heater Control: Control of gate driver for external heater MOSFET 0: GH_heater is turned off (default) 1: GH_heater is turned on OUTHS Configuration Bits: High-side Driver OUTHS Configuration For OUTHS bits configuration see Table 103: OUTx Configuration bits Table 103. OUTx Configuration bits OUTx_3 OUTx_2 OUTx_1 OUTx_0 Description 0 0 0 0 Off (default) 0 0 0 1 On 0 0 1 0 Timer1 0 0 1 1 Timer2 0 1 0 0 PWM1 0 1 0 1 PWM2 0 1 1 0 PWM3 0 1 1 1 PWM4 1 0 0 0 PWM5 1 0 0 1 PWM6 1 0 1 0 PWM7 1 0 1 1 PWM8 1 1 0 0 PWM9 1 1 0 1 PWM10 1 1 1 0 DIR1 1 1 1 1 DIR2 DS11546 Rev 5 157/197 196 SPI Registers 7.4.6 L99DZ100G, L99DZ100GP Control Register CR6 (0x06) OUT13_3 OUT15_0 OUT12_0 0 OUT15_1 OUT12_1 1 OUT15_2 OUT12_2 2 OUT15_3 OUT12_3 3 OUT14_0 OUT11_0 4 OUT14_1 OUT11_1 5 OUT14_2 OUT11_2 6 OUT14_3 OUT11_3 7 OUT13_0 19 18 17 16 15 14 13 12 11 10 OUT9_0 8 OUT13_1 20 0 0 0 0 0 0 0 0 0 0 0 0 0 Access 9 OUT13_2 21 OUT9_1 Reset 22 OUT9_2 Bit name 23 OUT9_3 Table 104. Control Register CR6 0 0 0 0 0 0 0 0 0 0 0 R/W Table 105. CR6 signals description Bit Name 23 OUT9_3 22 OUT9_2 21 OUT9_1 20 OUT9_0 19 OUT11_3 18 OUT11_2 17 OUT11_1 16 OUT11_0 15 OUT12_3 14 OUT12_2 13 OUT12_1 12 OUT12_0 11 OUT13_3 10 OUT13_2 9 OUT13_1 8 OUT13_0 7 OUT14_3 6 OUT14_2 5 OUT14_1 4 OUT14_0 3 OUT15_3 2 OUT15_2 1 OUT15_1 0 OUT15_0 158/197 Description OUT9 Configuration Bits: High-Side Driver OUT9 Configuration For OUT9 bits configuration see Table 103: OUTx Configuration bits OUT11 Configuration Bits: High-Side Driver OUT11 Configuration For OUT11 bits configuration see Table 103: OUTx Configuration bits OUT12 Configuration Bits: High-Side Driver OUT12 Configuration For OUT12 bits configuration see Table 103: OUTx Configuration bits OUT13 Configuration Bits: High-Side Driver OUT13 Configuration For OUT13 bits configuration see Table 103: OUTx Configuration bits OUT14 Configuration Bits: High-Side Driver OUT14 Configuration For OUT14 bits configuration see Table 103: OUTx Configuration bits OUT15 Configuration Bits: High-side Driver OUT15 Configuration For OUT15 bits configuration see Table 103: OUTx Configuration bits DS11546 Rev 5 L99DZ100G, L99DZ100GP 7.4.7 SPI Registers Control Register CR7 (0x07) Access CM_SEL_0 0 CM_SEL_1 0 0 CM_SEL_2 0 1 CM_SEL_3 0 2 Reserved 0 3 CM_EN OUTHS_OCR 0 4 OUT5_OC0 OUT8_OCR 0 5 OUT5_OC1 OUT7_OCR 0 6 OCR_FREQ OUT6_OCR 0 7 HS_TON_0 OUT5_OCR 0 8 HS_TON_1 OUT4_OCR 0 9 HB_TON_0 19 18 17 16 15 14 13 12 11 10 HB_TON_1 20 Reserved 21 OUT3_OCR Reset 22 OUT2_OCR Bit name 23 OUT1_OCR Table 106. Control Register CR7 0 0 0 0 0 0 0 1 0 0 0 0 0 R/W Table 107. CR7 signals description Bit Name 23 OUT1_OCR 22 OUT2_OCR 21 OUT3_OCR 20 OUT4_OCR 19 OUT5_OCR 18 OUT6_OCR 17 OUT7_OCR 16 OUT8_OCR 15 OUTHS_OCR 14:13 Reserved 12 HB_TON_1 11 HB_TON_0 10 HS_TON_1 9 HS_TON_0 8 OCR_FREQ 7 OUT5_OC1 6 OUT5_OC0 Description Overcurrent recovery for OUTx 0: overcurrent recovery is turned off (default) 1: overcurrent recovery is turned on Overcurrent recovery for OUTHS 0: overcurrent recovery is turned off (default) 1: overcurrent recovery is turned on -- Half-bridge minimum ON time and related overcurrent recovery frequency For details see Table 108: Half-bridge minimum ON time and related overcurrent recovery frequency High-side minimum ON time and related overcurrent recovery frequency For details see Table 109: High-side minimum ON time and related overcurrent recovery frequency Overcurrent recovery frequency See Table 108: Half-bridge minimum ON time and related overcurrent recovery frequency and Table 109: High-side minimum ON time and related overcurrent recovery frequency Overcurrent Threshold for OUT5 00: IOC5_3 overcurrent threshold 3 (default) 01: IOC5_1 overcurrent threshold 1 10: IOC5_2 overcurrent threshold 2 11: IOC5_3 overcurrent threshold 3 DS11546 Rev 5 159/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 107. CR7 signals description (continued) Bit Name 5 CM_EN 4 Reserved 3 CM_SEL_3 2 CM_SEL_2 1 CM_SEL_1 0 CM_SEL_0 Description Current monitor: 0: off (3-state) 1: on (default) -- Current Monitor Select Bits. A current image of the selected binary coded output is multiplexed to the CM output. If a corresponding output does not exist, the current monitor is deactivated. 0000: OUT1 0001: OUT2 0010: OUT3 0011: OUT4 0100: OUT5 0101: OUT6 0110: OUT7 0111: OUT8 1000: OUT9 1001: OUT10 1010: OUT11 1011: OUT12 1100: OUT13 1101: OUT14 1110: OUT15 1111: OUT_HS Table 108. Half-bridge minimum ON time and related overcurrent recovery frequency HB_TON_1 HB_TON_ OCR_FREQ TON_min (recovery frequency) 0 0 0 104 s (1.7 kHz) 0 0 1 104 s (3 kHz) 0 1 0 88 s (2.2 kHz) 0 1 1 88 s (3.8 kHz) 1 0 0 80 s (2.6 kHz) 1 0 1 80 s (4.4 kHz) 1 1 0 72 s (3 kHz) 1 1 1 72 s (5 kHz) Table 109. High-side minimum ON time and related overcurrent recovery frequency 160/197 HS_TON_1 HS_TON_ OCR_FREQ TON_min (recovery frequency) 0 0 0 104 s (1.7 kHz) 0 0 1 104 s (3 kHz) DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 109. High-side minimum ON time and related overcurrent recovery frequency 7.4.8 HS_TON_1 HS_TON_ OCR_FREQ TON_min (recovery frequency) 0 1 0 88 s (2.2 kHz) 0 1 1 88 s (3.8 kHz) 1 0 0 80 s (2.6 kHz) 1 0 1 80 s (4.4 kHz) 1 1 0 72 s (3 kHz) 1 1 1 72 s (5 kHz) Control Register CR8 (0x08) 21 20 19 18 17 16 15 14 13 12 11 10 OUT3_OCR_THX_EN OUT4_OCR_THX_EN OUT5_OCR_THX_EN OUT6_OCR_THX_EN OUT7_OCR_THX_EN OUT8_OCR_THX_EN OUTHS_OCR_THX_EN Reset 22 OUT2_OCR_THX_EN Bit name 23 OUT1_OCR_THX_EN Table 110. Control Register CR8 1 1 1 1 1 1 1 1 1 Access 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 Resrved 0 0 0 0 0 0 0 0 0 R/W Table 111. CR8 signals description Bit Name 23 OUT1_OCR_THX_EN 22 OUT2_OCR_THX_EN 21 OUT3_OCR_THX_EN 20 OUT4_OCR_THX_EN 19 OUT5_OCR_THX_EN 18 OUT6_OCR_THX_EN 17 OUT7_OCR_THX_EN 16 OUT8_OCR_THX_EN Description Enable Overcurrent Recovery with Thermal Expiration for OUTx. 0: Overcurrent Recovery with Thermal Expiration is off 1: Overcurrent Recovery with Thermal Expiration is on (default) The output is turned off after Thermal Expiration. DS11546 Rev 5 161/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 111. CR8 signals description (continued) Bit Name Description 15 OUTHS_OCR_THX_EN 14:0 Reserved 7.4.9 Enable Overcurrent Recovery with Thermal Expiration for OUTHS. 0: Overcurrent Recovery with Thermal Expiration is off 1: Overcurrent Recovery with Thermal Expiration is on (default) The output is turned off after Thermal Expiration. -- Control Register CR9 (0x09) Access OUT11_OC OUT10_OC OUT9_OC 0 OUT12_OC 1 OUT13_OC 2 OUT14_OC 0 3 OUT15_OC 0 4 OUTHS_OC 0 5 OUT9_OL 0 6 OUT10_OL 0 7 OUT11_OL 0 8 OUT12_OL Reserved 9 OUT13_OL 19 18 17 16 15 14 13 12 11 10 OUT14_OL 0 20 OUT15_OL 0 21 OUTHS_OL Reset 22 OUT8_RDSON Bit name 23 OUT7_RDSON Table 112. Control Register CR9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W Table 113. CR9 signals description Bit Name Description 23 OUT7_RDSON Select Rdson for OUT7 0: ron_low (default) 1: ron_high 22 OUT8_RDSON Select Rdson for OUT8 0: ron_low (default) 1: ron_high 21:16 Reserved 15 OUTHS_OL 14 OUT15_OL 13 OUT14_OL 12 OUT13_OL 11 OUT12_OL 10 OUT11_OL 9 OUT10_OL 8 OUT9_OL 162/197 -- Open-load Threshold for OUTx 0: IOLD1 ; high-current mode (default) 1: IOLD1; low-current mode DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 113. CR9 signals description (continued) Bit Name 7 OUTHS_OC 6 OUT15_OC 5 OUT14_OC 4 OUT13_OC 3 OUT12_OC 2 OUT11_OC 1 OUT10_OC 0 OUT9_OC 7.4.10 Description Overcurrent Threshold for OUTx 0: IOC; high-current mode (default) 1: IOC; low-current mode Control Register CR10 (0x0A) Access SLEW_2 SLEW_1 SLEW_0 0 0 SLEW_3 0 1 SLEW_4 1 2 OL_H2L1 1 3 OL_H1L2 1 4 H_OLTH_HIGH GH_TH_0 0 5 COPT_0 GH_TH_1 0 6 COPT_1 GH_TH_2 1 7 COPT_2 Reserved 1 8 COPT_3 GH_OL_EN 1 9 SDS 19 18 17 16 15 14 13 12 11 10 SD 20 Reserved 21 DIAG_0 Reset 22 DIAG_1 Bit name 23 DIAG_2 Table 114. Control Register CR10 0 0 1 1 1 1 0 0 0 0 0 0 0 0 R/W Table 115. CR10 signals description Bit Name 23 DIAG_2 22 DIAG_1 21 DIAG_0 20 GH_OL_EN 19 Reserved Description Drain-source monitoring threshold for external H-bridge 000: VSCd1_HB 001: VSCd2_HB 010: VSCd3_HB 011: VSCd4_HB 100: VSCd5_HB 101: VSCd6_HB 110: VSCd7_HB 111: VSCd7_HB (default) Control open-load diagnosis for Gate Heater output 0: open-load diagnosis off (default) 1: open-load diagnosis on -- DS11546 Rev 5 163/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 115. CR10 signals description (continued) Bit Name 18 GH_TH_2 17 GH_TH_1 16 GH_TH_0 15:14 Reserved 13 SD 12 SDS 11 COPT_3 10 COPT_2 9 COPT_1 8 COPT_0 7 H_OLTH_HIGH H-bridge OL high threshold (5/6 * VS) select 6 OL_H1L2 Test open-load condition between H1 and L2 5 OL_H2L1 Test open-load condition between H2 and L1 4 SLEW_4 3 SLEW_3 2 SLEW_2 1 SLEW_1 0 SLEW_0 164/197 Description Drain source monitoring threshold voltage for external heater MOSFET 000: VSCd1_HE 001: VSCd2_HE 010: VSCd3_HE 011: VSCd4_HE 100: VSCd5_HE 101: VSCd6_HE 110: VSCd7_HE 111: VSCd8_HE (default) -- Slow decay Slow decay single Cross current protection time 0000: not allowed 0001: tccp0001 0010: tccp0010 0011: tccp0011 0100: tccp0100 0101: tccp0101 0110: tccp0110 0111: tccp0111 1000: tccp1000 1001: tccp1001 1010: tccp1010 1011: tccp1011 1100: tccp1100 1101: tccp1101 1110: tccp1110 1111: tccp1111 (default) Binary coded slew rate of H-bridge (bit0 = LSB; bit4 = MSB) 00000: Control disabled (default) 11111: IGHxmax DS11546 Rev 5 L99DZ100G, L99DZ100GP 7.4.11 SPI Registers Control Register CR11 (0x0B) 0 0 0 0 Access 0 0 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 EC_0 0 6 EC_1 0 Reserved 7 EC_2 0 8 EC_3 Reserved 9 EC_4 Reset 19 18 17 16 15 14 13 12 11 10 EC_5 Bit name 20 Reserved 21 ECV_OCR 22 ECV_LS 23 ECON Table 116. Control Register CR11 1 0 0 0 0 0 R/W Table 117. CR11 signals description Bit Name Description 23:14 Reserved -- 13 ECV_LS Control of ECV low-side switch 0: ECV low-side switch off (default) 1: ECV low-side switch on 12 ECV_OCR Overcurrent recovery for output ECV 0: overcurrent recovery is turned off (default) 1: overcurrent recovery is turned on 11:9 Reserved -- 8 ECON 7:6 Reserved 5 EC_5 4 EC_4 3 EC_3 2 EC_2 1 EC_1 0 EC_0 Electro-chrome Control The electro-chrome control enables the driver at pin ECDR and switches OUT10 directly on ignoring the control bits OUT10_x in CR5 0: Electro-chrome control off (default) 1: Electro-chrome control on -- EC Reference Voltage Bits The reference voltage for the electro-chrome voltage controller at pin ECV is binary coded. (bit0 = LSB; bit5 = MSB) 00 0000: VECV = 0 V xx xxxx: VECV = VCTRLmax/63 x register value 11 1111: VECV = VCTRLmax For ECV_HV (Configuration Register) = 0, the maximum EC control voltage is clamped at lower value (see Section 3.4.20: Electro-chrome mirror driver) DS11546 Rev 5 165/197 196 SPI Registers 7.4.12 L99DZ100G, L99DZ100GP Control Register CR12 (0x0C) PMW5_FREQ_1 PMW5_FREQ_0 PMW6_FREQ_1 PMW6_FREQ_0 PMW7_FREQ_1 PMW10_FREQ_0 PMW4_FREQ_0 4 PMW10_FREQ_1 PMW4_FREQ_1 5 PMW9_FREQ_0 PMW3_FREQ_0 6 PMW9_FREQ_1 PMW3_FREQ_1 7 PMW8_FREQ_0 19 18 17 16 15 14 13 12 11 10 PMW2_FREQ_0 8 PMW8_FREQ_1 20 0 0 0 0 0 0 0 0 0 0 0 0 0 Access 9 PMW7_FREQ_0 21 PMW2_FREQ_1 Reset 22 PMW1_FREQ_0 Bit name 23 PMW1_FREQ_1 Table 118. Control Register CR12 0 0 0 0 0 0 0 R/W Table 119. CR12 signals description Bit Name 23 PMW1_FREQ_1 22 PMW1_FREQ_0 21 PMW2_FREQ_1 20 PMW2_FREQ_0 19 PMW3_FREQ_1 18 PMW3_FREQ_0 17 PMW4_FREQ_1 16 PMW4_FREQ_0 15 PMW5_FREQ_1 14 PMW5_FREQ_0 166/197 Description Frequency of PWM channel PWM1 00: fPWMx(00) (default) 01: fPWMx(01) 10: fPWMx(10) 11: fPWMx(11) Frequency of PWM channel PWM2 00: fPWMx(00) (default) 01: fPWMx(01) 10: fPWMx(10) 11: fPWMx(11) Frequency of PWM channel PWM3 00: fPWMx(00) (default) 01: fPWMx(01) 10: fPWMx(10) 11: fPWMx(11) Frequency of PWM channel PWM4 00: fPWMx(00) (default) 01: fPWMx(01) 10: fPWMx(10) 11: fPWMx(11) Frequency of PWM channel PWM5 00: fPWMx(00) (default) 01: fPWMx(01) 10: fPWMx(10) 11: fPWMx(11) DS11546 Rev 5 3 2 1 0 Reserved 0 0 0 0 L99DZ100G, L99DZ100GP SPI Registers Table 119. CR12 signals description (continued) Bit Name 13 PMW6_FREQ_1 12 PMW6_FREQ_0 11 PMW7_FREQ_1 10 PMW7_FREQ_0 9 PMW8_FREQ_1 8 PMW8_FREQ_0 7 PMW9_FREQ_1 6 PMW9_FREQ_0 5 PMW10_FREQ_1 Frequency of PWM channel PWM10 00: fPWMx(00) (default) 01: fPWMx(01) PMW10_FREQ_0 10: fPWMx(10) 11: fPWMx(11) 4 3:0 Description Reserved 7.4.13 Frequency of PWM channel PWM6 00: fPWMx(00) (default) 01: fPWMx(01) 10: fPWMx(10) 11: fPWMx(11) Frequency of PWM channel PWM7 00: fPWMx(00) (default) 01: fPWMx(01) 10: fPWMx(10) 11: fPWMx(11) Frequency of PWM channel PWM8 00: fPWMx(00) (default) 01: fPWMx(01) 10: fPWMx(10) 11: fPWMx(11) Frequency of PWM channel PWM9 00: fPWMx(00) (default) 01: fPWMx(01) 10: fPWMx(10) 11: fPWMx(11) -- Control Register CR13 (0x0D) to CR17 (0x11) Access 0 0 0 PWMy_DC_0 0 1 PWMy_DC_1 0 2 PWMy_DC_2 0 3 PWMy_DC_3 0 4 PWMy_DC_4 PWMx_DC_0 0 5 PWMy_DC_5 PWMx_DC_1 0 6 PWMy_DC_6 PWMx_DC_2 0 7 PWMy_DC_7 PWMx_DC_3 0 8 PWMy_DC_8 PWMx_DC_4 0 9 PWMy_DC_9 PWMx_DC_5 0 Reserved 19 18 17 16 15 14 13 12 11 10 PWMx_DC_6 0 20 PWMx_DC_7 0 21 PWMx_DC_8 Bit name Reset 22 Reserved 23 PWMx_DC_9 Table 120. Control Register CR13 to CR17 0 0 0 0 0 0 0 0 0 0 R/W Where: x = 1 + (z * 2), z = 0 to 4 DS11546 Rev 5 167/197 196 SPI Registers L99DZ100G, L99DZ100GP y = 2 + (z * 2), z = 0 to 4 Table 121. CR13 to CR17 signals description Bit Name 23:22 Reserved 21 PWMx_DC_9 20 PWMx_DC_8 19 PWMx_DC_7 18 PWMx_DC_6 17 PWMx_DC_5 16 PWMx_DC_4 15 PWMx_DC_3 14 PWMx_DC_2 13 PWMx_DC_1 12 PWMx_DC_0 11:10 Reserved 9 PWMy_DC_9 8 PWMy_DC_8 7 PWMy_DC_7 6 PWMy_DC_6 5 PWMy_DC_5 4 PWMy_DC_4 3 PWMy_DC_3 2 PWMy_DC_2 1 PWMy_DC_1 0 PWMy_DC_0 7.4.14 Description -- Binary coded on-dutycycle of PWM channel PWMx (bit12 = LSB; bit21 = MSB) 00 0000 0000: duty cycle 0% (default) xx xxxx xxxx: duty cycle 100%/1023 x register value 11 1111 1111. duty cycle 100% -- Binary coded on-dutycycle of PWM channel PWMy (bit0 = LSB; bit9 = MSB) 00 0000 0000: duty cycle 0% (default) xx xxxx xxxx: duty cycle 100%/1023 x register value 11 1111 1111. Duty cycle 100% Binary coded on-dutycycle of PWM channel PWMy Control Register CR18 (0x12) to CR22 (0x16) 168/197 5 4 3 2 1 0 OUTx_VLED_9 OUTx_VLED_8 OUTx_VLED_7 OUTy_AUTOCOMP_EN OUTy_VLED_9 OUTy_VLED_8 OUTy_VLED_7 OUTy_VLED_6 OUTy_VLED_5 OUTy_VLED_4 OUTy_VLED_3 OUTy_VLED_2 OUTy_VLED_1 OUTy_VLED_0 DS11546 Rev 5 Reserved 6 OUTx_VLED_0 7 OUTx_VLED_1 8 OUTx_VLED_2 9 OUTx_VLED_3 19 18 17 16 15 14 13 12 11 10 OUTx_VLED_4 20 OUTx_VLED_5 21 OUTx_VLED_6 22 OUTx_AUTOCOMP_EN Bit name 23 Reserved Table 122. Control Register CR18 L99DZ100G, L99DZ100GP SPI Registers Table 122. Control Register CR18 (continued) Reset 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access 0 0 0 0 0 0 0 R/W Where: x = 7 + (z * 2), z = 0 to 4 y = 8 + (z * 2), z = 0 to 4 Table 123. CR18 to CR22 signals description Bit Name 23 Reserved 22 OUTx_AUTOCOMP_EN 21 OUTx_VLED_9 20 OUTx_VLED_8 19 OUTx_VLED_7 18 OUTx_VLED_6 17 OUTx_VLED_5 16 OUTx_VLED_4 15 OUTx_VLED_3 14 OUTx_VLED_2 13 OUTx_VLED_1 12 OUTx_VLED_0 11 Reserved 10 OUTy_AUTOCOMP_EN 9 OUTy_VLED_9 8 OUTy_VLED_8 7 OUTy_VLED_7 6 OUTy_VLED_6 5 OUTy_VLED_5 4 OUTy_VLED_4 3 OUTy_VLED_3 2 OUTy_VLED_2 1 OUTy_VLED_1 0 OUTy_VLED_0 Description -- Setting this bit to `1' enables the automatic VS compensation for OUTx Binary coded nominal LED voltage of OUTx (bit12 = LSB; bit21 = MSB) 00 0000 0000: VLED = 0 V (default) xx xxxx xxxx: VLED = VAINVS /1023 x register value 01 1101 0000: VLED = VAINVS VLED is clamped at 10 V (0x1D0h) -- Setting this bit to `1' enables the automatic VS compensation for OUTy Binary coded nominal LED voltage of OUTy (bit0 = LSB; bit9 = MSB) 00 0000 0000: VLED = 0 V (default) xx xxxx xxxx: VLED = VAINVS /1023 x register value 01 1101 0000: VLED = VAINVS VLED is clamped at 10 V (0x1D0h) DS11546 Rev 5 169/197 196 SPI Registers 7.4.15 L99DZ100G, L99DZ100GP Control Register CR23 (0x17) Table 124. Control Register CR23 EXT_ID_3 EXT_ID_2 EXT_ID_1 EXT_ID_0 0 EXT_ID_4 1 EXT_ID_5 2 EXT_ID_6 0 3 EXT_ID_7 0 4 EXT_ID_8 0 5 EXT_ID_9 0 6 EXT_ID_10 0 7 EXT_ID_11 0 8 EXT_ID_12 Reserved 9 EXT_ID_13 19 18 17 16 15 14 13 12 11 10 EXT_ID_14 Reset 20 EXT_ID_15 Bit name 21 EXT_ID_16 22 EXT_ID_17 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R/W Table 125. CR23 signals description Bit Name 23:18 Reserved -- EXT_ID_x Extended CAN Identifier Definition of Extended CAN Identifier which will cause a wake-up (WUF) To enable wake-up frame detection on Extended CAN Identifier also CAN_IDE (Control Register 24, bit 22) must be set ID Bits are maskable in CR25 17:0 7.4.16 Description Control Register CR24 (0x18) ID_0 Reserved 0 ID_1 DLC_0 1 ID_2 DLC_1 2 ID_3 DLC_2 3 ID_4 DLC_3 4 ID_5 SAMPLE_0 5 ID_6 SAMPLE_1 6 ID_7 SAMPLE_2 7 ID_8 SAMPLE_3 8 ID_9 BR_0 0 0 0 0 1 0 1 0 0 0 0 0 0 Access 9 ID_10 BR_1 Reset 22 21 20 19 18 17 16 15 14 13 12 11 10 CAN_IDE Bit name 23 Reserved Table 126. Control Register CR24 0 0 0 0 0 0 0 0 0 0 0 R/W Table 127. CR24 signals description Bit Name 23 Reserved -- 22 CAN_IDE Enable CAN wake-up frame detection on Extended Identifier 0: CAN Identifier matching based on CAN Standard Message Format (default) 1: CAN Identifier Matching based on CAN Extended Message Format 170/197 Description DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 127. CR24 signals description (continued) Bit Name 21 BR_1 20 BR_0 19 SAMPLE_3 18 SAMPLE_2 17 SAMPLE_1 16 SAMPLE_0 15 DLC_3 14 DLC_2 13 DLC_1 12 DLC_0 11 Reserved 10 ID_10 9 ID_9 8 ID_8 7 ID_7 6 ID_6 5 ID_5 4 ID_4 3 ID_3 2 ID_2 1 ID_1 0 ID_0 Description Bit Rate for CAN wake-up frame detection 00: 500 kbit/s (default) 01: 250 kbit/s 10: 500 kbit/s 11: 125 kbit/s Sample Point for CAN wake-up frame detection 0000: 65.625 % 0001: 67.1875 % 0010: 67.75 % ... 1010: 81.25 % (default) ... 1110: 87.5 % 1111: 89.065 % CAN Data Length Code Defines the amount of Data Bytes used for the CAN wake-up frame detection. Possible values up to 8 Byte according to CAN message format -- CAN Identifier Definition of CAN Identifier which will cause a wake-up (WUF) ID Bits are maskable in CR26 DS11546 Rev 5 171/197 196 SPI Registers 7.4.17 L99DZ100G, L99DZ100GP Control Register CR25 (0x19) Table 128. Control Register CR25 EXT_ID_MASK_3 EXT_ID_MASK_2 EXT_ID_MASK_1 EXT_ID_MASK_0 0 EXT_ID_MASK_4 1 EXT_ID_MASK_5 2 EXT_ID_MASK_6 0 3 EXT_ID_MASK_7 0 4 EXT_ID_MASK_8 0 5 EXT_ID_MASK_9 0 6 EXT_ID_MASK_10 0 7 EXT_ID_MASK_11 0 8 EXT_ID_MASK_12 Reserved 9 EXT_ID_MASK_13 19 18 17 16 15 14 13 12 11 10 EXT_ID_MASK_14 Reset 20 EXT_ID_MASK_15 Bit name 21 EXT_ID_MASK_16 22 EXT_ID_MASK_17 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R/W Table 129. CR25 signals description Bit Name 23:18 Reserved 17:0 Description -- Masking Bits for Extended CAN Identifier 0: Extended CAN Identifier Bit will be matched (default) 1: Extended CAN Identifier Bit will be ignored for matching EXT_ID_MASK_x 7.4.18 Control Register CR26 (0x1A) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID_MASK_6 ID_MASK_5 ID_MASK_4 ID_MASK_3 ID_MASK_2 ID_MASK_1 ID_MASK_0 20 ID_MASK_7 21 ID_MASK_8 22 ID_MASK_9 23 ID_MASK_10 Table 130. Control Register CR26 0 0 0 0 0 0 0 0 0 0 0 Bit name Reset Reserved 0 0 0 0 0 0 Access 0 0 0 0 0 0 0 R/W Table 131. CR26 signals description Bit Name 23:11 Reserved 10:0 ID_MASK_x Description -- Masking Bits Standard CAN Identifier 0: CAN Identifier Bit will be matched (default) 1: CAN Identifier Bit will be ignored for matching The extended ID and extended ID mask are composed as follows (mask is composed by equivalent bits in CR25 and CR26: 172/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Figure 61. Extended ID and extended ID mask 67',' E E E E E E E E E E &5ELW ,'B (;7,' E E E E E E E ,'B E E E &5ELW ,'B E E 655 ,'( ,'B E E E E E E E E E E E E E E E E &5ELW (;,'B E E (;,'B ("1($'5 7.4.19 Control Register CR27 (0x1B) DATA_BYTE2_5 DATA_BYTE2_4 DATA_BYTE2_3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_BYTE1_0 DATA_BYTE2_6 0 DATA_BYTE1_1 DATA_BYTE2_7 1 DATA_BYTE1_2 DATA_BYTE3_0 2 DATA_BYTE1_3 DATA_BYTE3_1 3 DATA_BYTE1_4 DATA_BYTE3_2 4 DATA_BYTE1_5 DATA_BYTE3_3 5 DATA_BYTE1_6 DATA_BYTE3_4 6 DATA_BYTE1_7 19 18 17 16 15 14 13 12 11 10 DATA_BYTE3_5 7 DATA_BYTE2_0 20 Access 8 DATA_BYTE2_1 21 Reset 9 DATA_BYTE2_2 22 DATA_BYTE3_6 Bit name 23 DATA_BYTE3_7 Table 132. Control Register CR27 0 0 0 0 0 0 0 R/W Table 133. CR27 signals description Bit Name 23:16 DATA_BYTE3 15:8 DATA_BYTE2 7:0 DATA_BYTE1 7.4.20 Description Data field for data matching Control Register CR28 (0x1C) Access DATA_BYTE4_0 DATA_BYTE5_3 0 DATA_BYTE4_1 DATA_BYTE5_4 1 DATA_BYTE4_2 DATA_BYTE5_5 2 DATA_BYTE4_3 DATA_BYTE5_6 3 DATA_BYTE4_4 DATA_BYTE5_7 4 DATA_BYTE4_5 DATA_BYTE6_0 5 DATA_BYTE4_6 DATA_BYTE6_1 6 DATA_BYTE4_7 DATA_BYTE6_2 7 DATA_BYTE5_0 19 18 17 16 15 14 13 12 11 10 DATA_BYTE6_3 8 DATA_BYTE5_1 20 DATA_BYTE6_4 9 DATA_BYTE5_2 21 DATA_BYTE6_5 Reset 22 DATA_BYTE6_6 Bit name 23 DATA_BYTE6_7 Table 134. Control Register CR28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W DS11546 Rev 5 173/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 135. CR28 signals description Bit Name 23:16 DATA_BYTE6 15:8 DATA_BYTE5 7:0 DATA_BYTE4 7.4.21 Description Data field for data matching Control Register CR29 (0x1D) Table 136. Control Register CR29 DATA_BYTE7_1 DATA_BYTE7_0 0 0 DATA_BYTE7_2 0 1 DATA_BYTE7_3 0 2 DATA_BYTE7_4 0 3 DATA_BYTE7_5 0 4 DATA_BYTE7_6 0 5 DATA_BYTE7_7 0 6 DATA_BYTE8_0 0 7 DATA_BYTE8_1 Reset 8 DATA_BYTE8_2 Reserved 9 DATA_BYTE8_3 19 18 17 16 15 14 13 12 11 10 DATA_BYTE8_4 Bit name 20 DATA_BYTE8_5 21 DATA_BYTE8_6 22 DATA_BYTE8_7 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access R/W Table 137. CR29 signals description Bit Name 23:16 Reserved 15:8 DATA_BYTE8 7:0 DATA_BYTE7 7.4.22 Description -- Data field for data matching Control Register CR34 (0x22) 21 20 19 18 17 16 15 14 13 12 11 10 Bit name Reset 9 8 7 6 5 4 3 0 0 0 0 0 0 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 Access R/W 174/197 DS11546 Rev 5 0 0 2 1 0 WD_EN 22 ICMP 23 CP_OFF Table 138. Control Register CR34 0 0 1 L99DZ100G, L99DZ100GP SPI Registers Table 139. CR34 signals description Bit Name 23:3 Reserved -- CP_OFF Charge pump control 0: Enabled; charge pump on in active mode (default) 1: Disabled; charge pump off in active mode setting CP_OFF = 1 is only possible when CP_OFF_EN = 1 2 ICMP V1 load current supervision 0: Enabled; Watchdog is disabled in V1 Standby when Iv1< ICMP (default) 1: Disabled; watchdog is disabled upon transition into V1_standby mode setting ICMP = 1 is only possible when ICMP_config_en = 1 WD_EN Watchdog Enable 0: Watchdog disabled 1: Watchdog enabled (default) Writing to this bit is only possible during CAN Flash mode (VTxDL > Vflash) 1 0 7.4.23 Description Configuration Register (0x3F) MASK_EC_OL MASK_OL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 TRIG MASK_TW 1 2 Reserved MASK_OL_LS1 CAN_SUP_5V2_EN MASK_OL_HS1 3 FS_FORCED WD_CONFIG_EN 4 CP_DITH_DIS ICMP_CONFIG_EN 5 CP_LOW_CONFIG DM 6 CP_OFF_EN ECV_HV 7 MASK_GW 19 18 17 16 15 14 13 12 11 10 TSD_CONFIG 8 MASK_PLE 20 Access 9 MASK_SPIE 21 LIN_HS_EN Reset 22 LIN_WU_CONFIG Bit name 23 WU_CONFIG Table 140. Configuration Register 0 1 R/W Table 141. CR signals description Bit 23 22 Name WU_CONFIG LIN_WU_CONFIG Description Configuration of input pin WU Input configured as wake-up input 0: WU configured as wake-up input 1: WU configured for input voltage measurement (default) Configuration of LIN wake-up behaviour 0: wake up at recessive - dominant - recessive with tdom > tdom_LIN (default) (according to LIN 2.2a and Hardware Requirements for Transceivers version 1.3) 1: wake up at recessive - dominant transition DS11546 Rev 5 175/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 141. CR signals description (continued) Bit Name 21 LIN_HS_EN 20 TSD_CONFIG 19 18 17 16 15 14 13 12 176/197 ECV_HV DM ICMP_CONFIG_EN WD_CONFIG_EN Description Configuration of LIN transceiver bit rate 0: LIN transceiver in normal communication mode (20kbit/s) (default) 1: LIN transceiver in high speed mode for fast Flashing (115kbit/s) Configuration of thermal shutdown behaviour 0: in case of TSD1 all power stages are switched off (default) 1: selective shut down of power stage cluster Configuration of maximum voltage of electrochrome controller (see electrical parameter VCTRLmax) 0: maximum electrochrome controller voltage clamped to 1.2V (typ); (default) 1: maximum electrochrome controller voltage set to 1.5V (typ) H-bridge configuration 0: single motor mode (default) 1: dual motor mode ICMP configuration Enable 0: writing ICMP = 1 is blocked (writing ICMP=0 is possible); (default) 1: writing ICMP = 1 is possible with next SPI command bit is automatically reset to 0 after next SPI command Watchdog configuration Enable 0: writing to WD Configuration (CR2 [0:1] is blocked (default) 1: writing to WD Configuration Bits is possible with next SPI command bit is automatically reset to 0 after next SPI command MASK_OL_HS1 Mask Open-load HS1 0: Open-load condition at HS1 is not masked (default) 1: Open-load condition at HS1 is masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error (GSB bit 7) MASK_OL_LS1 Mask Open-load LS1 0: Open-load condition at LS1 is not masked (default) 1: Open-load condition at LS1 is masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error (GSB bit 7) MASK_TW Mask Thermal Warning 0: Thermal warning is not masked (default) 1: Thermal warning is masked i.e. it is reported as a Global Warning (GSB bit 1) but not as a Global Error (GSB bit 7) MASK_EC_OL Mask Electro-chrome Open-load 0: Open-load condition at ECV and OUT10 is not masked (default) 1: Open-load condition at ECV and OUT10 is masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error (GSB bit 7) DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 141. CR signals description (continued) Bit 11 Name MASK_OL Description Mask open-load 0: Open-load condition at all outputs are not masked (default) 1: Open-load condition at all outputs are masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error (GSB bit 7) MASK_SPIE Mask SPI error 0: SPI errors are not masked (default) 1: SPI errors are masked i.e. reported as am SPI Error (GSB bit 5) but not as a Global Error (GSB bit 7) MASK_PLE Mask physical layer error 0: Physical Layer Errors are not masked (default) 1: Physical Layer Errors are masked i.e. reported as a Physical Layer Error (GSB bit 4) but not as a Global Error (GSB bit 7) MASK_GW Mask global warning 0: Global Warning conditions are not masked (default) 1: Global Warning conditions are masked i.e. reported as a Global Warning (GSB bit 1) but not as a Global Error (GSB bit 7) CP_OFF_EN Charge pump control enable 0: writing CP_OFF = 1 is blocked (writing CP OFF = 0 is possible); (default) 1: writing CP_OFF = 1 is possible with next SPI command Bit is automatically reset to 0 after next SPI command 6 CP_LOW_CONFIG Charge pump low configuration 0: CP_low (SR 2, bit 9) is latched and outputs are off until R&C; (default) 1: CP_low (SR 2, bit 9) is a `live' bit; outputs are re-activated automatically upon recovery of the charge pump output voltage 5 CP_DITH_DIS Charge pump clock dithering 0: CP clock dithering is enabled; (default) 1: CP clock dithering is disabled FS_FORCED Force LSx_FSO ON LSx_FSO low-side outputs are forced ON (to allow diagnosis of the fail-safe path) 0: LSx_FSO outputs are controlled by the Fail-safe logic (default) 1: LSx_FSO outputs are forced ON and the device enters Fail-Safe mode; no NReset is generated 10 9 8 7 4 3 CAN_SUP_5V2_EN 2:1 Reserved 0 TRIG CAN supplied by V2 enable (to allow CAN Partial Networking in V1stdby) 0: CAN supplied by V1; (default) 1: CAN supplied by V2; in this case the configuration CR1<5:4> = 11 is ignored -- Watchdog Trigger bit DS11546 Rev 5 177/197 196 SPI Registers L99DZ100G, L99DZ100GP 7.5 Status Registers 7.5.1 Status Register SR1 (0x31) 9 8 7 6 5 4 3 2 1 0 WDFAIL_CNT_1 WDFAIL_CNT_0 DEVICE_STATE_1 DEVICE_STATE_0 TSD2 TSD1 FORCED_SLEEP_TSD2/V1SC FORCED_SLEEP_WD WDFAIL VPOR WAKE_CAN R/C WDFAIL_CNT_2 WU_WAKE R WDFAIL_CNT_3 Reserved R/C V1_RESTART_0 WU_STATE Access V1_RESTART_1 Bit name V1_RESTART_2 19 18 17 16 15 14 13 12 11 10 V1UV 20 DEBUG_ACTIVE 21 WAKE_TIMER 22 WAKE_LIN 23 Reserved Table 142. Status Register SR1 (0x31) R R/C Table 143. SR1 signals description Bit Name 23 Reserved 22 WU_STATE 21 Reserved Description -- State of WU input 0: input level is low 1: input level is high The bit shows the momentary status of WU and cannot be cleared ("Live bit") Note: The status is only valid if WU is configured as wake-up input in Configuration Register (0x3F). Otherwise this bit is read at its previous logic state -- 20 WU_WAKE Wake-up by WU: shows wake up source 1: wake-up Bits are latched until a "Read and clear" command 19 WAKE_CAN Wake-up by CAN: shows wake up source 1: wake-up Bits are latched until a "Read and clear" command 18 WAKE_LIN Wake-up by LIN: shows wake up source 1: wake-up Bits are latched until a "Read and clear" command 17 WAKE_TIMER Wake-up by Timer: shows wake up source 1: wake-up Bits are latched until a "Read and clear" command 178/197 DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 143. SR1 signals description (continued) Bit Name 16 DEBUG_ACTIVE 15 V1UV 14 V1_RESTART_2 13 V1_RESTART_1 12 V1_RESTART_0 11 WDFAIL_CNT_3 10 WDFAIL_CNT_2 9 WDFAIL_CNT_1 8 WDFAIL CNT_0 7 DEVICE_STATE_1 6 DEVICE_STATE_0 Description Debug Mode Active: indicates Device is in Debug mode 1: Debug mode The bit shows the momentary status and cannot be cleared ("Live bit") Indicates undervoltage condition at voltage regulator V1 (V1 < VRTx) 1: undervoltage Bit is latched until a "Read and clear" command Indicates the number of TSD2 events which caused a restart of voltage regulator V1 Bits cannot be cleared; counter will be cleared automatically if no additional TSD2 event occurs within 1 minute. Indicates number of subsequent watchdog failures. Bits cannot be cleared; will be cleared with a valid watchdog trigger State from which the device woke up 00: Active mode, after Read&Clear command or after Flash mode state 01: Active mode after wake-up from V1_standby mode (before Read&Clear command) 10: in Active mode after Power-on or after wake-up from Vbat_standby mode (before Read&Clear command) 11: Flash mode (LIN Flash or CAN Flash mode) Bit is latched until a "Read and clear" command After a "read and clear access", the device state will be updated TSD2 Thermal Shutdown 2 was reached Bit is latched until a "Read and clear" command 4 TSD1 Thermal Shutdown 1 was reached (Logical Or combination of all TSD1_CLx; see status register SR6). This bit cannot be cleared directly. It is reset if the corresponding TSD1_CLx bits in SR6 are cleared. 3 FORCED_SLEEP_ TSD2/V1SC 2 FORCED_SLEEP_WD 1 WDFAIL Watchdog failure Bit is latched until a "Read and clear" command 0 VPOR VS Power-on Reset threshold (VPOR) reached Bit is latched until a "Read and clear" command 5 Device entered Forced Vbat_standby mode due to: - Thermal shutdown or - Short circuit on V1 during startup Bit is latched until a "Read and clear" command Device entered Forced Vbat_standby mode due to multiple watchdog failures Bit is latched until a "Read and clear" command DS11546 Rev 5 179/197 196 SPI Registers 7.5.2 L99DZ100G, L99DZ100GP Status Register SR2 (0x32) R/C 9 8 7 6 5 4 3 2 1 0 CP_LOW TW V2SC V2FAIL V1FAIL VSREG_EW VSREG_OV VSREG_UV VS_OV VS_UV SPI_SCK_CNT SPI_INV_CMD DSMON_LS1 CAN_PERM_REC DSMON_LS2 CAN_RXD_REC DSMON_HS1 LIN_PERM_REC Access DSMON_HS2 19 18 17 16 15 14 13 12 11 10 CAN_SUP_LOW 20 CAN_TXD_DOM 21 CAN_PERM_DOM 22 LIN_TXD_DOM Bit name 23 LIN_PERM_DOM Table 144. Status Register SR2 (0x32) R R/C Table 145. SR2 signals description Bit Name 23 LIN_PERM_DOM 22 LIN_TXD_DOM TxDL pin is dominant for t > tdom(TXDL) The LIN transmitter is disabled until the bit is cleared Bit is latched until a "Read and clear" command 21 LIN_PERM_REC LIN bus signal does not follow TxDL within tLIN The LIN transmitter is disabled until the bit is cleared Bit is latched until a "Read and clear" command 20 CAN_RXD_REC RxDC has not followed TxDC for 4 times The CAN transmitter is disabled until the bit is cleared Bit is latched until a "Read and clear" command 19 CAN_PERM_REC CAN bus signal did not follow TxDC for 4 times The CAN transmitter is disabled until the bit is cleared Bit is latched until a "Read and clear" command 18 CAN_PERM_DOM CAN bus signal is dominant for t > tCAN Bit is latched until a "Read and clear" command 17 CAN_TXD_DOM TxDC pin is dominant for t > tdom(TXDC) The CAN transmitter is disabled until the bit is cleared Bit is latched until a "Read and clear" command 16 CAN_SUP_LOW Voltage at CAN supply pin reached the CAN supply low warning threshold VCANSUP < VCANSUPlow Bit is latched until a "Read and clear" command 15 DSMON_HS2 14 DSMON_HS1 13 DSMON_LS2 12 DSMON_LS1 180/197 Description LIN bus signal is dominant for t > tdom(bus) Bit is latched until a "Read and clear" command Drain-Source Monitoring `1' indicates a short-circuit or open-load condition was detected Bit is latched until a "Read and clear" command DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 145. SR2 signals description (continued) Bit Name Description 11 SPI_INV_CMD Invalid SPI command `1' indicates one of the following conditions was detected: - access to undefined address - Write operation to Status Register - DI stuck at '0' or '1' - CSN timeout - Parity failure - invalid or undefined setting The SPI frame is ignored Bit is latched until a "Read and clear" command 10 SPI_SCK_CNT SPI clock counter `1' indicates an SPI frame with wrong number of CLK cycles was detected Bit is latched until a valid SPI frame 9 CP_LOW 8 7 6 5 TW V2SC Charge pump voltage low `1' indicates that the charge pump voltage is too low Bit is latched until a "Read and clear" command Thermal warning `1' indicates the temperature has reached the thermal warning threshold (logical OR combination of bits TW_CLx in SR6) Bit is latched until a "Read and clear" command V2 short circuit detection `1' indicates a short circuit to GND condition of V2 at turn-on of the regulator (V2 < V2_fail for t > tv2_short) Bit is latched until a "Read and clear" command V2FAIL V2 failure detection `1' indicates a V2 fail event occurred since last readout (V2 < V2_fail for t > tv2_fail) Bit is latched until a "Read and clear" command V1FAIL V1 failure detection `1' indicates a V1 fail event occurred since last readout (V1 < V1_fail for t > tv1_fail) Bit is latched until a "Read and clear" command 4 VSREG_EW VSREG early warning `1' indicates the voltage at VSREG has reached the early warning threshold (configured in CR3) In Active mode, an interrupt pulse is generated at NINT Bit is latched until a "Read and clear" command. Bit needs a "Read and clear" command after wake-up from standby modes 3 VSREG_OV VSREG overvoltage `1' indicates the voltage at VSREG has reached the overvoltage threshold Bit is latched until a "Read and clear" command DS11546 Rev 5 181/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 145. SR2 signals description (continued) Bit Name Description VSREG undervoltage `1' indicates the voltage at VSREG has reached the undervoltage threshold Bit is latched until a "Read and clear" command 2 VSREG_UV 1 VS_OV VS overvoltage `1' indicates the voltage at VS has reached the overvoltage threshold Bit is latched until a "Read and clear" command 0 VS_UV VS undervoltage `1' indicates the voltage at VS has reached the undervoltage threshold Bit is latched until a "Read and clear" command 7.5.3 Status Register SR3 (0x33) Access R/C 182/197 DS11546 Rev 5 9 8 7 6 5 4 3 2 1 0 OUT9_OC OUT10_OC OUT11_OC OUT12_OC OUT13_OC OUT14_OC OUT15_OC OUTHS_OC_TH_EX LS2FSO_OC LS1FSO_OC OUT8_OC_TH_EX OUT7_OC_TH_EX OUT6_LS_OC_TH_EX OUT3_HS_OC_TH_EX OUT6_HS_OC_TH_EX OUT2_LS_OC_TH_EX OUT5_LS_OC_TH_EX OUT2_HS_OC_TH_EX OUT5_HS_OC_TH_EX 19 18 17 16 15 14 13 12 11 10 OUT4_LS_OC_TH_EX 20 OUT4_HS_OC_TH_EX 21 OUT3_LS_OC_TH_EX 22 OUT1_LS_OC_TH_EX Bit name 23 OUT1_HS_OC_TH_EX Table 146. Status Register SR3 (0x33) L99DZ100G, L99DZ100GP SPI Registers Table 147. SR3 signals description Bit Name 23 OUT1_HS_OC_TH_EX 22 OUT1_LS_OC_TH_EX 21 OUT2_HS_OC_TH_EX 20 13 OUT2_LS_OC_TH_EX Overcurrent shutdown OUT3_HS_OC_TH_EX `1' indicates the output was shut down due to overcurrent condition. If Overcurrent Recovery is disabled (CR7: OUTx_OCR = 0): OUT3_LS_OC_TH_EX Bit is set upon overcurrent condition and output is turned off. OUT4_HS_OC_TH_EX If Overcurrent Recovery is enabled (CR7: OUTx_OCR = 1): OUT4_LS_OC_TH_EX In case of overcurrent condition this bit is not set. The output goes into Overcurrent Recovery mode and OUTx_OCR_alert in SR4 is set to '1' OUT5_HS_OC_TH_EX In case of Thermal Expiration enabled (CR8: OUTx_OCR_THx_en = 1): OUT5_LS_OC_TH_EX Bit is set after thermal expiration and output is turned off OUT6_HS_OC_TH_EX Bit is latched until a "Read and clear" command 12 OUT6_LS_OC_TH_EX 11 OUT7_OC_TH_EX 10 OUT8_OC_TH_EX 9 OUT9_OC 8 OUT10_OC 7 OUT11_OC 6 OUT12_OC 5 OUT13_OC 4 OUT14_OC 3 OUT15_OC 19 18 17 16 15 14 2 OUTHS_OC_TH_EX 1 LS2FSO_OC 0 LS1FSO_OC Description Overcurrent shutdown `1' indicates the output was shut down due to overcurrent condition. Bit is latched until a "Read and clear" command Overcurrent shutdown `1' indicates the output was shut down due to overcurrent condition. If Overcurrent Recovery is disabled (CR7: OUTx_OCR = 0): Bit is set upon overcurrent condition and output is turned off. If Overcurrent Recovery is enabled (CR7: OUTx_OCR = 1): In case of overcurrent condition this bit is not set. The output goes into Overcurrent Recovery mode and OUTx_OCR_alert in SR4 is set to '1' In case of Thermal Expiration enabled (CR8: OUTx_OCR_THx_en = 1): Bit is set after thermal expiration and output is turned off Bit is latched until a "Read and clear" command Overcurrent shutdown `1' indicates the output was shut down due to overcurrent condition. Bit is latched until a "Read and clear" command DS11546 Rev 5 183/197 196 SPI Registers 7.5.4 L99DZ100G, L99DZ100GP Status Register SR4 (0x34) 2 1 0 Reserved DSMON_HEAT ECV_OC 8 OUTHS_OCR_ALERT 9 OUT8_OCR_ALERT OUT7_OCR_ALERT OUT6_LS_OCR_ALERT OUT3_HS_OCR_ALERT OUT6_HS_OCR_ALERT OUT2_LS_OCR_ALERT OUT5_LS_OCR_ALERT OUT2_HS_OCR_ALERT Access OUT5_HS_OCR_ALERT 19 18 17 16 15 14 13 12 11 10 OUT4_LS_OCR_ALERT 20 OUT4_HS_OCR_ALERT 21 OUT3_LS_OCR_ALERT 22 OUT1_LS_OCR_ALERT Bit name 23 OUT1_HS_OCR_ALERT Table 148. Status Register SR4 (0x34) 7 R/C R R 6 5 4 3 R/C Table 149. SR4 signals description Bit Name 23 OUT1_HS_OCR_ALERT 22 OUT1_LS_OCR_ALERT 21 OUT2_HS_OCR_ALERT 20 OUT2_LS_OCR_ALERT 19 OUT3_HS_OCR_ALERT 18 OUT3_LS_OCR_ALERT 17 OUT4_HS_OCR_ALERT 16 OUT4_LS_OCR_ALERT 15 OUT5_HS_OCR_ALERT 14 OUT5_LS_OCR_ALERT 13 OUT6_HS_OCR_ALERT 12 OUT6_LS_OCR_ALERT 11 OUT7_OCR_ALERT 10 OUT8_OCR_ALERT 9:3 Reserved 2 184/197 OUTHS_OCR_ALERT Description Autorecovery Alert `1' indicates that the output reached the overcurrent threshold and is in autorecovery mode Bit is not latched and cannot be cleared. -- Autorecovery Alert `1' indicates that the output reached the overcurrent threshold and is in autorecovery mode Bit is not latched and cannot be cleared. DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 149. SR4 signals description (continued) Bit Name Description 1 DSMON_HEAT 0 ECV_OC 7.5.5 Drain-Source Monitoring Heater output `1' indicates a short-circuit condition was detected Bit is latched until a "Read and clear" command Overcurrent shutdown `1' indicates the output was shut down due to overcurrent condition. Bit is latched until a "Read and clear" command Status Register SR5 (0x35) Access 7 6 5 4 3 2 OUT10_OL OUT11_OL OUT12_OL OUT13_OL OUT14_OL OUT15_OL OUTHS_OL 1 0 ECV_OL 8 GH_OL 9 OUT9_OL OUT8_OL OUT7_OL OUT6_LS_OL OUT3_HS_OL OUT6_HS_OL OUT2_LS_OL OUT5_LS_OL OUT2_HS_OL OUT5_HS_OL 19 18 17 16 15 14 13 12 11 10 OUT4_LS_OL 20 OUT4_HS_OL 21 OUT3_LS_OL 22 OUT1_LS_OL Bit name 23 OUT1_HS_OL Table 150. Status Register SR5 (0x35) R/C DS11546 Rev 5 185/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 151. SR5 signals description Bit Name 23 OUT1_HS_OL 22 OUT1_LS_OL 21 OUT2_HS_OL 20 OUT2_LS_OL 19 OUT3_HS_OL 18 OUT3_LS_OL 17 OUT4_HS_OL 16 OUT4_LS_OL 15 OUT5_HS_OL 14 OUT5_LS_OL 13 OUT6_HS_OL 12 OUT6_LS_OL 11 OUT7_OL 10 OUT8_OL 9 OUT9_OL 8 OUT10_OL 7 OUT11_OL 6 OUT12_OL 5 OUT13_OL 4 OUT14_OL 3 OUT15_OL 2 OUTHS_OL 1 GH_OL 0 ECV_OL 186/197 Description Open-load `1' indicates an open-load condition was detected at the output Bit is latched until a "Read and clear" command DS11546 Rev 5 L99DZ100G, L99DZ100GP 7.5.6 SPI Registers Status Register SR6 (0x36) Access R R/C 3 2 TSD1_CL3 1 0 TSD1_CL1 4 TSD1_CL2 5 TSD1_CL4 6 TSD1_CL5 TW_CL1 R 7 TSD1_CL6 8 Reserved 9 TW_CL2 TW_CL3 TW_CL4 TW_CL5 Reserved TW_CL6 19 18 17 16 15 14 13 12 11 10 Reserved 20 ECV_VHI 21 ECV_VNR 22 WD_TIMER_STATE_0 Bit name 23 WD_TIMER_STATE_1 Table 152. Status Register SR6 (0x36) R/C Table 153. SR6 signals description Bit 23 22 21:18 Name Description WD_TIMER_STATE_1 Watchdog timer status 00: 0 - 33% WD_TIMER_STATE_0 01: 33 - 66% 11: 66 - 100% Reserved -- 17 ECV_VNR Electrochrome voltage not reached: electrochrome voltage status '1' indicates the electrochrome voltage is not reached Bit is not latched 16 ECV_VHI Electrochrome voltage high: electrochrome voltage status '1' indicates the electrochrome voltage is not reached Bit is not latched 15:14 Resrved -- 13 TW_CL6 12 TW_CL5 11 TW_CL4 10 TW_CL3 9 TW_CL2 8 TW_CL1 7:6 Reserved Thermal warning for Cluster x `1' indicates Cluster x has reached the thermal warning threshold Bit is latched until a "Read and clear" command -- DS11546 Rev 5 187/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 153. SR6 signals description (continued) Bit Name 5 TSD1_CL6 4 TSD1_CL5 3 TSD1_CL4 2 TSD1_CL3 1 TSD1_CL2 0 TSD1_CL1 7.5.7 Description Thermal shutdown of Cluster x `1' indicates Cluster x has reached the thermal shutdown threshold (TSD1) and the output cluster was shut down Bit is latched until a "Read and clear" command Status Register SR7 (0x37) to SR9 (0x39) R TEMP_CLy_8 TEMP_CLy_7 TEMP_CLy_6 TEMP_CLy_5 R/C 4 3 2 1 0 TEMP_CLy_0 5 TEMP_CLy_1 6 TEMP_CLy_2 7 TEMP_CLy_3 8 TEMP_CLy_4 9 TEMP_CLy_9 Reserved TEMP_CLx_0 TEMP_CLx_1 TEMP_CLx_2 TEMP_CLx_3 TEMP_CLx_4 TEMP_CLx_5 R/C 19 18 17 16 15 14 13 12 11 10 TEMP_CLx_6 Access 20 TEMP_CLx_7 Bit name 21 TEMP_CLx_8 22 Reserved 23 TEMP_CLx_9 Table 154. Status Register SR7 (0x37) to SR9 (0x39) R Where: x = 2 + (z * 2), z = 0 to 2 y = 1 + (z * 2), z = 0 to 2 Table 155. SR7 to SR9 signals description Bit Name 23:22 Reserved 21 TEMP_CLx_9 20 TEMP_CLx_8 19 TEMP_CLx_7 18 TEMP_CLx_6 17 TEMP_CLx_5 16 TEMP_CLx_4 15 TEMP_CLx_3 14 TEMP_CLx_2 13 TEMP_CLx_1 12 TEMP_CLx_0 11:10 Reserved 188/197 Description -- Temperature Cluster x: Binary coded voltage of temperature diode for cluster x (bit12 = LSB; bit21 = MSB) (see Section 4.34: Thermal clusters) Bits cannot be cleared. -- DS11546 Rev 5 L99DZ100G, L99DZ100GP SPI Registers Table 155. SR7 to SR9 signals description (continued) Bit Name 9 TEMP_CLy_9 8 TEMP_CLy_8 7 TEMP_CLy_7 6 TEMP_CLy_6 5 TEMP_CLy_5 4 TEMP_CLy_4 3 TEMP_CLy_3 2 TEMP_CLy_2 1 TEMP_CLy_1 0 TEMP_CLy_0 7.5.8 Description Temperature Cluster y: binary coded voltage of temperature diode for cluster y (bit0 = LSB; bit9 = MSB) (see Section 4.34: Thermal clusters) Bits cannot be cleared. Status Register SR10 (0x3A) 9 VSREG_0 VSREG_1 VSREG_2 VSREG_3 VSREG_4 VSREG_5 R/C 19 18 17 16 15 14 13 12 11 10 VSREG_6 Access 20 VSREG_7 Bit name 21 VSREG_8 22 Reserved 23 VSREG_9 Table 156. Status Register SR10 (0x3A) 8 7 6 5 4 3 2 1 0 Reserved R R/C Table 157. SR10 signals description Bit Name 23:22 Reserved 21 VSREG_9 20 VSREG_8 19 VSREG_7 18 VSREG_6 17 VSREG_5 16 VSREG_4 15 VSREG_3 14 VSREG_2 13 VSREG_1 12 VSREG_0 11:0 Reserved Description -- Binary coded voltage at VSREG pin (bit12 = LSB; bit21 = MSB) 00 0000 0000: 0V xx xxxx xxxx: VAINVS/1023 x register value 11 1111 1111: VAINVS Bits cannot be cleared. -- DS11546 Rev 5 189/197 196 SPI Registers 7.5.9 L99DZ100G, L99DZ100GP Status Register SR11 (0x3B) R VWU_8 VWU_7 VWU_6 VWU_5 R/C Table 159. SR11 signals description Bit Name 23 Reserved 21 VS_9 20 VS_8 19 VS_7 18 VS_6 17 VS_5 16 VS_4 15 VS_3 14 VS_2 13 VS_1 12 VS_0 11:10 Reserved 9 VWU_9 8 VWU_8 7 VWU_7 6 VWU_6 5 VWU_5 4 VWU_4 3 VWU_3 2 VWU_2 1 VWU_1 0 VWU_0 190/197 Description -- Binary coded voltage at VS pin (bit12 = LSB; bit21 = MSB) 00 0000 0000: 0V xx xxxx xxxx: VAINVS/1023 x register value 11 1111 1111: VAINVS Bits cannot be cleared. -- Binary coded voltage at WU pin (bit0 = LSB; bit9 = MSB) 00 0000 0000: 0V xx xxxx xxxx: VAINVS/1023 x register value 11 1111 1111: VAINVS Bits cannot be cleared. DS11546 Rev 5 4 3 2 1 0 VWU_0 5 VWU_1 6 VWU_2 7 VWU_3 8 VWU_4 9 VWU_9 Reserved VS_0 VS_1 VS_2 VS_3 VS_4 VS_5 R/C 19 18 17 16 15 14 13 12 11 10 VS_6 Access 20 VS_7 Bit name 21 VS_8 22 Reserved 23 VS_9 Table 158. Status Register SR11 (0x3B) R L99DZ100G, L99DZ100GP 7.5.10 SPI Registers Status Register SR12 (0x3C) Access R/C R SWRD_CR23 SYSERR OSC_FAIL CAN_SILENT R/C 4 3 2 1 0 FDERR 5 WUF 6 WUP 7 CANTO 8 TX_SYNC 9 SWRD_CR24 SWRD_CR25 SWRD_CR26 SWRD_CR27 SWRD_CR28 SWRD_CR29 Reserved FECNT_0 19 18 17 16 15 14 13 12 11 10 FECNT_1 20 FECNT_2 21 FECNT_3 Bit name 22 Reserved 23 FECNT_4 Table 160. Status Register SR12 (0x3B) R Table 161. SR12 signals description Bit Name 23:21 Reserved -- 20 FECNT_4 19 FECNT_3 18 FECNT_2 17 FECNT_1 16 FECNT_0 CAN Frame Detect Error Counter This counter is increased by 1 in case a frame was not received/decoded correctly (CRC error, stuff-bit error, form error). The counter is decreased by 1 with every frame which is decoded correctly If FECNT = 31, the next erroneous frame will wake-up the device, set FDERR = 1 and reset FECNTx = 0 `Live' Bit Updated after each sent CAN Frame 15 Reserved -- 14 SWRD_CR29 13 SWRD_CR28 12 SWRD_CR27 11 SWRD_CR26 10 SWRD_CR25 9 SWRD_CR24 8 SWRD_CR23 7 SYSERR 6 OSC_FAIL Description Status flag for Read operation to Selective Wakeup relevant Registers 0: Read not done 1: Read done All bits must be `1' in order to allow activation of selective wake-up (set SWEN = 1) Bits are automatically cleared if the configuration of the respective Control Register is modified CAN System Error Bit is a logical OR combination of: NOT(SWRD_x) OR OSC_Fail OR FD_ERR If SWRD_x are all 1, OSC_Fail is 0 and FD_ERR is 0, this bit is 0, otherwise this bit is 1. The selective wake feature cannot be enabled (SW_EN = 1) if SYS_ERR = 1 In case of a SYS_ERR the selective wake-up feature is disabled (SW_EN = 0) Live bit; will be updated upon change of SWRD_x, OSC_Fail and FD_ERR CAN selective wake oscillator failure OSC Failure Flag (used device internally) Bit is latched until a read and clear access DS11546 Rev 5 191/197 196 SPI Registers L99DZ100G, L99DZ100GP Table 161. SR12 signals description (continued) Bit Name Description 5 CAN_SILENT Online monitoring bit to see if there is silence on the bus for longer than tSilence This flag shows the actual status of the CAN bus (activity/silence). A microcontroller in Stop mode may check this flag priodically 4 TX_SYNC Status flag for synchronous reference oscillator of the CAN transceiver. Indicates that the last received frame was decoded correctly 0: Not synchronous 1: Synchronous `Live' Bit Updated after each sent CAN Frame CAN communication timeout Bit is set if there is no communication on the bus for t > tSilence CANTO indicates that there was a transition from TRX BIAS to TRX Sleep Bit is latched until a read and clear access 3 CANTO 2 WUP Wake up flag for Wake up Pattern Bit is latched until a read and clear access 1 WUF Wake up flag for Wake up Frame Bit is latched until a read and clear access 0 192/197 FDERR Frame Detect Error This bit is set at overflow of the Frame Error Counter (FECNT) in SR12 In case of a Frame Detect Error, the device will wake up from TRX BIAS mode Bit is latched until a read and clear access DS11546 Rev 5 L99DZ100G, L99DZ100GP 8 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 8.1 LQFP-64 package information Figure 62. LQFP-64 package dimension ("1($'5 Table 162. LQFP-64 mechanical data Millimeters Symbol Min. Typ. Max. 0 3.5 6 1 0 9 12 2 11 12 13 3 11 12 13 DS11546 Rev 5 193/197 196 Package information L99DZ100G, L99DZ100GP Table 162. LQFP-64 mechanical data (continued) Millimeters Symbol Min. Typ. A 1.60 A1 0.05 A2 1.35 0.15 1.40 b 0.17 c 0.09 c1 0.09 0.20 0.23 0.20 0.127 D 12.00 BSC D1 10.00 BSC D2 0.16 6.85 5.7 e 0.50 BSC E 12.00 BSC E1 10.00 BSC E2 4.79 E3 3.3 L 0.45 0.60 L1 1.00 N 64 R1 0.08 R2 0.08 S 0.20 aaa 0.20 bbb 0.20 ccc 0.08 ddd 0.08 DS11546 Rev 5 0.75 0.20 Tolerance of form and position 194/197 1.45 0.27 b1 D3 Max. L99DZ100G, L99DZ100GP Package information Figure 63. LQFP-64 footprint ("1($'5 8.2 LQFP-64 marking information Figure 64. LQFP-64 marking information .BSLJOHBSFB .BSLJOHBSFB PS 4QFDJBMGVODUJPOEJHJUT &4&OHJOFFSJOHTBNQMF CMBOL$PNNFSDJBMTBNQMF -2'15017*&8 OPUJOTDBMF ("%(."( Parts marked as ES are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples. DS11546 Rev 5 195/197 196 Revision history 9 L99DZ100G, L99DZ100GP Revision history Table 163. Document revision history 196/197 Date Revision Changes 16-Mar-2016 1 Initial release. 01-Sep-2016 2 Updated Table 3: Absolute maximum ratings; Updated Table 12: Reset output; Updated Table 15: Charge pump electrical characteristics; Updated Table 17: Power outputs switching times; Updated Table 18: Current monitoring; Updated Table 20: H-bridge driver; Updated Section 4.7.2: Non-recoverable failures - forced Vbat_standby mode; Updated Table 115: CR10 signals description; Updated Table 143: SR1 signals description; Added Section 8.2: LQFP-64 marking information 12-Sep-2016 3 Updated Table 4: ESD protection. 29-Sep-2016 4 Added AEC Q100 compliant qualified Updated Section 8.2: LQFP-64 marking information 11-Mar-2019 5 Moved "Device summary" table in cover page. Added the "Sustainable Technology" logo to the datasheet in cover page. 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2019 STMicroelectronics - All rights reserved DS11546 Rev 5 197/197 197