ACPM-7891
Tri-Band Power Amplifier Module
EGSM, DCS and PCS Multi-slot GPRS
Data Sheet and Application Note
Description
The ACPM-7891 is a fully matched tri-band EGSM/
DCS/PCS power amplifier module designed on Avago
Technologies’ leading edge Enhancement Mode
PHEMT (E-pHEMT) process.
The ACPM-7891 has the highest Power-added Efficiency
(PAE) for all three bands of operation in the industry,
enabling customers to design handset, PDA and data
card with up to 15% longer transmit or talk time.
The Avago ACPM-7891 provides a cost effective dual
or tri-band GSM PA solution with the additional ben-
efit of excellent efficiency enabling multi-slot GPRS
operation and extended transmit time. The device is
internally matched to 50Ω and therefore an effective
design can be implemented quickly with a few addi-
tional capacitors for d.c. blocking of the output ports
and bypassing of the supply pins.
Features
• Highest Power Added Efficiency in the industry
•
Performance guaranteed for GPRS Class 10 (2-Slot)
transmit operation
• Broadband DCS/PCS match for flat Pout and PAE
• Low harmonics
• Single 3.5 Volt supply (nominal)
• 50 Ohms input & output impedance
• Small SMT package 6 x 12 x 1.4 mm
Specifications
• 60% PAE at +35 dBm Pout for ESGM
• 56% PAE at +32.5 dBm Pout for DCS 1800
• 56% PAE at +32.5 dBm Pout for PCS 1900
Applications
• Cellular handsets
• Data modules for PDA
• Data cards for laptops
1
13 Gnd
12 Gnd
11 RF
out
DCS/PCS
10 Gnd
9 Gnd
8 Gnd
7
Gnd
6
RF
out
EGSM
5 Gnd
18
RF
in
DCS/PCS
RF
in
EGSM
V
dd1,2
DCS/PCS
19Gnd
20
21
V
dd1,2
Bypass
22Gnd
Gnd
23
V
dd1,2
Bypass
V
dd1,2
EGSM 24
25
26
Gnd
2
V
apc
EGSM
3
Gnd YYWWDDLLLL
Agilent
ACPM-7891
4
17 16 15 14
V
dd3
EGSM
Gnd
V
apc
DCS/PCS
Gnd
V
dd3
DCS/PCS
Pin Connections and Package Marking
Notes:
Package marking provides orientation and identification.
“YYWWDDLLLL” = Year, Week, Day and Lot Code indicates the year, week,
day and lot of manufacture.
2
Absolute Maximum Ratings
Symbol Parameter Units Absolute Maximum
Vdd Supply Voltage V 6
Pin max Input Power dBm +10
Vapc Gain Control Voltage V 4
IDS Operating Case Temperature °C -30 to 90
TSTG Storage Temperature °C -40 to 125
Common Electrical Characteristics
Test conditions Vdd = +3.5V, a pulse width of 1154 µs and a duty cycle of 25% at a case temperature of +25°C unless otherwise stated.
Parameter Test Conditions Symbol Min Typ Max Units
Supply Voltage Vdd 2.7 3.5 5.3 V
Leakage Current Vapc= 0.06V Idd 20 µA
Control Voltage Range Vapc 0V
dd – 0.3 V
Control Current Iapc 3mA
Nominal Input Impedance Zin 50 Ω
Nominal Output Impedance Zout 50 Ω
Rise And Fall Time Tr to (Pout1 – 0.5 dB) Vapc set to achieve Pout1 tr,tf12 µs
3
EGSM Electrical Characteristics
Test conditions Vdd= +3.5V, a pulse width of 1154 µs and a duty cycle of 25% at a case temperature of +25°C unless otherwise stated.
Parameter Test Conditions Symbol Min Typ Max Units
Frequency Range Fo880 900 915 MHz
Output Power Nominal Conditions Pin = +2 dBm Pout1 34.5 35 dBm
Vapc = 2.2V
Efficiency Pout=Pout1 PAE 55 60 %
Output Power in off mode Vapc = 0.2V, Pin = 4 dBm -40 -36 dBm
Input Power Pin 0 2 4 dBm
Input VSWR Pin = 0 dBm 1.5 2.5
Stability Vdd = 3.0 to 5.3V, No parasitic oscillation > -36 dBm
Pin = 0– 4 dBm,
Pout ≤34.5 dBm,
Vapc ≤2.2V,
VSWR ≤8:1, all phases
Load mismatch robustness Vdd = 3.0 to 5.3V, No module damage or permanent degradation
Pin = 0– 4 dBm,
Pout ≤34.5 dBm,
Vapc ≤2.2V,
VSWR ≤10:1, all phases
t = 20 sec
Second Harmonic Vdd = 3.5V 2Fo-5 dBm
Pin = 0 dBm
Pout = 34.5 dBm
Vapc = controlled for Pout
Third Harmonic Vdd = 3.5V 3Fo-5 dBm
Pin = 0 dBm
Pout = 34.5 dBm
Vapc = controlled for Pout
Fourth to Eighth Harmonics Vdd = 3.5V 4Fo-8Fo-10 dBm
Pin = 0 dBm
Pout = 34.5 dBm
Vapc = controlled for Pout
Noise Power F=925 to 935 MHz, Pn-72 dBm
Pout ≤34.0 dBm,
Pin = 0 dBm
RBW = 100 kHz
F = 925 to 960 MHz, Pn-82 dBm
Pout ≤34.0 dBm,
Pin = 0 dBm
RBW = 100 kHz
Band to Band Isolation Measured at DCS freq EGSM signal: -25 dBm
Vdd = 3.5V
Pin = +2 dBm
Pout = 34.5 dBm (fixed)
Control Slope (Peak) Pout = -5 dBm to Pout 400 dB/V
AM-AM Pin = 0– 4 dBm 5 dB/dB
Pout = 6 dBm to Pout
AM-PM Pin = 0– 4 dBm 6 deg/dB
Pout = 6 dBm to Pout
4
DCS & PCS Electrical Characteristics
Test conditions Vdd= +3.5V, a pulse width of 1154 µs and a duty cycle of 25% at a case temperature of +25°C unless otherwise stated.
Parameter Test Conditions Symbol Min Typ Max Units
Frequency Range DCS Fo1710 1750 1785 MHz
PCS 1850 1880 1910
Output Power Nominal Conditions Pin = 2 dBm Pout1 32.0 32.5 dBm
Vapc = 2.2V
Efficiency Pout = Pout1 DCS PAE 50 56 %
PCS PAE 50 56
Output Power in off mode Vapc = 0.2V, Pin = 4 dBm -40 -36 dBm
Input Power Pin 0 2 4 dBm
Input VSWR Pin = 0 dBm 1.5 2.5
Stability Vdd = 3.0 to 5.3V, No parasitic oscillation > -36 dBm
Pin = 0– 4 dBm,
Pout ≤32 dBm,
Vapc ≤2.2V,
VSWR ≤8:1, all phases
Load mismatch robustness Vdd = 5.3V, No module damage or permanent degradation
Pin = 0– 4 dBm,
Pout ≤32 dBm,
Vapc ≤2.2V,
VSWR ≤10:1, all phases
t = 20 sec
Second Harmonic Vdd = 3.5V 2Fo-5 dBm
Pin = 0 dBm
Pout = 32 dBm
Vapc = controlled for Pout
Third Harmonic Vdd = 3.5V 3Fo-5 dBm
Pin = 0 dBm
Pout = 32 dBm
Vapc = controlled for Pout
Fourth to Eighth Harmonics Vdd = 3.5V 4Fo – 8Fo-10 dBm
Pin = 0 dBm
Pout = 32 dBm
Vapc = controlled for Pout
Noise Power F = 1805 to 1880 MHz, Pn-77 dBm
F = 1930 to 1990 MHz,
Pout ≤31.5 dBm,
Pin = 0 dBm
RBW = 100 kHz
Control Slope (Peak) Pout = -5 dBm to Pout1 350 dB/V
AM-AM Pin = 0 – 4 dBm 5 dB/dB
Pout = 6 dBm to Pout1
AM-PM Pin = 0 – 4 dBm 6 deg/dB
Pout = 6 dBm to Pout1
5
GPRS Electrical Characteristics
Test conditions Vdd= +3.5V, a pulse width of 1154 µs and a duty cycle of 25% at a case temperature of +25°C unless otherwise stated.
Psat: Pin = 0 dBm; Vapc = 2.2V
Pout (dBm) PAE (%)
880 MHz 900 MHz 915 MHz 880 MHz 900 MHz 915 MHz
Class 8 (1-slot) 35.18 35.40 35.40 60.23 60.47 59.55
Class 10 (2-slot) 35.15 35.45 35.43 60.07 61.02 59.77
Class 12 (4-slot) 35.16 35.32 35.36 60.09 59.62 59.35
Psat: Pin = 0 dBm; Vapc = 2.2V
Pout (dBm) PAE (%)
1710 MHz 1750 MHz 1785 MHz 1710 MHz 1750 MHz 1785 MHz
Class 8 (1-slot) 33.00 33.08 33.12 59.00 59.19 59.62
Class 10 (2-slot) 33.00 33.08 33.10 59.35 59.42 59.40
Class 12 (4-slot) 33.00 33.08 33.10 59.35 59.42 59.40
Psat: Pin = 0 dBm; Vapc = 2.2V
Pout (dBm) PAE (%)
1850 MHz 1880 MHz 1910 MHz 1850 MHz 1880 MHz 1910 MHz
Class 8 (1-slot) 33.10 33.10 33.02 59.14 58.93 58.66
Class 10 (2-slot) 33.10 33.10 33.02 59.14 58.93 58.66
Class 12 (4-slot) 33.10 33.04 32.96 58.75 58.50 58.25
6
Typical Performance
Test conditions: Vdd = +3.5V, case temperature of +25°C, and Zo=50 ohms unless otherwise stated.
Vdd (V)
Figure 1. PAE and Pout vs Vdd
(EGSM Band, Pin = 2 dBm, Vapc = 2.2V).
Pout (dBm)
2.7 3.1 3.7 3.9
PAE
Pout
3.32.9 3.5
37
36
35
34
33
32
31
PAE (%)
64
62
60
58
56
54
52
Vdd (V)
Figure 2. PAE and Pout vs Vdd
(DCS 1750 MHz, Pin = 2 dBm, Vapc = 2.2V).
Pout (dBm)
2.7 3.1 3.7 3.93.32.9 3.5
34
33
32
31
30
29
28
PAE (%)
58
56
54
52
50
48
46
PAE
Pout
Vdd (V)
Figure 3. PAE and Pout vs Vdd
(PCS 1880 MHz, Pin = 2 dBm, Vapc = 2.2V).
Pout (dBm)
2.7 3.1 3.7 3.93.32.9 3.5
34
33
32
31
30
29
28
PAE (%)
58
56
54
52
50
48
46
PAE
Pout
Vapc (V)
Figure 4. Pout and Idd vs Vapc
(EGSM Band, Pin = 0 dBm, Vdd = 3.5V).
Pout (dBm)
0.75 1.25 2.251.75
40
30
20
10
0
-10
-20
-30
-40
-50
-60
Idd (mA)
2000
1800
1600
1400
1200
1000
800
600
400
200
0
Idd
Pout
Vapc (V)
Figure 5. Pout and Idd vs Vapc
(DCS 1750 MHz, Pin= 0 dBm, Vdd = 3.5V).
Pout (dBm)
0.75 1.25 2.251.75
40
30
20
10
0
-10
-20
-30
-40
-50
-60
Idd (mA)
1000
900
800
700
600
500
400
300
200
100
0
Idd
Pout
Vapc (V)
Figure 6. Pout and Idd vs Vapc
(PCS 1880 MHz, Pin= 0 dBm, Vdd = 3.5V).
Pout (dBm)
0.75 1.25 2.251.75
40
30
20
10
0
-10
-20
-30
-40
-50
-60
Idd (mA)
1000
900
800
700
600
500
400
300
200
100
0
Idd
Pout
Vapc (V)
Figure 7. Pout and Idd vs Vapc
(Vdd EGSM Band, Pin = 0 dBm, Vdd = 3.0V).
Pout (dBm)
0.75 1.25 2.25
Idd
Pout
1.75
40
30
20
10
0
-10
-20
-30
-40
-50
-60
Idd (mA)
2000
1800
1600
1400
1200
1000
800
600
400
200
0
Vapc (V)
Figure 8. Pout and Idd vs Vapc
(DCS 1750 MHz, Pin = 0 dBm, Vdd = 3.0V).
Pout (dBm)
0.75 1.25 2.25
Idd
Pout
1.75
40
30
20
10
0
-10
-20
-30
-40
-50
-60
Idd (mA)
1000
900
800
700
600
500
400
300
200
100
0
Vapc (V)
Figure 9. Pout and Idd vs Vapc
(PCS 1880 MHz, Pin = 0 dBm, Vdd = 3.0V).
Pout (dBm)
0.75 1.25 2.251.75
40
30
20
10
0
-10
-20
-30
-40
-50
-60
Idd (mA)
1000
900
800
700
600
500
400
300
200
100
0
Idd
Pout
7
Typical Performance, continued
Test conditions: Vdd = +3.5V, case temperature of +25°C, and Zo=50 ohms unless otherwise stated.
FREQUENCY (MHz)
Figure 10. 2nd and 3rd Harmonic Performance
(EGSM Band, Pin = 0 dBm, Pout = 34.5 dBm,
Vdd = 3.5V).
HARMONICS (dBm)
880 890 915895885 910905900
-10
-15
-20
-25
-30
-35
-40
2nd Fo
3rd Fo
FREQUENCY (MHz)
Figure 11. 2nd and 3rd Harmonic Performance
(DCS Band, Pin = 0 dBm, Pout = 32 dBm,
Vdd = 3.5V).
HARMONICS (dBm)
1710 1730 17401720 1770 178017601750
-10
-15
-20
-25
-30
2nd Fo
3rd Fo
FREQUENCY (MHz)
Figure 12. 2nd and 3rd Harmonic Performance
(PCS Band, Pin = 0 dBm, Pout = 32 dBm,
Vdd = 3.5V).
HARMONICS (dBm)
1850 1960 1870 1900 1910
1890
1880
-25
-28
-31
-34
-37
-40
2nd Fo
3rd Fo
FREQUENCY (MHz)
Figure 13. 2nd and 3rd Harmonic Performance
(EGSM Band, Pin = 0 dBm, Pout = 34.5 dBm,
Vdd = 3.0V).
HARMONICS (dBm)
880 890
2nd Fo
3rd Fo
895885 910 915905900
-10
-15
-20
-25
-30
-35
-40
FREQUENCY (MHz)
Figure 14. 2nd and 3rd Harmonic Performance
(DCS Band, Pin = 0 dBm, Pout = 32 dBm,
Vdd = 3.0V).
HARMONICS (dBm)
1710 1730 17401720 1770 178017601750
-15
-20
-25
-30
-35
2nd Fo
3rd Fo
FREQUENCY (MHz)
Figure 15. 2nd and 3rd Harmonic Performance
(PCS Band, Pin = 0 dBm, Pout = 32 dBm,
Vdd = 3.0V).
HARMONICS (dBm)
1850 1870 18801860 1900 19101890
-20
-25
-30
-35
-40
2nd Fo
3rd Fo
FREQUENCY (MHz)
Figure 16. Isolation Performance
(EGSM Band, Pin = 4 dBm, Vapc = 0.2V).
ISOLATION (dBm)
880 890 895885 910 915905900
-51
-52
-52
-53
-53
-54
-54
-55
-55
3.0V
3.5V
FREQUENCY (MHz)
Figure 17. Isolation Performance
(DCS Band, Pin = 4 dBm, Vapc = 0.2V).
ISOLATION (dBm)
1710 1730 1740
1720 1770 178017601750
-40
-41
-42
-43
-44
-45
3.0V
3.5V
FREQUENCY (MHz)
Figure 18. Isolation Performance
(PCS Band, Pin=4 dBm, Vapc=0.2V).
ISOLATION (dBm)
1850 1870 18801860 1900 19101890
-36
-37
-38
-39
-40
-41
3.0V
3.5V
8
Typical Performance, continued
Test conditions: Vdd = +3.5V, case temperature of +25°C, and Zo=50 ohms unless otherwise stated.
Vapc (V)
Figure 19. Pout/Vapc and Idd/Vapc vs. Vapc
(EGSM band, Vdd = 3.5V).
Pout/Vapc (dB/V)
0.95 1.45 2.45
Idd/Vapc
Pout/Vapc
1.95
300
250
200
150
100
50
0
Idd/Vapc (mA/V)
3000
2500
2000
1500
1000
500
0
Vapc (V)
Figure 20. Pout/Vapc and Idd/Vapc vs. Vapc
(DCS 1750 MHz, Vdd = 3.5V).
Pout/Vapc (dB/V)
0.70 1.20 2.201.70
350
300
250
200
150
100
50
0
Idd/Vapc (mA/V)
3500
3000
2500
2000
1500
1000
500
0
Idd/Vapc
Pout/Vapc
Vapc (V)
Figure 21. Pout/Vapc and Idd/Vapc vs. Vapc
(PCS 1880 MHz, Vdd = 3.5V).
Pout/Vapc (dB/V)
0.90 1.40 2.401.90
300
250
200
150
100
50
0
Idd/Vapc (mA/V)
3000
2500
2000
1500
1000
500
0
Idd/Vapc
Pout/Vapc
Vapc (V)
Figure 22. Pout/Vapc and Idd/Vapc vs. Vapc
(EGSM band, Vdd = 3.0V).
Pout/Vapc (dB/V)
0.95 1.45 2.451.95
300
250
200
150
100
50
0
Idd/Vapc (mA/V)
3000
2500
2000
1500
1000
500
0
Idd/Vapc
Pout/Vapc
Vapc (V)
Figure 23. Pout/Vapc and Idd/Vapc vs. Vapc
(DCS 1750 MHz, Vdd = 3.0V).
Pout/Vapc (dB/V)
0.90 1.40 2.401.90
300
250
200
150
100
50
0
Idd/Vapc (mA/V)
3000
2500
2000
1500
1000
500
0
Idd/Vapc
Pout/Vapc
Vapc (V)
Figure 24. Pout/Vapc and Idd/Vapc vs. Vapc
(PCS 1880 MHz, Vdd = 3.0V).
Pout/Vapc (dB/V)
0.90 1.40 2.401.90
300
250
200
150
100
50
0
Idd/Vapc (mA/V)
3000
2500
2000
1500
1000
500
0
Idd/Vapc
Pout/Vapc
9
Pin Description Table
No. Function Description Notes
1 Gnd
2 Vapc EGSM EGSM Control Voltage See datasheet Figure 4
3 Gnd
4 Vdd3 EGSM EGSM Supply 3rd stage 3.5V nominal – output stage, bypass with 0.033 µF//220 pF[1]
5 Gnd
6 Gnd
7 RFout EGSM EGSM Output 50Ω nominal, external d.c. blocking required – 33 pF
8 Gnd
9 Gnd
10 Gnd
11 RFout DCS/PCS DCS/PCS Output 50Ω nominal, external d.c. blocking required – 33 pF
12 Gnd
13 Gnd
14 Vdd3 DCS/PCS DCS/PCS Supply 3rd stage 3.5V nominal – output stage, bypass with 0.033 µF//27 pF[1]
15 Gnd
16 Vapc DCS/PCS DCS/PCS Control voltage See datasheet Figure 5 (DCS) and Figure 6 (PCS)
17 Gnd
18 RFin DCS/PCS DCS/PCS Input +2 dBm GMSK, 50Ω nominal, internally d.c. blocked
19 Gnd
20 Vdd1,2 DCS/PCS DCS/PCS Supply 1st and 2nd stages 3.5V nominal – driver stages, bypass with 0.033 µF
21 Vdd1,2 Bypass DCS/PCS 1st and 2nd stage bypassing bypass with 12 pF
22 Gnd
23 Vdd1,2 Bypass EGSM 1st and 2nd stage bypassing bypass with 220 pF
24 Vdd1,2 EGSM EGSM Supply 1st and 2nd stages 3.5V nominal – driver stages, bypass with 0.033 µF
25 Gnd
26 RFin EGSM EGSM Input +2 dBm GMSK, 50Ω nominal, internally d.c. blocked
Note:
1. In addition a 2.2 µF capacitor should be connected to pins 4 and 14 or alternatively star connections can be made from a single 2.2 µF capacitor keeping
the connection distances as short as possible.
C7
4
7C8 EGSM RFout
1Vdd
Vdd
14
DCS/PCS RFin 18
20
C2
Vdd
Agilent
ACPM-7891
YYWW
Vdd
11 C11 DCS/PCS RFout
C9
C13
21
C3
23
C4
24
C5
C14
EGSM RFin 26
Component
Label
C2
C3
C4
C5
C7
C8
C9
C11
C13
C14
Component
Value
.033 µF
12 pF
220 pF
.033 µF
220 pF
33 pF
.033 µF
33 pF
.033 µF
27 pF
Demo Board Schematic for PA Only
10
Ordering Information
Part Number No. of Devices Container
ACPM-7891-BLK 10 Bulk
ACPM-7891-TR1 1000 13” Tape and Reel
Package Dimensions
1
13
12
11
10
9
8
7
6
50.0352 (0.92)
0.0080 (0.20)
18
19
20
21
22
23
24
25
26
23
Agilent
ACPM-7891
YYWWDDLLLL
4
17 16 15 14
0.0000 (0.00)
0.0300 (0.76)
0.0430 (1.09)
0.1932 (4.91)
0.2792 (7.09)
0.4295 (10.91)
0.4644 (11.80)
0.0590 (1.50)
0.0000 (0.00)
0.2362 (6.00)
0.0382 (0.92) 0.0430 (1.09)
0.1932 (4.91)
0.2282 (5.80)
0.0582 (1.48)
0.0835 (2.12)
0.1307 (3.32)
0.1780 (4.52)
0.2062 (5.24)
0.0582 (1.48)
0.0835 (2.12)
0.1307 (3.32)
0.1780 (4.52)
0.2252 (5.72)
0.2725 (6.92)
0.3197 (8.12)
0.3670 (9.32)
0.4142 (10.52)
0.4424 (11.24)
0.4724 (12.00)
Note:
Measurements are in inches (millimeters).
TOP VIEW END VIEW BOTTOM VIEW
11
Tape Dimensions and Device Orientation
Agilent
ACPM-7891
YYWWDDLLLL
Notes:
Drawing not to scale.
Measurements are in millimeters (inches).
12.20 (0.476)
2.25 (0.088)
24.00 ± 0.30 (0.936±0.012)
11.50 ± 0.10 (0.449±0.004)
1.75±0.100 (0.068±0.004)
6.66 (0.260)
DEVICE IN CARRIER TAPE
CARRIER TAPE
12.00 (0.468)
PIN 1 position (permanent)
4.00±0.10 (0.156±0.004)
ACPM-7891 carrier tape
ACPM-7891
in carrier tape
2.00±0.10 (0.078±0.004)
∅1.50 (∅0.059)
∅1.50±0.100 (∅0.059±0.004)
0.30±0.05 (0.012±0.00)
USER
FEED
DIRECTION
COVER TAPE
CARRIER
TAPE
REEL
12
Applications Information
Introduction
The Avago ACPM-7891 provides a cost effective dual
or tri-band GSM Power Amplifier (PA) solution with
the additional benefit of multi-slot GPRS operation,
giving excellent efficiency and extended transmit
time. Figure 1 illustrates how the ACPM-7891 fits
into a typical dual-band or tri-band terminal design.
The device is internally matched to 50Ω and there-
fore an effective design can be implemented quickly
with a few additional capacitors for d.c. blocking of
the output ports and bypassing of the supply pins.
The control loop can also be implemented quickly by
using an integrated power controller such as the
LT1758-2 from Linear Technology. An example using
this controller is given later in this note. The required
loop performance and stability can be achieved more
easily in this way, without the need for complex and
time consuming design work around an external error
comparator or discrete Schottky diode detector.
Demoboards are available, and design engineers can
evaluate the RF performance of the ACPM-7891 power
amplifier to implement a solution quickly by using
this application note in conjunction with the
datasheet.
Figure 1. ACPM-7891 in a Typical Dual-band or Tri-band Terminal.
Antenna
Coupler
Switch/Diplexer
Loop Control
Chipset
Transmit
Baseband
Receive
900MHz
900MHz
1800MHz
1800MHz
1900MHz
1900MHz
DAC
ACPM-7891
ACPM-7891 Performance
Figure 2 plots the actual output power of the ACPM-
7891 PA for GSM900, DCS1800 and PCS1900 bands
as a function of the control voltage, Vapc. The input
power to the PA is a GMSK modulated RF carrier of
a constant power level of 2 dBm. The PA’s maximum
output power is 35 dBm in the GSM900 band, and 33
dBm for the DCS1800/PCS1900 band at a control
voltage of 2.2V. The input RF carrier and control
voltage are both pulsed, following the GSM TDMA
characteristic response with a period of 4.615ms and
a duty cycle of 12.5~25% per the GSM standard.
40
35
30
25
20
15
10
5
0
-5
-10
-15
-20
0.75 0.95 1.15 1.35 1.55 1.75 1.95 2.15
Vapc (V)
Pout (dBm)
EGSM
DCS
PCS
Figure 2. Output Power vs. Control Voltage for the ACPM-7891
Power Amplifier.
13
ACPM-7891 Evaluation
There are two options available when evaluating the
ACPM-7891. Option A is to use the fully assembled
and tested ACPM-7891 Test Board from Avago which
includes the PA and associated passive components.
This board can be used to evaluate the basic perfor-
mance of the PA against the typical electrical
characteristics provided in the datasheet. All maxi-
mum and minimum PA parameters are verified prior
to sending out this board.
Option B allows the PA performance to be evaluated
within a power control loop environment by using
the ACPM-7891 PA Control Board from Avago which
incorporates the commercially available control loop
IC LT1758-2 from Linear Technologies. This device is
Table 1. EGSM Test Conditions.
Parameter Symbol Test Condition
Operating Frequency f (MHz) Tx EGSM frequency range: 880 ~ 915 MHz
Supply Voltage Vdd (V) Nominal voltage 3.5V. Extreme voltage
conditions of 2.7V and 5.3V
Input Power Level Pin (dBm) 2 dBm ± 2 dBm
Control Voltage Vapc (V) Standard DAC output control level estimated
at 0.1 to 2.6V. Maximum Vapc level: Vdd-0.3V
Temperature To (C) -30, +25, +85°C
Table 2. DCS/PCS Test Conditions.
Parameter Symbol Test Condition
Operating Frequency f (MHz) Tx DCS frequency range: 1710 ~ 1785 MHz
Tx PCS frequency range: 1850 ~ 1910 MHz
Supply Voltage Vdd (V) Nominal voltage 3.5V. Extreme voltage
conditions of 2.7V and 5.3V
Input Power Level Pin (dBm) 2 dBm ± 2 dBm
Control Voltage Vapc (V) Standard DAC output control level estimated
at 0.1 to 2.6V. Maximum Vapc level: Vdd-0.3V
Temperature To (C) -30, +25, +85°C
used as an example; however, alternative off-the-
shelf power control ICs are available from Linear
Technologies, Analog Devices and other suppliers.
The ACPM-7891 PA Control Board can be used in
conjunction with an LT1758 Demoboard, available
from Linear Technologies, which supplies the DAC
and timing functions. Alternatively the DAC and
timing functions can be supplied by a conventional
two channel function generator.
Demo Board Test Conditions
For both types of demoboards, a common set of test
conditions apply. Tables 1 and 2 detail the test
conditions for EGSM, DCS and PCS at Vdd = +3.5V,
pulse width of 1154 µs, and a duty cycle of 25% for a
case temperature of +25°C.
14
Option A
ACPM-7891 Test Board
Figure 3 shows the schematic for the ACPM-7891
Test Board which provides a straightforward method
of testing and evaluating the ACPM-7891. External
RF sources, power and Vapc supplies are used.
Option B
Power Control Loop Design
The implementation of a transmitter power control is
one of the most engineering-intensive and time-con-
suming aspects of GSM handset design. It dictates the
Figure 3. Schematic of ACPM-7891 Test Board.
DCS/PCS RFou
t
Gnd
Vdd
EGSM RFout
C11
11
14
20
C2
C8
C13
C14
7
4
24
C5
C9
C7C4
23
26
2
C3
21
18
16
DCS/PCS RFin
EGSM Vapc
EGSM RFin
DCS/PCS Vapc
1, 3, 5, 6, 8, 9, 10, 12, 13, 15, 17, 19, 22, 25
Component Component
Label Value
C2 .033 µF
C3 12 pF
C4 220 pF
C5 .033 µF
C7 220 pF
C8 33 pF
C9 .033 µF
C11 33 pF
C13 .033 µF
C14 27 pF
correct transmit power level and burst shaping in a
GSM network. The use of an off-the-shelf power con-
trol IC helps simplify the engineering effort and
shorten the design cycle time.
The ACPM-7891 PA Control Board includes the
ACPM-7891 PA, Linear Technology LTC1758-2 power
control IC, EGSM/DCS/PCS directional couplers, tri-
band diplexer and a 20-pin interface socket designed
to work with an LTC1758 demo board from Linear
Technology.
15
Figure 4 depicts the basic block diagram of the ACPM-
7891 PA control board, Figure 5 shows the control
board layout, and Table 3 details its bill of materials.
The supporting LTC1758 demoboard is available upon
request from Linear Technology. It has a 900 MHz and
an 1800 MHz RF channel controlled by the LTC1758.
Timing signals for TXEN are generated on the board
using a 13 MHz crystal reference. The PCTL power
control pin is driven by a 10-bit DAC and the DAC
profile can be loaded via a serial port. The serial port
data is stored in flash memory which is capable of
storing eight ramp profiles. The board is supplied
preloaded with four GSM power profiles and four
DCS power profiles, covering the entire power range.
External timing signals can also be used in place of
the internal crystal controlled timing.
RFou
t
DIPLEXER
DIRECTIONAL
COUPLER
RFout DCS/PCS
DIRECTIONAL
COUPLER
50Ω
50Ω
33 pF
33 pF
33 pF
220 pF
2.2 pF
2.2 pF
220 pF
33 pF
11
7
RFout EGSM
ACPM-7891
RFin DCS/PCS
RFin EGSM
26
Vdd EGSMVAPC EGSM
4
2
RFin EGSM
TXEN
PCTL
TXEN
VPCA
VCC
VIN
RF
SHDN
SHDN
33 pF
VBATT
GND
LTC1758
DAC
68Ω
RFin
DCS/PCS
18
16 14
Vdd3 DCS/PCSVAPC DCS/PCS
Figure 4. Block Diagram of the ACPM-7891 PA Control Board.
16
Figure 5. ACPM-7891 Control Board Layout.
Table 3. Bill of Materials for ACPM-7891 Control Board.
Qty Device Type, Component Value & Tolerance Reference
1 Avago ACPM-7891 Power Amplifier U1
2 CAP_C0402-.033µF,+80,-20A .033µF +80 C24,C31
1 CAP_C0402- 15pF,5%, 50V, CEA 15pF 5% C3
2 CAP_C0402- 220pF,10%, 50V, A 220pF10% C33,C36
11 CAP_C0402- 33pF,5%, 50V, CEA 33pF 5% C4, C5, C8, C9, C10, C27, C28, C32, C35, C44, C45
1 CAP_C0402- 47pF,5%, 50V, CEA 47pF 5% C7
2 CAP_C0603- .1µF,5%, 20V, CEA .1µF 5% C2, C6
1 CAP_TANT_C0805_T-ECST1AZ225R, CB 2.2µF +/-20% C34
1 CAP_TANT_SMT6032-ECST1AZ225R, CB 2.2µF +/-20% C4
1 CAP_C1206- .47µF,+80-20%, A .47µF +80-20% C1
1 CONN20PIN_EDGE20-CONN20PIN,HEAB J2
6 TP_FLAT-TP TP1, TP2, TP4, TP5, TP6, TP7
5 JUMPER_2 J1, J3, J4, J5, J6
1 Murata LDC211G7420H-055, Directional Coupler X1
1 Murata LDC21897M20H-056, Directional Coupler X3
1 Murata LFD31897MDP1A010, Diplexer X2
1 CAP_1812- 22µF, 10%, 10V, Taiyo Yuden LMK432 C11
1 Linear Technology LTC1758_LT_MSOP8, Control Loop IC U2
1 MCR01J680, 68 5% R1
2 RC-4-0402-50R0J, 50 5% R2, R3
3 SMA_3 RF1, RF2, RF6
17
ACPM-7891 PA Control Board
We have designed the ACPM-7891 PA control board
to interface with the LTC1758 demo board to sim-
plify engineering efforts. Test Setup I, Figure 6,
illustrates the equipment setup if the LTC1758 demo
board is to be used with the ACPM-7891 PA Control
Board.
However, the ACPM-7891 PA Control Board can also
be tested without using the LTC1758 demo board.
Test Setup II, Figure 7, illustrates the equipment
setup under that scenario.
Serial Connection
PA Control Board
HP 6623A
20 Ways
External Signal
Control Board
Power Divider
20 dB pad
20 dB pad
HP 8593E
HP E4406A
Vapc RAMP
Tek 2235
HP E4437B
Computer
3 dB pad
Figure 6. Test Setup with the LT1758 Demoboard.
HP E4437B
3 dB pad
HP 3245A
PA Control Board
HP 6623A
RAMP
TX_EN
Vdd
SHDN
Tek 2235
Vapc RAMP
Power Divider 20 dB pad
HP 8593E
HP E4406A
20 dB pad
Figure 7. Test Setup without the LT1758 Demoboard.
18
Test Setup I
(With Linear Tech Board)
Connect an RF signal generator with GMSK modu-
lated signal to RFin EGSM port (RF2) or RFin DCS/
PCS (RF1) on the PA control board. The maximum
input power at RF1 and RF2 is +10 dBm. Typically
+2 dBm is applied for the EGSM, DCS/PCS channels.
Connect two measurement instruments, one for spec-
trum analyzer and the other VSA, to RFout (RF6). The
maximum output power should be limited to +35 dBm.
Connect the LTC-1758 demo board and the ACPM-
7891 PA control board using 20 pin-connection socket.
The external signal control board supplies bias volt-
age to PA control board and three timing signals —
SHDN, TXEN and PCTL — to generate VPCA signal of
the LTC1758. The VPCA signal is Power control volt-
age output and drives VAPC voltage of ACPM-7891 to
define power ramp profile. Figure C2 in Appendix C
details the LTC1758 timing diagram.
The RF power supply voltage of the PA control board
is set by VBATT ADJ on the external signal control
board. This voltage can be varied over a 2.7V to 5.3V
range and is nominally set to 3.5V. The VBATT voltage
can be monitored on TP5 on the PA control board.
Linear Technologies supplies the application pro-
gram associated with the .txt file to be downloaded to
the FLASH memory. The program controls the code
level of the DAC, whose data range is –1V to +1V.
–1V corresponds to the zero code level and the actual
10-bit DAC range is 0V to +2.048V. The resolution is
set about 2mV per step. The first sample of the data
file is assigned the “default” value, which is included
1251 sample waveform of input data. This is a “code”
value for the Lab View application program. The first
sample being the default value and the other 1250
samples being the waveform data to be outputted to
the DAC. The default value will then be loaded into all
memory locations after the 1250 samples have been
loaded. After programming the flash 16k segments
the system can be set to run by setting the rotary
switch to the programmed memory segment and
resetting the external signal control board using the
reset switch.
Test Setup I I (Without Linear Tech Board)
Without LTC1758 demo board, we can get the same
test result as above test. In this case, the Avago (HP)
3245A generates two relevant signals, TX_EN and
RAMP with synchronized time.
Connect an RF signal generator with GMSK modu-
lated signal to RFin EGSM port (RF2) or RFin DCS/
PCS (RF1) on the PA control board. Typically +2 dBm
is applied for the EGSM, DCS/PCS channels. Connect
two measurement instruments, one for spectrum
analyzer and the other VSA, to RFout (RF6). The
maximum output power should be limited to +35 dBm.
Avago (HP) E4406A: The Avago E4406A, transmitter
tester is used to measure power level in EGSM/DCS/
PCS mode displaying the characteristic time mask.
Avago (HP) E4437B: The signal generator is used to
provide GMSK GSM modulated input signal at a
defined frequency.
Avago (HP)8593E: The Avago 8991A is a spectrum
analyzer used to measure the output power of diplexer
in the frequency and time domain.
Tek 2235: The Tek 2235 is an oscilloscope used to
monitor RAMP signal and Vapc connected using the
test points of PA control board.
Avago (HP) 6623A: The Avago 6623A, power supply
is nominally set to voltage 3.5V for Vdd.
SHDN is set to 2.8V as high mode during TXEN and
RAMP are enable.
Avago (HP) 3245A: The Avago 3245A, function gen-
erator with two channels is set to two relevant signals
based on the GSM specification. One signal generates
TX_EN with 2.7V that has a period of 4.615 ms with
a duty cycle of 12.5% (577 µs) and 216 Hz frequency.
This TX_EN connects to TX_EN (TP7) pin on the RF
control board.
The other signal is RAMP signal that is same as PCTL
of LTC1758. This RAMP connects to RAMP (TP6) pin
on the RF control board.
19
Test Results
Using the demoboard with the Linear Technology IC,
the results shown in Table 4 were obtained.
The LTC1758 RAMP signal is generated from a DAC
and a simple single-pole filter is used to shape the
power ramp. The input RF signal is based on the GSM
GMSK modulated signal.
The results highlight the excellent power control func-
tionality obtained by using the ACPM-7891 in
conjunction with a power loop controller such as the
LT1758. Results are given for all three bands, at four
example power level settings, with the supply voltage
at 3V, 3.6V and 4.3V. The figures show that excellent
power output control is maintained over this supply
voltage range, illustrating that the ACPM-7891 can
enable designs that meet GSM transmitter
specifications.
Table 4. Results with variable Vdd and three point frequency ranges
GSM900
GSM5 (33 dBm) GSM10 (23 dBm) GSM15 (13 dBm) GSM19 (5 dBm)
Frequency Vdd Vapc Pout Vapc Pout Vapc Pout Vapc Pout
(V) (V) (dBm) (V) (dBm) (V) (dBm) (V) (dBm)
900 MHz 3.0 2.00 33.07 1.3 23.54 1.1 13.49 1.0 5.09
3.6 1.60 33.04 1.3 23.55 1.1 13.51 1.0 5.12
4.3 1.58 33.04 1.3 23.56 1.1 13.52 1.0 5.09
DCS1800
DCS0 (30 dBm) DCS5 (20 dBm) DCS10 (10 dBm) DCS15 (0 dBm)
Frequency Vdd Vapc Pout Vapc Pout Vapc Pout Vapc Pout
(V) (V) (dBm) (V) (dBm) (V) (dBm) (V) (dBm)
1750 MHz 3.0 2.0 30.35 1.3 20.20 1.1 10.42 1.0 0.08
3.6 1.7 30.32 1.3 20.17 1.1 10.40 1.0 0.06
4.3 1.7 30.28 1.3 20.14 1.1 10.37 1.0 0.06
PCS1900
PCS0 (30 dBm) PCS5 (20 dBm) PCS10 (10 dBm) PCS15 (0 dBm)
Frequency Vdd Vapc Pout Vapc Pout Vapc Pout Vapc Pout
(V) (V) (dBm) (V) (dBm) (V) (dBm) (V) (dBm)
1880 MHz 3.0 1.95 29.26 1.3 20.12 1.1 10.64 1.0 -0.04
3.6 1.7 29.24 1.3 20.10 1.1 10.60 1.0 -0.05
4.3 1.7 29.20 1.3 20.07 1.1 10.56 1.0 -0.09
20
G
Appendix A
ACPM-7891 PA Control Board Layout
Bottom GND
Power Top
21
0.150 [3.82]
0.220 [5.59]
0.043 [1.09]
0.011 [0.26]
0.022 [0.56]
0.022 [0.56]
0.236 [6.00]
0.2317 [5.52]
0.189 [4.80]
0.142 [3.60]
0.236 [2.40]
0.047 [1.20]
0.000 [0.00]
0.000 [0.00]
0.024 [0.60]
0.071 [1.80]
0.099 [2.52]
0.118 [3.00]
Figure B1. Recommended Stencil.
Appendix B
Stencil Design on PCB for ACPM-7891
In order to dissipate heat, additional via holes on the
PCB are needed on the printed circuit board.
Solder mask should not be applied to thermal/ground
plane underneath the vias in a way that will reduce
heat transfer efficiency from conductive paddle to
ambient. The stencil design enables solder paste to fill
up the vias and form a solid conducting bar that
further improves the thermal dissipation.
A properly designed solder screen or stencil is re-
quired to ensure optimum amount of solder paste is
deposited onto the PCB pads. The recommended
stencil layout is shown in Figure B1. The stencil has
a solder paste deposition opening approximately
90% of the PCB pad. Reducing stencil opening of the
conductive paddle potentially generate void under-
neath, on the other hand stencil opening larger than
100% will lead to excessive solder paste smear across
the conductive paddle to adjacent I/O pads.
22
Appendix C
LTC1758 Theory of Operation
The LTC1758-2 is a dual band RF power controller
for RF power amplifiers operating in the 850 MHz to
2 GHz range.
RF power is controlled by driving the RF amplifier
power control pins and sensing the resultant RF
output power via a directional coupler. The RF sense
voltage is peak detected using an on-chip Schottky
diode. This detected voltage is compared to the DAC
voltage at the PCTL pin to control the output power.
The RF power amplifier is protected against high
supply current and high power control pin voltages.
Internal and external offsets are cancelled over tem-
perature by an autozero control loop, allowing
accurate low power programming. The shutdown
feature disables the part and reduces the supply
current to <1_A.
Modes of Operation
The LTC1758-2 supports three operating modes: shut-
down, autozero and enable.
In shutdown mode (SHDN = Low) the part is disabled
and supply currents will be reduced to <1_A. VPCA
and VPCB will be connected to ground via 100_
switches.
In autozero mode (SHDN = High, TXEN = Low) VPCA
and VPCB will remain connected to ground and the
part will be in the autozero mode. The part must
remain in autozero for at least 50_s to allow for the
autozero circuit to settle.
In enable mode (SHDN = High, TXEN = High) the
control loop and protection functions will be opera-
tional. When TXEN is switched high, acquisition will
begin. The control amplifier will start to ramp the
control voltage to the RF power amplifier. The RF
amplifier will then start to turn on. The feedback
signal from the directional coupler and the output
power will be detected by the LTC1758-2 at the RF
pin. The loop closes and the amplifier output tracks
the DAC voltage ramping at PCTL. The RF power
output will then follow the programmed power
profile from the DAC.
The LTC1758 datasheet provides more detailed de-
scription of the part’s operation and can be
downloaded from Linear Technology’s website.
TOP VIEW
1
RF
SHDN
BSEL
GND
10
9
8
7 TXEN
PCTL6
2
3
4
5
V
IN
V
CC
V
PCA
V
PCB
MS10 Package
10-Lead Plastic MSOP
Figure C1. LTC-1758-2 Pinout.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited
in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies, Limited. All rights reserved.
Obsoletes 5988-8926EN
5988-9542EN May 22, 2006
Shutdown
SHDN
BSEL
TXEN
PCTL
VPCA
VPCB
Start
Voltage
Start
Voltage
Note 1
Autozero Enable
t
1
t
2
t
S
tS: autozero settling time, 50µs minimum
t1: BSEL change prior to TXEN, 200ns typical
t2: BSEL change after TXEN, 200ns typical
Note 1: The external DAC driving the PCTL pin can be enabled during autozero. The autozero system
will cancel the DAC transient. the DAC must be settled to an offset ≥ 400mv before TXEN
is asserted hi
g
h.
MODE
Shutdown
Autozero
Enable
SHDN
Low
High
High
TXEN
Low
Low
High
OPERATION
Disabled
Autozero
Power Control
Figure C2. LTC1758-2 Timing Diagram.
