CS4244 4 In/4 Out Audio CODEC with PCM and TDM Interfaces DAC Features System Features Advanced multibit delta-sigma modulator 24-bit resolution Differential or single-ended outputs Dynamic range (A-weighted) - -109 dB differential - Common Applications Automotive audio systems AV, Blu-Ray(R) Disc, and DVD receivers Audio interfaces, mixing consoles, and effects processors -105 dB single-ended THD+N - -90 dB differential - -88 dB single ended General Description 2 Vrms full-scale output into 3-k AC load The CS4244 provides four multibit analog-to-digital and four multi-bit digital-to-analog - converters and is compatible with differential inputs and either differential or single-ended outputs. Digital volume control, noise gating, and muting is provided for each DAC path. A selectable high-pass filter is provided for the 4 ADC inputs. The CS4244 supports master and slave modes and TDM, left-justified, and IS modes. Rail-to-rail operation ADC Features Advanced multibit delta-sigma modulator 24-bit resolution Differential inputs -105 dB dynamic range (A-weighted) This product is available in a 40-pin QFN package in Automotive (-40C to +85C) and Commercial (0C to +70C) temperature grades. The CDB4244 Customer Demonstration Board is also available for device evaluation and implementation suggestions. See "Ordering Information" on page 64 for complete details. -88 dB THD+N 2 Vrms full-scale input VA 5.0 VDC VDREG 2.5 V AIN1 AIN2 AIN3 AIN4 () () () () TDM, left justified, and IS serial inputs and outputs IC host control port Supports logic levels between 5 and 1.8 V Supports sample rates up to 96 kHz LDO Analog Supply Multi-bit ADC Digital Filters Channel Volume , Mute, Invert , Noise Gate Master Volume Control Interpolation Filter Multi-bit Modulators Serial Audio Interface DAC & Analog Filters AOUT1 AOUT2 AOUT3 AOUT4 () () () () Control Port Level Translator SDOUT1 SDOUT2 VL 1.8 to 5.0 VDC http://www.cirrus.com SDIN2 SDIN1 Frame Sync Clock / LRCK Master Clock In Serial Clock In/Out Copyright Cirrus Logic, Inc. 2014 (All Rights Reserved) INT RST I2 C Control Data OCT `14 DS900F2 CS4244 TABLE OF CONTENTS 1. PIN DESCRIPTIONS ............................................................................................................................ 5 1.1 I/O Pin Characteristics ...................................................................................................................... 6 2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 7 3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8 RECOMMENDED OPERATING CONDITIONS ..................................................................................... 8 ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 8 DC ELECTRICAL CHARACTERISTICS ................................................................................................ 9 TYPICAL CURRENT CONSUMPTION ................................................................................................ 10 ANALOG INPUT CHARACTERISTICS (COMMERCIAL GRADE) ...................................................... 11 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE GRADE) ....................................................... 12 ADC DIGITAL FILTER CHARACTERISTICS ....................................................................................... 14 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL GRADE) .................................................. 15 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE GRADE) ................................................... 16 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 17 DIGITAL I/O CHARACTERISTICS ....................................................................................................... 18 SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE .................................................... 19 SWITCHING SPECIFICATIONS - CONTROL PORT .......................................................................... 21 4. APPLICATIONS ................................................................................................................................... 22 4.1 Power Supply Decoupling, Grounding, and PCB Layout ............................................................... 22 4.2 Recommended Power-up & Power-down Sequence ..................................................................... 22 4.3 IC Control Port ............................................................................................................................... 24 4.4 System Clocking ............................................................................................................................. 26 4.5 Serial Port Interface ........................................................................................................................ 28 4.6 Internal Signal Path ....................................................................................................................... 31 4.7 Reset Line ...................................................................................................................................... 42 4.8 Error Reporting and Interrupt Behavior .......................................................................................... 42 5. REGISTER QUICK REFERENCE ........................................................................................................ 45 6. REGISTER DESCRIPTIONS ................................................................................................................ 47 6.1 Device I.D. A-F (Address 01h-03h) (Read Only) ....................................................................... 47 6.2 Revision I.D. (Address 05h) (Read Only) ....................................................................................... 47 6.3 Clock & SP Select (Address 06h) ................................................................................................... 48 6.4 Sample Width Select (Address 07h) ............................................................................................... 49 6.5 Serial Port Control (Address 08h) ................................................................................................... 49 6.6 Serial Port Data Select (Address 09h) ............................................................................................ 50 6.7 ADC Control 1 (Address 0Fh) ......................................................................................................... 51 6.8 ADC Control 2 (Address 10h) ......................................................................................................... 51 6.9 DAC Control 1 (Address 12h) ......................................................................................................... 52 6.10 DAC Control 2 (Address 13h) ....................................................................................................... 52 6.11 DAC Control 3 (Address 14h) ....................................................................................................... 53 6.12 DAC Control 4 (Address 15h) ....................................................................................................... 53 6.13 Volume Mode (Address 16h) ........................................................................................................ 54 6.14 Master and DAC1-4 Volume Control (Address 17h, 18h, 19h, 1Ah, & 1Bh) ................................ 55 6.15 Interrupt Control (Address 1Eh) .................................................................................................... 55 6.16 Interrupt Mask 1 (Address 1Fh) .................................................................................................... 56 6.17 Interrupt Mask 2 (Address 20h) .................................................................................................... 57 6.18 Interrupt Notification 1 (Address 21h) (Read Only) ...................................................................... 57 6.19 Interrupt Notification 2 (Address 22h) (Read Only) ...................................................................... 58 7. ADC FILTER PLOTS ............................................................................................................................ 59 8. DAC FILTER PLOTS ............................................................................................................................ 60 9. PACKAGE DIMENSIONS ................................................................................................................... 62 10. ORDERING INFORMATION .............................................................................................................. 63 11. REVISION HISTORY .......................................................................................................................... 63 DS900F2 2 CS4244 LIST OF FIGURES Figure 1.CS4244 Pinout .............................................................................................................................. 5 Figure 2.Typical Connection Diagram ......................................................................................................... 7 Figure 3.Test Circuit for ADC Performance Testing .................................................................................. 13 Figure 4.PSRR Test Configuration ............................................................................................................ 13 Figure 5.Equivalent Output Test Load ...................................................................................................... 16 Figure 6.TDM Serial Audio Interface Timing ............................................................................................. 20 Figure 7.PCM Serial Audio Interface Timing ............................................................................................. 20 Figure 8.IC Control Port Timing ............................................................................................................... 21 Figure 9.System Level Initialization and Power-Up/Down Sequence ....................................................... 23 Figure 10.DAC DC Loading ...................................................................................................................... 24 Figure 11.Timing, IC Write ....................................................................................................................... 25 Figure 12.Timing, IC Read ....................................................................................................................... 25 Figure 13.Master Mode Clocking .............................................................................................................. 27 Figure 14.TDM System Clock Format ....................................................................................................... 28 Figure 15.32-bit Receiver Channel Block .................................................................................................. 28 Figure 16.Serial Data Coding and Extraction Options within the TDM Streams ....................................... 29 Figure 17.Left Justified Format ................................................................................................................. 30 Figure 18.IS Format ................................................................................................................................. 30 Figure 19.Audio Path Routing ................................................................................................................... 31 Figure 20.Conventional SDOUT (Left) vs. Sidechain SDOUT (Right) Configuration ................................ 32 Figure 21.DAC1-4 Serial Data Source Selection ...................................................................................... 33 Figure 22.Example Serial Data Source Selection ..................................................................................... 34 Figure 23.ADC Path .................................................................................................................................. 35 Figure 24.Single-Ended to Differential Active Input Filter ......................................................................... 36 Figure 25.Single-Ended to Differential Active Input Filter - DC Coupled Input Signal (VA/2 Centered) .... 36 Figure 26.DAC1-4 Path ............................................................................................................................. 37 Figure 27.De-emphasis Curve .................................................................................................................. 38 Figure 28.Passive Analog Output Filter .................................................................................................... 38 Figure 29.Volume Implementation for the DAC1-4 Path ........................................................................... 39 Figure 30.Soft Ramp Behavior .................................................................................................................. 40 Figure 31.Interrupt Behavior and Example Interrupt Service Routine ....................................................... 44 Figure 32.ADC Stopband Rejection .......................................................................................................... 59 Figure 33.ADC Transition Band ................................................................................................................ 59 Figure 34.ADC Transition Band (Detail) .................................................................................................... 59 Figure 35.ADC Passband Ripple .............................................................................................................. 59 Figure 36.ADC HPF (48 kHz) .................................................................................................................... 59 Figure 37.ADC HPF (96 kHz) .................................................................................................................... 59 Figure 38.SSM DAC Stopband Rejection ................................................................................................. 60 Figure 39.SSM DAC Transition Band ....................................................................................................... 60 Figure 40.SSM DAC Transition Band (Detail) ........................................................................................... 60 Figure 41.SSM DAC Passband Ripple ..................................................................................................... 60 Figure 42.DSM DAC Stopband Rejection ................................................................................................. 61 Figure 43.DSM DAC Transition Band ....................................................................................................... 61 Figure 44.DSM DAC Transition Band (Detail) ........................................................................................... 61 Figure 45.DSM DAC Passband Ripple ..................................................................................................... 61 Figure 46.Package Drawing ...................................................................................................................... 62 DS900F2 3 CS4244 LIST OF TABLES Table 1. Speed Modes .............................................................................................................................. 26 Table 2. Common Clock Frequencies ....................................................................................................... 26 Table 3. Master Mode Left Justified and IS Clock Ratios ........................................................................ 27 Table 4. Slave Mode Left Justified and IS Clock Ratios .......................................................................... 27 Table 5. Slave Mode TDM Clock Ratios ................................................................................................... 27 Table 6. Soft Ramp Rates ......................................................................................................................... 41 Table 7. Noise Gate Bit Depth Settings .................................................................................................... 41 Table 8. Error Reporting and Interrupt Behavior Details ........................................................................... 42 DS900F2 4 CS4244 SCL AD0 AD1 AD2/SDOUT2 INT RST TSTO1 TSTO2 AOUT1+ AOUT1- 40 39 38 37 36 35 34 33 32 31 1. PIN DESCRIPTIONS SDA 1 30 AOUT2+ SDIN1 2 29 AOUT2- SDIN2 3 28 AOUT3+ FS/LRCK 4 27 AOUT3- MCLK 5 26 AOUT4+ SCLK 6 25 AOUT4- SDOUT1 7 24 VBIAS VL 8 23 VREF GND 9 22 VQ VDREG 10 21 GND 19 20 FILT+ VA 16 AIN2- 18 15 AIN3- AIN2+ AIN1- 14 AIN3+ 17 13 AIN4- AIN1+ 12 AIN4+ 11 Top-Down (Though Package) View Figure 1. CS4244 Pinout Pin Name SDA SDINx Pin # 1 2,3 Pin Description Serial Control Data (Input/Output) - Bi-directional data I/O for the IC control port. Serial Data Input (Input) - Input channels serial audio data. FS/LRCK 4 Frame Synchronization Clock/Left/Right Clock (Input/Output) - Determines which channel or frame is currently active on the serial audio data line. MCLK 5 Master Clock (Input) -Clock source for the internal logic, processing, and modulators. SCLK 6 Serial Clock (Input/Output) -Serial Clock for the serial data port. SDOUT1 7 Serial Data Output 1 (Output) - ADC data output into a multi-slot TDM stream or AIN1 and AIN2 ADC data output in Left Justified and IS modes. VL 8 Interface Power (Input) - Positive power for the digital interface level shifters. GND VDREG 9,21 10 Ground (Input) - Ground reference for the I/O and digital, analog sections. Digital Power (Output) - Internally generated positive power supply for digital section. AINx+ Positive Analog Input (Input) - Positive input signals to the internal analog to digital converters. The 11,13,15, full scale analog input level is specified in the Analog Input Characteristics tables on pages 12 and 17 13. AINx- Negative Analog Input (Input) - Negative input signals to the internal analog to digital converters. 12,14,16, The full scale analog input level is specified in the Analog Input Characteristics tables on pages 12 18 and 13. FILT+ DS900F2 19 Positive Voltage Reference (Output) - Positive reference voltage for the internal ADCs. 5 CS4244 VA 20 Analog Power (Input) - Positive power for the analog sections. VQ 22 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VREF 23 Analog Power Reference (Input) - Return pin for the VBIAS cap. VBIAS 24 Positive Voltage Reference (Output) - Positive reference voltage for the internal DACs. AOUTx- Negative Analog Output (Output) - Negative output signals from the internal digital to analog con25,27,29, verters. The full scale analog output level is specified in the Analog Output Characteristics tables 31 on pages 16 and 17. AOUTx+ Positive Analog Output (Output) - Positive output signals from the internal digital to analog convert26,28,30, ers. The full scale analog output level is specified in the Analog Output Characteristics tables on 32 pages 16 and 17. TSTOx 33,34 Test Outputs (Output) - Test outputs. These pins should be left unconnected. RST 35 Reset (Input) - Applies reset to the internal circuitry when pulled low. INT 36 Interrupt (Output) - Sent to DSP to indicate an interrupt condition has occurred. AD2/SDOUT2 37 IC Address Bit 2/Serial Data Output 2 (Input/Output) - Sets the IC address bit 2 at reset. Functions as Serial Data Out 2 for AIN3 and AIN4 ADC data output in Left Justified and IS modes. High impedance in TDM mode. See Section 4.3 IC Control Port for more details concerning this mode of operation. AD1 38 IC Address Bit 1 (Input) - Sets the IC address bit 1. AD0 39 IC Address Bit 0 (Input) - Sets the IC address bit 0. SCL 40 Serial Control Port Clock (Input) - Serial clock for the IC control port. GND - 1.1 Thermal Pad - The thermal pad on the bottom of the device should be connected to the ground plane via an array of vias. I/O Pin Characteristics Input and output levels and associated power supply voltage are shown in the table below. Logic levels should not exceed the corresponding power supply voltage. Power Supply VL Pin Name I/O Driver SCL Input SDA Input/Output INT Output CMOS/Open Drain CMOS/Open Drain 5.0 V CMOS 5.0 V CMOS 5.0 V CMOS 5.0 V CMOS Input RST MCLK Input FS/LRCK Input/Output SCLK Input/Output SDOUT1 Output SDINx Input AD0,1 Input AD2/SDOUT2 Input/Output Internal Connections Receiver (Note 1) Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis Weak Pull-down (~500k 5.0 V CMOS, with Hysteresis (Note 2) - (Note 2) Weak Pull-down (~500k Weak Pull-down (~500k Weak Pull-down (~500k Weak Pull-down (~500k Weak Pull-down (~500k (Note 2) (Note 2) 5.0 V CMOS, with Hysteresis 5.0 V CMOS, with Hysteresis 5.0 V CMOS, with Hysteresis 5.0 V CMOS, with Hysteresis 5.0 V CMOS, with Hysteresis 5.0 V CMOS 5.0 V CMOS Notes: 1. Internal connection valid when device is in reset. 2. This pin has no internal pull-up or pull-down resistors. External pull-up or pull-down resistors should be added in accordance with Figure 2. DS900F2 6 CS4244 2. TYPICAL CONNECTION DIAGRAM VL Rp (x4) **** Digital Signal Processor Pull Up or Down Based upon Desired Address *** 40 39 38 37 36 35 34 33 32 31 S CL A D0 A D1 AD2/ SDOUT2 INT RST TSTO 1 TSTO 2 AOUT1+ AOUT1- Analog Output Filter * AOUT2+ 30 SDIN 1 AOUT2- 29 3 SDIN 2 AOUT3+ 28 4 FS/LRCK AOUT3- 27 5 MCLK AOUT4+ 26 6 SCLK AOUT4- 25 7 SDOUT1 VBIAS 24 8 VL VREF 23 9 GND VQ 22 10 VDREG GND 21 1 SDA 2 Analog Output Filter * Analog Output Filter * +1.8 V to +5.0 V CS4244 Analog Output Filter * 10uF 0.1uF 0. 1uF 10uF A IN4- A IN3+ A IN3- A IN2+ A IN2- A IN1+ A IN1- FI LT+ VA 10uF A IN4+ 0.1uF 11 12 13 14 15 16 17 18 19 20 0.1uF 10uF Analog Input Filter ** Analog Input Filter ** Analog Input Filter ** Analog Input Filter ** 1uF +3.3 V to +5.0 V * See Section 4.6.4 ** See Section 4.6.2.2 *** See Section 4.3 **** See Switching Specifications - Control Port Figure 2. Typical Connection Diagram DS900F2 7 CS4244 3. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS GND = 0 V; all voltages with respect to ground. (Note 3) Parameters Symbol Min Typ Max Units Analog Core VA 3.135 4.75 3.3 5 3.465 5.25 V V Level Translator VL 1.71 - 5.25 V TA -40 0 - +85 +70 C C TJ -40 - +150 C DC Power Supply Temperature Ambient Operating Temperature - Power Applied Automotive Commercial Junction Temperature Notes: 3. Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied outside of these limits. Operation outside of these limits may adversely affect device reliability. ABSOLUTE MAXIMUM RATINGS GND = 0 V; all voltages with respect to ground. Parameters Symbol Min Max Units Analog Core VA -0.3 5.5 V Level Translator VL -0.3 5.5 V (Note 4) IVDREG - 10 A Input Current (Note 5) Iin - 10 mA Analog Input Voltage (Note 6) VINA - 0.3 VA + 0.4 V Logic Level Input Voltage (Note 6) VIND -0.3 VL + 0.4 V Ambient Operating Temperature - Power Applied TA -55 +125 C Storage Temperature Tstg -65 +150 C DC Power Supply VDREG Current Inputs Temperature WARNING: OPERATION BEYOND THESE LIMITS MAY RESULT IN PERMANENT DAMAGE TO THE DEVICE. Notes: 4. No external loads should be connected to the VDREG pin. Any connection of a load to this point may result in errant operation or performance degradation in the device. 5. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 6. The maximum over/under voltage is limited by the input current. DS900F2 8 CS4244 DC ELECTRICAL CHARACTERISTICS GND = 0 V; all voltages with respect to ground. Parameters Min Typ Max Units - 2.5 0.5 - V - VA 23 - 1 V k A - 0.5*VA 77 - 0 V k A VDREG (Note 7) Nominal Voltage Output Impedance FILT+ Nominal Voltage Output Impedance DC Current Source/Sink VQ Nominal Voltage Output Impedance DC Current Source/Sink Notes: 7. No external loads should be connected to the VDREG pin. Any connection of a load to this point may result in errant operation or performance degradation in the device. DS900F2 9 CS4244 TYPICAL CURRENT CONSUMPTION This table represents the power consumption for individual circuit blocks within the CS4244. CS4244 is configured as shown in Figure 2 on page 8. VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC; FS = 100 kHz; MCLK = 25.6 MHz; DAC load is 3 k; All input signals are zero (digital zero for SDINx inputs and AC coupled to ground for AINx inputs) . Typical Current [mA] (unless otherwise noted) (Note 9), (Note 12) Functional Block Reset Overhead 1 (All lines held static, RST line pulled low.) Power Down Overhead 2 (All lines clocks and data lines active, RST line pulled high, All PDNx bits set high.) PLL (Note 10) 3 (Current drawn resulting from PLL being active. PLL is active for 256x and 384x) DAC Overhead 4 (Current drawn whenever any of the four DACs are powered up.) DAC Channel (Note 8) 5 (Current drawn per each DAC powered up.) ADC Overhead 6 (Current drawn whenever any of the four ADCs are powered up.) ADC Group 7 (Current drawn due to an ADC "group" being powered up. See (Note 11)) ADC Channel 8 (Current drawn per each ADC powered up.) VA/VL 5 3.3 5 3.3 5 3.3 5 3.3 5 3.3 5 3.3 5 3.3 5 3.3 iVA iVL 0.030 0.020 5 5 1 1 50 45 5 4 11 11 2 2 2 2 0.001 0.001 0.101 0.101 0.109 0.066 Notes: 8. Full-scale differential output signal. 9. Current consumption increases with increasing FS and increasing MCLK. Values are based on FS of 100 kHz and MCLK of 25.6 MHz. Current variance between speed modes is small. 10. PLL is activated by setting the MCLK RATE bit to either 000 (operating in 256x mode) or 001 (operating in 384kHz). 11. Internal to the CS4244, the analog to digital converters are grouped together in stereo pairs. ADC1 and ADC2 are grouped together as are ADC3 and ADC4. The ADC group current draw is the current that is drawn whenever one of these groups become active. 12. To calculate total current draw for an arbitrary amount of ADCs or DACs, the following equations apply: Total Running Current Draw from VA Supply = Power Down Overhead + PLL (If Applicable)+ DAC Current Draw + ADC Current Draw where DAC Current Draw = DAC Overhead + (Number of DACs x DAC Channel) ADC Current Draw = ADC Overhead + (Number of active ADC Groups x ADC Group) + (Number of active ADC Channels x ADC Channel) and Total Running Current Draw from VL Supply = PDN Overhead + (Number of active ADC Channels x ADC Channel) DS900F2 10 CS4244 ANALOG INPUT CHARACTERISTICS (COMMERCIAL GRADE) Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 8. Input sine wave: 1 kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; TA = 25 C; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specified; Sample Rate = 48 kHz; all Power Down ADCx bits = 0. VA, VREF = 3.3 V Parameter Min VA, VREF = 5.0 V Typ Max Min Typ Max Unit 101 98 - 99 96 105 102 - dB dB -95 -38 -89 -32 - -88 -42 -82 -36 dB dB 0.2 100 - - 0.2 100 - ppm/C 0.0001 0.25 90 - - 0.0001 0.25 90 - % Full Scale % Full Scale dB 1.66*VA 40 60 1.74*VA - 45 20 - Dynamic Range A-weighted 95 unweighted 92 Total Harmonic Distortion + Noise -1 dBFS -60 dBFS Other Analog Characteristics Interchannel Gain Mismatch Gain Drift Offset Error (Note 13) High Pass Filter On High Pass Filter Off Interchannel Isolation Full-scale Input Voltage (Differential Inputs) 1.58*VA Input Impedance Common Mode Rejection (Differential Inputs) PSRR (Note 14) 1 kHz 60 Hz - DS900F2 1.58*VA 1.66*VA 1.74*VA 40 60 - 45 20 - dB Vpp k dB dB dB 11 CS4244 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE GRADE) Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 8. Input sine wave: 1 kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; TA = -40 to +85 C; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specified; Sample Rate = 48 kHz; all Power Down ADCx bits = 0. VA, VREF = 3.3 V Parameter Min VA, VREF = 5.0 V Typ Max Min Typ Max Unit 101 98 - 97 94 105 102 - dB dB -95 -38 -87 -30 - -88 -42 -80 -34 dB dB 0.2 100 - - 0.2 100 - ppm/C 0.0001 0.25 90 - - 0.0001 0.25 90 - % Full Scale % Full Scale dB 1.66*VA 40 60 1.74*VA - 45 20 - Dynamic Range A-weighted 93 unweighted 90 Total Harmonic Distortion + Noise -1 dBFS -60 dBFS Other Analog Characteristics Interchannel Gain Mismatch Gain Drift Offset Error (Note 13) High Pass Filter On High Pass Filter Off Interchannel Isolation Full-scale Input Voltage (Differential Inputs) 1.58*VA Input Impedance Common Mode Rejection (Differential Inputs) PSRR (Note 14) 1 kHz 60 Hz - 1.58*VA 1.66*VA 1.74*VA 40 60 - 45 20 - dB Vpp k dB dB dB Notes: 13. AINx+ connected to AINx-. 14. Valid with the recommended capacitor values on FILT+ and VQ. See Figure 4 for test configuration. DS900F2 12 CS4244 634 470 pF VA 4.7 uF - 90.9 CS4244 AINx + 100 k Analog Signal + 100 k 100 k + 2700 pF 100 k 100 k + Analog Signal 100 k 4.7 uF CS4244 AINx 90.9 - VA 470 pF 634 Figure 3. Test Circuit for ADC Performance Testing +Vcc +Vcc Operational Amplifier Power DAC DUT PWR + OUT GND GND -Vcc Analog Out - + - + OUT Analog Generator Digital Out - + Analyzer Test Equipment Figure 4. PSRR Test Configuration DS900F2 13 CS4244 ADC DIGITAL FILTER CHARACTERISTICS Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 8. Input sine wave: 1 kHz; VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specified. See filter plots in Section 7. on page 60. Parameter (Note 15) Passband (Frequency Response) Min to -0.1 dB corner Typ Max Unit 0 - 0.4535 Fs -0.09 - 0.17 dB Stopband 0.6 - - Fs Stopband Attenuation 70 - - dB - 9.5/Fs - s - 2 11 - Hz Hz Passband Ripple Single-Speed Mode ADC Group Delay (Note 16) High-Pass Filter Characteristics (48 kHz Fs) Frequency Response -3.0 dB -0.13 dB Phase Deviation @ 20 Hz Passband Ripple Filter Settling Time (Note 17) - 10 - Deg -0.09 - 0.17 dB - 25000/Fs 0 s - 9.5/Fs - s Double-Speed Mode ADC Group Delay (Note 16) High-Pass Filter Characteristics (96 kHz Fs) Frequency Response -3.0 dB -0.13 dB - 4 22 - Hz Hz Phase Deviation @ 20 Hz - 10 - Deg -0.15 - 0.17 dB 25000/Fs 0 s Passband Ripple Filter Settling Time (Note 17) - Note: 15. Response is clock-dependent and will scale with Fs. 16. The ADC group delay is measured from the time the analog inputs are sampled on the AINx pins to the FS/LRCK transition (rising or falling) after the last bit of that (group of) sample(s) has been transmitted on SDOUTx. 17. The amount of time from input of half-full-scale step function until the filter output settles to 0.1% of full scale. DS900F2 14 CS4244 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL GRADE) Test Conditions (unless otherwise specified). Device configured as shown in Section 2. on page 8. VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; TA = 25 C; Full-scale 1 kHz input sine wave; Sample Rate = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz; Specifications apply to all channels unless otherwise indicated; all Power Down DACx bits = 0. See (Note 19) on page 17. VA, VREF= 3.3 V (Differential/Single-ended) Parameter VA, VREF= 5.0 V (Differential/Single-ended) Min Typ Max Min Typ Max Unit 100/96 97/93 89 86 106/102 103/99 95 92 - 103/99 100/96 89 86 109/105 106/102 95 92 - dB dB dB dB - -90/-88 -84/-82 - -90/-88 -84/-82 Dynamic Performance Dynamic Range 18 to 24-Bit 16-Bit A-weighted unweighted A-weighted unweighted Total Harmonic Distortion + Noise 1.48*VA/ 1.56*VA/ 1.64*VA/ 1.48*VA/ 1.56*VA/ 1.64*VA/ 0.74*VA 0.78*VA 0.82*VA 0.74*VA 0.78*VA 0.82*VA Full-scale Output Voltage dB Vpp Interchannel Isolation (1 kHz) - 100 - - 100 - dB Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB Gain Drift - 100 - - 100 - ppm/C AC-Load Resistance (RL)(Note 19) 3 - - 3 - - k Load Capacitance (CL)(Note 19) - - 100 - - 100 pF 10 - - 10 - - k - 100 - - 100 - - 60 60 - - 60 60 - dB dB Parallel DC-Load Resistance(Note 20) Output Impedance PSRR (Note 21) DS900F2 1 kHz 60 Hz 15 CS4244 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE GRADE) Test Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 8. VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.; TA = -40 to +85 C; Full-scale 1 kHz input sine wave; Sample Rate = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz; Specifications apply to all channels unless otherwise indicated; all Power Down DACx bits = 0. See (Note 19). VA, VREF= 3.3 V (Differential/Single-ended) Parameter VA, VREF= 5.0 V (Differential/Single-ended) Min Typ Max Min Typ Max Unit 98/94 95/91 87 84 106/102 103/99 95 92 - 101/97 98/94 87 84 109/105 106/102 95 92 - dB dB dB dB - -90/-88 -82/-80 - -90/-88 -82/-80 Dynamic Performance Dynamic Range 18 to 24-Bit 16-Bit A-weighted unweighted A-weighted unweighted Total Harmonic Distortion + Noise 1.48*VA/ 1.56*VA/ 1.64*VA/ 1.48*VA/ 1.56*VA/ 1.64*VA/ 0.74*VA 0.78*VA 0.82*VA 0.74*VA 0.78*VA 0.82*VA Full-scale Output Voltage dB Vpp Interchannel Isolation (1 kHz) - 100 - - 100 - dB Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB Gain Drift - 100 - - 100 - ppm/C AC-Load Resistance (RL)(Note 19) 3 - - 3 - - k Load Capacitance (CL)(Note 19) - - 100 - - 100 pF 10 - - 10 - - k - 100 - - 100 - - 60 60 - - 60 60 - dB dB Parallel DC-Load Resistance(Note 20) Output Impedance PSRR (Note 21) 1 kHz 60 Hz Notes: 18. One LSB of triangular PDF dither added to data. 19. Loading configuration is given in Figure 5 below. 22 F V OUT AOUTx R L C L GND Figure 5. Equivalent Output Test Load 20. Parallel combination of all DAC DC loads. See Section 4.2.3. 21. Valid with the recommended capacitor values on FILT+ and VQ. See Figure 4 for test configuration. DS900F2 16 CS4244 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Test Conditions (unless otherwise specified): VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC. The filter characteristics have been normalized to the sample rate (FS) and can be referenced to the desired sample rate by multiplying the given characteristic by FS. Parameter Single-Speed Mode Passband (Note 22) Frequency Response 20 Hz to 20 kHz StopBand StopBand Attenuation DAC1-4 Group Delay (Note 24) Double-Speed Mode Passband (Note 22) Frequency Response 20 Hz to 20 kHz StopBand StopBand Attenuation DAC1-4 Group Delay (Note 24) to -0.05 dB corner to -3 dB corner (Note 23) to -0.1 dB corner to -3 dB corner (Note 23) Min Typ Max Unit 0 0 -0.01 0.5465 102 - 11/Fs 0.4780 0.4996 +0.12 - FS FS dB FS dB s 0 0 -0.05 0.5770 80 - 7/Fs 0.4650 0.4982 +0.2 - FS FS dB FS dB s Notes: 22. Response is clock-dependent and will scale with FS. 23. For Single-Speed Mode, the measurement bandwidth is 0.5465 FS to 3 FS. For Double-Speed Mode, the measurement bandwidth is 0.577 FS to 1.4 FS. 24. The DAC group delay is measured from the FS/LRCK transition (rising or falling) before the first bit of a (group of) sample(s) is transmitted on the SDINx pins to the time it appears on the AOUTx pins. DS900F2 17 CS4244 DIGITAL I/O CHARACTERISTICS Parameters High-Level Input Voltage (all input pins except RST) (% of VL) (VL = 1.8 V) High-Level Input Voltage (all input pins except RST) (% of VL) (VL = 2.5 V, 3.3 V, or 5 V) Low-Level Input Voltage (all input pins except RST) (% of VL) High-Level Input Voltage (RST pin) Low-Level Input Voltage (RST pin) Symbol Min Typ Max Units VIH 75% - - V VIH 70% - - V VIL - - 30% V VIH 1.2 - - V VIL - - 0.3 V High-Level Output Voltage at Io = 2 mA (% of VL) VOH 80% - - V Low-Level Output Voltage at Io = 2 mA (% of VL) VOL - - 20% V Iin - - 10 A - 8 - pF Input Leakage Current Input Capacitance DS900F2 18 CS4244 SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE VA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC. Parameters RST pin Low Pulse Width (Note 25) MCLK Frequency MCLK Duty Cycle SCLK Duty Cycle Input Sample Rate (FS/LRCK pin) (Note 26) Single-Speed Mode Double-Speed Mode SCLK Falling Edge to SDOUTx Valid (VL = 1.8 V) SCLK Falling Edge to SDOUTx Valid (VL = 2.5 V) SCLK Falling Edge to SDOUTx Valid (VL = 3.3 V or 5 V) TDM Slave Mode SCLK Frequency (Note 27) FS/LRCK High Time Pulse (Note 28) FS/LRCK Rising Edge to SCLK Rising Edge SDINx Setup Time Before SCLK Rising Edge SDINx Hold Time After SCLK Rising Edge PCM Slave Mode SCLK Frequency FS/LRCK Duty Cycle FS/LRCK Edge to SCLK Rising Edge SDINx Setup Time Before SCLK Rising Edge SDINx Hold Time After SCLK Rising Edge PCM Master Mode SCLK Frequency FS/LRCK Duty Cycle FS/LRCK Edge to SCLK Rising Edge SDINx Setup Time Before SCLK Rising Edge SDINx Hold Time After SCLK Rising Edge (VL = 1.8 V) SDINx Hold Time After SCLK Rising Edge (VL = 2.5 V, 3.3 V, or 5 V) Symbol Min Units ms FS FS tdh2 tdh2 tdh2 1 7.68 45 45 30 60 - Max 25.6 55 55 50 100 31 22 17 MHz % % kHz kHz ns ns ns tlpw 256x 1/fSCLK 512x (n-1)/fSCLK FS ns tlcks tds tdh1 5 3 5 - ns ns ns tlcks tds tdh1 32x 45 5 3 5 64x 55 - FS % ns ns ns tlcks tds 64x 45 5 5 64x 55 - FS % ns ns tdh1 11 - ns tdh1 10 - ns (Note 29) Notes: 25. After applying power to the CS4244, RST should be held low until after the power supplies and MCLK are stable. 26. MCLK must be synchronous to and scale with FS. 27. The SCLK frequency must remain less than or equal to the MCLK frequency. For this reason, SCLK may range from 256x to 512x only in single speed mode. In double speed mode, 256x is the only ratio supported. 28. The MSB of CH1 is always aligned with the second SCLK rising edge following FS/LRCK rising edge. 29. Where "n" is equal to the MCLK to LRCK ratio (set by the Master Clock Rate register bits), i.e. in 256x mode, n = 256, in 512x mode, n = 512, etc. DS900F2 19 CS4244 ~ ~ ~ tLPW FS/LRCK (input) tlcks SCLK (input) tds tdh1 SDINx MSB (input) tdh2 MSB-1 tdh2 SDOUT1 MSB (output) MSB-1 Figure 6. TDM Serial Audio Interface Timing FS/LRCK (input/output) tlcks SCLK (input/output) tds SDINx (input) tdh1 MSB MSB-1 MSB MSB-1 tdh2 SDOUTx (output) Figure 7. PCM Serial Audio Interface Timing DS900F2 20 CS4244 SWITCHING SPECIFICATIONS - CONTROL PORT Test conditions (unless otherwise specified): Inputs: Logic 0 = GND = 0 V, Logic 1 = VL; SDA load capacitance equal to maximum value of Cb specified below (Note 30). Parameters Symbol Min Max Unit SCL Clock Frequency fscl - 550 kHz RESET Rising Edge to Start tirs (Note 31) - ns Bus Free Time Between Transmissions tbuf 1.3 - s Start Condition Hold Time (prior to first clock pulse) thdst 0.6 - s Clock Low time tlow 1.3 - s Clock High Time thigh 0.6 - s tsust 0.6 - s thddi 0 0.9 s SDA Output Hold Time from SCL Falling thddo 0.2 0.9 s SDA Setup time to SCL Rising tsud 100 - ns Rise Time of SCL and SDA tr - 300 ns Fall Time SCL and SDA tf - 300 ns tsusp 0.6 - s SDA Bus Load Capacitance Cb - 400 pF SDA Pull-Up Resistance Rp 500 - Setup Time for Repeated Start Condition SDA Input Hold Time from SCL Falling (Note 32) Setup Time for Stop Condition Notes: 30. All specifications are valid for the signals at the pins of the CS4244 with the specified load capacitance. 31. 2 ms + (3000/MCLK). See Section 4.2.1. 32. Data must be held for sufficient time to bridge the transition time, tf, of SCL. RST t irs Stop Repeated Start Start Stop SDA t buf t t high t hdst tf hdst t susp SCL t low t hdd t sud t sust tr Figure 8. IC Control Port Timing DS900F2 21 CS4244 4. APPLICATIONS 4.1 Power Supply Decoupling, Grounding, and PCB Layout As with any high-resolution converter, the CS4244 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 2 shows the recommended power arrangements, with VA connected to clean supplies. VDREG, which powers the digital circuitry, is generated internally from an on-chip regulator from the VA supply. The VDREG pin provides a connection point for the decoupling capacitors, as shown in Figure 2. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS4244 as possible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS4244 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+, VBIAS, and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+, VBIAS, and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from their respective pins and GND.VA_SEL For optimal heat dissipation from the package, it is recommended that the area directly under the device be filled with copper and tied to the ground plane. The use of vias connecting the topside ground to the backside ground is also recommended. 4.2 Recommended Power-up & Power-down Sequence The initialization and Power-Up/Down sequence flow chart is shown in Figure 9. For the CS4244 Reset is defined as all lines held static, RST line is pulled low. Power Down is defined as all lines (excluding MCLK) held static, RST line is high, all PDNx bits are `1'. Running is defined as RST line high, all PDNx bits are `0'. 4.2.1 Power-up The CS4244 enters a reset state upon the initial application of VA and VL. When these power supplies are initially applied to the device, the audio outputs, AOUTxx, are clamped to VQ which is initially low. Additionally, the interpolation and decimation filters, delta-sigma modulators and control port registers are all reset and the internal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and low-pass filters are powered down. The device remains in the reset state until the RST pin is brought high. Once RST is brought high, the control port address is latched after 2 ms + (3000/MCLK). Until this latching transition is complete, the device will not respond to IC reads or writes, but the IC bus may still be used during this time. Once the latching transition is complete, the address is latched and the control port is accessible. At this point and the desired register settings can be loaded per the interface descriptions detailed in the Section 4.3 IC Control Port. To ensure specified performance and timing, the VA_SEL must be set to "0" for VA = 3.3 VDC and "1" for VA = 5.0 VDC before audio output begins. After the RST pin is brought high and MCLK is applied, the outputs begin to ramp with VQ towards the nominal quiescent voltage. VQ will charge to VA/2 upon initial power up. The time that it takes to charge up to VA/2 is governed by the size of the capacitor attached to the VQ pin. With the capacitor value shown in the typical connection diagram, the charge time will be approximately 250 ms. The gradual voltage ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage. Once FS/LRCK is valid, MCLK occurrences are counted over one FS period to determine the MCLK/FS ratio. With MCLK valid and any of the PDNx bits cleared, the internal voltage references will transition to their nominal voltage. Power is applied to the D/A converters and filters, and the analog outputs are un-clamped from the quiescent voltage, VQ. Afterwards, normal operation begins. DS900F2 22 CS4244 4.2.2 Power-down To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turning off the power. In order to do this in a controlled manner, it is recommended that all the converters be muted to start the sequence. Next, set PDNx for all converters to 1 to power them down internally. Then, FS/LRCK and SCLK can be removed if desired. Finally, the "VQ RAMP" bit in the "DAC Control 4" register must be set to `1' for a period of 50 ms before applying reset or removing power or MCLK. During this time, voltage on VQ and the audio outputs discharge gradually to GND. If power is removed before this 50 ms time period has passed, a transient will occur and a slight click or pop may be heard. There is no minimum time for a power cycle. Power may be re-applied at any time. It is important to note that all clocks should be applied and removed in the order specified in Figure 9. If MCLK is removed or applied before RST has been pulled low, audible pops, clicks and/or distortion can result. If either SCLK or FS/LRCK is removed or applied before all PDNx bits are set to 1, audible pops, clicks and/or distortion can result. Note: Timings are approximate and based upon the nominal value of the passive components specified in the "Typical Connection Diagram" on page 8. See Section 4.6.5.2 for volume ramp behavior. System Unpowered Apply VL, VA, and MCLK 250 ms VCM Ready (>90% of Typical) Remove VL, VA, and MCLK Set RST 2 ms + (3000/ MCLK) Write all required configuration settings to Control Port 2 ms + (3000 /MCLK) I2C Address Captured & Control Port Ready Clear RST 50 ms Set VQ_RAMP bit Write VA_SEL bit (in 0Fh) appropriately for VA 250 ms Stop SCLK, FS/LRCK, SDINx Start SCLK, FS/LRCK, SDINx Set all PDN DAC & ADC bits Clear PDN DACx & ADCx bits Set Mute ADCx bits ADC Data Available on SDOUTx Clear Mute ADCx bits Clear Mute DACx bits delay dependent on DAC mute / unmute behavior DACx Fully Operational delay dependent on DAC mute / unmute behavior Set Mute DACx bits System Operational Figure 9. System Level Initialization and Power-Up/Down Sequence 4.2.3 DAC DC Loading Figure 10 shows the analog output configuration during power-up, with the AOUTx pins clamped to VQ to prevent pops and clicks. Thus any DC loads (RLx) on the output pins will be in parallel when the switches are closed. These DC loads will pull the VQ voltage down towards ground. If the parallel combination of all DC loads exceeds the specification shown in the Analog Output Characteristics tables on pages 16 DS900F2 23 CS4244 and 17, the VQ voltage will never rise to its minimum operating voltage. If the VQ voltage never rises above this minimum operating voltage, the device will not finish the power-up sequence and normal operation will not begin. Also note that any AOUTx pin(s) with a DC load must remain powered up (PDN DACx = 0) to keep the VQ net at its nominal voltage during normal operation, otherwise clipping may occur on the outputs. Note that the load capacitors (CLx) are also in parallel during power-up. The amount of total capacitance on the VQ net during power-up will affect the amount of time it takes for the VQ voltage to rise to its nominal operating voltage after VA power is applied. The time period can be calculated using the time constant given by the internal series resistor and the load capacitors. AOUT1+ RL1+ CL1+ RL 1- CL1- RL2+ CL2+ RL 2- CL2- RL3+ CL3+ RL 3- CL3- RL4+ CL4+ RL 4- CL4- S1 AOUT1- AOUT2+ VA S2 ~140k AOUT2- VQ NET ~140k AOUT3+ External VQ capacitor S3 AOUT3- AOUT4+ S4 AOUT4- Figure 10. DAC DC Loading 4.3 IC Control Port All device configuration is achieved via the IC control port registers as described in the Switching Specifications - Control Port table. The operation via the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the IC pins should remain static if no operation is required. The CS4244 acts as an IC slave device. SDA is a bidirectional data line. Data is clocked into and out of the device by the clock, SCL. The AD0 and AD1 pins form the two least significant bits of the chip address and should be connected through a resistor to VL or GND as desired. The SDOUT2 pin is used to set the AD2 bit by connecting a resistor from the SDOUT2 pin to VL or to GND. The state of these pins are sensed after the CS4244 is released from reset. DS900F2 24 CS4244 The signal timings for a read and write cycle are shown in Figure 11 and Figure 12. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4244 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 4 bits of the 7-bit address field are fixed at 0010. To communicate with a CS4244, the chip address field, which is the first byte sent to the CS4244, should match 0010 followed by the settings of the ADx pins. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS4244 after each input byte is read, and is input to the CS4244 from the microcontroller after each transmitted byte. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) 0 SDA 0 1 0 MAP BYTE AD2 AD1 AD0 0 6 INCR 5 4 DATA +1 DATA 3 2 1 0 ACK 7 6 1 0 ACK 7 6 DATA +n 1 0 7 6 1 0 ACK ACK STOP START Figure 11. Timing, IC Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) SDA 0 0 1 0 AD2 AD1 AD0 0 INCR ACK START STOP MAP BYTE 6 5 4 3 2 1 0 CHIP ADDRESS (READ) 0 0 1 0 DATA 7 AD2 AD1 AD0 1 ACK START ACK DATA +1 0 7 ACK 0 DATA + n 7 0 NO ACK STOP Figure 12. Timing, IC Read Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown in Figure 12, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 0010xxx0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 0010xxx1 (chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. DS900F2 25 CS4244 4.3.1 Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudocode above for implementation details. 4.3.1.1 Map Increment (INCR) The CS4244 has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to `0', MAP will stay constant for successive IC reads or writes. If INCR is set to `1', MAP will autoincrement after each byte is read or written, allowing block reads or writes of successive registers. 4.4 System Clocking The CS4244 will operate at sampling frequencies from 30 kHz to 100 kHz. This range is divided into two speed modes as shown in Table 1. Mode Sampling Frequency Single-Speed 30-50 kHz Double-Speed 60-100 kHz Table 1. Speed Modes The serial port clocking must be changed while all PDNx bits are set. If the clocking is changed otherwise, the device will enter a mute state, see Section 4.8 on page 43. 4.4.1 Master Clock The ratio of the MCLK frequency to the sample rate must be an integer. The FS/LRCK frequency is equal to FS, the frequency at which all of the slots of the TDM stream or channels in Left Justified or IS formats are clocked into or out of the device. The Speed Mode and Master Clock Rate bits configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and FS/LRCK frequencies. The CS4244 has an internal fixed ratio PLL. This PLL is activated when the "MCLK RATE[2:0]" bits in the "Clock & SP Sel." register are set to either 000 or 001, corresponding to 256x or 384x. When in either of these two modes, the PLL will activate to adjust the frequency of the incoming MCLK to ensure that the internal state machines operate at a nominal 24.576 MHz rate. As is shown in the Typical Current Consumption table, activation of the PLL will increase the power consumption of the CS4244. FS/LRCK (kHz) MCLK (MHz) 128x (Note 33) 192x (Note 33) 256x 384x 512x 32 - - 8.1920 12.2880 16.3840 44.1 - - 11.2896 16.9344 22.5792 48 - - 12.2880 18.4320 24.5760 64 8.1920 12.2880 16.3840 - - 88.2 11.2896 16.9344 22.5792 - - 96 12.2880 18.4320 24.5760 - - Mode DSM SSM Table 2. Common Clock Frequencies Note: 33. 128x and 192x ratios valid only in Left Justified or IS formats. DS900F2 26 CS4244 4.4.2 Master Mode Clock Ratios As a clock master, FS/LRCK and SCLK will operate as outputs internally derived from MCLK. FS/LRCK is equal to FS and SCLK is equal to 64x FS as shown in Figure 13. TDM format is not supported in Master Mode. MCLK Rate Bits /512 00 01 FS/LRCK MCLK /1.5 x2 000 /256 x2 001 Speed Mode Bits /1 010 /8 00 /4 01 SCLK PLL active Figure 13. Master Mode Clocking The resulting valid master mode clock ratios are shown in Table 3 below. SSM DSM MCLK/FS 256x, 384x, 512x 128x, 192x, 256x SCLK/FS 64x 64x Table 3. Master Mode Left Justified and IS Clock Ratios 4.4.3 Slave Mode Clock Ratios In Slave Mode, SCLK and FS/LRCK operate as inputs. The FS/LRCK clock frequency must be equal to the sample rate, FS, and must be synchronously derived from the supplied master clock, MCLK. The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to 512x, 256x, 128x, 64x, 48x or 32x FS, depending on the desired format and speed mode. Refer to Table 4 and Table 5 for required clock ratios. SSM DSM MCLK/FS 256x, 384x, 512x 128x, 192x, 256x SCLK/FS 32x, 48x, 64x, 128x 32x, 48x, 64x Table 4. Slave Mode Left Justified and IS Clock Ratios (Note 34) SSM DSM MCLK/FS 256x, 384x, 512x 512x 256x SCLK/FS 256x 512x 256x Table 5. Slave Mode TDM Clock Ratios Note: 34. For all cases, the SCLK frequency must be less than or equal to the MCLK frequency. DS900F2 27 CS4244 4.5 Serial Port Interface The serial port interface format is selected by the Serial Port Format register bits. The TDM format is available in Slave Mode only. 4.5.1 TDM Mode The serial port of the CS4244 supports the TDM interface format with varying bit depths from 16 to 24 as shown in Figure 15. Data is clocked out of the ADC on the falling edge of SCLK and clocked into the DAC on the rising edge. As indicated in Figure 15, TDM data is received most significant bit (MSB) first, on the second rising edge of the SCLK occurring after a FS/LRCK rising edge. All data is valid on the rising edge of SCLK. All bits are transmitted on the falling edge of SCLK. Each slot is 32 bits wide, with the valid data sample left justified within the slot. Valid data lengths are 16, 18, 20, or 24 bits. FS/LRCK identifies the start of a new frame and is equal to the sample rate, FS. As shown in Figure 14, FS/LRCK is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data sample and must be held valid for at least 1 SCLK period. Frame FS/LRCK SCLK SDINx & SDOUT1 Channel 1 Channel 2 Channel N-1 Channel N (N 16) Figure 14. TDM System Clock Format 32-Bit Channel Block MSB -1 -2 -3 -4 -5 -6 -7 +3 +2 +1 LSB 24-Bit Audio Word 8-Bit Zero Pad Figure 15. 32-bit Receiver Channel Block The structure in which the serial data is coded into the TDM slots is shown in Figure 16. SDOUT2 is unused in TDM mode and is placed in a high-impedance state. When using a 48 kHz sample rate with a 24.576 MHz MCLK and SCLK, a 16 slot TDM structure can be realized. When using a 48 kHz sample rate with 12.288 MHz SCLK and 24.576 MHz MCLK, or a 96 kHz sample rate with a 24.576 MHz MCLK and SCLK, an 8 slot TDM structure can be realized. The data that is coded into the TDM slots is extracted into the appropriate signal path via the settings in the Control port. Please refer to Section 4.6.1 Routing the Serial Data within the Signal Paths for more details. DS900F2 28 DS900F2 0's [7:0] ADC1 Data[31:8] ADC1 Data[31:8] SDIN2 SDOUT1 SDOUT1 with Sidechain x [7:0] 0's [7:0] Input Data 2.1 [31:8] ADC1 Data [31:8] ADC1 Data [31:8] SDIN1 SDIN2 SDOUT1 SDOUT1 with Sidechain 0's [7:0] x [7:0] Input Data 1.1 [31:8] Slot 1 [31:0] x [7:0] Input Data 2.1 [31:8] SDIN1 0's [7:0] x [7:0] Slot 1 [31:0] Input Data 1.1 [31:8] 0's [7:0] ADC2 Data [31:8] 0's [7:0] 0's [7:0] ADC4 Data [31:8] ADC4 Data [31:8] x [7:0] Input Data 2.4 [31:8] 0's [7:0] 0's [7:0] x[7:0] x [7:0] x [7:0] Output Data (SDIN2 Slot 1) 0's [31:0] Input Data 2.5 [31:8] Input Data 1.5 [31:8] Slot 5 [31:0] ADC3 Data [31:8] ADC3 Data [31:8] Input Data 2.3 [31:8] x [7:0] Slot 3 [31:0] Input Data 1.3 [31:8] ...... 0's [7:0] 0's [7:0] x [7:0] FS/LRCK = 48kHz x [7:0] x [7:0] Output Data (SDIN2 Slot 4) 0's [31:0] Input Data 2.8 [31:8] Input Data 1.8 [31:8] x [7:0] Output Data (SDIN2 Slot 5) 0's [31:0] Input Data 2.9 [31:8] x [7:0] Slot 9 [31:0] Input Data 1.9 [31:8] SCLK = 24.576MHz Slot 8 [31:0] x [7:0] Output Data (SDIN2 Slot 1) 0's [31:0] Input Data 2.5 [31:8] x [7:0] Slot 5 [31:0] Input Data 1.5 [31:8] MCLK = 24.576MHz ADC4 Data [31:8] ADC4 Data[31:8] Input Data 2.4 [31:8] x [7:0] Slot 4 [31:0] Input Data 1.4 [31:8] ...... x[7:0] x [7:0] x [7:0] Output Data (SDIN2 Slot 8) 0's [31:0] Input Data 2.12 [31:8] Input Data 1.12 [31:8] Slot 12 [31:0] Output Data (SDIN2 Slot 2) 0's [31:0] Input Data 2.6 [31:8] x [7:0] Slot 6 [31:0] Input Data 1.6 [31:8] x[7:0] Input Data 2.7 [31:8] x [7:0] x [7:0] Output Data (SDIN2 Slot 9) 0's [31:0] Input Data 2.13 [31:8] Input Data 1.13 [31:8] Slot 13 [31:0] Output Data (SDIN2 Slot 3) 0's [31:0] x [7:0] Slot 7 [31:0] Input Data 1.7 [31:8] Figure 16. Serial Data Coding and Extraction Options within the TDM Streams ...... x [7:0] Input Data 1.4 [31:8] Slot 4 [31:0] 0's [7:0] x [7:0] Input Data 2.2 [31:8] ADC2 Data [31:8] x [7:0] Slot 2 [31:0] Input Data 1.2 [31:8] SCLK = 12.288/24.576MHz FS/LRCK = 48/96kHz MCLK = 12.288/24.576MHz ...... x[7:0] x [7:0] x [7:0] Output Data (SDIN2 Slot 12) 0's [31:0] Input Data 2.16 [31:8] Input Data 1.16 [31:8] Slot 16 [31:0] Output Data (SDIN2 Slot 4) 0's [31:0] Input Data 2.8 [31:8] x [7:0] Slot 8 [31:0] Input Data 1.8 [31:8] CS4244 29 CS4244 4.5.2 Left Justified and IS Modes The serial port of the CS4244 supports the Left Justified and IS interface formats with valid bit depths of 16, 18, 20, or 24 bits for the SDOUTx pins and 24 bits for the SDINx pins. All data is valid on the rising edge of SCLK. Data is clocked out of the ADC on the falling edge of SCLK and clocked into the DAC on the rising edge. In Master Mode each slot is 32 bits wide. In Left Justified mode (see Figure 17) the data is received or transmitted most significant bit (MSB) first, on the first rising edge of the SCLK occurring after a FS/LRCK edge. The left channel is received or transmitted while FS/LRCK is logic high. In IS mode (see Figure 18) the data is received or transmitted most significant bit (MSB) first, on the second rising edge of the SCLK occurring after a FS/LRCK edge. The left channel is received or transmitted while FS/LRCK is logic low. The AIN1 and AIN2 signals are transmitted on the SDOUT1 pin; the AIN3 and AIN4 signals are transmitted on the SDOUT2 pin. The data on the SDIN1 pin is routed to AOUT1 and AOUT2; the data on the SDIN2 pin is routed to AOUT3 and AOUT4. FS/LRCK SCLK SDINx SDOUTx L e ft C h a n n e l M SB R ig h t C h a n n e l LS B MSB LS B MSB AOUT 2 or 4 AIN 2 or 4 AOUT 1 or 3 AIN 1 or 3 Figure 17. Left Justified Format FS/LRCK L e ft C h a n n e l R ig h t C h a n n e l SCLK SDINx SDOUTx M SB LS B M SB LS B MSB AOUT 2 or 4 AIN 2 or 4 AOUT 1 or 3 AIN 1 or 3 Figure 18. IS Format DS900F2 30 CS4244 4.6 Internal Signal Path VD 2.5 VDC 2.5 V AIN1 AIN2 AIN3 AIN4 () () () () VA 5.0 VDC LDO Analog Supply Multi-bit ADC Digital Filters Channel Volume , Mute, Invert , Noise Gate Master Volume Control Interpolation Filter Multi-bit Modulators Serial Audio Interface DAC & Analog Filters AOUT1 () AOUT2 () AOUT3 () AOUT4 () Control Port Level Translator SDOUT1 SDOUT2 SDIN2 SDIN1 VL 1.8 to 5.0 VDC Frame Sync Clock / LRCK Master Clock In Serial Clock In/ Out INT RST I2C Control Data Figure 19. Audio Path Routing The CS4244 device includes two paths in which audio data can be routed. The analog input path, shown in yellow, allows up to four analog signals to be combined into a single TDM stream on the SDOUT1 pin or output as stereo pairs on the SDOUT1 and SDOUT2 pins. The DAC1-4 path, highlighted in blue, converts serial audio data to analog audio data. 4.6.1 Routing the Serial Data within the Signal Paths 4.6.1.1 ADC Signal Routing In TDM mode, the CS4244 is designed to load the first four slots of the TDM stream on the SDOUT1 pin with the internal ADC data. Additionally, in order to minimize the number of SDOUT lines that must be run to the system controller in a multiple IC application, the SDOUT data for up to 4 devices can be loaded into a single TDM stream by side chaining the devices together, as shown in Figure 20. To enable the sidechain feature, the "SDO CHAIN" bit in the "SP Control" register must be set. DS900F2 31 CS4244 DSP DSP Device D x Device D SDOUT1 x SDIN2 x SDIN1 x Each of the device's ADC data is reflected in the TDM stream on SDOUT1 and then routed to the system controller. x SDIN2 x SDIN1 Device C x SDOUT1 SDOUT1 Device C x SDOUT1 x SDIN2 x SDIN2 x SDIN1 x SDIN1 Device B x SDOUT1 The ADC data of Device D is coded into the first four slots of the output TDM stream, followed by the first 12 slots of the TDM stream coming in on SDIN2, placing the ADC data from Device C into slots 5-8, the ADC data from Device B into slots 9-12, and the ADC data from Device A into slots 13-16 of the outgoing TDM stream. The ADC data of Device C is coded into the first four slots of the output TDM stream, followed by the first 12 slots of the TDM stream coming in on SDIN2, placing the ADC data from Device B into slots 5-8 and the ADC data from Device A into slots 9-12 of the outgoing TDM stream. Device B x SDOUT1 x SDIN2 x SDIN2 x SDIN1 x SDIN1 Device A The ADC data of Device B is coded into the first four slots of the output TDM stream, followed by the first 12 slots of the TDM stream coming in on SDIN2, placing the ADC data from Device A into slots 5-8 of the outgoing TDM stream. Device A x SDOUT1 x SDOUT1 x SDIN2 x SDIN2 x SDIN1 x SDIN1 ADC data from Device A is loaded into the first 4 slots of the 16 slot TDM Stream going out of SDOUT1 pin of Device A. The last 12 slots are all coded as " 0's". Note: This diagram shows the configuration for 16 slot TDM streams. If 8 slot TDM streams are used, two separate serial data lines will need to be connected from the DSP. One would carry the serial data for Devices C&D and the other would carry the serial data for Devices A&B Figure 20. Conventional SDOUT (Left) vs. Sidechain SDOUT (Right) Configuration In Left Justified or IS mode, the CS4244 transmits the AIN1 and AIN2 signals on the SDOUT1 pin and the AIN3 and AIN4 signals on the SDOUT2 pin. 4.6.1.2 DAC1-4 Signal Routing In TDM mode, the "DAC1-4 SOURCE[2:0]" bits in the "SP Data Sel." register advise the CS4244 where data for the DAC1-4 path is located within the incoming TDM streams. Details for this register and the bit settings can be found in Figures 21 and 22. In Left Justified or IS mode, the CS4244 routes the data on the SDIN1 pin to DAC1 and DAC2 and the data on the SDIN2 pin to DAC3 and DAC4. DS900F2 32 DS900F2 Slot 1 [31:0] Slot 1 [31:0] SDIN2 ...... Slot 4 [31:0] Slot 4 [31:0] Slot 2 [31:0] Slot 1 [31:0] SDIN2 SDIN1 Slot 2 [31:0] Slot 1 [31:0] SDIN1 ...... Slot 8 [31:0] Slot 8 [31:0] SCLK = 24.576MHz FS/LRCK = 48kHz MCLK = 24.576MHz Slot 4 [31:0] Slot 4 [31:0] Slot 9 [31:0] Slot 9 [31:0] Slot 5 [31:0] Slot 5 [31:0] ...... Slot 12 [31:0] Slot 12 [31:0] Slot 6 [31:0] Slot 6 [31:0] Figure 21. DAC1-4 Serial Data Source Selection Slot 5 [31:0] Slot 5 [31:0] Slot 3 [31:0] Slot 3 [31:0] SCLK = 12.288/24.576MHz FS/LRCK = 48/96kHz MCLK = 12.288/24.576MHz Slots 13-16 of SDIN2 111 Slots 1-4 of SDIN2 100 Slots 5-8 of SDIN2 Slots 13-16 of SDIN1 011 Slots 9-12 of SDIN2 Slots 5-8 of SDIN1 Slots 9-12 of SDIN1 001 010 110 Slots 1-4 of SDIN1 000 101 DAC1-4 Data is in: DAC1-4 Source [2:0] Slot 13 [31:0] Slot 13 [31:0] Slot 7 [31:0] Slot 7 [31:0] ...... Slot 16 [31:0] Slot 16 [31:0] Slot 8 [31:0] Slot 8 [31:0] CS4244 33 DS900F2 SDIN2 SDIN1 x Slot 1 [31:0] DAC1 [23:0] x x Slot 2 [31:0] DAC2 [23:0] x x x Slot 4 [31:0] DAC4 [23:0] x x x Slot 5 [31:0] x x Slot 6 [31:0] Figure 22. Example Serial Data Source Selection x Slot 3 [31:0] DAC3 [23:0] SCLK = 12.288/24.576MHz FS/LRCK = 48/96kHz MCLK = 12.288/24.576MHz Slots 13-16 of SDIN2 111 Slots 1-4 of SDIN2 100 Slots 5-8 of SDIN2 Slots 13-16 of SDIN1 011 Slots 9-12 of SDIN2 Slots 5-8 of SDIN1 Slots 9-12 of SDIN1 001 010 110 Slots 1-4 of SDIN1 000 101 DAC1-4 Data is in: DAC1-4 Source [2:0] x x Slot 7 [31:0] x x Slot 8 [31:0] CS4244 34 CS4244 4.6.2 ADC Path VD 2.5 VDC 2.5 V AIN1 AIN2 AIN3 AIN4 () () () () VA 5.0 VDC LDO Analog Supply Multi-bit ADC Digital Filters Master Volume Control Channel Volume , Mute, Invert, Noise Gate Interpolation Filter Multi-bit Modulators Serial Audio Interface DAC & Analog Filters AOUT1 AOUT2 AOUT3 AOUT4 () () () () Control Port Level Translator SDOUT1 SDOUT2 SDIN2 Frame Sync Clock / LRCK SDIN1 VL 1.8 to 5.0 VDC Master Clock In Serial Clock In/ Out INT RST I2 C Control Data Figure 23. ADC Path 4.6.2.1 Analog Inputs AINx+ and AINx- are line-level differential analog inputs. The analog input pins do not self-bias and must be externally biased to VA/2 to avoid clipping of the input signal. The full-scale analog input levels are scaled according to VA and can be found in the Analog Input Characteristics tables on pages 12 and 13. The ADC output data is in two's complement binary format. For inputs above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively, and cause the ADC Overflow bit in the Interrupt Notification 1 register to be set to a `1'. 4.6.2.2 Active ADC Input Filter The analog modulator samples the input at 6.144 MHz (internal MCLK = 12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are multiples of the digital passband frequency (n 6.144 MHz), where n = 0,1,2,... Refer to Figure 24 for a recommended analog input filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capacitors that have a large voltage coefficient (such as general-purpose ceramics) must be avoided since these can degrade signal linearity. DS900F2 35 CS4244 634 470 pF C0G - 22 F AINx+ + 634 634 100 k VA ADC1-4 * Place close to AINx pins 91 2700 pF C0G 470 pF C0G 100 k 100 k - * 91 AINx- + 0.01 F 100 k 22 F Figure 24. Single-Ended to Differential Active Input Filter 4.6.2.3 ADC HPF The ADC path contains an optional HPF which can be enabled or disabled for all four ADCs via the "ENABLE HPF" bit in the "ADC Control 1" register. The HPF should only be disabled when the DC component of the input signal needs to be preserved in the digital output data. The HPF characteristics are given in the ADC Digital Filter Characteristics table and plotted in Section 7. The Analog Input Characteristics tables on pages 12 and 13 specify the DC offset error when the HPF is enabled or disabled. The following figure shows how the recommended single-ended to differential active input filter (Figure 24) can be modified to allow for DC coupled inputs when the HPF is disabled. Note that the voltage swing should not exceed the ADC full-scale input specification. 634 470 pF C0G - AINx+ + 634 634 100 k 2700 pF C0G 470 pF C0G VA 100 k + 100 k 0.01 F ADC1-4 * Place close to AINx pins 91 91 * AINx- 22 F Figure 25. Single-Ended to Differential Active Input Filter - DC Coupled Input Signal (VA/2 Centered) DS900F2 36 CS4244 4.6.3 DAC1-4 Path VD 2.5 VDC 2.5 V AIN1 AIN2 AIN3 AIN4 () () () () VA 5.0 VDC LDO Analog Supply Multi-bit ADC Digital Filters Channel Volume , Mute, Invert , Noise Gate Master Volume Control Interpolation Filter Multi-bit Modulators Serial Audio Interface DAC & Analog Filters AOUT1 AOUT2 AOUT3 AOUT4 () () () () Control Port Level Translator SDOUT1 SDOUT2 SDIN2 VL 1.8 to 5.0 VDC SDIN1 Frame Sync Clock / LRCK Master Clock In Serial Clock In/Out INT RST 2 I C Control Data Figure 26. DAC1-4 Path The AOUT1-4 signals are driven by the data placed into the DAC1-4 path. This data can be placed into the DAC1-4 path via the DAC1-4 Data Source settings in the control port. These settings allow the input source to be selected from any of the up to 32 slots of data on the incoming TDM streams on SDIN1 and SDIN2. The DAC1-4 path also includes individual channel mutes. Separate volume controls are available for each channel, along with a master volume control that simultaneously attenuates all four channels. The master volume attenuation is added to any channel attenuation that is applied. 4.6.3.1 De-emphasis Filter The CS4244 includes on-chip digital de-emphasis for 32, 44.1, and 48 kHz sample rates. It is not supported for 96 kHz or for any settings in Double-speed Mode. The filter response is adjusted to be appropriate for a particular base rate by the Base Rate Advisory bits. This filter response, shown in Figure 27, will vary if these bits are not set appropriately for the given base rate. The frequency response of the de-emphasis curve scales proportionally with changes in sample rate, FS. Please see Section 6.9.2 DAC1-4 De-emphasis for de-emphasis control. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. DS900F2 37 CS4244 De-emphasis is only available in Single-speed Mode. Gain dB T1=50 s 0dB T2 = 15 s -10dB F1 3.183 kHz F2 Frequency 10.61 kHz Figure 27. De-emphasis Curve 4.6.4 Analog Outputs The recommended differential passive output filter is shown below. The filter has a flat frequency response in the audio band while rejecting as much signal energy outside of the audio band as possible. The filter has a single-pole high-pass filter to AC-couple the output signal to the load and a single-pole low-pass filter to attenuate high-frequency energy resulting from the CS4244 DAC's noise shaping function. DAC1-4 22 F 470 AOUTx+ 1500 pF C0G 47 k 22 F 470 AOUTx47 k 1500 pF C0G Figure 28. Passive Analog Output Filter DS900F2 38 CS4244 4.6.5 Volume Control The CS4244 includes a volume control for the DAC1-4 signal path. The implementation details for the volume control and other associated peripheries for DAC1-4 is shown in Figure 29 below. Digital volume steps, adjustable noise gating, muting, and soft ramping are provided on each DAC channel. INV DACx DACx Data 1 0 DAC1-4 Noise Gate Threshold Noise Gate x DACx Volume Register Setting + Master Volume Register Setting Limiter (+6 to -90 dB) Soft Ramp MUTE DACx Interpolation Filter Modulator DAC AOUTx 0 1 DAC1-4 ATT Figure 29. Volume Implementation for the DAC1-4 Path 4.6.5.1 Mute Behavior Each DAC channel volume is controlled by the sum (in dB) of the individual channel volume and the master volume registers. The channel and master volume control registers have a range of +6 dB to -90 dB with a nominal resolution of 6.02/16 dB per each bit, which is approximately 0.4 dB. The sum of the two volume settings is limited to a range of +6 dB to -90 dB. Any volume setting below this range will result in infinite attenuation thus muting the channel. A DAC channel may alternatively be muted by using the mute register bits, the power down bits, or the Noise Gate feature. For any case when the mute engages (volume is less than -90 dB, power down bit is set, mute bit is set, or Noise Gate is engaged), the CS4244 will mute the channel immediately or soft-ramp the volume down at a rate specified by the MUTE DELAY[1:0] bits depending on the settings of the DAC14 ATT. bit in the "DAC Control 3" register. This behavior also applies when unmuting a channel. 4.6.5.2 Soft Ramp The CS4244 soft ramp feature (enabled using the DAC1-4 ATT. bit) is activated on mute and unmute transitions as well as any normal volume register changes. To avoid any potential audible artifacts due to the soft ramping, the volume control algorithm implements the ramping function differently based upon how the user attempts to control the volume. If the user changes the volume in distant discrete steps such as what would happen if a button were pressed on a user interface to temporarily add attenuation to or mute a channel, then the volume is ramped from the current setting to the new setting at a constant rate set by the MUTE DELAY[1:0] bits. Alternatively, if the user controls the volume through a knob or slider interface, a volume envelope is sampled at a slow, not-necessarily uniform rate (typically 1-20 Hz) and sent to the CS4244. In this case the ramping algorithm detects a short succession of volume changes attempting to track the volume envelope and dynamically adjusts the soft-ramp rate. If the CS4244 were to use a constant ramp rate between the volume changes it receives, its output volume envelope may either lag behind the user-generated envelope if the ramp rate is set too low (possibly not reaching the peaks and dulling the envelope) or the output volume envelope may cause a stair-case effect resulting in audible zipper noise if the ramp rate is set too high. By instead adapting the soft-ramp rate to fit the envelope given by the incoming volume samples, the envelope lag time is limited and the zipper DS900F2 39 CS4244 noise is avoided. In this mode the soft ramp algorithm linearly interpolates the volume between the volume changes. There is a lag of one volume change sample since two samples are required to calculate the first ramp rate. See Figure 30 for the soft ramp diagram. On the first volume sample received, the CS4244 only detects the possible beginning of a volume envelope sequence and resets an envelope counter. The volume starts ramping to the new volume setting at a constant rate controlled by the MUTE DELAY[1:0] setting. If the envelope counter times out before a new volume sample is received, the next received sample is treated in the same way as the previous sample and the ramp rate is kept constant. In this way, as long as the volume samples are distant from each other by more than the envelope counter time out, the rate is kept constant resulting in the soft-ramp behavior described in the button-press example. However if the next volume sample is received before the envelope counter times out, then it is assumed to be part of a volume envelope sequence. The envelope counter is reset and as long as new samples are received in succession before a time out occurs, the sequence is continued. Starting at the second volume sample of an envelope sequence, the ramp rate is adjusted using the equation shown in Figure 30. Wait State Envelope Counter Running USER: Change Volume or Mute Register Envelope Counter Timed Out? Yes Reset Envelope Counter No Reset Envelope Counter Ramp Rate Ramp Rate = MUTE_DELAY New Volume Setting - Current Volume Setting Time Between Volume Changes MIN_DELAY Limit Ramp Rate MAX_DELAY Figure 30. Soft Ramp Behavior Two control parameters allow the user to limit the ramp-rate range to achieve optimum effect. The MIN DELAY[2:0] setting limits the maximum ramp rate; higher values will introduce more lag in the envelope tracking while providing a smoother ramp. The MAX DELAY[2:0] setting limits the minimum ramp rate; lower values will permit closer tracking of the envelope but may re-introduce zipper noise. The default values of these registers are recommended as a starting point. It is possible to disable the volume envelope DS900F2 40 CS4244 tracking and always produce a constant ramp rate. To accomplish this, set the MIN DELAY[2:0] and MAX DELAY[2:0] values to match the MUTE DELAY[1:0] setting. The envelope counter time out period which defines the boundary between the two soft-ramping behaviors depends on the base rate. It is equal to approximately 100,000/Fs. The MUTE DELAY[1:0], MIN DELAY[2:0], and MAX DELAY[2:0] bits specify a delay equal to a multiple of the base period between volume steps of 6.02/64 dB, which is approximately 0.1 dB. This is the internal resolution of the volume control engine. Consequently the soft-ramp rate can be expressed in ms/dB as shown in Table 6. Fs = 48 kHz or 96 kHz (Base = 48 kHz) Ramp Rate Time to Ramp Time to Ramp to Full Scale 6 dB (ms) (ms) ms/dB 1 x Base 21.33 1.33 0.22 2 x Base 42.67 2.67 4 x Base 85.33 5.33 8 x Base 170.67 16 x Base 341.33 Fs = 32 kHz or 64 kHz (Base = 32 kHz) Time to Ramp Time to Ramp to Full Scale 6 dB (ms) (ms) ms/dB 32 2 0.33 0.44 64 4 0.66 0.89 128 8 1.33 10.67 1.77 256 16 2.66 21.33 3.54 512 32 5.32 32 x Base 682.67 42.67 7.09 1024 64 10.63 64 x Base 1365.33 85.33 14.17 2048 128 21.26 128 x Base 2730.67 170.67 28.35 4096 256 42.52 Table 6. Soft Ramp Rates Full-scale ramp is 96 dB (-90 dB to +6 dB) 4.6.5.3 Noise Gate The CS4244 is equipped with a Noise Gate feature that mutes the output if the signal drops below a given bit depth for 8192 samples. While the enabling or disabling of the Noise Gate feature is done for the entire DAC1-4 output path, each of the channels within the path have separate monitoring circuitry that will trigger the Noise Gate function independently of the other channels. For instance, if the Noise Gate were enabled for and one of the channels were to exhibit a pattern of more than 8192 samples of either all "1's" or all "0's", the output for that particular channel would be muted (and subsequently unmuted), independently of the other channels. To enable the Noise Gate feature, set the DAC1-4 NG[2:0] bits to the desired bit depth. The available bit depth settings are shown in Table 7. DAC1-4 NG[2:0] Setting Channel is muted after "x" bits 000 Upper 13 Bits (-72 dB) 001 Upper 14 Bits (-78 dB) 010 Upper 15 Bits (-82 dB) 011 Upper 16 Bits (-90 dB) 100 Upper 17 Bits (-94 dB) 101 Upper 18 Bits (-102 dB) 110 Upper 24 Bits (-138 dB) 111 Noise Gate Disabled Table 7. Noise Gate Bit Depth Settings DS900F2 41 CS4244 When the upper "x" bits, as dictated by the DAC1-4 NG[2:0] settings, are either all "1's" or all "0's" for 8192 consecutive samples, the Noise Gate will engage for that channel. Setting these bits to `111' will disable the Noise Gate feature. If the Noise Gate feature engages, it will transition into and out of mute as dictated by the DAC1-4 ATT. bit in the "DAC Control 3" register. 4.7 Reset Line The reset line of the CS4244 is used to place the device into a reset condition. In this condition, all of the values of the CS4244 control port are set to their default values. This mode of operation is the lowest power mode of operation for the CS4244 and should be used whenever the device is not operating in order to save power. During the power up and power down sequence, it is often necessary for the CS4244 devices to be placed into (and taken out of) reset at a different moment in time than the amplifiers to which they are connected in order to minimize audible clicks and pops during the sequence. For this reason, it is advisable to run separate reset lines for each type of device, i.e. one reset line for the CS4244 devices and one for the amplifier devices. 4.8 Error Reporting and Interrupt Behavior The CS4244 is equipped with a suite of error reporting and protection. The types of errors that are detected, the notification method for these errors, and the steps needed to clear the errors are detailed in Table 8. It is important to note that the interrupt notification bits for all of the errors are triggered on the edge of the occurrence of the event. They are not level-triggered and therefore do not indicate the presence of an error in real time. This means that, a "1" in the error's respective field inside the Interrupt Notification register only indicates that the error has occurred since the last time the register was cleared and not necessarily that the error is currently occurring. Name of Error Event(s) that Caused the Error All PDNx bits must be set Outputs Muted and then cleared to Upon Occurrence? resume normal operation? Disallowed Test Mode Entry (Note 35) Device has entered test mode due to an errant IC write. No No Serial Port Error FS/LRCK, or SCLK has become invalid. Yes Yes Clocking Error The speed mode which the device is receiving is different than the speed mode set in the SPEED MODE bits, or the PLL is unlocked from input signal. Yes Yes ADCx Overflow ADC inputs are larger than the permitted full scale signal. No No (Normal operation will continue but audible distortion will occur.) DACx Clip DAC output level is larger than the available rail voltage. No No Normal operation will continue but audible distortion will occur. Table 8. Error Reporting and Interrupt Behavior Details Note: 35. This error is provided to aid in trouble shooting during software development. Entry into the test mode of the device may cause permanent damage to the device and should not be done intentionally. DS900F2 42 CS4244 4.8.1 Interrupt Masking An occurrence of any of the errors mentioned above will cause the interrupt line to engage in order to notify the system controller that an error has occurred. If it is preferred that the error not cause the interrupt line to engage, this error can be masked in its respective mask register. It is important to note that, in the event of an error, the interrupt notification bit for the respective error will reflect the occurrence of the event, regardless of the setting of the mask bit. Setting the mask bit only prevents the interrupt pin from being flagged upon the occurrence. 4.8.2 Interrupt Line Operation As mentioned previously, the interrupt line of the CS4244 will be pulled low or high (depending on the settings of the "INT PIN[1:0]" bits in the "Interrupt Control" register) after an interrupt condition occurs, provided that the event is not masked in the mask register. If the CS4244's interrupt line is to be connected onto a single bus with other devices, it is advisable to use it in the open drain mode of operation. If no other devices are connected to the interrupt line, it may be used in the CMOS mode of operation. When used in the open drain configuration, it is necessary to connect a pull-up resistor to this net, which will ensure a known state on the net when no error is present. Please refer to the typical connection diagram for the appropriate pull-up resistor value. 4.8.3 Error Reporting and Clearing In the event of an error, the interrupt line will be engaged - provided the mask bit for that error is not set. When the interrupt notification registers are read to determine the source of the error, the mask bit for whichever error occurred will be set automatically by the CS4244. The system controller should begin to take corrective action to clear the error. Once the error has been cleared, the system controller should clear the mask bit in the appropriate mask register to ensure that a subsequent occurrence of the error will cause the interrupt line to engage appropriately. This behavior is detailed in Figure 31 on page 45. DS900F2 43 CS4244 USER: Mask bit(s) set to 0 New Unmasked Error New Unmasked Error New Unmasked Error New Unmasked Error New Unmasked Error New Unmasked Error Unmasked error occurs Status Register bit changes to `1' and INT pin set to active level USER: Read Status Registers (see status bit(s) = `1') Mask bit(s) of corresponding status bit(s) set to `1' INT pin set to inactive level Status Register bit(s) set to `1' USER: Takes Corrective Action All Status Register bits cleared Are any errors still occurring? Yes No USER: Read Status Registers (see all status bits = `0') Figure 31. Interrupt Behavior and Example Interrupt Service Routine DS900F2 44 CS4244 5. REGISTER QUICK REFERENCE Default values are shown below the bit names. AD Function 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 (Read Only Bits are shown in Italics) 01h p 48 02h p 48 03h p 48 04h 05h p 48 06h p 49 07h p 50 08h p 50 09h p 51 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh p 52 10h p 52 11h 12h p 53 13h p 53 14h p 54 15h p 54 Device ID A&B Device ID C&D Device ID E&F Variant ID Revision ID Clock & SP Sel. Sample Width Sel. SP Control SP Data Sel. Reserved Reserved Reserved Reserved Reserved ADC Control 1 ADC Control 2 Reserved DAC Control 1 DAC Control 2 DEV. ID A[3:0] 0 1 0 0 DEV. ID B[3:0] 0 0 0 0 1 0 1 DEV. ID C[3:0] DEV. ID D[3:0] 1 DEV. ID E[3:0] 0 0 DEV. ID F[3:0] 0 0 0 0 Reserved [3:0] 0 0 Reserved [3:0] 0 0 0 0 ALPHA REV. ID[3:0] x x NUMERIC REV. ID[3:0] x x BASE RATE[1:0] SPEED MODE[1:0] 0 0 0 SDOUTx SW[1:0] 1 x 1 1 0 1 0 1 0 1 Reserved 0 0 0 0 0 1 1 1 1 1 0 Reserved[1:0] 1 SP FORMAT[1:0] Reserved x Reserved 1 Reserved[1:0] Reserved[2:0] 0 x MCLK RATE[2:0] 0 INPUT SW[1:0] INV SCLK x 1 1 SDO CHAIN MSTR/SLV 0 0 0 DAC1-4 SOURCE[2:0] Reserved[2:0] 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VA_SEL ENABLE HPF INV. ADC4 INV. ADC3 INV. ADC2 INV. ADC1 Reserved[7:0] Reserved[7:0] 1 1 1 1 Reserved[7:0] 1 1 1 1 Reserved[7:0] 1 1 1 Reserved 0 Reserved Reserved[2:0] 0 Reserved Reserved[3:0] 1 1 0 0 0 0 0 0 MUTE ADC4 MUTE ADC3 MUTE ADC2 MUTE ADC1 PDN ADC4 PDN ADC3 PDN ADC2 PDN ADC1 1 1 1 1 1 1 1 1 Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 DAC1-4 DE Reserved Reserved Reserved[2:0] 1 1 1 DAC1-4 NG[2:0] 1 1 1 Reserved[2:0] Reserved 0 0 0 0 0 Reserved INV. DAC4 INV. DAC3 INV. DAC2 INV. DAC1 1 1 1 0 0 0 0 0 DAC Control 3 Reserved DAC1-4 ATT. Reserved Reserved MUTE DAC4 MUTE DAC3 MUTE DAC2 MUTE DAC1 1 0 1 DAC Control 4 VQ RAMP DS900F2 0 Reserved[1:0] 0 0 1 1 1 1 1 Reserved PDN DAC4 PDN DAC3 PDN DAC2 PDN DAC1 1 1 1 1 1 45 CS4244 AD Function 7 6 5 4 3 2 1 0 (Read Only Bits are shown in Italics) 16h p 55 17h p 56 18h p 56 19h p 56 1Ah p 56 1Bh p 56 1Ch 1Dh Volume Mode Master Volume DAC1 Volume DAC2 Volume DAC3 Volume DAC4 Volume MUTE DELAY[1:0] 1 p 56 1Fh p 58 21h p 58 22h p 59 0 0 0 0 0 0 0 0 Interrupt Mask 1 Interrupt Mask 2 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC1 VOLUME[7:0] 1 0 DAC2 VOLUME[7:0] 0 0 0 1 0 DAC3 VOLUME[7:0] 0 0 0 1 0 DAC4 VOLUME[7:0] 0 0 0 1 0 0 0 1 Reserved[7:0] Reserved[3:0] Reserved Interrupt Control 0 1 Reserved p 57 20h 0 MAX DELAY[2:0] MASTER VOLUME[7:0] 1 1Eh MIN DELAY[2:0] 0 INT MODE 1 INT PIN[1:0] Reserved[3:0] 1 1 0 1 0 Reserved Reserved Reserved Reserved Reserved 0 1 0 0 0 0 0 0 MASK TST MODE ERR MASK SP ERR MASK CLK ERR Reserved MASK ADC4 OVFL MASK ADC3 OVFL MASK ADC2 OVFL MASK ADC1 OVFL 0 0 0 1 0 0 0 0 Reserved MASK DAC4 CLIP MASK DAC3 CLIP MASK DAC2 CLIP MASK DAC1 CLIP Reserved Reserved Reserved 0 0 1 0 0 0 0 0 Interrupt Notification 1 TST MODE SP ERR CLK ERR Reserved ADC4 OVFL ADC3 OVFL ADC2 OVFL ADC1 OVFL x x x x x x x x Interrupt Notification 2 Reserved Reserved Reserved Reserved DAC4 CLIP DAC3 CLIP DAC2 CLIP DAC1 CLIP x x x x x x x x DS900F2 46 CS4244 6. REGISTER DESCRIPTIONS All registers are read/write unless otherwise stated. All "Reserved" bits must maintain their default state. Default values are shaded. 6.1 Device I.D. A-F (Address 01h-03h) (Read Only) 7 6 5 4 3 2 DEV. ID A[3:0] 7 6 5 6 4 3 2 1 0 1 0 DEV. ID D[3:0] 5 4 3 2 DEV. ID E[3:0] 6.1.1 0 DEV. ID B[3:0] DEV. ID C[3:0] 7 1 DEV. ID F[3:0] Device I.D. (Read Only) Device I.D. code for the CS4244. Example:. 6.2 DEV. ID A[3:0] DEV. ID B[3:0] DEV. ID C[3:0] DEV. ID D[3:0] DEV. ID E[3:0] DEV. ID F[3:0] Part Number 4h 2h 3h 4h 0h 0h CS4244 Revision I.D. (Address 05h) (Read Only) 7 6 5 4 3 2 1 0 AREVID3 AREVID2 AREVID1 AREVID0 NREVID3 NREVID2 NREVID1 NREVID0 6.2.1 Alpha Revision (Read Only) CS4244 Alpha (silicon) revision level. 6.2.2 AREVID[3:0] Alpha Revision Level Ah A ... ... Numeric Revision (Read Only) CS4244 Numeric (metal) revision level. NREVID[3:0] Numeric Revision Level 0h 0 ... ... Note: The Alpha and Numeric revision I.D. are used to form the complete device revision I.D. Example: A0, A1, B0, B1, B2, etc. DS900F2 47 CS4244 6.3 Clock & SP Select (Address 06h) 7 6 BASE RATE[1:0] 6.3.1 5 4 SPEED MODE[1:0] 3 2 MCLK RATE[2:0] 1 0 Reserved Base Rate Advisory Advises the CS4244 of the base rate of the incoming base rate. This allows for the de-emphasis filters to be adjusted appropriately. The CS4244 includes on-chip digital de-emphasis for 32, 44.1, and 48 kHz base rates. It is not supported for 96 kHz or for any settings in Double Speed Mode. 6.3.2 BASE RATE Base Rate is: 00 48 kHz 01 44.1 kHz 10 32 kHz 11 Reserved Speed Mode Sets the speed mode in which the CS4244 will operate.. SPEED MODE 6.3.3 Speed Mode is: 00 Single Speed Mode 01 Double Speed Mode 10 Reserved 11 Auto Detect (Slave Mode only) Master Clock Rate Sets the rate at which the master clock is entering the CS4244. Settings are given in "x" multiplied by the incoming sample rate, as MCLK must scale directly with incoming sample rate. DS900F2 MCLK RATE MCLK is: 000 256xFS in Single Speed Mode or 128xFS in Double Speed Mode 001 384xFS in Single Speed Mode or 192xFS in Double Speed Mode 010 512xFS in Single Speed Mode or 256xFS in Double Speed Modex 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Reserved 48 CS4244 6.4 Sample Width Select (Address 07h) 7 6 SDOUTx SW[1:0] 6.4.1 5 4 INPUT SW[1:0] 3 2 1 Reserved[1:0] 0 Reserved[1:0] Output Sample Width These bits set the width of the samples placed into the outgoing SDOUTx streams. OUTPUT SW Sample Width is: 00 16 bits 01 18 bits 10 20 bits 11 24 bits Note: 6.4.2 Bits wider than the Output Sample Width setting are cleared within the SDOUTx data stream. Input Sample Width These bits set the width of the samples coming into the CS4244 through the SDINx TDM streams. INPUT SW Sample Width is: 00 16 bits 01 18 bits 10 20 bits 11 24 bits Note: 6.5 In Left Justified or IS mode, the Input Sample Width is fixed to 24 bits. Serial Port Control (Address 08h) 7 INV SCLK 6.5.1 6 5 Reserved[2:0] 4 3 2 SP FORMAT[1:0] 1 SDO CHAIN 0 MASTER/ SLAVE Invert SCLK When set, this bit inverts the polarity of the SCLK signal. 6.5.2 INV SCLK SCLK is: 0 Not Inverted 1 Inverted Serial Port Format Sets the format of both the incoming serial data signals and outgoing serial data signals. DS900F2 SP FORMAT Format is: 00 Left Justified 01 IS 10 TDM (Slave Mode Only) 11 Reserved 49 CS4244 6.5.3 Serial Data Output Sidechain Setting this bit enables the SDOUT1 side chain feature. In this mode, the samples from multiple devices can be coded into one TDM stream. See Section 4.6.2 ADC Path for details. SDO CHAIN 6.5.4 Sidechain is: 0 Disabled 1 Enabled Master/Slave Setting this bit places the CS4244 in master mode, clearing it places it in slave mode. MASTER/SLAVE 0 Slave Mode 1 Master Mode Note: 6.6 CS4244 is in: IS and Left Justified are the only serial port formats available if the CS4244 is in Master Mode. Serial Port Data Select (Address 09h) 7 Reserved 6.6.1 6 Reserved 5 4 DAC1-4 SOURCE[2:0] 3 2 1 Reserved[2:0] 0 DAC1-4 Data Source Sets which portion of data is to be routed to the DAC1-4 data paths. DAC1-4 SOURCE Data is routed into the DAC1-4 path from: DS900F2 000 Slots 1-4 of the TDM stream on SDIN1 001 Slots 5-8 of the TDM stream on SDIN1 010 Slots 9-12 of the TDM stream on SDIN1 011 Slots 13-16 of the TDM stream on SDIN1 100 Slots 1-4 of the TDM stream on SDIN2 101 Slots 5-8 of the TDM stream on SDIN2 110 Slots 9-12 of the TDM stream on SDIN2 111 Slots 13-16 of the TDM stream on SDIN2 50 CS4244 6.7 ADC Control 1 (Address 0Fh) 7 6 5 4 3 2 1 0 Reserved Reserved VA_SEL ENABLE HPF INV. ADC4 INV. ADC3 INV. ADC2 INV. ADC1 6.7.1 VA Select Scales internal operational voltages appropriately for VA level. Configuring this bit appropriately for the VA voltage level used in the application is imperative to ensure proper operation of the device. VA_SEL 6.7.2 Must be set when VA is: 0 3.3 VDC 1 5 VDC Enable High-pass Filter Enables high-pass filter for the ADC path. ENABLE HPF 6.7.3 High Pass Filter is: 0 Disabled 1 Enabled Inv. ADCx Inverts the polarity of the ADCx signal. INV. ADCx 6.8 ADCx Polarity is: 0 Not Inverted 1 Inverted ADC Control 2 (Address 10h) 7 MUTE ADC4 6.8.1 6 MUTE ADC3 5 MUTE_ADC2 4 MUTE ADC1 3 PDN ADC4 2 PDN ADC3 1 PDN ADC2 0 PDN ADC1 Mute ADCx Mutes the ADCx signal 6.8.2 MUTE ADCx ADC is: 0 Not Muted 1 Muted Power Down ADCx Powers down the ADCx path. DS900F2 PDN ADCx ADC is: 0 Powered Up 1 Powered Down 51 CS4244 6.9 DAC Control 1 (Address 12h) 7 6 DAC1-4 NG 6.9.1 5 4 DAC1-4 DE 3 Reserved 2 Reserved 1 0 Reserved DAC1-4 Noise Gate This sets the bit depth at which the Noise Gate feature should engage for the DAC1-4 path. 6.9.2 DAC1-4 NG[2:0] Noise Gate is set at: [b] 000 Upper 13 Bits (72 dB) 001 Upper 14 Bits (78 dB) 010 Upper 15 Bits (84 dB) 011 Upper 16 Bits (90 dB) 100 Upper 17 Bits (96 dB) 101 Upper 18 Bits (102 dB) 110 Upper 24 Bits (138 dB) 111 Noise Gate Disabled DAC1-4 De-emphasis Enables or disables de-emphasis for the DAC1-4 path. See Section 4.6.3.1 for details. The CS4244 includes on-chip digital de-emphasis for 32, 44.1, and 48 kHz base rates. It is not supported for 96 kHz or for any settings in Double-speed Mode. DAC1-4 DE 6.10 De-emphasis is: 0 Disabled 1 Enabled DAC Control 2 (Address 13h) 7 6 Reserved[2:0] 5 4 Reserved 3 INV. DAC4 2 INV. DAC3 1 INV. DAC2 0 INV. DAC1 6.10.1 Inv. DACx Inverts the polarity of the DACx signal. DS900F2 INV. DACx DACx Polarity is: 0 Not Inverted 1 Inverted 52 CS4244 6.11 DAC Control 3 (Address 14h) 7 Reserved 6.11.1 6 DAC1-4 ATT 5 Reserved 4 Reserved 3 MUTE DAC4 2 MUTE DAC3 1 MUTE DAC2 0 MUTE DAC1 DAC1-4 Attenuation Sets the mode of attenuation used for the DAC1-4 path. DAC1-4 ATT Attenuation events happen: 0 On a soft ramp 1 Immediately Note: 6.11.2 Please see Section 4.6.5 Volume Control for more details regarding the attenuation modes. Mute DACx Mutes the DACx signal. 6.12 MUTE DACx DACx is: 0 Not Muted 1 Muted DAC Control 4 (Address 15h) 7 VQ RAMP 6 5 Reserved[1:0] 4 Reserved 3 PDN DAC4 2 PDN DAC3 1 PDN DAC2 0 PDN DAC1 6.12.1 VQ Ramp Ramps common mode voltage "VQ" down to ground. This bit needs to be set before asserting reset pin. VQ RAMP Effect: 0 VQ is set at nominal level (VA/2) 1 VQ is ramped from nominal level to ground. 6.12.2 Power Down DACx Powers down the DACx path. DS900F2 PDN DACx DACx is: 0 Powered Up 1 Powered Down 53 CS4244 6.13 Volume Mode (Address 16h) 7 6 MUTE DELAY[1:0] 5 4 MIN DELAY[2:0] 3 2 1 MAX DELAY[2:0] 0 6.13.1 Mute Delay Sets the delay between the volume steps during muting and unmuting of a signal when attenuation mode is set to soft ramp. Each step of the ramp is equal to 6.02/64 dB ~= 0.094 dB. Settings are given as "x" times the base period. MUTE DELAY Delay is: 00 1x 01 4x 10 16x 11 64x 6.13.2 Minimum Delay Sets the minimum delay before each volume transition. Settings are given in "x" times the base period. See Section 4.6.5 Volume Control for more details regarding the operation of the volume control. MIN DELAY Minimum Delay is: 000 1x 001 2x 010 4x 011 8x 100 16x 101 32x 110 64x 111 128x 6.13.3 Maximum Delay Sets the maximum delay before the volume transition. Settings are given in "x" times the base period. See Section 4.6.5 Volume Control for more details regarding the operation of the volume control. DS900F2 MAX DELAY Maximum Delay is: 000 1x 001 2x 010 4x 011 8x 100 16x 101 32x 110 64x 111 128x 54 CS4244 6.14 Master and DAC1-4 Volume Control (Address 17h, 18h, 19h, 1Ah, & 1Bh) 7 6 5 4 3 x VOLUME[7:0] 2 1 0 6.14.1 x Volume Control Sets the level of the x Volume Control. Each volume step equals 6.02/16 dB ~= 0.38 dB. See Section 4.6.5.1 on page 40 for the muting behavior of these volume registers. 6.15 x VOLUME x Volume is: [dB] 00000000 +6.02 00001111 +0.38 00010000 0 00010001 -0.38 00011000 -3.01 ... ... 11111110 -89.55 (most total attenuation before mute) 11111111 -89.92 (least total attenuation before unmute) Interrupt Control (Address 1Eh) 7 INT MODE 6 5 INT POL [1:0] 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Reserved 6.15.1 INT MODE Sets the behavior mode of the interrupt registers of the device. In the default configuration, if the interrupt notification registers are read and any error is found to have occurred since the last clearing of that register, the device will automatically set the corresponding mask bit in the appropriate mask register. In the nondefault configuration, mask bits are not set automatically. INT MODE Upon the reading of an error out of the interrupt notification bits, the CS4244 will: 0 Automatically set the corresponding mask bit. 1 Not set the corresponding mask bit. 6.15.2 Interrupt Pin Polarity Sets the output mode of the interrupt pin. DS900F2 INT POL Output mode of the interrupt pin is: 00 Active High 01 Active Low 10 Active Low/Open Drain 11 Reserved 55 CS4244 6.16 Interrupt Mask 1 (Address 1Fh) 7 6 MASK TST MODE ERR MASK SP ERR 5 MASK CLK ERR 4 3 2 1 0 Reserved MASK ADC4 OVFL MASK ADC3 OVFL MASK ADC2 OVFL MASK ADC1 OVFL 6.16.1 Test Mode Error Interrupt Mask Controls whether a Test Mode Error event flags the interrupt pin. A test mode error occurs when an inadvertent IC write places the device in test mode. MASKTSTMOD ERR In the event of a Test Mode Error event, Interrupt Pin will: 0 Be Flagged 1 Not be flagged 6.16.2 Serial Port Error Interrupt Mask Controls whether the interrupt pin if flagged when any of the following parameters are changed without first powering down the device (i.e., setting all Power Down ADCx and Power Down DACx bits): * Serial Port Format: SP FORMAT[1:0] * Speed Mode: SPEED MODE (In slave mode, changing the MCLK/FS ratio without powering down the device, flags this error and the Clocking Error. In master mode, changing MCLK frequency without the device being powered down does not flag this or the Clocking Error since MCLK/FS does not change.) * Master/Slave: MSTR/SLV MASK SP ERR In the event of a Serial Port Error event, Interrupt Pin will: 0 Be Flagged 1 Not be flagged 6.16.3 Clocking Error Interrupt Mask Allows or prevents a Clocking Error event from flagging the interrupt pin. See Section 4.8 for details. MASK CLK ERR In the event of a Clocking Error event, Interrupt Pin will: 0 Be Flagged 1 Not be flagged 6.16.4 ADCx Overflow Interrupt Mask Allows or prevents an ADCx Overflow event from flagging the interrupt pin. MASK ADCx OVFL In the event of an ADCx Overflow event, Interrupt Pin will: DS900F2 0 Be Flagged 1 Not be flagged 56 CS4244 6.17 Interrupt Mask 2 (Address 20h) 7 6 Reserved 5 Reserved Reserved 4 3 2 1 0 Reserved MASK DAC4 CLIP MASK DAC3 CLIP MASK DAC2 CLIP MASK DAC1 CLIP 1 ADC2 OVFL 0 ADC1 OVFL 6.17.1 DACx Clip Interrupt Mask Allows or prevents a DACx Clip event from flagging the interrupt pin. MASK DACx CLIP In the event of a DACx Clip event, Interrupt Pin will: 6.18 0 Be Flagged 1 Not be flagged Interrupt Notification 1 (Address 21h) (Read Only) 7 TST MODE ERR 6 SP ERR 5 CLK ERR 4 Reserved 3 ADC4 OVFL 2 ADC3 OVFL 6.18.1 Test Mode Error A Test Mode Error has occurred since the last clearing of the Interrupt Notification register. TSTMOD ERR Since the last clearing of the Interrupt Notification Register, a Test Mode Error: 0 Has Not Occurred 1 Has Occurred 6.18.2 Serial Port Error A Serial Port Error has occurred since the last clearing of the Interrupt Notification register. SP ERR Since the last clearing of the Interrupt Notification Register, a Serial Port Error: 0 Has Not Occurred 1 Has Occurred 6.18.3 Clocking Error A Clocking Error has occurred since the last clearing of the Interrupt Notification register. CLK ERR Since the last clearing of the Interrupt Notification Register, a Clocking Error: 0 Has Not Occurred 1 Has Occurred 6.18.4 ADCx Overflow An ADCx Overflow has occurred since the last clearing of the Interrupt Notification register. ADCx OVFL DS900F2 Since the last clearing of the Interrupt Notification Register, a ADCx Overflow Error: 0 Has Not Occurred 1 Has Occurred 57 CS4244 6.19 Interrupt Notification 2 (Address 22h) (Read Only) 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved DAC4 CLIP DAC3 CLIP DAC2 CLIP DAC1 CLIP 6.19.1 DACx Clip A DACx Clip has occurred since the last clearing of the Interrupt Notification register. DACx CLIP DS900F2 Since the last clearing of the Interrupt Notification Register, a DACx Clip Error: 0 Has Not Occurred 1 Has Occurred 58 CS4244 7. ADC FILTER PLOTS a sto 0 -10 -10 -20 -20 -30 -30 -40 -40 Amplitude (dB) Amplitude (dB) Stopband Rejection 0 -50 -50 -60 -60 -70 -70 -80 -80 -90 -90 -100 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency (normalized to Fs) 0.7 0.8 0.9 -100 0.4 1 0.42 Figure 32. ADC Stopband Rejection 0.44 0.46 0.48 0.5 0.52 Frequency (normalized to Fs) -1 0.04 -2 0.03 -3 0.02 -4 0.01 Amplitude (dB) Amplitude (dB) 0.05 -5 -0.01 -7 -0.02 -8 -0.03 -9 -0.04 0.48 0.49 0.5 0.51 Frequency (normalized to Fs) 0.52 0.53 0.54 0.55 -0.05 0 0.05 Figure 34. ADC Transition Band (Detail) -0.5 -1 -1 -1.5 -2 -2.5 -2.5 4 6 8 10 Frequency (Hz) 12 14 16 Figure 36. ADC HPF (48 kHz) DS900F2 18 0.35 0.4 0.45 0.5 20 ass te espo se ( s 96 ) -1.5 -2 2 0.2 0.25 0.3 Frequency (normalized to Fs) g -0.5 0 0.15 Figure 35. ADC Passband Ripple 0 -3 0.1 48kHz) 0 Amplitude (dB) Amplitude (dB) High Pass Filter Response (Fs 0.6 0.58 0 -6 0.47 0.56 Passband Ripple Transition Band (Detail) 0.46 0.54 Figure 33. ADC Transition Band 0 -10 0.45 a d -3 0 2 4 6 8 10 Frequency (Hz) 12 14 16 18 20 Figure 37. ADC HPF (96 kHz) 59 CS4244 8. DAC FILTER PLOTS DS900F2 Figure 38. SSM DAC Stopband Rejection Figure 39. SSM DAC Transition Band Figure 40. SSM DAC Transition Band (Detail) Figure 41. SSM DAC Passband Ripple 60 CS4244 DS900F2 Figure 42. DSM DAC Stopband Rejection Figure 43. DSM DAC Transition Band Figure 44. DSM DAC Transition Band (Detail) Figure 45. DSM DAC Passband Ripple 61 CS4244 9. PACKAGE DIMENSIONS 40L QFN (6 6 MM BODY) PACKAGE DRAWING D b 2.00 REF e PIN #1 CORNER 2.00 REF PIN #1 IDENTIFIER 0.500.10 LASER MARKING E2 E A1 L D2 A Figure 46. Package Drawing INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A 0.0315 0.0354 0.0354 0.8 0.85 0.9 1 A1 0 0.0014 0.002 0 0.035 0.05 1 b 0.0078 0.0098 0.011 0.2 0.25 0.3 1,2 D D2 0.2362 BSC 0.1594 E E2 0.1634 4 0.2362 BSC 0.1594 e L 0.1614 6 BSC 0.1614 0.0177 4.2 6 BSC 0.1634 4 0.0197 BSC 0.0118 4.1 1 4.1 1 4.2 0.5 BSC 0.0197 0.3 0.45 1 1 1 0.5 1 JEDEC #: MO-220 Controlling Dimension is Millimeters. Notes: 1. Dimensioning and tolerance per ASME Y4.5M - 1994. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. DS900F2 62 CS4244 10.ORDERING INFORMATION Product CS4244 CDB4244 Description 4 In/4 Out CODEC Package Pb-Free 40-QFN CS4244 Evaluation Board Grade Temp Range Container Order# Rail CS4244-CNZ Commercial 0 to +70C Tape and Reel CS4244-CNZR Rail CS4244-DNZ Automotive -40 to +85C Tape and Reel CS4244-DNZR - - - CDB4244 Yes - 11.REVISION HISTORY Release Changes F1 MAR `12 - Updated the Commercial temperature ranges from -40 to +85C to 0 to +70C and the Automotive temperature ranges from -40 to +105C to -40 to +85C in the following sections: "General Description" on page 1, "Recommended Operating Conditions" on page 9, "Analog Input Characteristics (Automotive Grade)" on page 13, "ADC Digital Filter Characteristics" on page 15, "Analog Output Characteristics (Automotive Grade)" on page 17, and Section 10. Ordering Information. - Updated PSRR specification in the Analog Input Characteristics (Commercial Grade) and Analog Input Characteristics (Automotive Grade) tables. - Removed note about ADC CM bits in the Analog Input Characteristics (Commercial Grade) and Analog Input Characteristics (Automotive Grade) tables. - Removed TA test condition from "ADC Digital Filter Characteristics" on page 15. - Added analog input pins must be externally biased to Section 4.6.2.1. - Changed ADC CM bits to reserved in Section 5 and Section 6.6. - Changed part number for automotive grade in Section 10. Ordering Information from ENZ to DNZ. F2 OCT `14 - Updated dimensions and figure in Section 9. Package Dimensions. (Data sheet change only; no change has been made to the physical device.) Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com. 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