Integrated Circuit Solution Inc. 1
LPSR018-0D 07/06/2001
IS62LV1024L/LL
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
DESCRIPTION
The 1+51 IS62LV1024L and IS62LV1024LL are low power
and low Vcc,131,072-word by 8-bit CMOS static RAMs. They
are fabricated using 1+51's high-performance CMOS technol-
ogy. This highly reliable process coupled with innovative circuit
design techniques, yields higher performance and low power
consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS62LV1024L and IS62LV1024LL are available in 32-pin
8*20mm TSOP-1, 8*13.4mm TSOP-1, 450mil SOP and 48-pin
6*8mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE1
OE
WE
512 X 2048
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
CE2
IS62LV1024L
IS62LV1024LL
128K x 8 LOW POWER and LOW Vcc
CMOS STATIC RAM
FEATURES
Access times of 45, 55, and 70 ns
Low active power: 60 mW (typical)
Low standby power: 15 µW (typical) CMOS
standby
Low data retention voltage: 2V (min.)
Available in Low Power (-L) and
Ultra Low Power (-LL)
Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
TTL compatible inputs and outputs
Single 2.7V to 3.6V power supply
2Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
IS62LV1024L/LL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
32-Pin SOP
PIN DESCRIPTIONS
A0-A16 Address Inputs
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
NC No Connection
Vcc Power
GND Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
PIN CONFIGURATION
32-Pin 8x20mm TSOP-1 and 8x13.4mm TSOP-1
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 2.7V to 3.6V
Industrial 40°C to +85°C 2.7V to 3.6V
48-Pin 6x8mm TF-BGA
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0 A1 CE2 A3 A6 A8
I/O
5
A2 WE A4 A7 I/O
1
I/O
6
NC A5 I/O
2
GND Vcc
Vcc GND
I/O
7
NC NC I/O
3
I/O
8
OE CE1 A16 A15 I/O
4
A9 A10 A11 A12 A13 A14
Integrated Circuit Solution Inc. 3
LPSR018-0D 07/06/2001
IS62LV1024L/LL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND 0.5 to Vcc + 0.5 V
VCC Vcc related to GND 0.3 to +4.6 V
TBIAS Temperature Under Bias 40 to +85 °C
TSTG Storage Temperature 65 to +150 °C
PTPower Dissipation 0.7 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = 1.0 mA 2.2 V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL Input LOW Voltage 0.3 0.4 V
ILI Input Leakage GND ≤ VIN ≤ VCC 1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC 1 1 µA
Notes:
1. VIL = 3.0V for pulse width less than 10 ns.
TRUTH TABLE
Mode WEWE
WEWE
WE CE1CE1
CE1CE1
CE1 CE2 OEOE
OEOE
OE I/O Operation Vcc Current
Not Selected X H X X High-Z ISB, ISB
(Power-down) X X L X High-Z ISB, ISB
Output Disabled H L H H High-Z ICC
Read H L H L DOUT ICC
Write L L H X DIN ICC
4Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
IS62LV1024L/LL
IS62LV1024L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-45L ns -55L ns -70L ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., CE = VIL Com. 40 35 30 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. 45 40 35
ISBTTL Standby Current VCC = Max., Com. 0.3 0.3 0.3 mA
(TTL Inputs) VIN = VIH or VIL, CE1
≥
VIH Ind. 0.4 0.4 0.4
or CE2
≤
VIL, f = 0
ISB CMOS Standby VCC = Max., f = 0 Com. 50 50 50 µA
Current (CMOS Inputs) CE1
≥
VCC  0.2V, Ind. 75 75 75
CE2
≤
0.2V,
or VIN
≥
VCC  0.2V, VIN
≤
0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS62LV1024LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-45LL ns -55LL ns -70LL ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., CE = VIL Com. 40 35 30 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. 45 40 35
ISBTTL Standby Current VCC = Max., Com. 0.2 0.2 0.2 mA
(TTL Inputs) VIN = VIH or VIL, CE1
≥
VIH Ind. 0.3 0.3 0.3
or CE2
≤
VIL, f = 0
ISB CMOS Standby VCC = Max., f = 0 Com. 5 5 5 µA
Current (CMOS Inputs) CE1
≥
VCC  0.2V, Ind. 10 10 10
CE2
≤
0.2V,
or VIN
≥
VCC  0.2V, VIN
≤
0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc. 5
LPSR018-0D 07/06/2001
IS62LV1024L/LL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-45 -55 -70
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 45 55 70 ns
tAA Address Access Time 45 55 70 ns
tOHA Output Hold Time 10 10 10 ns
tACECE1 Access Time 45 55 70 ns
tACE CE2 Access Time 45 55 70 ns
tDOE OE Access Time 20 25 35 ns
tLZOE
 
OE to Low-Z Output 0 5 5 ns
tHZOE
 
OE to High-Z Output 0 15 0 20 0 25 ns
tLZCE
 
CE1 to Low-Z Output 5 7 10 ns
tLZCE
 
CE2 to Low-Z Output 5 7 10 ns
tHZCE
 
CE1 or CE2 to High-Z Output 0 15 0 20 0 25 ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Times 5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1
AC TEST LOADS
Figure 1. Figure 2.
100 pF
Including
jig and
scope
OUTPUT
1 TTL
5 pF
Including
jig and
scope
OUTPUT
1 TTL
6Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
IS62LV1024L/LL
DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
HIGH-Z DATA VALID
t
HZCE
ADDRESS
OE
CE1
CE2
DOUT
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
READ CYCLE NO. 2(1,3)
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
Integrated Circuit Solution Inc. 7
LPSR018-0D 07/06/2001
IS62LV1024L/LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low
Power)
-45 -55 -70
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 45 55 70 ns
tSCECE1 to Write End 35 50 60 ns
tSCE CE2 to Write End 35 50 60 ns
tAW Address Setup Time to Write End 35 50 60 ns
tHA Address Hold from Write End 0 0 0 ns
tSA Address Setup Time 0 0 0 ns
tPWE
"
WE Pulse Width 35 40 55 ns
tSD Data Setup to Write End 25 25 30 ns
tHD Data Hold from Write End 0 0 0 ns
tHZWE
 
WE LOW to High-Z Output 15 20 0 25 ns
tLZWE
 
WE HIGH to Low-Z Output 5 5 5 ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
DATA-IN VALID
DATA UNDEFINED
tWC
tSCE1
tSCE2
tAW
tHA
tPWE(4)
tHZWE
HIGH-Z
tLZWE
tSA
tSD tHD
ADDRESS
CE1
CE2
WE
DOUT
DIN
AC WAVEFORMS
WRITE CYCLE NO. 1 (9-9-
9-9-
9- Controlled)(1,2)
8Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
IS62LV1024L/LL
WRITE CYCLE NO. 2 (+-+-
+-+-
+-, CE2 Controlled)(1,2)
HIGH-Z
DATA UNDEFINED
DATA-IN VALID
t
WC
t
SCE1
t
SA
t
HA
t
SCE2
t
PWE(4)
t
AW
t
HZWE
t
SD
t
HD
t
LZWE
ADDRESS
DIN
CE1
CE2
WE
DOUT
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Max. Unit
VDR Vcc for Data Retention See Data Retention Waveform 2.0 3.6 V
IDR Data Retention Current Vcc = 2.0V, CE1
≥
Vcc  0.2V Com. (-L) 30 µA
Com. (-LL) 5 µA
Ind. (-L) 50 µA
Ind. (-LL) 10 µA
tSDR Data Retention Setup Time See Data Retention Waveform 0 ns
tRDR Recovery Time See Data Retention Waveform tRC ns
DATA RETENTION WAVEFORM (+-+-
+-+-
+- Controlled)
V
CC
CE1 ≥ V
CC
- 0.2V
t
SDR
t
RDR
V
DR
CE1
GND
3.0V
2.2V
Data Retention Mode
Integrated Circuit Solution Inc. 9
LPSR018-0D 07/06/2001
IS62LV1024L/LL
DATA RETENTION WAVEFORM (CE2 Controlled)
V
CC
CE2 ≤ 0.2V
t
SDR
t
RDR
V
DR
0.4V
CE2
GND
3.0V
2.2V
Data Retention Mode
IS62LV1024L
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
45 IS62LV1024L-45Q 450mil SOP
IS62LV1024L-45T 8*20mm TSOP-1
IS62LV1024L-45H 8*13.4mm TSOP-1
IS62LV1024L-45B 6*8mm TF-BGA
55 IS62LV1024L-55Q 450mil SOP
IS62LV1024L-55T 8*20mm TSOP-1
IS62LV1024L-55H 8*13.4mm TSOP-1
IS62LV1024L-55B 6*8mm TF-BGA
70 IS62LV1024L-70Q 450mil SOP
IS62LV1024L-70T 8*20mm TSOP-1
IS62LV1024L-70H 8*13.4mm TSOP-1
IS62LV1024L-70B 6*8mm TF-BGA
IS62LV1024L
ORDERING INFORMATION
Industrial Range: 40°C to +85°C
Speed (ns) Order Part No. Package
45 IS62LV1024L-45QI 450mil SOP
IS62LV1024L-45TI 8*20mm TSOP-1
IS62LV1024L-45HI 8*13.4mm TSOP-1
IS62LV1024L-45BI 6*8mm TF-BGA
55 IS62LV1024L-55QI 450mil SOP
IS62LV1024L-55TI 8*20mm TSOP-1
IS62LV1024L-55HI 8*13.4mm TSOP-1
IS62LV1024L-55BI 6*8mm TF-BGA
70 IS62LV1024L-70QI 450mil SOP
IS62LV1024L-70TI 8*20mm TSOP-1
IS62LV1024L-70HI 8*13.4mm TSOP-1
IS62LV1024L-70BI 6*8mm TF-BGA
10 Integrated Circuit Solution Inc.
LPSR018-0D 07/06/2001
IS62LV1024L/LL
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
IS62LV1024LL
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
45 IS62LV1024LL-45Q 450mil SOP
IS62LV1024LL-45T 8*20mm TSOP-1
IS62LV1024LL-45H 8*13.4mm TSOP-1
IS62LV1024LL-45B 6*8mm TF-BGA
55 IS62LV1024LL-55Q 450mil SOP
IS62LV1024LL-55T 8*20mm TSOP-1
IS62LV1024LL-55H 8*13.4mm TSOP-1
IS62LV1024LL-55B 6*8mm TF-BGA
70 IS62LV1024LL-70Q 450mil SOP
IS62LV1024LL-70T 8*20mm TSOP-1
IS62LV1024LL-70H 8*13.4mm TSOP-1
IS62LV1024LL-70B 6*8mm TF-BGA
IS62LV1024LL
ORDERING INFORMATION
Industrial Range: 40°C to +85°C
Speed (ns) Order Part No. Package
45 IS62LV1024LL-45QI 450mil SOP
IS62LV1024LL-45TI 8*20mm TSOP-1
IS62LV1024LL-45HI 8*13.4mm TSOP-1
IS62LV1024LL-45BI 6*8mm TF-BGA
55 IS62LV1024LL-55QI 450mil SOP
IS62LV1024LL-55TI 8*20mm TSOP-1
IS62LV1024LL-55HI 8*13.4mm TSOP-1
IS62LV1024LL-55BI 6*8mm TF-BGA
70 IS62LV1024LL-70QI 450mil SOP
IS62LV1024LL-70TI 8*20mm TSOP-1
IS62LV1024LL-70HI 8*13.4mm TSOP-1
IS62LV1024LL-70BI 6*8mm TF-BGA