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Rev.3.00, Jul.13.2005, page 1 of 7
HD74LS138
3-Line-to-8-Line Decoders / Demultiplexers REJ03D0434–0300
Rev.3.00
Jul.13.2005
The HD74LS138 decodes one-of-eight line dependent on the conditions at the three binaly select inputs and the three
enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without ex ternal inverters and a 32-line decoder requires only one
inverter. An enable input can be us ed as a data input for demultiplexing applications.
Features
• Ordering Information
Part Name Package Type Package Code
(Previous Code) Package
Abbreviation Taping Abbreviation
(Quantity)
HD74LS138P DILP-16 pin PRDP0016AE-B
(DP-16FV) P -
HD74LS138FPEL SOP-16 pin (JEITA) PRSP0016DH-B
(FP-16DAV) FP EL (2,000 pcs/reel)
HD74LS138RPEL SOP-16 pin (JEDEC) PRSP0016DG-A
(FP-16DNV) RP EL (2,500 pcs/reel)
Note: Please consult the sales office for the above packa ge availability.
Pin Arrangement
(Top view)
V
CC
GND
15
161
2
3
4
5
6
7
14
89
10
11
12
13
A
B
Y
7
Y
6
G
1
G
2A
C
Y
0
Y
5
Y
4
Y
2
Y
1
A
B
C
G
2A
G
2B
G
1
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
G
2B
Y
3
Outputs
Select
Inputs
Outputs
Enable
Inputs
HD74LS138
Rev.3.00, Jul.13.2005, page 2 of 7
Function Table
Inputs
Enable Select Outputs
G1 G2* C B A Y0 Y
1 Y
2 Y
3 Y
4 Y
5 Y
6 Y
7
X H X X X H H H H H H H H
L X X X X H H H H H H H H
H L L L L L H H H H H H H
H L L L H H L H H H H H H
H L L H L H H L H H H H H
H L L H H H H H L H H H H
H L H L L H H H H L H H H
H L H L H H H H H H L H H
H L H H L H H H H H H L H
H L H H H H H H H H H H L
H ; high level, L ; low level, X ; irrelevant
* ; G2 = G2A + G2B
Block Diagram
Select
Inputs
Enable
Inputs
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
G1
G2A
G2B
A
B
C
Data
Outputs
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage VCC 7 V
Input voltage VIN 7 V
Power dissipation PT 400 mW
Storage temperature Tstg –65 to +150 °C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Symbol Min Typ Max Unit
Supply voltage VCC 4.75 5.00 5.25 V
IOH — — –400 µA
Output current IOL — — 8 mA
Operating temperature Topr –20 25 75 °C
HD74LS138
Rev.3.00, Jul.13.2005, page 3 of 7
Electrical Characteristics
(Ta = –20 to +75 °C)
Item Symbol min. typ.* max. Unit Condition
VIH 2.0 — — V
Input voltage VIL — — 0.8 V
VOH 2.7 — — V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
— — 0.4 IOL = 4 mA
Output voltage VOL — — 0.5 V IOL = 8 mA VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
IIH — — 20 µA VCC = 5.25 V, VI = 2.7 V
IIL — — –0.4 mA VCC = 5.25 V, VI = 0.4 V
Input current II — — 0.1 mA VCC = 5.25 V, VI = 7 V
Short-circuit output
current IOS –20 — –100 mA VCC = 5.25 V
Supply current ICC — 6.3 10 mA VCC = 5.25 V, Outputs enabled and open
Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA
Note: * VCC = 5 V, Ta = 25°C
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item Symbol Inputs Output
Levels
of delay min. typ. max. Unit Condition
tPLH — 13 20 ns
tPHL 2 — 27 41 ns
tPLH — 18 27 ns
tPLH
Binary
select
A, B, C Y 3 — 26 39 ns
tPLH — 12 18 ns
tPHL Enable
G2A, G2B 2 — 21 32 ns
tPLH — 17 26 ns
Propagation
delay time
tPLH Enable
G1
Y 3 — 25 38 ns
CL = 15 pF,
RL = 2 kΩ
HD74LS138
Rev.3.00, Jul.13.2005, page 4 of 7
Testing Method
Test Circuit
4.5V
Y
0
Load circuit 1
Output
V
CC
R
L
C
L
Input
P.G.
Z
out
= 50Ω
See Testing Table
A
B
C
G
1
G
2A
G
2B
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
1
Same as Load Circuit 1.
Output
Same as Load Circuit 1.
Output
Same as Load Circuit 1.
Output
Same as Load Circuit 1.
Output
Same as Load Circuit 1.
Output
Same as Load Circuit 1.
Output
Same as Load Circuit 1.
Output
Notes: 1. CL includes probe and jig capacitan ce.
2. All diodes are 1S2074(H).
Waveform
t
PLH
t
PHL
V
OH
V
OL
0 V
3 V
V
OH
V
OL
t
PHL
t
PLH
10%
90%
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
10%
90%
Input
In phase Output
Out of phase Output
t
TLH
t
THL
Note: Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50%
HD74LS138
Rev.3.00, Jul.13.2005, page 5 of 7
Relation Between Input and Output to Levels of Delay
Outputs
Inputs 2 levels of delay 3 levels of delay
A Y0 Y
2 Y
4 Y
6 Y
1 Y
3 Y
5 Y
7
B Y0 Y
1 Y
4 Y
5 Y
2 Y
3 Y
6 Y
7
C Y0 Y
1 Y
2 Y
3 Y
4 Y
5 Y
6 Y
7
G1 Y
0 to Y7
G2A, G2B Y
0 to Y7
HD74LS138
Rev.3.00, Jul.13.2005, page 6 of 7
Package Dimensions
7.62
DP-16FV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
19.2
6.3
5.06
MASS[Typ.]
1.05g
A
Z
b
D
E
A
b
c
θ
e
L
1
1
p
3
e
0.51
0.56
1.30
0.19 0.25 0.31
2.29 2.54 2.79
0
°
15
°
PRDP0016AE-BP-DIP16-6.3x19.2-2.54
20.32
7.4
0.40 0.48
1.12
2.54
1
p
1
3
1 8
16 9
e
b
A
LA
Z
e c
E
D
b
0.89
θ
( Ni/Pd/Au plating )
0.80
0.15
1.27
7.50 8.00
0.400.34
p
A
1
10.5
FP-16DAV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
2.20
0.900.700.50
5.50
0.200.100.00
0.46
0.250.200.15
7.80
8
°
0
°
0.12
1.15
10.06
0.24g
MASS[Typ.]
1
E
1
1
2
L
Z
H
y
x
θ
c
b
A
E
D
b
c
e
L
A
P-SOP16-5.5x10.06-1.27 PRSP0016DH-B
*1
*2
E
81
16 9
xM
p
*3
y
F
Index mark
b
D
E
H
Z
A
Terminal cross section
( Ni/Pd/Au plating )
p
c
b
1
1
Detail F
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
e
HD74LS138
Rev.3.00, Jul.13.2005, page 7 of 7
0.635
0.15
1.27
5.80 6.20
0.400.34
p
A
1
10.30
FP-16DNV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
1.75
1.270.600.40
3.95
0.250.140.10
0.46
0.250.200.15
6.10
8
°
0
°
0.25
1.08
9.90
0.15g
MASS[Typ.]
1
E
1
1
2
L
Z
H
y
x
θ
c
b
A
E
D
b
c
e
e
L
A
P-SOP16-3.95x9.9-1.27 PRSP0016DG-A
Index mark
E
1
y
xM
p
*3
*2
*1
F
8
916
E
H
D
A
Zb
Terminal cross section
( Ni/Pd/Au plating )
p
b
c
Detail F
1
1
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
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