FEATURES
DWide Supply Range: 7 V to 22 V
DGamma Correction Channels: 10
DIntegrated VCOM Buffer
DExcellent Output Current Drive:
− Gamma Channels:
> 30 mA at 0.5 V Swing to Rails(1)
− VCOM:
> 100 mA typ at 2 V Swing to Rails(1)
DLarge Capacitive Load Drive Capability
DRail-to-Rail Output
DPowerPAD Package
DLow-Power/Channel: < 500 µA
DHigh ESD Rating: 8 kV HBM, 2 kV CDM,
300 V MM
DSpecified for −25°C to +85°C
(1) See Typical Characteristic curves for details.
BUF11705
VDD
VCOM
Source Driver
Gamma 1
Gamma 2
Gamma 3
Gamma (n −2)
Gamma (n −1)
Gamma (n)
DESCRIPTION
The BUF11705 is a multi-channel buffer targeted
towards gamma correction in high-resolution LCD
panels. It i s pin-compatible with the existing BUF11702
and BUF11704 and operates at higher supply voltages
up to 22 V (24 V absolute max). The higher supply
voltage enables faster response times and brighter
images in large-screen LCD panels. This is especially
important in LCD TV applications.
The BUF11705 offers 10 gamma channels. For
additional s p a c e a n d c o s t s a v i n g s , a V COM channel with
> 100 mA drive capability is integrated into the
BUF11705.
The BUF11705 is available in the TSSOP-28,
PowerPAD package for dramatically increased power
dissipation capability. This allows, a large number of
channels to be handled safely in one package.
A flow-through pinout has been adopted to allow
simple PCB routing and maintain cost-effectiveness. All
inputs and outputs of the BUF11705 incorporate
internal ESD protection circuits that prevent functional
failures at voltages up to 8 kV (HBM), 2 kV (CDM), and
300 V (MM).
PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
BUF11705
SBOS349 − DECEMBER 2005
22-V Supply, 10+1 Channel
Gamma Correction Buffer
         
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Copyright 2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over o p e r a t i n g f ree-air temperature range unless otherwise noted(1)
PARAMETERS BUF11705 UNIT
Supply voltage, VDD(2) 24 V
Input voltage range, VI±VDD
Continuous total power dissipation See dissipation rating table
Operating free-air temperature range, TA−25 to +85 °C
Maximum junction temperature, TJ+125 °C
Storage temperature range, TSTG −65 to +150 °C
Lead temperature 1.6mm (1/16 inch) from case for 10s +260 °C
ESD rating:
Human body model (HBM) 8 kV
Charged-device model (CDM) 2 kV
Machine model (MM) 300 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD PACKAGE MARKING
BUF11705 TSSOP-28 BUF11705
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet or see the
TI website at www.ti.com.
DISSIPATION RATING TABLE
PACKAGE TYPE PACKAGE
DESIGNATOR θJC(1)
(°C/W)
qJA(1)
(°C/W) TA ≤ 25°C
POWER RATING
TSSOP-28 PWP (28) 0.72 27.9 3.58 W
(1) PowerPAD attached to PCB, 0 lfm airflow, and 76mm x 76mm copper area.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Supply voltage, VDD 7 22 V
Operating free-air temperature, TA−25 +85 °C
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ELECTRICAL CHARACTERISTICS: BUF11705
Over operating free-air temperature range, VDD = 18 V, T A = +25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
Gamma buffers
+25°C −1 20
VIO
Input of fset voltage
Gamma buffers
VI = 9V
Full range(1) 20
mV
V
IO
Input of fset voltage
VCOM
V
I
= 9V
+25°C −1 30
mV
V
COM Full range(1) 30
IIB
Input bias current
VI = VDD/2
+25°C 1
pA
I
IB
Input bias current
V
I
= V
DD
/2
Full range(1) 200
pA
PSRR
Power-Supply Rejection Ratio
VDD = 4.5 V to 22 V
+25°C 62 80
dB
PSRR
Power-Supply Rejection Ratio
V
DD
= 4.5 V to 22 V
Full range(1) 60
dB
Buffer gain VI = 5 V +25°C 0.9995 V/V
BW_3dB 3dB bandwidth
Gamma buffers
VCOM buffer CL = 100 pF, RL = 2 kΩ+25°C1
0.6 MHz
SR Slew rate Gamma buffers
VCOM buffer CL = 100 pF, RL = 2 kΩ
VIN = 2 V to 16 V +25°C1.6
4.6 V/µs
Crosstalk VIPP = 6 V, f = 1 kHz +25°C 85 dB
IDD
Supply current
ALL
VO = VDD/2
25°C 5 9.0
mA
I
DD
Supply current
ALL
VO = VDD/2
No Load Full range 9.0
mA
Buf fers 1-5 1 VDD
Common-mode input range Buf fers 6-10 +25°CGND VDD − 1 V
Common-mode input range
VCOM buffer
+25 C
1 VDD
V
VCOM buffer sinking
IO = 1 mA to 100 mA,
+25°C 1 5
V
COM
buffer sinking
IO = 1 mA to 100 mA,
VIN = 2 V Full range 5
VCOM b uffer sourc-
IO = −1 mA to −100 mA
+25°C 1 5
Load regulation
VCOM b uffer sourc-
ing
IO = −1 mA to −100 mA
VIN = 16 V Full range 5
mV/mA
Load regulation
Buf fers 1-10 sinking
IO = 1 mA to 10 mA
+25°C 1 5
mV/mA
Buf fers 1-10 sinking
IO = 1 mA to 10 mA
VIN = 1 V Full range 5
Buffers 1-10 sourc-
IO = −1 mA to −10 mA
+25°C 1 5
Buffers 1-10 sourc-
ing
IO = −1 mA to −10 mA
VIN = 17 V Full range 5
VOH1-5 Buffers 1-5 VIN = 18 V
ISOURCE = 10 mA +25°C 17.85 17.9 V
VOH6-10
High-level output
voltage
Buf fers 6-10
VIN = 17 V
ISINK = 10 mA
+25°C
17 17.15
V
V
OH6-10
voltage
Buf fers 6-10
VIN = 17 V
ISOURCE = 10 mA
+25
°
C
16.85 17
V
VOL1-5
Buf fers 1-5
VIN = 1 V
ISINK = 10 mA
+25°C
1.0 1.15
V
V
OL1-5 Low-level output
voltage
Buf fers 1-5
VIN = 1 V
ISOURCE = 10 mA
+25
°
C
0.85 1.0
V
VOL6-10
voltage
Buf fers 6-10 VIN = 0 V
ISINK = 10 mA +25°C 0 0.15 V
VOHCOM
High-level output
voltage
VCOM buffer
VIN = 16 V
ISINK = 100 mA
+25°C
16 16.15
V
V
OHCOM
High-level output
voltage
V
COM
buffer
VIN = 16 V
ISOURCE = 100 mA
+25
°
C
15.85 16
V
VOLCOM
Low-level output
voltage
VCOM buffer
VIN = 2 V
ISINK = 100 mA
+25°C
2 2.15
V
V
OLCOM
Low-level output
voltage
V
COM
buffer
VIN = 2 V
ISOURCE = 100 mA
+25
°
C
1.85 2
V
(1) Full range is −25°C to +85°C.
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4
EQUIVALENT SCHEMATICS OF INPUTS AND OUTPUTS
Previous
Stage
Previous
Stage
Inverting
Input Buffer
Output
VS
GND
OUTPUT STAGE OF ALL BUFFERS
Buffer
Input Buffer
Output
Next Stage
Next Stage
VS
GND
Internal to BUF11705
INPUT STAGE OF BUFFERS
BUF11705: 1 to 5 and VCOM
Buffer
Input Buffer
Output
Next Stage
Next Stage
VS
GND
Internal to BUF11705
INPUT STAGE OF BUFFERS
BUF11705:6to10
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
NC
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUTCOM
GND
VDD
NC
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
IN10
INCOM
GND
BUF11705
TSSOP−28
PowerPAD
NC = No Internal Connection
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TYPICAL CHARACTERISTICS
Over operating free-air temperature range, unless otherwise noted.
DC CURVES
Figure 1
INPUT OFFSET VOLTAGE vs INPUT VOLTAGE
20
15
10
5
0
−5
−10
−15
−20
VOS −Input Offset Voltage −mV
VIN −Input Voltage −V
0 3 6 9 12 15 18
VS=18V
Channels 1−5
Figure 2
INPUT OFFSET VOLTAGE vs INPUT VOLTAGE
20
15
10
5
0
−5
−10
−15
−20
VOS −Input Offset Voltage −mV
VIN −Input Voltage −V
0 3 6 9 12 15 18
VS=18V
Channels 6−10
Figure 3
INPUT OFFSET VOLTAGE vs INPUT VOLTAGE
20
15
10
5
0
−5
−10
−15
−20
VOS −Input Offset Voltage −mV
VIN −Input Voltage −V
0 3 6 9 12 15 18
Channels VCOM
VS=18V
Figure 4
INPUT BIAS CURRENT vs FREE−AIR TEMPERATURE
250
200
150
100
50
0
IIB −Input Bias Current −pA
TA−Free−Air Temperature −_C
0 102030405060708085
Figure 5
OUTPUT VOLTAGE vs OUTPUT CURRENT
18
16
14
12
10
8
6
4
2
0
VO−Output Voltage −V
IO−Output Current −mA
0 102030405060708090100
VDD =18V
Channels 1−5
+25_C
−10_C
−10_C
+85_C
+25_C
Figure 6
HIGH−LEVEL OUTPUT VOLTAGE vs
HIGH−LEVEL OUTPUT CURRENT
18.0
17.8
17.6
17.4
17.2
17.0
VOH −High−Level Output Voltage −V
IOH −High−Level Output Current −mA
0 1020304050515253545
VDD =18V
Channels 1−5
TA=+25
_C
TA=+85
_C
TA=−10_C
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TYPICAL CHARACTERISTICS (continued)
Over operating free-air temperature range, unless otherwise noted.
DC CURVES (continued)
Figure 7
OUTPUT VOLTAGE vs OUTPUT CURRENT
18
16
14
12
10
8
6
4
2
0
VO−Output Voltage −V
IO−Output Current −mA
0 102030405060708090100
VSUPPLY =18V
Channels 6−10
−10_C
+25_C
+85_C
Figure 8
LOW−LEVEL OUTPUT VOLTAGE vs
LOW−LEVEL OUTPUT CURRENT (Detailed View)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VOL −Low−Level Output Voltage −V
IOL −Low−Level Output Current −mA
0 1020304050
Channels 6−10
+25_C
−10_C
+85_C
Figure 9
OUTPUT VOLTAGE vs OUTPUT CURRENT
18
16
14
12
10
8
6
4
2
0
VO−Output Voltage −V
IO−Output Current −mA
0 25 50 75 100 125 150 175 200 225 250
VSUPPLY =18V
VCOM Buffer −10_C
+25_C+85_C
Figure 10
SUPPLY CURRENT vs SUPPLY VOLTAGE
6
5
4
3
2
1
0
Supply Current −mA
Supply Voltage −V
02468101214161820
Figure 11
SUPPLY CURRENT vs FREE−AIR TEMPERATURE
6
5
4
3
2
1
0
IQ−Supply Current −mA
TA−Free−Air Temperature −_C
−50 −25 0 25 50 75 100 125
VS=18V
Figure 12
INPUT BIAS CURRENT vs INPUT VOLTAGE
5
4
3
2
1
0
−1
−2
−3
−4
−5
IB−Input Bias Current −pA
VIN −Input Voltage −V
0481216202 6 10 14 18
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TYPICAL CHARACTERISTICS (continued)
Over operating free-air temperature range, unless otherwise noted.
AC CURVES
Figure 13
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
80
70
60
50
40
30
20
10
0
PSRR −Power−Supply Rejection Ratio −dB
f−Frequency −Hz
10 100 1 k 10 k 100 k 1 M 10 M
VCOM Buffer
Gamma Channels
VDD =10V
RL=2k
CL=100pF
Figure 14
CROSSTALK vs FREQUENCY
0
20
40
60
80
100
120
140
CMRR −Common−Mode Rejection Ratio −dB
f−Frequency −Hz
10 100 1 k 10 k 100 k 1 M
VSUPPLY =10V
VIN =1V
PP
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TYPICAL CHARACTERISTICS (continued)
Over operating free-air temperature range, unless otherwise noted.
SMALL- AND LARGE-SIGNAL WAVEFORM CURVES
Figure 15
SMALL−SIGNAL WAVEFORM
t−Time −500 ns/div
50 mV/div
RLOAD =2k
Ω
CLOAD =100pF
Channels 1−5
Figure 16
SMALL−SIGNAL WAVEFORM
t−Time −500 ns/div
50 mV/div
RLOAD =2k
Ω
CLOAD =100pF
Channels 6−10
Figure 17
SMALL−SIGNAL WAVEFORM
VCOM BUFFER
t−Time −500 ns/div
50 mV/div
RLOAD =2k
Ω
CLOAD = 100 pF
VCOM Buffer
Figure 18
LARGE−SIGNAL WAVEFORM
t−Time −4µs/div
3V/div
RLOAD =2k
Ω
CLOAD = 100 pF
VDD =15V
Channels 1−5
Figure 19
LARGE−SIGNAL WAVEFORM
t−Time −4µs/div
3V/div
RLOAD =2k
Ω
CLOAD = 100 pF
VDD =15V
Channels 6−10
Figure 20
LARGE−SIGNAL WAVEFORMVCOM BUFFER
t−Time −4µs/div
3V/div
RLOAD =2k
Ω
CLOAD = 100 pF
VCOM Buffer
VDD =15V
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APPLICATION INFORMATION
The requirements on the number of gamma correction
channels vary greatly from panel to panel. Therefore,
the BUF11705 series of gamma correction buffer o ffers
different channel combinations using 10 gamma
channels plus one VCOM channel. The VCOM channel
can be used to drive the VCOM node on the LCD panel.
Gamma correction voltages are often generated using
a simple resistor ladder, as shown in Figure 21. The
BUF11705 buffers the various nodes on the gamma
correction resistor ladder. The low output impedance of
the BUF11705 forces the external gamma correction
voltage on the respective reference node of the LCD
source driver. Figure 21 shows an example of the
BUF11705 in a typical block diagram driving an LCD
source driver with 10-channel gamma correction
reference inputs.
BUF11705
VDD
RS(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
(1)
(1)
(1)
VCOM (1) Optional resistor increases stability.
(2) Optional capacitor.
Source Driver
Gamma 1
Gamma 2
Gamma 3
Gamma 8
Gamma 9
Gamma 10
Figure 21. LCD Source Driver Typical Block Diagram
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ESD RATINGS
The BUF11705 has excellent ESD performance: 8 kV
HBM; 2 kV CDM; and 300 V MM. These ESD ratings
allow for increased manufacturability, fewer production
failures, and higher reliability.
INPUT VOLTAGE RANGE GAMMA BUFFERS
Figure 22 shows a typical gamma correction curve with
10 gamma correction reference points (GMA1 through
GMA10). As can be seen from this curve, the voltage
requirements for each buffer vary greatly. The swing
capability of the input stages of the various buffers is
carefully matched to the application. Buffers 1 through
5 have input stages that include VDD, but will only swing
within 1 V to GND. Buf fers 1 through 5 have only a single
NMOS input stage. Buffers 6 through 10 have only a
single PMOS input stage. The input range of the PMOS
input stage includes GND.
VDD1
GMA1
GMA2
GMA3
GMA4
GMA5
GMA6
GMA7
GMA8
GMA9
GMA10
VSS1 01020
Input Data (Hex)
30 40
Figure 22. Gamma Correction Curve
OUTPUT VOLTAG E SWING GAMMA BUFFERS
The output stages have been designed to match the
characteristic of the input stage. This means that the
output stage of buffers 1 through 5 swing very close to
VDD (typically, VCC − 100 mV at 10 mA). The ability of
buffers 1 through 5 to swing to GND is limited. Buffers
6 through 10 swing closer to GND than VDD. Buffers 6
through 10 are designed to swing very close to GND;
typically, GND + 100 mV at a 10 mA load current. See
the Typical Characteristics for more details. This
approach significantly reduces the silicon area and
overall cost of the whole solution. However, due to this
architecture, the correct buffer must be connected to
the correct gamma correction voltage. Connect buffer
1 to the gamma voltage closest to VDD, and buffers 2
through 5 t o the sequentially voltages. Buffer 10 should
be connected to the gamma correction voltage closest
to GND (or the negative rail), and buf fers 9 through 6 to
the sequentially higher voltages.
COMMON BUFFER (VCOM)
The common buffer output of the BUF11705 has a
greater output drive capability than the gamma buffers
in order to meet the heavier current demands of driving
the common node of the LCD panel. The common
buffer output was also designed to drive heavier
capacitive lo a d s . E x c e l l e n t o u t p u t s w i n g i s p o s s i b l e w i t h
high currents ( > 100 mA), as shown in Figure 23.
OUTPUT VOLTAGE vs OUTPUT CURRENT
Output Voltage −V
Output Current −mA
0 50 100 150 200 25025 75 125 175 225
18
17
16
15
14
13
12
11
7
6
5
4
3
2
1
0
VDD =18V
TA=25
_C
Figure 23. VCOM Output Drive Capability
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CAPACITI VE LOAD DRIVE
The BUF11705 has been designed to sink/source large
dc currents. Its output stage has been designed to
deliver output current transients with little disturbance
of the output voltage. However, there are times when
very fast current pulses are required. Therefore, in LCD
source driver buffer applications, it is quite normal for
capacitors to be placed at the outputs of the reference
buffers. These capacitors improve the transient load
regulation and will typically have values of 100pF or
more. The BUF11705 gamma buffers were designed to
drive capacitances in excess of 100 pF. The output is
able to swing within 150 mV of the rails on
10 mA of output current, as shown in Figure 24.
OUTPUT VOLTAGE vs OUTPUT CURRENT
Output Voltage −V
Output Current −mA
0 10203040505 15253545
18.0
17.8
17.6
17.4
17.2
17.0
1.0
0.8
0.6
0.4
0.2
0
Channels 1−5
Channels 6−10
VDD =18V
TA=25
_C
Figure 24. Gamma Buffer Drive Capability
APPLICATIONS WITH >10 GAMMA CHANNELS
When a greater number of gamma correction channels
are required, two or more BUF11705 devices can be
used in parallel, as shown in Figure 25. This capability
provides a cost-effective way of creating more refer-
ence voltages over the use of quad-channel op amps or
buffers. The suggested configuration in Figure 25
simplifies layout. The various different channel versions
provide a high degree of flexibility and also minimize
total cost and space.
BUF11705
BUF11705
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
GMA11
12
13
14
15
16
OUT17 17
OUT18 18
OUT19 19
OUT20 GMA20
OUT7
OUT8
OUT9
OUT10
GMA1
2
3
4
5
6
7
8
9
GMA10
Figure 25. Creating > 10 Gamma Voltage
Channels
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COMPLETE LCD SOLUTION FROM TI
In addition to the BUF11705 line of gamma correction
buffers, T I o f fers a complete set of ICs for the LCD panel
market, including various power-supply solutions, and
audio power solutions. Figure 26 shows the total IC
solution from TI.
2.7Vto5V
3.3 V
nn
26 V
−14 V
15 V
TPS651xx
LCD
Supply
TPA300x
Audio
Speaker
Driver
Logic and
Timing
Controller
High−Resolution
TFT−LCS Panel
Source Driver
Gamma Correction
Reference
BUF11705
VCOM
Gate Driver
Figure 26. TI LCD Solution
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13
GENERAL PowerPAD DESIGN
CONSIDERATIONS
The BUF11705 is available in the thermally-enhanced
PowerPAD package. This package is constructed using
a downset leadframe upon which the die is mounted, as
shown in Figure 27(a) and (b). This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package; see Figure 27(c).
Due to this thermal pad having direct thermal contact
with the die, excellent thermal performance is achieved
by providing a good thermal path away from the thermal
pad.
The PowerPAD package allows for both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper
area, heat can be conducted away from the package
into either a ground plane or other heat-dissipating
device. Soldering the PowerPAD to the PCB is
always required, even with applications that have
low power dissipation. This provides the necessary
thermal and mechanical connection between the lead
frame die pad and the PCB.
The PowerPAD must be connected to the most
negative supply voltage of the device.
1. Prepare the PCB with a top-side etch pattern. There
should b e etching for the leads as well as etch for the
thermal pad.
2. Place recommended holes in the area of the thermal
pad. Ideal thermal land size and thermal via patterns
can be seen in technical brief, SLMA002 PowerPAD
Thermally-Enhanced Package, available for down-
load at www.ti.com. These holes should be 13 mils
in diameter . Keep them small, so that solder wicking
through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the
BUF11705 IC. These additional vias may be larger
than the 13-mil diameter vias directly under the
thermal pad. They can be larger because they are
not in the thermal pad area to be soldered; so that,
wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane,
do not use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing the
heat transfer during soldering operations. Web
connections make the soldering of vias easier. In
this application, however, low thermal resistance is
desired for the most efficient heat transfer.
Therefore, the holes under the BUF11705
PowerPAD package should make their connection
to the internal ground plane with a complete
connection around the entire circumference of the
plated-through hole.
6. The top-side solder mask should leave the terminals
of the package and the thermal pad area with its ten
holes exposed. The bottom-side solder mask
should cover the holes of the thermal pad area. This
prevents solder from being pulled away from the
thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
8. With these preparatory steps in place, the
BUF11705 IC is simply placed in position and run
through the solder reflow operation as any standard
surface-mount component. This preparation results
in a properly installed part.
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
The thermal pad is electrically isolated from all terminals in the package.
Figure 27. Views of Thermally-Enhanced DGN Package
"#$$%&'
SBOS349 − DECEMBER 2005
www.ti.com
14
For a given qJA, the maximum power dissipation is
shown in Figure 28, and is calculated by the following
formula:
PD+ǒTMAX *TA
qJA Ǔ
Where:
PD = maximum power dissipation (W)
TMAX = absolute maximum junction temperature (125°C)
TA = free-ambient air temperature (°C)
qJA = qJC + qCA
qJC = thermal coef ficient from junction to case (°C/W)
qCA = thermal coefficient from case-to-ambient air (°C/W)
Maximum Power Dissipation −W
8
7
6
5
4
3
2
1
0
−40 −20 0 20
TA−Free−Air Temperature −_C
40 60 80 100
TSSOP−28
Dissipation with PowerPAD
soldered down.
Figure 28. Views of Thermally-Enhanced DGN Package
www.ti.com
PowerPAD is a trademark of Texas Instruments
PWP (R−PDSO−G28)
THERMAL INFORMATION
()*+  *)(+ 
PPTD032
Exposed Thermal Pad
15
14
28
1
6,46
5,35
2,35
1,60
This PowerPADt package incorporates an exposed thermal pad that is designed to be attached directly to an
external heatsink. When the thermal pad is soldered direct ly to the printed circuit board (PCB), the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a
ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from
the integrated circuit (IC).
The exposed thermal pad dimensions for this package are shown in the following illustration.
For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities,
refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
and Application Brief, PowerPAD Made Easy , Texas Instruments Literature No. SLMA004. Both documents are
available at www.ti.com.
Exposed Thermal Pad Dimensions
NOTE: All linear dimensions are in millimeters
Top View
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