2White Paper
2310A–03/01
Summary The first section of this paper describes the development of limitations in I/O connectivity
and logic reusability in Complex Programmable Logic Devices (CPLDs) over their 20-
year history. The second section describes the architectural enhancements (Logic Dou-
bling) in Atmel’s ATF15xx Families of CPLDs and how they address these limitations.
The third section describes several reference designs that illustrate both the limitations
and how Logic Doubling overcomes them and in each case compares Atmel’s ATF15xx
Families performance to that of typical industry-standard CPLDs.
The programmable logic designer is encouraged to download these reference designs
and Atmel’s design and fitter software, repeat these experiments and replicate results.
Using these examples and tools, the PLD designer can then apply Logic Doubling tech-
niques to new product designs, obtaining the benefits of more features in a smaller, and
possibly less expensive chip, or spare logic resources for future revisions and reduced
risk of PCB re-spin.
Logic Doubling
Background
The first PAL devices in the late 1970’s offered a single layer of simple logic: Inputs
were routed to an AND/OR block and then to the outputs. PALs had a single, rising-
edge CLK pin and a single register OE pin. If more layers of logic were needed, more
pins were required.
Although extremely limited by current standards, PALs had two advantages: all I/O sig-
nals were available to all logic cells, and relatively little logic was wasted. Each new
generation of programmable logic improved on the many other PAL shortcomings but
not these two.
Over the first decade, PALs evolved into “CMOS” SPLDs, and the 16V8, 20V8 and
22V10 became standard parts. These devices remained 100 percent connected
between the I/O pins and their logic cells. In the following decade, as the logic cells grew
in complexity, adding Product Term clocks, multiple OE terms, etc., more of the logic in
each cell was potentially left unused in the finished designs. The metric “usable gates”
(generally a fraction of about half of the total number of physical gates on the chip) came
into use as better way to describe the amount of logic typically accessible for use in a
finished design.
However, as the number of macrocells in a single CPLD is increased, the required sig-
nal routing area and loading on these nodes also increases according to the square law.
The resulting increased die size and speed penalty is simply too great, and so in larger
devices all nodes cannot be fed into all macrocells.
As 44-pin CPLDs emerged, new layers of hierarchy were added to their structures. Mac-
rocells were grouped into blocks usually of 16. Output enable functions were added, but
often at the logic block level of hierarchy, thus having limited flexibility.
In defining their CPLD architecture, most manufacturers decided to sacrifice connectiv-
ity for minimized die size and maximized speed. Fan-in to the blocks became limited,
logic utilization took another drop and routing flexibility, both within the macrocells and to
the I/O pads, was compromised. The term “pin-locking” was introduced to describe the
ability to preassign pins. Lack of pin-locking became a CPLD issue and was debated
hotly by leading competitors.
Over the last decade, the CPLD version of Moore’s law drove logic density higher. How-
ever, routing density, while improving, did not keep pace. The extra fuses and
interconnect required to make the increasing amount of unusable logic more accessible
would simply take up too much area on the chip, and rather than drive the already high
cost of CPLDs even higher, the trend toward inaccessible logic in each macrocell
continued.