Contents
Intel® MAX® 10 FPGA Device Datasheet..................................................................................................................................... 3
Electrical Characteristics...................................................................................................................................................... 3
Operating Conditions..................................................................................................................................................4
Switching Characteristics....................................................................................................................................................25
Core Performance Specifications.................................................................................................................................26
Periphery Performance Specifications..........................................................................................................................35
Configuration Specifications................................................................................................................................................57
JTAG Timing Parameters........................................................................................................................................... 58
Remote System Upgrade Circuitry Timing Specifications................................................................................................ 59
User Watchdog Internal Circuitry Timing Specifications..................................................................................................59
Uncompressed Raw Binary File (.rbf) Sizes.................................................................................................................. 59
Internal Configuration Time....................................................................................................................................... 60
Internal Configuration Timing Parameter..................................................................................................................... 61
I/O Timing....................................................................................................................................................................... 61
Programmable IOE Delay................................................................................................................................................... 62
Programmable IOE Delay On Row Pins........................................................................................................................ 62
Programmable IOE Delay for Column Pins....................................................................................................................63
Glossary.......................................................................................................................................................................... 64
Document Revision History for the Intel MAX 10 FPGA Device Datasheet...................................................................................66
Contents
Intel® MAX® 10 FPGA Device Datasheet
2
Intel® MAX® 10 FPGA Device Datasheet
This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for
Intel MAX® 10 devices.
Table 1. Intel MAX 10 Device Grades and Speed Grades Supported
Device Grade Speed Grade Supported
Commercial • –C7
• –C8 (slowest)
Industrial • –I6 (fastest)
• –I7
Automotive • –A6
• –A7
Note: The –I6 and –A6 speed grades of the Intel MAX 10 FPGA devices are not available by default in the Intel Quartus® Prime
software. Contact your local Intel sales representatives for support.
Related Information
Device Ordering Information, Intel MAX 10 FPGA Device Overview
Provides more information about the densities and packages of devices in the Intel MAX 10.
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Intel MAX 10 devices.
M10-DATASHEET | 2018.06.29
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no
responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by
Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
Operating Conditions
Intel MAX 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and
reliability of the Intel MAX 10 devices, you must consider the operating requirements described in this section.
Absolute Maximum Ratings
This section defines the maximum operating conditions for Intel MAX 10 devices. The values are based on experiments
conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the
device is not implied for these conditions.
Caution: Conditions outside the range listed in the absolute maximum ratings tables may cause permanent damage to the device.
Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the
device.
Single Supply Devices Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings for Intel MAX 10 Single Supply Devices
Symbol Parameter Min Max Unit
VCC_ONE Supply voltage for core and periphery through on-die voltage
regulator
–0.5 3.9 V
VCCIO Supply voltage for input and output buffers –0.5 3.9 V
VCCA Supply voltage for phase-locked loop (PLL) regulator and analog-to-
digital converter (ADC) block (analog)
–0.5 3.9 V
Dual Supply Devices Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings for Intel MAX 10 Dual Supply Devices
Symbol Parameter Min Max Unit
VCC Supply voltage for core and periphery –0.5 1.63 V
VCCIO Supply voltage for input and output buffers –0.5 3.9 V
VCCA Supply voltage for PLL regulator (analog) –0.5 3.41 V
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
4
Symbol Parameter Min Max Unit
VCCD_PLL Supply voltage for PLL regulator (digital) –0.5 1.63 V
VCCA_ADC Supply voltage for ADC analog block –0.5 3.41 V
VCCINT Supply voltage for ADC digital block –0.5 1.63 V
Absolute Maximum Ratings
Table 4. Absolute Maximum Ratings for Intel MAX 10 Devices
Symbol Parameter Min Max Unit
VIDC input voltage –0.5 4.12 V
IOUT DC output current per pin –25 25 mA
TSTG Storage temperature –65 150 °C
TJOperating junction temperature –40 125 °C
Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal
is equivalent to 100% duty cycle.
For example, a signal that overshoots to 4.17 V can only be at 4.17 V for ~11.7% over the lifetime of the device; for a device
lifetime of 11.4 years, this amounts to 1.33 years.
Table 5. Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame for Intel MAX 10 Devices
Condition (V) Overshoot Duration as % of High Time Unit
4.12 100.0 %
4.17 11.7 %
4.22 7.1 %
4.27 4.3 %
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
5
Condition (V) Overshoot Duration as % of High Time Unit
4.32 2.6 %
4.37 1.6 %
4.42 1.0 %
4.47 0.6 %
4.52 0.3 %
4.57 0.2 %
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for Intel MAX 10 devices. The tables list the
steady-state voltage values expected from Intel MAX 10 devices. Power supply ramps must all be strictly monotonic, without
plateaus.
Single Supply Devices Power Supplies Recommended Operating Conditions
Table 6. Power Supplies Recommended Operating Conditions for Intel MAX 10 Single Supply Devices
Symbol Parameter Condition Min Typ Max Unit
VCC_ONE(1)Supply voltage for core and periphery through on-
die voltage regulator
— 2.85/3.135 3.0/3.3 3.15/3.465 V
VCCIO(2) Supply voltage for input and output buffers 3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3 3.15 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
1.5 V 1.425 1.5 1.575 V
continued...
(1) VCCA must be connected to VCC_ONE through a filter.
(2) VCCIO for all I/O banks must be powered up during user mode because VCCIO I/O banks are used for the ADC and I/O functionalities.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
6
Symbol Parameter Condition Min Typ Max Unit
1.35 V 1.2825 1.35 1.4175 V
1.2 V 1.14 1.2 1.26 V
VCCA (1)Supply voltage for PLL regulator and ADC block
(analog)
— 2.85/3.135 3.0/3.3 3.15/3.465 V
Dual Supply Devices Power Supplies Recommended Operating Conditions
Table 7. Power Supplies Recommended Operating Conditions for Intel MAX 10 Dual Supply Devices
Symbol Parameter Condition Min Typ Max Unit
VCC Supply voltage for core and periphery — 1.15 1.2 1.25 V
VCCIO (3) Supply voltage for input and output buffers 3.3 V 3.135 3.3 3.465 V
3.0 V 2.85 3 3.15 V
2.5 V 2.375 2.5 2.625 V
1.8 V 1.71 1.8 1.89 V
1.5 V 1.425 1.5 1.575 V
1.35 V 1.2825 1.35 1.4175 V
1.2 V 1.14 1.2 1.26 V
VCCA(4) Supply voltage for PLL regulator (analog) — 2.375 2.5 2.625 V
VCCD_PLL(5) Supply voltage for PLL regulator (digital) — 1.15 1.2 1.25 V
VCCA_ADC Supply voltage for ADC analog block — 2.375 2.5 2.625 V
VCCINT Supply voltage for ADC digital block — 1.15 1.2 1.25 V
(3) VCCIO for all I/O banks must be powered up during user mode because VCCIO I/O banks are used for the ADC and I/O functionalities.
(4) All VCCA pins must be powered to 2.5 V (even when PLLs are not used), and must be powered up and powered down at the same
time.
(5) VCCD_PLL must always be connected to VCC through a decoupling capacitor and ferrite bead.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
7
Recommended Operating Conditions
Table 8. Recommended Operating Conditions for Intel MAX 10 Devices
Symbol Parameter Condition Min Max Unit
VIDC input voltage — –0.5 3.6 V
VOOutput voltage for I/O pins — 0 VCCIO V
TJOperating junction temperature Commercial 0 85 °C
Industrial –40(6)100 °C
Automotive –40(6)125 °C
tRAMP Power supply ramp time — (7) 10 ms
IDiode Magnitude of DC current across PCI* clamp diode when
enabled
— — 10 mA
Programming/Erasure Specifications
Table 9. Programming/Erasure Specifications for Intel MAX 10 Devices
This table shows the programming cycles and data retention duration of the user flash memory (UFM) and configuration flash memory (CFM) blocks.
For more information about data retention duration with 10,000 programming cycles for automotive temperature devices, contact your Intel quality
representative.
Erase and reprogram cycles (E/P) (8) (Cycles/
page)
Temperature (°C) Data retention duration (Years)
10,000 85 20
10,000 100 10
(6) –40°C is only applicable to Start of Test, when the device is powered-on. The device does not stay at the minimum junction
temperature for a long time.
(7) There is no absolute minimum value for the ramp time requirement. Intel characterized the minimum ramp time at 200 μs.
(8) The number of E/P cycles applies to the smallest possible flash block that can be erased or programmed in each Intel MAX 10 device.
Each Intel MAX 10 device has multiple flash pages per device.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
8
DC Characteristics
Supply Current and Power Consumption
Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel Quartus
Prime Power Analyzer feature.
Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a
magnitude estimate of the device power because these currents vary greatly with the usage of the resources.
The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you
complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated
signal activities that, when combined with detailed circuit models, yield very accurate power estimates.
Related Information
•Early Power Estimator User Guide
Provides more information about power estimation tools.
•Power Analysis chapter, Intel Quartus Prime Handbook
Provides more information about power estimation tools.
I/O Pin Leakage Current
The values in the table are specified for normal device operation. The values vary during device power-up. This applies for all
VCCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, 1.35, and 1.2 V).
10 µA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be the observed
when the diode is on.
Input channel leakage of ADC I/O pins due to hot socket is up to maximum of 1.8 mA. The input channel leakage occurs when
the ADC IP core is enabled or disabled. This is applicable to all Intel MAX 10 devices with ADC IP core, which are 10M04,
10M08, 10M16, 10M25, 10M40, and 10M50 devices. The ADC I/O pins are in Bank 1A.
Table 10. I/O Pin Leakage Current for Intel MAX 10 Devices
Symbol Parameter Condition Min Max Unit
IIInput pin leakage current VI = 0 V to VCCIOMAX –10 10 µA
IOZ Tristated I/O pin leakage current VO = 0 V to VCCIOMAX –10 10 µA
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
9
Table 11. ADC_VREF Pin Leakage Current for Intel MAX 10 Devices
Symbol Parameter Condition Min Max Unit
Iadc_vref ADC_VREF pin leakage current Single supply mode — 10 µA
Dual supply mode — 20 µA
Bus Hold Parameters
Bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed.
Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode.
Table 12. Bus Hold Parameters for Intel MAX 10 Devices
Parameter Condition VCCIO (V) Unit
1.2 1.5 1.8 2.5 3.0 3.3
Min Max Min Max Min Max Min Max Min Max Min Max
Bus-hold low, sustaining
current
VIN > VIL
(maximum)
8 — 12 — 30 — 50 — 70 — 70 — µA
Bus-hold high, sustaining
current
VIN < VIH
(minimum)
–8 — –12 — –30 — –50 — –70 — –70 — µA
Bus-hold low, overdrive
current
0 V < VIN <
VCCIO
— 125 — 175 — 200 — 300 — 500 — 500 µA
Bus-hold high, overdrive
current
0 V < VIN <
VCCIO
— –125 — –175 — –200 — –300 — –500 — –500 µA
Bus-hold trip point — 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
10
Series OCT without Calibration Specifications
Table 13. Series OCT without Calibration Specifications for Intel MAX 10 Devices
This table shows the variation of on-chip termination (OCT) without calibration across process, voltage, and temperature (PVT).
Description VCCIO (V) Resistance Tolerance Unit
–C7, –I6, –I7, –A6, –A7 –C8
Series OCT without calibration 3.00 ±35 ±30 %
2.50 ±35 ±30 %
1.80 ±40 ±35 %
1.50 ±40 ±40 %
1.35 ±40 ±50 %
1.20 ±45 ±60 %
Series OCT with Calibration at Device Power-Up Specifications
Table 14. Series OCT with Calibration at Device Power-Up Specifications for Intel MAX 10 Devices
OCT calibration is automatically performed at device power-up for OCT enabled I/Os.
Description VCCIO (V) Calibration Accuracy Unit
Series OCT with calibration at device power-up 3.00 ±12 %
2.50 ±12 %
1.80 ±12 %
1.50 ±12 %
1.35 ±12 %
1.20 ±12 %
OCT Variation after Calibration at Device Power-Up
The OCT resistance may vary with the variation of temperature and voltage after calibration at device power-up.
Use the following table and equation to determine the final OCT resistance considering the variations after calibration at
device power-up.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
11
Table 15. OCT Variation after Calibration at Device Power-Up for Intel MAX 10 Devices
This table lists the change percentage of the OCT resistance with voltage and temperature.
Description Nominal Voltage dR/dT (%/°C) dR/dV (%/mV)
OCT variation after calibration at device power-up 3.00 0.25 –0.027
2.50 0.245 –0.04
1.80 0.242 –0.079
1.50 0.235 –0.125
1.35 0.229 –0.16
1.20 0.197 –0.208
Figure 1. Equation for OCT Resistance after Calibration at Device Power-Up
For
For
The definitions for equation are as follows:
• T1 is the initial temperature.
• T2 is the final temperature.
• MF is multiplication factor.
• Rinitial is initial resistance.
• Rfinal is final resistance.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
12
• Subscript x refers to both V and T.
• ∆RV is variation of resistance with voltage.
• ∆RT is variation of resistance with temperature.
• dR/dT is the change percentage of resistance with temperature after calibration at device power-up.
• dR/dV is the change percentage of resistance with voltage after calibration at device power-up.
• V1 is the initial voltage.
• V2 is final voltage.
The following figure shows the example to calculate the change of 50 Ω I/O impedance from 25°C at 3.0 V to 85°C at 3.15 V.
Figure 2. Example for OCT Resistance Calculation after Calibration at Device Power-Up
B
1
B
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
13
Pin Capacitance
Table 16. Pin Capacitance for Intel MAX 10 Devices
Symbol Parameter Maximum Unit
CIOB Input capacitance on bottom I/O pins 8 pF
CIOLRT Input capacitance on left/right/top I/O pins 7 pF
CLVDSB Input capacitance on bottom I/O pins with dedicated LVDS output (9) 8 pF
CADCL Input capacitance on left I/O pins with ADC input (10) 9 pF
CVREFLRT Input capacitance on left/right/top dual purpose VREF pin when used as VREF or user
I/O pin (11)
48 pF
CVREFB Input capacitance on bottom dual purpose VREF pin when used as VREF or user I/O pin 50 pF
CCLKB Input capacitance on bottom dual purpose clock input pins (12)7 pF
CCLKLRT Input capacitance on left/right/top dual purpose clock input pins (12)6 pF
Internal Weak Pull-Up Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up.
(9) Dedicated LVDS output buffer is only available at bottom I/O banks.
(10) ADC pins are only available at left I/O banks.
(11) When VREF pin is used as regular input or output, Fmax performance is reduced due to higher pin capacitance. Using the VREF pin
capacitance specification from device datasheet, perform SI analysis on your board setup to determine the Fmax of your system.
(12) 10M40 and 10M50 devices have dual purpose clock input pins at top/bottom I/O banks.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
14
Table 17. Internal Weak Pull-Up Resistor for Intel MAX 10 Devices
Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
Symbol Parameter Condition Min Typ Max Unit
R_PU Value of I/O pin (dedicated and dual-purpose)
pull-up resistor before and during configuration,
as well as user mode if the programmable pull-up
resistor option is enabled
VCCIO = 3.3 V ± 5% 7 12 34 kΩ
VCCIO = 3.0 V ± 5% 8 13 37 kΩ
VCCIO = 2.5 V ± 5% 10 15 46 kΩ
VCCIO = 1.8 V ± 5% 16 25 75 kΩ
VCCIO = 1.5 V ± 5% 20 36 106 kΩ
VCCIO = 1.2 V ± 5% 33 82 179 kΩ
Hot-Socketing Specifications
Table 18. Hot-Socketing Specifications for Intel MAX 10 Devices
Symbol Parameter Maximum
IIOPIN(DC) DC current per I/O pin 300 µA
IIOPIN(AC) AC current per I/O pin 8 mA (13)
Hysteresis Specifications for Schmitt Trigger Input
Intel MAX 10 devices support Schmitt trigger input on all I/O pins. A Schmitt trigger feature introduces hysteresis to the input
signal for improved noise immunity, especially for signal with slow edge rate.
(13) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is I/O pin capacitance and dv/dt
is the slew rate.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
15
Table 19. Hysteresis Specifications for Schmitt Trigger Input for Intel MAX 10 Devices
Symbol Parameter Condition Minimum Unit
VHYS Hysteresis for Schmitt trigger input VCCIO = 3.3 V 180 mV
VCCIO = 2.5 V 150 mV
VCCIO = 1.8 V 120 mV
VCCIO = 1.5 V 110 mV
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
16
Figure 3. LVTTL/LVCMOS Input Standard Voltage Diagram
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
17
Figure 4. Schmitt Trigger Input Standard Voltage Diagram
VHYS
I/O Standards Specifications
Tables in this section list input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and
IOL) for various I/O standards supported by Intel MAX 10 devices.
For minimum voltage values, use the minimum VCCIO values. For maximum voltage values, use the maximum VCCIO values.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
18
Single-Ended I/O Standards Specifications
Table 20. Single-Ended I/O Standards Specifications for Intel MAX 10 Devices
To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specification (4 mA), you
should set the current strength settings to 4 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the datasheet.
I/O Standard VCCIO (V) VIL (V) VIH (V) VOL (V) VOH (V) IOL (mA) IOH (mA)
Min Typ Max Min Max Min Max Max Min
3.3 V LVTTL 3.135 3.3 3.465 –0.3 0.8 1.7 3.6 0.45 2.4 4 –4
3.3 V LVCMOS 3.135 3.3 3.465 –0.3 0.8 1.7 3.6 0.2 VCCIO – 0.2 2 –2
3.0 V LVTTL 2.85 3 3.15 –0.3 0.8 1.7 VCCIO
+ 0.3
0.45 2.4 4 –4
3.0 V LVCMOS 2.85 3 3.15 –0.3 0.8 1.7 VCCIO
+ 0.3
0.2 VCCIO – 0.2 0.1 –0.1
2.5 V LVTTL and
LVCMOS
2.375 2.5 2.625 –0.3 0.7 1.7 VCCIO
+ 0.3
0.4 2 1 –1
1.8 V LVTTL and
LVCMOS
1.71 1.8 1.89 –0.3 0.35 ×
VCCIO
0.65 ×
VCCIO
2.25 0.45 VCCIO –
0.45
2 –2
1.5 V LVCMOS 1.425 1.5 1.575 –0.3 0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO
+ 0.3
0.25 ×
VCCIO
0.75 ×
VCCIO
2 –2
1.2 V LVCMOS 1.14 1.2 1.26 –0.3 0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO
+ 0.3
0.25 ×
VCCIO
0.75 ×
VCCIO
2 –2
3.3 V Schmitt Trigger 3.135 3.3 3.465 –0.3 0.8 1.7 VCCIO
+ 0.3
— — — —
2.5 V Schmitt Trigger 2.375 2.5 2.625 –0.3 0.7 1.7 VCCIO
+ 0.3
— — — —
1.8 V Schmitt Trigger 1.71 1.8 1.89 –0.3 0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO
+ 0.3
— — — —
1.5 V Schmitt Trigger 1.425 1.5 1.575 –0.3 0.35 ×
VCCIO
0.65 ×
VCCIO
VCCIO
+ 0.3
— — — —
3.0 V PCI 2.85 3 3.15 — 0.3 ×
VCCIO
0.5 ×
VCCIO
VCCIO
+ 0.3
0.1 ×
VCCIO
0.9 ×
VCCIO
1.5 –0.5
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
19
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Table 21. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel MAX 10 Devices
I/O Standard VCCIO (V) VREF (V) VTT (V) (14)
Min Typ Max Min Typ Max Min Typ Max
SSTL-2 Class I, II 2.375 2.5 2.625 1.19 1.25 1.31 VREF – 0.04 VREF VREF + 0.04
SSTL-18 Class I, II 1.7 1.8 1.9 0.833 0.9 0.969 VREF – 0.04 VREF VREF + 0.04
SSTL-15 Class I, II 1.425 1.5 1.575 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO
SSTL-135 Class I, II 1.283 1.35 1.45 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO
HSTL-18 Class I, II 1.71 1.8 1.89 0.85 0.9 0.95 0.85 0.9 0.95
HSTL-15 Class I, II 1.425 1.5 1.575 0.71 0.75 0.79 0.71 0.75 0.79
HSTL-12 Class I, II 1.14 1.2 1.26 0.48 × VCCIO
(15)
0.5 × VCCIO (15)0.52 × VCCIO
(15)
— 0.5 × VCCIO —
0.47 × VCCIO
(16)
0.5 × VCCIO (16)0.53 × VCCIO
(16)
HSUL-12 1.14 1.2 1.3 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO — — —
(14) VTT of transmitting device must track VREF of the receiving device.
(15) Value shown refers to DC input reference voltage, VREF(DC).
(16) Value shown refers to AC input reference voltage, VREF(AC).
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
20
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Table 22. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel MAX 10 Devices
To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL-15 Class I specification (8 mA), you
should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and IOH specifications in the datasheet.
I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL (mA) IOH (mA)
Min Max Min Max Min Max Min Max Max Min
SSTL-2 Class I — VREF –
0.18
VREF
+ 0.18
— — VREF –
0.31
VREF
+ 0.31
— VTT – 0.57 VTT + 0.57 8.1 –8.1
SSTL-2 Class II — VREF –
0.18
VREF
+ 0.18
— — VREF –
0.31
VREF
+ 0.31
— VTT – 0.76 VTT + 0.76 16.4 –16.4
SSTL-18 Class I — VREF –
0.125
VREF
+ 0.125
— — VREF –
0.25
VREF
+ 0.25
— VTT –
0.475
VTT
+ 0.475
6.7 –6.7
SSTL-18 Class II — VREF –
0.125
VREF
+ 0.125
— — VREF –
0.25
VREF
+ 0.25
— 0.28 VCCIO –
0.28
13.4 –13.4
SSTL-15 Class I — VREF – 0.1 VREF + 0.1 — — VREF –
0.175
VREF
+ 0.175
— 0.2 ×
VCCIO
0.8 ×
VCCIO
8 –8
SSTL-15 Class II — VREF – 0.1 VREF + 0.1 — — VREF –
0.175
VREF
+ 0.175
— 0.2 ×
VCCIO
0.8 ×
VCCIO
16 –16
SSTL-135 — VREF –
0.09
VREF
+ 0.09
— — VREF –
0.16
VREF
+ 0.16
— 0.2 ×
VCCIO
0.8 ×
VCCIO
— —
HSTL-18 Class I — VREF – 0.1 VREF + 0.1 — — VREF – 0.2 VREF + 0.2 — 0.4 VCCIO –
0.4
8 –8
HSTL-18 Class II — VREF – 0.1 VREF + 0.1 — — VREF – 0.2 VREF + 0.2 — 0.4 VCCIO –
0.4
16 –16
HSTL-15 Class I — VREF – 0.1 VREF + 0.1 — — VREF – 0.2 VREF + 0.2 — 0.4 VCCIO –
0.4
8 –8
HSTL-15 Class II — VREF – 0.1 VREF + 0.1 — — VREF – 0.2 VREF + 0.2 — 0.4 VCCIO –
0.4
16 –16
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
21
I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL (mA) IOH (mA)
Min Max Min Max Min Max Min Max Max Min
HSTL-12 Class I –0.15 VREF –
0.08
VREF
+ 0.08
VCCIO
+ 0.15
–0.24 VREF –
0.15
VREF
+ 0.15
VCCIO
+ 0.24
0.25 ×
VCCIO
0.75 ×
VCCIO
8 –8
HSTL-12 Class II –0.15 VREF –
0.08
VREF
+ 0.08
VCCIO
+ 0.15
–0.24 VREF –
0.15
VREF
+ 0.15
VCCIO
+ 0.24
0.25 ×
VCCIO
0.75 ×
VCCIO
14 –14
HSUL-12 — VREF –
0.13
VREF
+ 0.13
— — VREF –
0.22
VREF
+ 0.22
— 0.1 ×
VCCIO
0.9 ×
VCCIO
— —
Differential SSTL I/O Standards Specifications
Differential SSTL requires a VREF input.
Table 23. Differential SSTL I/O Standards Specifications for Intel MAX 10 Devices
I/O Standard VCCIO (V) VSwing(DC) (V) VX(AC) (V) VSwing(AC) (V)
Min Typ Max Min Max(17) Min Typ Max Min Max
SSTL-2 Class I, II 2.375 2.5 2.625 0.36 VCCIO VCCIO/2 –
0.2
— VCCIO/
2+ 0.2
0.7 VCCIO
SSTL-18 Class I, II 1.7 1.8 1.9 0.25 VCCIO VCCIO/2 –
0.175
— VCCIO/
2+ 0.175
0.5 VCCIO
SSTL-15 Class I, II 1.425 1.5 1.575 0.2 — VCCIO/2 –
0.15
— VCCIO/2
+ 0.15
2(VIH(AC) –
VREF)
2(VIL(AC) –
VREF)
SSTL-135 1.283 1.35 1.45 0.18 — VREF –
0.135
0.5 × VCCIO VREF
+ 0.135
2(VIH(AC) –
VREF)
2(VIL(AC) –
VREF)
Differential HSTL and HSUL I/O Standards Specifications
Differential HSTL requires a VREF input.
(17) The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended
limits (VIH(DC) and VIL(DC)).
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
22
Table 24. Differential HSTL and HSUL I/O Standards Specifications for Intel MAX 10 Devices
I/O Standard VCCIO (V) VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) VDIF(AC)
(V)
Min Typ Max Min Max Min Typ Max Min Typ Max Min
HSTL-18 Class I, II 1.71 1.8 1.89 0.2 — 0.85 — 0.95 0.85 — 0.95 0.4
HSTL-15 Class I, II 1.425 1.5 1.575 0.2 — 0.71 — 0.79 0.71 — 0.79 0.4
HSTL-12 Class I, II 1.14 1.2 1.26 0.16 VCCIO 0.48 ×
VCCIO
0.5 ×
VCCIO
0.52 ×
VCCIO
0.48 ×
VCCIO
0.5 ×
VCCIO
0.52 ×
VCCIO
0.3
HSUL-12 1.14 1.2 1.3 0.26 — 0.5 ×
VCCIO –
0.12
0.5 ×
VCCIO
0.5 ×
VCCIO
+ 0.12
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
0.44
Differential I/O Standards Specifications
Table 25. Differential I/O Standards Specifications for Intel MAX 10 Devices
I/O Standard VCCIO (V) VID (mV) VICM (V) (18) VOD (mV) (19)(20) VOS (V) (19)
Min Typ Max Min Max Min Condition Max Min Typ Max Min Typ Max
LVPECL (21) 2.375 2.5 2.625 100 — 0.05 DMAX ≤ 500 Mbps 1.8 — — — — — —
0.55 500 Mbps ≤ DMAX ≤
700 Mbps
1.8
1.05 DMAX > 700 Mbps 1.55
LVDS 2.375 2.5 2.625 100 — 0.05 DMAX ≤ 500 Mbps 1.8 247 — 600 1.125 1.25 1.375
0.55 500 Mbps ≤ DMAX ≤
700 Mbps
1.8
continued...
(18) VIN range: 0 V ≤ VIN ≤ 1.85 V.
(19) RL range: 90 ≤ RL ≤ 110 Ω.
(20) Low VOD setting is only supported for RSDS standard.
(21) LVPECL input standard is only supported at clock input. Output standard is not supported.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
23
I/O Standard VCCIO (V) VID (mV) VICM (V) (18) VOD (mV) (19)(20) VOS (V) (19)
Min Typ Max Min Max Min Condition Max Min Typ Max Min Typ Max
1.05 DMAX > 700 Mbps 1.55
BLVDS (22) 2.375 2.5 2.625 100 — — — — — — — — — —
mini-LVDS (23)2.375 2.5 2.625 — — — — — 300 — 600 1 1.2 1.4
RSDS (23)2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.5
PPDS (Row I/Os)
(23)
2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.4
TMDS(24) 2.375 2.5 2.625 100 — 0.05 DMAX ≤ 500 Mbps 1.8 — — — — — —
0.55 500 Mbps ≤ DMAX ≤
700 Mbps
1.8
1.05 DMAX > 700 Mbps 1.55
Sub-LVDS (25) 1.71 1.8 1.89 100 — 0.55 — 1.25 (26)0.8 0.9 1
SLVS 2.375 2.5 2.625 100 — 0.05 — 1.1 (26) (27)
continued...
(18) VIN range: 0 V ≤ VIN ≤ 1.85 V.
(19) RL range: 90 ≤ RL ≤ 110 Ω.
(20) Low VOD setting is only supported for RSDS standard.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
24
I/O Standard VCCIO (V) VID (mV) VICM (V) (18) VOD (mV) (19)(20) VOS (V) (19)
Min Typ Max Min Max Min Condition Max Min Typ Max Min Typ Max
HiSpi 2.375 2.5 2.625 100 — 0.05 DMAX ≤ 500 Mbps 1.8 — — — — — —
0.55 500 Mbps ≤ DMAX ≤
700 Mbps
1.8
1.05 DMAX > 700 Mbps 1.55
Related Information
Intel MAX 10 LVDS SERDES I/O Standards Support, Intel MAX 10 High-Speed LVDS I/O User Guide
Provides the list of I/O standards supported in single supply and dual supply devices.
Switching Characteristics
This section provides the performance characteristics of Intel MAX 10 core and periphery blocks.
(18) VIN range: 0 V ≤ VIN ≤ 1.85 V.
(19) RL range: 90 ≤ RL ≤ 110 Ω.
(20) Low VOD setting is only supported for RSDS standard.
(22) No fixed VIN , VOD , and VOS specifications for Bus LVDS (BLVDS). They are dependent on the system topology.
(23) Mini-LVDS, RSDS, and Point-to-Point Differential Signaling (PPDS) standards are only supported at the output pins for Intel MAX 10
devices.
(24) Supported with requirement of an external level shift
(25) Sub-LVDS input buffer is using 2.5 V differential buffer.
(26) Differential output depends on the values of the external termination resistors.
(27) Differential output offset voltage depends on the values of the external termination resistors.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
25
Core Performance Specifications
Clock Tree Specifications
Table 26. Clock Tree Specifications for Intel MAX 10 Devices
Device Performance Unit
–I6 –A6, –C7 –I7 –A7 –C8
10M02 450 416 416 382 402 MHz
10M04 450 416 416 382 402 MHz
10M08 450 416 416 382 402 MHz
10M16 450 416 416 382 402 MHz
10M25 450 416 416 382 402 MHz
10M40 450 416 416 382 402 MHz
10M50 450 416 416 382 402 MHz
PLL Specifications
Table 27. PLL Specifications for Intel MAX 10 Devices
VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead.
Symbol Parameter Condition Min Typ Max Unit
fIN (28)Input clock frequency — 5 — 472.5 MHz
fINPFD Phase frequency detector (PFD) input frequency — 5 — 325 MHz
continued...
(28) This parameter is limited in the Intel Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different
for each I/O standard.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
26
Symbol Parameter Condition Min Typ Max Unit
fVCO (29) PLL internal voltage-controlled oscillator (VCO)
operating range
— 600 — 1300 MHz
fINDUTY Input clock duty cycle — 40 — 60 %
tINJITTER_CCJ (30) Input clock cycle-to-cycle jitter FINPFD ≥ 100 MHz — — 0.15 UI
FINPFD < 100 MHz — — ±750 ps
fOUT_EXT (28)PLL output frequency for external clock output — — — 472.5 MHz
fOUT PLL output frequency to global clock –6 speed grade — — 472.5 MHz
–7 speed grade — — 450 MHz
–8 speed grade — — 402.5 MHz
tOUTDUTY Duty cycle for external clock output Duty cycle set to 50% 45 50 55 %
tLOCK Time required to lock from end of device
configuration
— — — 1 ms
tDLOCK Time required to lock dynamically After switchover, reconfiguring
any non-post-scale counters or
delays, or when areset is
deasserted
— — 1 ms
tOUTJITTER_PERIOD_IO
(31)
Regular I/O period jitter FOUT ≥ 100 MHz — — 650 ps
FOUT < 100 MHz — — 75 mUI
tOUTJITTER_CCJ_IO (31)Regular I/O cycle-to-cycle jitter FOUT ≥ 100 MHz — — 650 ps
FOUT < 100 MHz — — 75 mUI
continued...
(29) The VCO frequency reported by the Intel Quartus Prime software in the PLL summary section of the compilation report takes into
consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower
than the fVCO specification.
(30) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source,
which is less than 200 ps.
(31) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification
applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
27
Symbol Parameter Condition Min Typ Max Unit
tPLL_PSERR Accuracy of PLL phase shift — — — ±50 ps
tARESET Minimum pulse width on areset signal. — 10 — — ns
tCONFIGPLL Time required to reconfigure scan chains for
PLLs
— — 3.5 (32) —SCANCLK
cycles
fSCANCLK scanclk frequency — — — 100 MHz
Table 28. PLL Specifications for Intel MAX 10 Single Supply Devices
For V36 package, the PLL specification is based on single supply devices.
Symbol Parameter Condition Max Unit
tOUTJITTER_PERIOD_DEDCLK (31)
Dedicated clock output period jitter FOUT ≥ 100 MHz 660 ps
FOUT < 100 MHz 66 mUI
tOUTJITTER_CCJ_DEDCLK (31) Dedicated clock output cycle-to-cycle jitter FOUT ≥ 100 MHz 660 ps
FOUT < 100 MHz 66 mUI
Table 29. PLL Specifications for Intel MAX 10 Dual Supply Devices
Symbol Parameter Condition Max Unit
tOUTJITTER_PERIOD_DEDCLK (31)Dedicated clock output period jitter FOUT ≥ 100 MHz 300 ps
FOUT < 100 MHz 30 mUI
tOUTJITTER_CCJ_DEDCLK (31)Dedicated clock output cycle-to-cycle jitter FOUT ≥ 100 MHz 300 ps
FOUT < 100 MHz 30 mUI
(32) With 100 MHz scanclk frequency.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
28
Embedded Multiplier Specifications
Table 30. Embedded Multiplier Specifications for Intel MAX 10 Devices
Mode Number of Multipliers Power Supply Mode Performance Unit
–I6 –A6, –C7, –I7,
–A7
–C8
9 × 9-bit multiplier 1 Single supply mode 198 183 160 MHz
Dual supply mode 310 260 210 MHz
18 × 18-bit multiplier 1 Single supply mode 198 183 160 MHz
Dual supply mode 265 240 190 MHz
Memory Block Performance Specifications
Table 31. Memory Block Performance Specifications for Intel MAX 10 Devices
Memory Mode Resources Used Power Supply Mode Performance Unit
LEs M9K
Memory
–I6 –A6, –C7, –I7,
–A7
–C8
M9K Block FIFO 256 × 36 47 1 Single supply mode 232 219 204 MHz
Dual supply mode 330 300 250 MHz
Single-port 256 × 36 0 1 Single supply mode 232 219 204 MHz
Dual supply mode 330 300 250 MHz
Simple dual-port 256 × 36
CLK 0 1 Single supply mode 232 219 204 MHz
Dual supply mode 330 300 250 MHz
True dual port 512 × 18
single CLK 0 1 Single supply mode 232 219 204 MHz
Dual supply mode 330 300 250 MHz
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
29
Internal Oscillator Specifications
Table 32. Internal Oscillator Frequencies for Intel MAX 10 Devices
You can access to the internal oscillator frequencies in this table. The duty cycle of internal oscillator is approximately 45%–55%.
Device Frequency Unit
Minimum Typical Maximum
10M02 55 82 116 MHz
10M04
10M08
10M16
10M25
10M40 35 52 77 MHz
10M50
UFM Performance Specifications
Table 33. UFM Performance Specifications for Intel MAX 10 Devices
Block Mode Interface Device Frequency Unit
Minimum Maximum
UFM Avalon®-MM slave Parallel (33) 10M02 (34)3.43 7.25 MHz
10M04, 10M08, 10M16, 10M25, 10M40,
10M50
5 116 MHz
Serial (34)10M02, 10M04, 10M08, 10M16, 10M25 3.43 7.25 MHz
10M40, 10M50 2.18 4.81 MHz
(33) Clock source is derived from user, except for 10M02 device.
(34) Clock source is derived from 1/16 of the frequency of the internal oscillator.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
30
ADC Performance Specifications
Single Supply Devices ADC Performance Specifications
Table 34. ADC Performance Specifications for Intel MAX 10 Single Supply Devices
Parameter Symbol Condition Min Typ Max Unit
ADC resolution — — — — 12 bits
ADC supply voltage VCC_ONE — 2.85 3.0/3.3 3.465 V
External reference voltage VREF — VCC_ONE –
0.5
— VCC_ONE V
Sampling rate FSAccumulative sampling rate — — 1 MSPS
Operating junction temperature range TJ— –40 25 125 °C
Analog input voltage VIN Prescalar disabled 0 — VREF V
Prescalar enabled (35) 0 — 3.6 V
Input resistance RIN — — (36)— —
Input capacitance CIN — — (36)— —
DC Accuracy Offset error and drift Eoffset Prescalar disabled –0.2 — 0.2 %FS
Prescalar enabled –0.5 — 0.5 %FS
Gain error and drift Egain Prescalar disabled –0.5 — 0.5 %FS
Prescalar enabled –0.75 — 0.75 %FS
Differential non linearity DNL External VREF, no missing
code
–0.9 — 0.9 LSB
Internal VREF, no missing
code
–1 — 1.7 LSB
continued...
(35) Prescalar function divides the analog input voltage by half. The analog input handles up to 3.6 V for the Intel MAX 10 single supply
devices.
(36) Download the SPICE models for simulation.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
31
Parameter Symbol Condition Min Typ Max Unit
Integral non linearity INL — –2 — 2 LSB
AC Accuracy Total harmonic distortion THD FIN = 50 kHz, FS = 1 MHz,
PLL
–65 (37) — — dB
Signal-to-noise ratio SNR FIN = 50 kHz, FS = 1 MHz,
PLL
54 (38) — — dB
Signal-to-noise and distortion SINAD FIN = 50 kHz, FS = 1 MHz,
PLL
53 (39) — — dB
On-Chip Temperature
Sensor
Temperature sampling rate TS— — — 50 kSPS
Absolute accuracy — –40 to 125°C,
with 64 samples averaging
(40)
— — ±10 °C
Conversion Rate (41) Conversion time — Single measurement — — 1 Cycle
Continuous measurement — — 1 Cycle
Temperature measurement — — 1 Cycle
Related Information
SPICE Models for Intel FPGAs
(37) THD with prescalar enabled is 6dB less than the specification.
(38) SNR with prescalar enabled is 6dB less than the specification.
(39) SINAD with prescalar enabled is 6dB less than the specification.
(40) For the Intel Quartus Prime software version 15.0 and later, Modular ADC Core Intel FPGA IP and Modular Dual ADC Core Intel FPGA
IP cores handle the 64 samples averaging. For the Intel Quartus Prime software versions prior to 14.1, you need to implement your
own averaging calculation.
(41) For more detailed description, refer to the Timing section in the Intel MAX 10 Analog-to-Digital Converter User Guide.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
32
Dual Supply Devices ADC Performance Specifications
Table 35. ADC Performance Specifications for Intel MAX 10 Dual Supply Devices
Parameter Symbol Condition Min Typ Max Unit
ADC resolution — — — — 12 bits
Analog supply voltage VCCA_ADC — 2.375 2.5 2.625 V
Digital supply voltage VCCINT — 1.15 1.2 1.25 V
External reference voltage VREF — VCCA_ADC –
0.5
— VCCA_ADC V
Sampling rate FSAccumulative sampling rate — — 1 MSPS
Operating junction temperature range TJ— –40 25 125 °C
Analog input voltage VIN Prescalar disabled 0 — VREF V
Prescalar enabled (42) 0 — 3 V
Analog supply current (DC) IACC_ADC Average current — 275 450 µA
Digital supply current (DC) ICCINT Average current — 65 150 µA
Input resistance RIN — — (43)— —
Input capacitance CIN — — (43)— —
DC Accuracy Offset error and drift Eoffset Prescalar disabled –0.2 — 0.2 %FS
Prescalar enabled –0.5 — 0.5 %FS
Gain error and drift Egain Prescalar disabled –0.5 — 0.5 %FS
Prescalar enabled –0.75 — 0.75 %FS
Differential non linearity DNL External VREF, no missing
code
–0.9 — 0.9 LSB
continued...
(42) Prescalar function divides the analog input voltage by half. The analog input handles up to 3 V input for the Intel MAX 10 dual supply
devices.
(43) Download the SPICE models for simulation.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
33
Parameter Symbol Condition Min Typ Max Unit
Internal VREF, no missing
code
–1 — 1.7 LSB
Integral non linearity INL — –2 — 2 LSB
AC Accuracy Total harmonic distortion THD FIN = 50 kHz, FS = 1 MHz,
PLL
–70 (44)(45)
(46)
— — dB
Signal-to-noise ratio SNR FIN = 50 kHz, FS = 1 MHz,
PLL
62 (47)(48)(46)— — dB
Signal-to-noise and distortion SINAD FIN = 50 kHz, FS = 1 MHz,
PLL
61.5 (49)
(50)(46)
— — dB
On-Chip Temperature
Sensor
Temperature sampling rate TS— — — 50 kSPS
Absolute accuracy — –40 to 125°C,
with 64 samples averaging
(51)
— — ±5 °C
continued...
(44) Total harmonic distortion is –65 dB for dual function pin.
(45) THD with prescalar enabled is 6dB less than the specification.
(46) When using internal VREF, THD = 66 dB, SNR = 58 dB and SINAD = 57.5 dB for dedicated ADC input channels.
(47) Signal-to-noise ratio is 54 dB for dual function pin.
(48) SNR with prescalar enabled is 6dB less than the specification.
(49) Signal-to-noise and distortion is 53 dB for dual function pin.
(50) SINAD with prescalar enabled is 6dB less than the specification.
(51) For the Intel Quartus Prime software version 15.0 and later, Modular ADC Core and Modular Dual ADC Core IP cores handle the 64
samples averaging. For the Intel Quartus Prime software versions prior to 14.1, you need to implement your own averaging
calculation.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
34
Parameter Symbol Condition Min Typ Max Unit
Conversion Rate (52) Conversion time — Single measurement — — 1 Cycle
Continuous measurement — — 1 Cycle
Temperature measurement — — 1 Cycle
Related Information
SPICE Models for Intel FPGAs
Periphery Performance Specifications
This section describes the periphery performance, high-speed I/O, and external memory interface.
Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and
perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable
frequency in your system.
High-Speed I/O Specifications
For more information about the high-speed and low-speed I/O performance pins, refer to the respective device pin-out files.
Related Information
Documentation: Pin-Out Files for Intel FPGAs
(52) For more detailed description, refer to the Timing section in the Intel MAX 10 Analog-to-Digital Converter User Guide.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
35
True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications
Table 36. True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
True PPDS transmitter is only supported at bottom I/O banks. Emulated PPDS transmitter is supported at the output pin of all I/O banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency
(high-speed I/O
performance pin)
×10 5 — 155 5 — 155 5 — 155 MHz
×8 5 — 155 5 — 155 5 — 155 MHz
×7 5 — 155 5 — 155 5 — 155 MHz
×4 5 — 155 5 — 155 5 — 155 MHz
×2 5 — 155 5 — 155 5 — 155 MHz
×1 5 — 310 5 — 310 5 — 310 MHz
HSIODR Data rate (high-speed
I/O performance pin)
×10 100 — 310 100 — 310 100 — 310 Mbps
×8 80 — 310 80 — 310 80 — 310 Mbps
×7 70 — 310 70 — 310 70 — 310 Mbps
×4 40 — 310 40 — 310 40 — 310 Mbps
×2 20 — 310 20 — 310 20 — 310 Mbps
×1 10 — 310 10 — 310 10 — 310 Mbps
fHSCLK Input clock frequency
(low-speed I/O
performance pin)
×10 5 — 150 5 — 150 5 — 150 MHz
×8 5 — 150 5 — 150 5 — 150 MHz
×7 5 — 150 5 — 150 5 — 150 MHz
×4 5 — 150 5 — 150 5 — 150 MHz
×2 5 — 150 5 — 150 5 — 150 MHz
×1 5 — 300 5 — 300 5 — 300 MHz
HSIODR Data rate (low-speed
I/O performance pin)
×10 100 — 300 100 — 300 100 — 300 Mbps
×8 80 — 300 80 — 300 80 — 300 Mbps
×7 70 — 300 70 — 300 70 — 300 Mbps
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
36
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
×4 40 — 300 40 — 300 40 — 300 Mbps
×2 20 — 300 20 — 300 20 — 300 Mbps
×1 10 — 300 10 — 300 10 — 300 Mbps
tDUTY Duty cycle on
transmitter output
clock
— 45 — 55 45 — 55 45 — 55 %
TCCS(53) Transmitter channel-
to-channel skew
— — — 300 — — 300 — — 300 ps
tx Jitter(54) Output jitter (high-
speed I/O
performance pin)
— — — 425 — — 425 — — 425 ps
Output jitter (low-
speed I/O
performance pin)
— — — 470 — — 470 — — 470 ps
tRISE Rise time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tFALL Fall time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tLOCK Time required for the
PLL to lock, after
CONF_DONE signal
goes high, indicating
the completion of
device configuration
— — — 1 — — 1 — — 1 ms
(53) TCCS specifications apply to I/O banks from the same side only.
(54) TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
37
True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Single Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Table 37. True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
True RSDS transmitter is only supported at bottom I/O banks. Emulated RSDS transmitter is supported at the output pin of all I/O banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency
(high-speed I/O
performance pin)
×10 5 — 50 5 — 50 5 — 50 MHz
×8 5 — 50 5 — 50 5 — 50 MHz
×7 5 — 50 5 — 50 5 — 50 MHz
×4 5 — 50 5 — 50 5 — 50 MHz
×2 5 — 50 5 — 50 5 — 50 MHz
×1 5 — 100 5 — 100 5 — 100 MHz
HSIODR Data rate (high-speed
I/O performance pin)
×10 100 — 100 100 — 100 100 — 100 Mbps
×8 80 — 100 80 — 100 80 — 100 Mbps
×7 70 — 100 70 — 100 70 — 100 Mbps
×4 40 — 100 40 — 100 40 — 100 Mbps
×2 20 — 100 20 — 100 20 — 100 Mbps
×1 10 — 100 10 — 100 10 — 100 Mbps
fHSCLK Input clock frequency
(low-speed I/O
performance pin)
×10 5 — 50 5 — 50 5 — 50 MHz
×8 5 — 50 5 — 50 5 — 50 MHz
×7 5 — 50 5 — 50 5 — 50 MHz
×4 5 — 50 5 — 50 5 — 50 MHz
×2 5 — 50 5 — 50 5 — 50 MHz
×1 5 — 100 5 — 100 5 — 100 MHz
HSIODR Data rate (low-speed
I/O performance pin)
×10 100 — 100 100 — 100 100 — 100 Mbps
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
38
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
×8 80 — 100 80 — 100 80 — 100 Mbps
×7 70 — 100 70 — 100 70 — 100 Mbps
×4 40 — 100 40 — 100 40 — 100 Mbps
×2 20 — 100 20 — 100 20 — 100 Mbps
×1 10 — 100 10 — 100 10 — 100 Mbps
tDUTY Duty cycle on
transmitter output
clock
— 45 — 55 45 — 55 45 — 55 %
TCCS(55) Transmitter channel-
to-channel skew
— — — 300 — — 300 — — 300 ps
tx Jitter(56) Output jitter (high-
speed I/O
performance pin)
— — — 425 — — 425 — — 425 ps
Output jitter (low-
speed I/O
performance pin)
— — — 470 — — 470 — — 470 ps
tRISE Rise time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tFALL Fall time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tLOCK Time required for the
PLL to lock, after
CONF_DONE signal
goes high, indicating
the completion of
device configuration
— — — 1 — — 1 — — 1 ms
(55) TCCS specifications apply to I/O banks from the same side only.
(56) TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
39
Dual Supply Devices True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications
Table 38. True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
True RSDS transmitter is only supported at bottom I/O banks. Emulated RSDS transmitter is supported at the output pin of all I/O banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency
(high-speed I/O
performance pin)
×10 5 — 155 5 — 155 5 — 155 MHz
×8 5 — 155 5 — 155 5 — 155 MHz
×7 5 — 155 5 — 155 5 — 155 MHz
×4 5 — 155 5 — 155 5 — 155 MHz
×2 5 — 155 5 — 155 5 — 155 MHz
×1 5 — 310 5 — 310 5 — 310 MHz
HSIODR Data rate (high-speed
I/O performance pin)
×10 100 — 310 100 — 310 100 — 310 Mbps
×8 80 — 310 80 — 310 80 — 310 Mbps
×7 70 — 310 70 — 310 70 — 310 Mbps
×4 40 — 310 40 — 310 40 — 310 Mbps
×2 20 — 310 20 — 310 20 — 310 Mbps
×1 10 — 310 10 — 310 10 — 310 Mbps
fHSCLK Input clock frequency
(low-speed I/O
performance pin)
×10 5 — 150 5 — 150 5 — 150 MHz
×8 5 — 150 5 — 150 5 — 150 MHz
×7 5 — 150 5 — 150 5 — 150 MHz
×4 5 — 150 5 — 150 5 — 150 MHz
×2 5 — 150 5 — 150 5 — 150 MHz
×1 5 — 300 5 — 300 5 — 300 MHz
HSIODR Data rate (low-speed
I/O performance pin)
×10 100 — 300 100 — 300 100 — 300 Mbps
×8 80 — 300 80 — 300 80 — 300 Mbps
×7 70 — 300 70 — 300 70 — 300 Mbps
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
40
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
×4 40 — 300 40 — 300 40 — 300 Mbps
×2 20 — 300 20 — 300 20 — 300 Mbps
×1 10 — 300 10 — 300 10 — 300 Mbps
tDUTY Duty cycle on
transmitter output
clock
— 45 — 55 45 — 55 45 — 55 %
TCCS(57) Transmitter channel-
to-channel skew
— — — 300 — — 300 — — 300 ps
tx Jitter(58) Output jitter (high-
speed I/O
performance pin)
— — — 425 — — 425 — — 425 ps
Output jitter (low-
speed I/O
performance pin)
— — — 470 — — 470 — — 470 ps
tRISE Rise time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tFALL Fall time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tLOCK Time required for the
PLL to lock, after
CONF_DONE signal
goes high, indicating
the completion of
device configuration
— — — 1 — — 1 — — 1 ms
(57) TCCS specifications apply to I/O banks from the same side only.
(58) TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
41
Emulated RSDS_E_1R Transmitter Timing Specifications
Table 39. Emulated RSDS_E_1R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency
(high-speed I/O
performance pin)
×10 5 — 85 5 — 85 5 — 85 MHz
×8 5 — 85 5 — 85 5 — 85 MHz
×7 5 — 85 5 — 85 5 — 85 MHz
×4 5 — 85 5 — 85 5 — 85 MHz
×2 5 — 85 5 — 85 5 — 85 MHz
×1 5 — 170 5 — 170 5 — 170 MHz
HSIODR Data rate (high-speed
I/O performance pin)
×10 100 — 170 100 — 170 100 — 170 Mbps
×8 80 — 170 80 — 170 80 — 170 Mbps
×7 70 — 170 70 — 170 70 — 170 Mbps
×4 40 — 170 40 — 170 40 — 170 Mbps
×2 20 — 170 20 — 170 20 — 170 Mbps
×1 10 — 170 10 — 170 10 — 170 Mbps
fHSCLK Input clock frequency
(low-speed I/O
performance pin)
×10 5 — 85 5 — 85 5 — 85 MHz
×8 5 — 85 5 — 85 5 — 85 MHz
×7 5 — 85 5 — 85 5 — 85 MHz
×4 5 — 85 5 — 85 5 — 85 MHz
×2 5 — 85 5 — 85 5 — 85 MHz
×1 5 — 170 5 — 170 5 — 170 MHz
HSIODR Data rate (low-speed
I/O performance pin)
×10 100 — 170 100 — 170 100 — 170 Mbps
×8 80 — 170 80 — 170 80 — 170 Mbps
×7 70 — 170 70 — 170 70 — 170 Mbps
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
42
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
×4 40 — 170 40 — 170 40 — 170 Mbps
×2 20 — 170 20 — 170 20 — 170 Mbps
×1 10 — 170 10 — 170 10 — 170 Mbps
tDUTY Duty cycle on
transmitter output
clock
— 45 — 55 45 — 55 45 — 55 %
TCCS(59) Transmitter channel-
to-channel skew
— — — 300 — — 300 — — 300 ps
tx Jitter(60) Output jitter (high-
speed I/O
performance pin)
— — — 425 — — 425 — — 425 ps
Output jitter (low-
speed I/O
performance pin)
— — — 470 — — 470 — — 470 ps
tRISE Rise time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tFALL Fall time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tLOCK Time required for the
PLL to lock, after
CONF_DONE signal
goes high, indicating
the completion of
device configuration
— — — 1 — — 1 — — 1 ms
(59) TCCS specifications apply to I/O banks from the same side only.
(60) TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
43
True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications
Table 40. True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply
Devices
True mini-LVDS transmitter is only supported at the bottom I/O banks. Emulated mini-LVDS_E_3R transmitter is supported at the output pin of all I/O banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency
(high-speed I/O
performance pin)
×10 5 — 155 5 — 155 5 — 155 MHz
×8 5 — 155 5 — 155 5 — 155 MHz
×7 5 — 155 5 — 155 5 — 155 MHz
×4 5 — 155 5 — 155 5 — 155 MHz
×2 5 — 155 5 — 155 5 — 155 MHz
×1 5 — 310 5 — 310 5 — 310 MHz
HSIODR Data rate (high-speed
I/O performance pin)
×10 100 — 310 100 — 310 100 — 310 Mbps
×8 80 — 310 80 — 310 80 — 310 Mbps
×7 70 — 310 70 — 310 70 — 310 Mbps
×4 40 — 310 40 — 310 40 — 310 Mbps
×2 20 — 310 20 — 310 20 — 310 Mbps
×1 10 — 310 10 — 310 10 — 310 Mbps
fHSCLK Input clock frequency
(low-speed I/O
performance pin)
×10 5 — 150 5 — 150 5 — 150 MHz
×8 5 — 150 5 — 150 5 — 150 MHz
×7 5 — 150 5 — 150 5 — 150 MHz
×4 5 — 150 5 — 150 5 — 150 MHz
×2 5 — 150 5 — 150 5 — 150 MHz
×1 5 — 300 5 — 300 5 — 300 MHz
HSIODR Data rate (low-speed
I/O performance pin)
×10 100 — 300 100 — 300 100 — 300 Mbps
×8 80 — 300 80 — 300 80 — 300 Mbps
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
44
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
×7 70 — 300 70 — 300 70 — 300 Mbps
×4 40 — 300 40 — 300 40 — 300 Mbps
×2 20 — 300 20 — 300 20 — 300 Mbps
×1 10 — 300 10 — 300 10 — 300 Mbps
tDUTY Duty cycle on
transmitter output
clock
— 45 — 55 45 — 55 45 — 55 %
TCCS(61) Transmitter channel-
to-channel skew
— — — 300 — — 300 — — 300 ps
tx Jitter(62) Output jitter (high-
speed I/O
performance pin)
— — — 425 — — 425 — — 425 ps
Output jitter (low-
speed I/O
performance pin)
— — — 470 — — 470 — — 470 ps
tRISE Rise time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tFALL Fall time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tLOCK Time required for the
PLL to lock, after
CONF_DONE signal
goes high, indicating
the completion of
device configuration
— — — 1 — — 1 — — 1 ms
(61) TCCS specifications apply to I/O banks from the same side only.
(62) TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
45
True LVDS Transmitter Timing
Single Supply Devices True LVDS Transmitter Timing Specifications
Table 41. True LVDS Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
True LVDS transmitter is only supported at the bottom I/O banks.
Symbol Parameter Mode –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency ×10 5 — 145 5 — 100 5 — 100 MHz
×8 5 — 145 5 — 100 5 — 100 MHz
×7 5 — 145 5 — 100 5 — 100 MHz
×4 5 — 145 5 — 100 5 — 100 MHz
×2 5 — 145 5 — 100 5 — 100 MHz
×1 5 — 290 5 — 200 5 — 200 MHz
HSIODR Data rate ×10 100 — 290 100 — 200 100 — 200 Mbps
×8 80 — 290 80 — 200 80 — 200 Mbps
×7 70 — 290 70 — 200 70 — 200 Mbps
×4 40 — 290 40 — 200 40 — 200 Mbps
×2 20 — 290 20 — 200 20 — 200 Mbps
×1 10 — 290 10 — 200 10 — 200 Mbps
tDUTY Duty cycle on
transmitter output
clock
— 45 — 55 45 — 55 45 — 55 %
TCCS(63) Transmitter channel-
to-channel skew
— — — 300 — — 300 — — 300 ps
tx Jitter(64) Output jitter — — — 1,000 — — 1,000 — — 1,000 ps
continued...
(63) TCCS specifications apply to I/O banks from the same side only.
(64) TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
46
Symbol Parameter Mode –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
tRISE Rise time 20 – 80%, CLOAD =
5 pF
— 500 — — 500 — — 500 — ps
tFALL Fall time 20 – 80%, CLOAD =
5 pF
— 500 — — 500 — — 500 — ps
tLOCK Time required for the
PLL to lock, after
CONF_DONE signal
goes high, indicating
the completion of
device configuration
— — — 1 — — 1 — — 1 ms
Dual Supply Devices True LVDS Transmitter Timing Specifications
Table 42. True LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
True LVDS transmitter is only supported at the bottom I/O banks.
Symbol Parameter Mode –I6 –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock
frequency
×10 5 — 360 5 — 340 5 — 310 5 — 300 MHz
×8 5 — 360 5 — 360 5 — 320 5 — 320 MHz
×7 5 — 360 5 — 340 5 — 310 5 — 300 MHz
×4 5 — 360 5 — 350 5 — 320 5 — 320 MHz
×2 5 — 360 5 — 350 5 — 320 5 — 320 MHz
×1 5 — 360 5 — 350 5 — 320 5 — 320 MHz
HSIODR Data rate ×10 100 — 720 100 — 680 100 — 620 100 — 600 Mbps
×8 80 — 720 80 — 720 80 — 640 80 — 640 Mbps
×7 70 — 720 70 — 680 70 — 620 70 — 600 Mbps
×4 40 — 720 40 — 700 40 — 640 40 — 640 Mbps
×2 20 — 720 20 — 700 20 — 640 20 — 640 Mbps
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
47
Symbol Parameter Mode –I6 –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
×1 10 — 360 10 — 350 10 — 320 10 — 320 Mbps
tDUTY Duty cycle on
transmitter output
clock
— 45 — 55 45 — 55 45 — 55 45 — 55 %
TCCS(65) Transmitter
channel-to-
channel skew
— — — 300 — — 300 — — 300 — — 300 ps
tx
Jitter(66)
Output jitter — — — 380 — — 380 — — 380 — — 380 ps
tRISE Rise time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — — 500 — ps
tFALL Fall time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — — 500 — ps
tLOCK Time required for
the PLL to lock,
after CONF_DONE
signal goes high,
indicating the
completion of
device
configuration
— — — 1 — — 1 — — 1 — — 1 ms
(65) TCCS specifications apply to I/O banks from the same side only.
(66) TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
48
Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications
Single Supply Devices Emulated LVDS_E_3R Transmitter Timing Specifications
Table 43. Emulated LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
Emulated LVDS_E_3R transmitters are supported at the output pin of all I/O banks.
Symbol Parameter Mode –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency
(high-speed I/O
performance pin)
×10 5 — 142.5 5 — 100 5 — 100 MHz
×8 5 — 142.5 5 — 100 5 — 100 MHz
×7 5 — 142.5 5 — 100 5 — 100 MHz
×4 5 — 142.5 5 — 100 5 — 100 MHz
×2 5 — 142.5 5 — 100 5 — 100 MHz
×1 5 — 285 5 — 200 5 — 200 MHz
HSIODR Data rate (high-speed
I/O performance pin)
×10 100 — 285 100 — 200 100 — 200 Mbps
×8 80 — 285 80 — 200 80 — 200 Mbps
×7 70 — 285 70 — 200 70 — 200 Mbps
×4 40 — 285 40 — 200 40 — 200 Mbps
×2 20 — 285 20 — 200 20 — 200 Mbps
×1 10 — 285 10 — 200 10 — 200 Mbps
fHSCLK Input clock frequency
(low-speed I/O
performance pin)
×10 5 — 100 5 — 100 5 — 100 MHz
×8 5 — 100 5 — 100 5 — 100 MHz
×7 5 — 100 5 — 100 5 — 100 MHz
×4 5 — 100 5 — 100 5 — 100 MHz
×2 5 — 100 5 — 100 5 — 100 MHz
×1 5 — 200 5 — 200 5 — 200 MHz
HSIODR Data rate (low-speed
I/O performance pin)
×10 100 — 200 100 — 200 100 — 200 Mbps
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
49
Symbol Parameter Mode –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
×8 80 — 200 80 — 200 80 — 200 Mbps
×7 70 — 200 70 — 200 70 — 200 Mbps
×4 40 — 200 40 — 200 40 — 200 Mbps
×2 20 — 200 20 — 200 20 — 200 Mbps
×1 10 — 200 10 — 200 10 — 200 Mbps
tDUTY Duty cycle on
transmitter output
clock
— 45 — 55 45 — 55 45 — 55 %
TCCS(67) Transmitter channel-
to-channel skew
— — — 300 — — 300 — — 300 ps
tx Jitter(68) Output jitter — — — 1,000 — — 1,000 — — 1,000 ps
tRISE Rise time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tFALL Fall time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tLOCK Time required for the
PLL to lock, after
CONF_DONE signal
goes high, indicating
the completion of
device configuration
— — — 1 — — 1 — — 1 ms
(67) TCCS specifications apply to I/O banks from the same side only.
(68) TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
50
Dual Supply Devices Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications
Table 44. Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply
Devices
Emulated LVDS_E_3R, SLVS, and Sub-LVDS transmitters are supported at the output pin of all I/O banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
fHSCLK Input clock frequency
(high-speed I/O
performance pin)
×10 5 — 300 5 — 275 5 — 275 MHz
×8 5 — 300 5 — 275 5 — 275 MHz
×7 5 — 300 5 — 275 5 — 275 MHz
×4 5 — 300 5 — 275 5 — 275 MHz
×2 5 — 300 5 — 275 5 — 275 MHz
×1 5 — 300 5 — 275 5 — 275 MHz
HSIODR Data rate (high-speed
I/O performance pin)
×10 100 — 600 100 — 550 100 — 550 Mbps
×8 80 — 600 80 — 550 80 — 550 Mbps
×7 70 — 600 70 — 550 70 — 550 Mbps
×4 40 — 600 40 — 550 40 — 550 Mbps
×2 20 — 600 20 — 550 20 — 550 Mbps
×1 10 — 300 10 — 275 10 — 275 Mbps
fHSCLK Input clock frequency
(low-speed I/O
performance pin)
×10 5 — 150 5 — 150 5 — 150 MHz
×8 5 — 150 5 — 150 5 — 150 MHz
×7 5 — 150 5 — 150 5 — 150 MHz
×4 5 — 150 5 — 150 5 — 150 MHz
×2 5 — 150 5 — 150 5 — 150 MHz
×1 5 — 300 5 — 300 5 — 300 MHz
HSIODR Data rate (low-speed
I/O performance pin)
×10 100 — 300 100 — 300 100 — 300 Mbps
×8 80 — 300 80 — 300 80 — 300 Mbps
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
51
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Typ Max Min Typ Max Min Typ Max
×7 70 — 300 70 — 300 70 — 300 Mbps
×4 40 — 300 40 — 300 40 — 300 Mbps
×2 20 — 300 20 — 300 20 — 300 Mbps
×1 10 — 300 10 — 300 10 — 300 Mbps
tDUTY Duty cycle on
transmitter output
clock
— 45 — 55 45 — 55 45 — 55 %
TCCS(69) Transmitter channel-
to-channel skew
— — — 300 — — 300 — — 300 ps
tx Jitter(70) Output jitter (high-
speed I/O
performance pin)
— — — 425 — — 425 — — 425 ps
Output jitter (low-
speed I/O
performance pin)
— — — 470 — — 470 — — 470 ps
tRISE Rise time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tFALL Fall time 20 – 80%, CLOAD
= 5 pF
— 500 — — 500 — — 500 — ps
tLOCK Time required for the
PLL to lock, after
CONF_DONE signal
goes high, indicating
the completion of
device configuration
— — — 1 — — 1 — — 1 ms
(69) TCCS specifications apply to I/O banks from the same side only.
(70) TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
52
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Single Supply Devices LVDS Receiver Timing Specifications
Table 45. LVDS Receiver Timing Specifications for Intel MAX 10 Single Supply Devices
LVDS receivers are supported at all banks.
Symbol Parameter Mode –C7, –I7 –A7 –C8 Unit
Min Max Min Max Min Max
fHSCLK Input clock frequency (high-
speed I/O performance pin)
×10 5 145 5 100 5 100 MHz
×8 5 145 5 100 5 100 MHz
×7 5 145 5 100 5 100 MHz
×4 5 145 5 100 5 100 MHz
×2 5 145 5 100 5 100 MHz
×1 5 290 5 200 5 200 MHz
HSIODR Data rate (high-speed I/O
performance pin)
×10 100 290 100 200 100 200 Mbps
×8 80 290 80 200 80 200 Mbps
×7 70 290 70 200 70 200 Mbps
×4 40 290 40 200 40 200 Mbps
×2 20 290 20 200 20 200 Mbps
×1 10 290 10 200 10 200 Mbps
fHSCLK Input clock frequency (low-
speed I/O performance pin)
×10 5 100 5 100 5 100 MHz
×8 5 100 5 100 5 100 MHz
×7 5 100 5 100 5 100 MHz
×4 5 100 5 100 5 100 MHz
×2 5 100 5 100 5 100 MHz
×1 5 200 5 200 5 200 MHz
HSIODR Data rate (low-speed I/O
performance pin)
×10 100 200 100 200 100 200 Mbps
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
53
Symbol Parameter Mode –C7, –I7 –A7 –C8 Unit
Min Max Min Max Min Max
×8 80 200 80 200 80 200 Mbps
×7 70 200 70 200 70 200 Mbps
×4 40 200 40 200 40 200 Mbps
×2 20 200 20 200 20 200 Mbps
×1 10 200 10 200 10 200 Mbps
SW Sampling window (high-
speed I/O performance pin)
— — 910 — 910 — 910 ps
Sampling window (low-
speed I/O performance pin)
— — 1,110 — 1,110 — 1,110 ps
tx Jitter(71) Input jitter — — 1,000 — 1,000 — 1,000 ps
tLOCK Time required for the PLL to
lock, after CONF_DONE
signal goes high, indicating
the completion of device
configuration
— — 1 — 1 — 1 ms
Dual Supply Devices LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications
Table 46. LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices
LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS receivers are supported at all banks.
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Max Min Max Min Max
fHSCLK Input clock frequency (high-
speed I/O performance pin)
×10 5 350 5 320 5 320 MHz
×8 5 360 5 320 5 320 MHz
×7 5 350 5 320 5 320 MHz
×4 5 360 5 320 5 320 MHz
continued...
(71) TX jitter is the jitter induced from core noise and I/O switching noise.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
54
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Max Min Max Min Max
×2 5 360 5 320 5 320 MHz
×1 5 360 5 320 5 320 MHz
HSIODR Data rate (high-speed I/O
performance pin)
×10 100 700 100 640 100 640 Mbps
×8 80 720 80 640 80 640 Mbps
×7 70 700 70 640 70 640 Mbps
×4 40 720 40 640 40 640 Mbps
×2 20 720 20 640 20 640 Mbps
×1 10 360 10 320 10 320 Mbps
fHSCLK Input clock frequency (low-
speed I/O performance pin)
×10 5 150 5 150 5 150 MHz
×8 5 150 5 150 5 150 MHz
×7 5 150 5 150 5 150 MHz
×4 5 150 5 150 5 150 MHz
×2 5 150 5 150 5 150 MHz
×1 5 300 5 300 5 300 MHz
HSIODR Data rate (low-speed I/O
performance pin)
×10 100 300 100 300 100 300 Mbps
×8 80 300 80 300 80 300 Mbps
×7 70 300 70 300 70 300 Mbps
×4 40 300 40 300 40 300 Mbps
×2 20 300 20 300 20 300 Mbps
×1 10 300 10 300 10 300 Mbps
SW Sampling window (high-
speed I/O performance pin)
— — 510 — 510 — 510 ps
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
55
Symbol Parameter Mode –I6, –A6, –C7, –I7 –A7 –C8 Unit
Min Max Min Max Min Max
Sampling window (low-
speed I/O performance pin)
— — 910 — 910 — 910 ps
tx Jitter(72) Input jitter — — 500 — 500 — 500 ps
tLOCK Time required for the PLL to
lock, after CONF_DONE
signal goes high, indicating
the completion of device
configuration
— — 1 — 1 — 1 ms
Memory Standards Supported by the Soft Memory Controller
Table 47. Memory Standards Supported by the Soft Memory Controller for Intel MAX 10 Devices
Contact your local sales representatives for access to the -I6 or -A6 speed grade devices in the Intel Quartus Prime software.
External Memory Interface
Standard
Rate Support Speed Grade Voltage (V) Max Frequency (MHz)
DDR3 SDRAM Half –I6 1.5 303
DDR3L SDRAM Half –I6 1.35 303
DDR2 SDRAM Half –I6 1.8 200
–I7 and –C7 167
LPDDR2(73) Half –I6 1.2 200(74)
Related Information
External Memory Interface Spec Estimator
Provides the specific details of the memory standards supported.
(72) TX jitter is the jitter induced from core noise and I/O switching noise.
(73) Intel MAX 10 devices support only single-die LPDDR2.
(74) To achieve the specified performance, constrain the memory device I/O and core power supply variation to within ±3%. By default,
the frequency is 167 MHz.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
56
Memory Output Clock Jitter Specifications
Intel MAX 10 devices support external memory interfaces up to 303 MHz. The external memory interfaces for Intel MAX 10
devices calibrate automatically.
The memory output clock jitter measurements are for 200 consecutive clock cycles.
The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output
routed on a PHY clock network.
DDR3 and LPDDR2 SDRAM memory interfaces are only supported on the fast speed grade device.
Table 48. Memory Output Clock Jitter Specifications for Intel MAX 10 Devices
Parameter Symbol –6 Speed Grade –7 Speed Grade Unit
Min Max Min Max
Clock period jitter tJIT(per) –127 127 –215 215 ps
Cycle-to-cycle period jitter tJIT(cc) — 242 — 360 ps
Related Information
Literature: External Memory Interfaces
Provides more information about external memory system performance specifications, board design guidelines, timing
analysis, simulation, and debugging information.
Configuration Specifications
This section provides configuration specifications and timing for Intel MAX 10 devices.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
57
JTAG Timing Parameters
Table 49. JTAG Timing Parameters for Intel MAX 10 Devices
The values are based on CL = 10 pF of TDO.
The affected Boundary Scan Test (BST) instructions are SAMPLE/PRELOAD, EXTEST, INTEST, and CHECK_STATUS.
Symbol Parameter Non-BST and non-CONFIG_IO Operation BST and CONFIG_IO Operation Unit
Minimum Maximum Minimum Maximum
tJCP TCK clock period 40 — 50 — ns
tJCH TCK clock high time 20 — 25 — ns
tJCL TCK clock low time 20 — 25 — ns
tJPSU_TDI JTAG port setup time 2 — 2 — ns
tJPSU_TMS JTAG port setup time 3 — 3 — ns
tJPH JTAG port hold time 10 — 10 — ns
tJPCO JTAG port clock to output — • 15 (for VCCIO = 3.3, 3.0,
and 2.5 V)
• 17 (for VCCIO = 1.8 and
1.5 V)
— • 18 (for VCCIO = 3.3, 3.0,
and 2.5 V)
• 20 (for VCCIO = 1.8 and
1.5 V)
ns
tJPZX JTAG port high impedance to
valid output
— • 15 (for VCCIO = 3.3, 3.0,
and 2.5 V)
• 17 (for VCCIO = 1.8 and
1.5 V)
— • 15 (for VCCIO = 3.3, 3.0,
and 2.5 V)
• 17 (for VCCIO = 1.8 and
1.5 V)
ns
tJPXZ JTAG port valid output to high
impedance
— • 15 (for VCCIO = 3.3, 3.0,
and 2.5 V)
• 17 (for VCCIO = 1.8 and
1.5 V)
— • 15 (for VCCIO = 3.3, 3.0,
and 2.5 V)
• 17 (for VCCIO = 1.8 and
1.5 V)
ns
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
58
Remote System Upgrade Circuitry Timing Specifications
Table 50. Remote System Upgrade Circuitry Timing Specifications for Intel MAX 10 Devices
Parameter Device Minimum Maximum Unit
tMAX_RU_CLK All — 40 MHz
tRU_nCONFIG 10M02, 10M04, 10M08, 10M16, 10M25 250 — ns
10M40, 10M50 350 — ns
tRU_nRSTIMER 10M02, 10M04, 10M08, 10M16, 10M25 300 — ns
10M40, 10M50 500 — ns
User Watchdog Internal Circuitry Timing Specifications
Table 51. User Watchdog Timer Specifications for Intel MAX 10 Devices
The specifications are subject to PVT changes.
Parameter Device Minimum Typical Maximum Unit
User watchdog frequency 10M02, 10M04, 10M08, 10M16,
10M25
3.4 5.1 7.3 MHz
10M40, 10M50 2.2 3.3 4.8 MHz
Uncompressed Raw Binary File (.rbf) Sizes
Table 52. Uncompressed .rbf Sizes for Intel MAX 10 Devices
Device CFM Data Size (bits)
Without Memory Initialization With Memory Initialization
10M02 554,000 —
10M04 1,540,000 1,880,000
10M08 1,540,000 1,880,000
10M16 2,800,000 3,430,000
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
59
Device CFM Data Size (bits)
Without Memory Initialization With Memory Initialization
10M25 4,140,000 4,780,000
10M40 7,840,000 9,670,000
10M50 7,840,000 9,670,000
Internal Configuration Time
The internal configuration time measurement is from the rising edge of nSTATUS signal to the rising edge of CONF_DONE
signal.
Table 53. Internal Configuration Time for Intel MAX 10 Devices (Uncompressed .rbf)
Device Internal Configuration Time (ms)
Unencrypted Encrypted
Without Memory Initialization With Memory Initialization Without Memory Initialization With Memory Initialization
Min Max Min Max Min Max Min Max
10M02 0.3 1.7 — — 1.7 5.4 — —
10M04 0.6 2.7 1.0 3.4 5.0 15.0 6.8 19.6
10M08 0.6 2.7 1.0 3.4 5.0 15.0 6.8 19.6
10M16 1.1 3.7 1.4 4.5 9.3 25.3 11.7 31.5
10M25 1.0 3.7 1.3 4.4 14.0 38.1 16.9 45.7
10M40 2.6 6.9 3.2 9.8 41.5 112.1 51.7 139.6
10M50 2.6 6.9 3.2 9.8 41.5 112.1 51.7 139.6
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
60
Table 54. Internal Configuration Time for Intel MAX 10 Devices (Compressed .rbf)
Compression ratio depends on design complexity. The minimum value is based on the best case (25% of original .rbf sizes) and the maximum value is based on
the typical case (70% of original .rbf sizes).
Device Internal Configuration Time (ms)
Unencrypted/Encrypted
Without Memory Initialization With Memory Initialization
Min Max Min Max
10M02 0.3 5.2 — —
10M04 0.6 10.7 1.0 13.9
10M08 0.6 10.7 1.0 13.9
10M16 1.1 17.9 1.4 22.3
10M25 1.1 26.9 1.4 32.2
10M40 2.6 66.1 3.2 82.2
10M50 2.6 66.1 3.2 82.2
Internal Configuration Timing Parameter
Table 55. Internal Configuration Timing Parameter for Intel MAX 10 Devices
Symbol Parameter Device Minimum Maximum Unit
tCD2UM CONF_DONE high to
user mode
10M02, 10M04, 10M08, 10M16, 10M25 182.8 385.5 μs
10M40, 10M50 275.3 605.7 μs
I/O Timing
The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing
analysis.
The Intel Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specific device
and design after you complete place-and-route.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
61
Table 56. I/O Timing for Intel MAX 10 Devices
These I/O timing parameters are for the 3.3-V LVTTL I/O standard with the maximum drive strength and fast slew rate for 10M08DAF484 device.
Symbol Parameter –C7, –I7 –C8 Unit
Tsu Global clock setup time –0.750 –0.808 ns
ThGlobal clock hold time 1.180 1.215 ns
Tco Global clock to output delay 5.131 5.575 ns
Tpd Best case pin-to-pin propagation delay through one LUT 4.907 5.467 ns
Programmable IOE Delay
Programmable IOE Delay On Row Pins
Table 57. IOE Programmable Delay on Row Pins for Intel MAX 10 Devices
The incremental values for the settings are generally linear. For exact values of each setting, refer to the Assignment Name column in the latest version of the
Intel Quartus Prime software.
The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Intel Quartus Prime software.
Parameter Paths Affected Number of
Settings
Minimum
Offset
Maximum Offset Unit
Fast Corner Slow Corner
–I7 –C8 –A6 –C7 –C8 –I7 –A7
Input delay from
pin to internal
cells
Pad to I/O
dataout to core
7 0 0.815 0.873 1.831 1.811 1.874 1.871 1.922 ns
Input delay from
pin to input
register
Pad to I/O input
register
8 0 0.924 0.992 2.081 2.055 2.125 2.127 2.185 ns
Delay from
output register to
output pin
I/O output
register to pad
2 0 0.479 0.514 1.069 1.070 1.117 1.105 1.134 ns
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
62
Programmable IOE Delay for Column Pins
Table 58. IOE Programmable Delay on Column Pins for Intel MAX 10 Devices
The incremental values for the settings are generally linear. For exact values of each setting, refer to the Assignment Name column in the latest version of the
Intel Quartus Prime software.
The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Intel Quartus Prime software.
Parameter Paths Affected Number of
Settings
Minimum
Offset
Maximum Offset Unit
Fast Corner Slow Corner
–I7 –C8 –A6 –C7 –C8 –I7 –A7
Input delay from
pin to internal
cells
Pad to I/O
dataout to core
7 0 0.81 0.868 1.823 1.802 1.864 1.862 1.912 ns
Input delay from
pin to input
register
Pad to I/O input
register
8 0 0.914 0.981 2.06 2.032 2.101 2.102 2.161 ns
Delay from
output register to
output pin
I/O output
register to pad
2 0 0.435 0.466 0.971 0.97 1.013 1.001 1.028 ns
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
63
Glossary
Table 59. Glossary
Term Definition
JTAG Timing Specifications
TDO
TCK
tJPZX tJPCO
tJPH
tJPXZ
tJCP
tJPSU
t JCL
tJCH
TDI
TMS
RLReceiver differential input discrete resistor (external to Intel MAX 10 devices).
RSKM (Receiver input skew margin) HIGH-SPEED I/O block: The total margin left after accounting for the sampling window and TCCS. RSKM = (TUI – SW – TCCS) / 2.
Sampling window (SW) HIGH-SPEED I/O Block: The period of time during which the data must be valid to capture it correctly. The setup and hold times
determine the ideal strobe position in the sampling window.
Single-ended voltage referenced I/O
standard
The AC input signal values indicate the voltage levels at which the receiver must meet its timing specifications. The DC input signal
values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input
crosses the AC value, the receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide
predictable receiver timing in the presence of input waveform ringing.
tCHigh-speed receiver/transmitter input and output clock period.
TCCS (Channel-to- channel-skew) HIGH-SPEED I/O block: The timing difference between the fastest and slowest output edges, including tCO variation and clock skew.
The clock is included in the TCCS measurement.
tcin Delay from clock pad to I/O input register.
tCO Delay from clock pad to I/O output.
tcout Delay from clock pad to I/O output register.
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
64
Term Definition
tDUTY HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
tFALL Signal high-to-low transition time (80–20%).
tHInput register hold time.
Timing Unit Interval (TUI) HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver
Input Clock Frequency Multiplication Factor) = tC/w).
tINJITTER Period jitter on PLL clock input.
tOUTJITTER_DEDCLK Period jitter on dedicated clock output driven by a PLL.
tOUTJITTER_IO Period jitter on general purpose I/O driven by a PLL.
tpllcin Delay from PLL inclk pad to I/O input register.
tpllcout Delay from PLL inclk pad to I/O output register.
tRISE Signal low-to-high transition time (20–80%).
tSU Input register setup time.
VCM(DC) DC common mode input voltage.
VDIF(AC) AC differential input voltage: The minimum AC input differential voltage required for switching.
VDIF(DC) DC differential input voltage: The minimum DC input differential voltage required for switching.
VHYS Hysteresis for Schmitt trigger input.
VICM Input common mode voltage: The common mode of the differential signal at the receiver.
VID Input differential Voltage Swing: The difference in voltage between the positive and complementary conductors of a differential
transmission at the receiver.
VIH Voltage input high: The minimum positive voltage applied to the input which is accepted by the device as a logic high.
VIH(AC) High-level AC input voltage.
VIH(DC) High-level DC input voltage.
VIL Voltage input low: The maximum positive voltage applied to the input which is accepted by the device as a logic low.
VIL (AC) Low-level AC input voltage.
VIL (DC) Low-level DC input voltage.
VIN DC input voltage.
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
65
Term Definition
VOCM Output common mode voltage: The common mode of the differential signal at the transmitter.
VOD Output differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential
transmission line at the transmitter. VOD = VOH – VOL.
VOH Voltage output high: The maximum positive voltage from an output which the device considers is accepted as the minimum positive
high level.
VOL Voltage output low: The maximum positive voltage from an output which the device considers is accepted as the maximum positive
low level.
VOS Output offset voltage: VOS = (VOH + VOL) / 2.
VOX (AC) AC differential Output cross point voltage: The voltage at which the differential output signals must cross.
VREF Reference voltage for SSTL, HSTL, and HSUL I/O Standards.
VREF(AC) AC input reference voltage for SSTL, HSTL, and HSUL I/O Standards. VREF(AC) = VREF(DC) + noise. The peak-to-peak AC noise on
VREF should not exceed 2% of VREF(DC).
VREF(DC) DC input reference voltage for SSTL, HSTL, and HSUL I/O Standards.
VSWING (AC) AC differential input voltage: AC Input differential voltage required for switching.
VSWING (DC) DC differential input voltage: DC Input differential voltage required for switching.
VTT Termination voltage for SSTL, HSTL, and HSUL I/O Standards.
VX (AC) AC differential Input cross point voltage: The voltage at which the differential input signals must cross.
Document Revision History for the Intel MAX 10 FPGA Device Datasheet
Document
Version
Changes
2018.06.29 • Removed links on instant-on feature.
• Added JTAG timing specifications term in Glossary.
• Renamed the following IP cores as per Intel rebranding:
— Renamed Altera Modular ADC IP core to Modular ADC core Intel FPGA IP core.
— Renamed Altera Modular Dual ADC IP core to Modular Dual ADC core Intel FPGA IP core.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
66
Date Version Changes
December 2017 2017.12.15 • Removed the units for "Input resistance" and "Input capacitance" parameters in the following tables:
—ADC Performance Specifications for Intel MAX 10 Single Supply Devices
—ADC Performance Specifications for Intel MAX 10 Dual Supply Devices
• Removed the specification with memory initialization for 10M02 device in the Uncompressed .rbf Sizes for Intel MAX 10
Devices table.
June 2017 2017.06.16 • Added notes for TJ for Industrial and Automotive devices in Recommended Operating Conditions for Intel MAX 10 Devices
table.
• Updated the parameter in Internal Weak Pull-Up Resistor for Intel MAX 10 Devices table.
• Changed "Performance" to "Frequency" in UFM Performance Specifications for Intel MAX 10 Devices table.
• Removed PowerPlay text from tool name.
February 2017 2017.02.21 • Rebranded as Intel.
October 2016 2016.10.31 • Updated the note to the Intel MAX 10 Device Grades and Speed Grades Supported table.
• Updated the Memory Standards Supported by the Soft Memory Controller for Intel MAX 10 Devices table.
May 2016 2016.05.02 • Updated tRAMP specifications in Recommended Operating Conditions for Intel MAX 10 Devices table.
— Removed standard POR and fast POR specifications.
— Updated maximum value from 3 ms to 10 ms and added a not for the minimum value.
• Added Supply Current and Power Consumption section.
• Added the following tables:
— Memory Standards Supported by the Soft Memory Controller for Intel MAX 10 Devices
— Internal Configuration Timing Parameter for Intel MAX 10 Devices
• Removed POR Delay Specifications for Intel MAX 10 Devices table.
• Updated the description in the Internal Configuration Time section.
• Updated the following tables:
—Internal Configuration Time for Intel MAX 10 Devices (Uncompressed .rbf)
—Internal Configuration Time for Intel MAX 10 Devices (Compressed .rbf)
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
67
Date Version Changes
January 2016 2016.01.22 • Added description about automotive temperature devices in the Programming/Erasure Specifications table.
• Changed the pin capacitance to maximum values.
• Updated maximum TCCS specifications from 410 ps to 300 ps in the following tables:
— True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated RSDS_E_1R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
— Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
• Added new table: True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Single Supply
Devices.
• Updated maximum fHSCLK and HSIODR specifications for –A6, –C7, and –I7 speed grades in True LVDS Transmitter Timing
Specifications for Intel MAX 10 Dual Supply Devices table.
• Updated SW specifications in the following tables:
— LVDS Receiver Timing Specifications for Intel MAX 10 Single Supply Devices
— LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices
• Updated maximum fHSCLK and HSIODR (high-speed I/O performance pin) specifications for –I6, –A6, –C7, –I7 speed
grades in LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices
table.
• Removed Internal Configuration Time information in the Uncompressed .rbf Sizes for Intel MAX 10 Devices table.
•Added Internal Configuration Time tables for uncompressed .rbf files and compressed .rbf files.
• Removed Preliminary tags for all tables.
November 2015 2015.11.02 • Added description to Maximum Allowed Overshoot During Transitions over a 11.4-Year Time Frame topic.
•Added ADC_VREF Pin Leakage Current for Intel MAX 10 Devices table.
• Updated the condition for "Bus-hold high, sustaining current" parameter from "VIN < VIL (minimum)" to "VIN < VIH
(minimum)" in Bus Hold Parameters table.
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
68
Date Version Changes
• Added –A6 speed grade in the following tables:
— Intel MAX 10 Device Grades and Speed Grades Supported
— Series OCT without Calibration Specifications for Intel MAX 10 Devices
— Clock Tree Specifications for Intel MAX 10 Devices
— Embedded Multiplier Specifications for Intel MAX 10 Devices
— Memory Block Performance Specifications for Intel MAX 10 Devices
— True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated RSDS_E_1R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices
— IOE Programmable Delay on Row Pins for Intel MAX 10 Devices
— IOE Programmable Delay on Column Pins for Intel MAX 10 Devices
• Updated the maximum value for input clock cycle-to-cycle jitter (tINJITTER_CCJ) with FINPFD < 100 MHz condition from 750 ps
to ±750 ps in PLL Specifications for Intel MAX 10 Devices table.
• Updated the dual supply mode performance in Embedded Multiplier Specifications for Intel MAX 10 Devices table.
• Updated the dual supply mode performance in Memory Block Performance Specifications for Intel MAX 10 Devices table.
• Added typical specifications in Internal Oscillator Frequencies for Intel MAX 10 Devices table.
• Updated specifications in UFM Performance Specifications for Intel MAX 10 Devices table.
• Updated sampling window specifications in LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for
Intel MAX 10 Dual Supply Devices table.
• Updated IOE programmable delay for row and column pins.
• Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.12 • Updated the maximum values in Internal Weak Pull-Up Resistor for Intel MAX 10 Devices table.
• Removed Internal Weak Pull-Up Resistor equation.
• Updated the note for input resistance and input capacitance parameters in the ADC Performance Specifications table for
both single supply and dual supply devices. Note: Download the SPICE models for simulation.
• Added a note to AC Accuracy - THD, SNR, and SINAD parameters in the ADC Performance Specifications for Intel MAX 10
Dual Supply Devices table. Note: When using internal VREF, THD = 66 dB, SNR = 58 dB and SINAD = 57.5 dB for
dedicated ADC input channels.
• Updated clock period jitter and cycle-to-cycle period jitter parameters in the Memory Output Clock Jitter Specifications for
Intel MAX 10 Devices table.
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
69
Date Version Changes
May 2015 2015.05.04 • Updated a note to VCCIO for both single supply and dual supply power supplies recommended operating conditions tables.
Note updated: VCCIO for all I/O banks must be powered up during user mode because VCCIO I/O banks are used for the
ADC and I/O functionalities.
• Updated Example for OCT Resistance Calculation after Calibration at Device Power-Up.
• Removed a note to BLVDS in Differential I/O Standards Specifications for Intel MAX 10 Devices table. BLVDS is now
supported in Intel MAX 10 single supply devices. Note removed: BLVDS TX is not supported in single supply devices.
• Updated ADC Performance Specifications for both single supply and dual supply devices.
— Changed the symbol for Operating junction temperature range parameter from TA to TJ.
— Edited sampling rate maximum value from 1000 kSPS to 1 MSPS.
— Added a note to analog input voltage parameter.
— Removed input frequency, fIN specification.
— Updated the condition for DNL specification: External VREF, no missing code. Added DNL specification for condition:
Internal VREF, no missing code.
— Added notes to AC accuracy specifications that the value with prescalar enabled is 6dB less than the specification.
— Added a note to On-Chip Temperature Sensor (absolute accuracy) parameter about the averaging calculation.
• Updated ADC Performance Specifications for Intel MAX 10 Single Supply Devices table.
— Added condition for On-Chip Temperature Sensor (absolute accuracy) parameter: with 64 samples averaging.
• Updated ADC Performance Specifications for Intel MAX 10 Dual Supply Devices table.
— Updated Digital Supply Voltage minimum value from 1.14 V to 1.15 V and maximum value from 1.26 V to 1.25 V.
• Updated fHSCLK and HSIODR specifications for –A7 speed grade in the following tables:
— True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
— Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— LVDS Receiver Timing Specifications for Intel MAX 10 Single Supply Devices
— LVDS, TMDS, HiSpi, SLVS, and Sub-LVDS Receiver Timing Specifications for Intel MAX 10 Dual Supply Devices
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
70
Date Version Changes
• Updated TCCS specifications in the following tables:
— True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated RSDS_E_1R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Single Supply Devices
— Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
• Updated tx Jitter specifications in the following tables:
— True PPDS and Emulated PPDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True RSDS and Emulated RSDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated RSDS_E_1R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True Mini-LVDS and Emulated Mini-LVDS_E_3R Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— True LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
— Emulated LVDS_E_3R, SLVS, and Sub-LVDS Transmitter Timing Specifications for Intel MAX 10 Dual Supply Devices
• Updated SW specifications in LVDS Receiver Timing Specifications for Intel MAX 10 Single Supply Devices table.
• Added a note to tx Jitter for all LVDS tables. Note: TX jitter is the jitter induced from core noise and I/O switching noise.
•Updated the description for tLOCK for all LVDS tables: Time required for the PLL to lock, after CONF_DONE signal goes high,
indicating the completion of device configuration.
• Updated Memory Output Clock Jitter Specifications section.
— Updated maximum external memory interfaces frequency from 300 MHz to 303 MHz.
— Updated PLL output routing from global clock network to PHY clock network.
• Added I/O Timing for Intel MAX 10 Devices table.
• Added VHYS in the Glossary table.
January 2015 2015.01.23 • Removed a note to VCCA in Power Supplies Recommended Operating Conditions for Intel MAX 10 Dual Supply Devices
table. This note is not valid: All VCCA pins must be connected together for EQFP package.
• Corrected the maximum value for tOUTJITTER_CCJ_ IO (FOUT ≥ 100 MHz) from 60 ps to 650 ps in PLL Specifications for Intel
MAX 10 Devices table.
December 2014 2014.12.15 • Restructured Programming/Erasure Specifications for Intel MAX 10 Devices table to add temperature specifications that
affect the data retention duration.
• Added statements in the I/O Pin Leakage Current section: Input channel leakage of ADC I/O pins due to hot socket is up
to maximum of 1.8 mA. The input channel leakage occurs when the ADC IP core is enabled or disabled. This is applicable
to all Intel MAX 10 devices with ADC IP core, which are 10M04, 10M08, 10M16, 10M25, 10M40, and 10M50 devices. The
ADC I/O pins are in Bank 1A.
• Added a statement in the I/O Standards Specifications section: You must perform timing closure analysis to determine the
maximum achievable frequency for general purpose I/O standards.
continued...
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
71
Date Version Changes
• Updated SSTL-2 Class I and II I/O standard specifications for JEDEC compliance as follows:
— VIL(AC) Max: Updated from VREF – 0.35 to VREF – 0.31
— VIH(AC) Min: Updated from VREF + 0.35 to VREF + 0.31
• Added a note to BLVDS in Differential I/O Standards Specifications for Intel MAX 10 Devices table: BLVDS TX is not
supported in single supply devices.
• Added a link to MAX 10 High-Speed LVDS I/O User Guide for the list of I/O standards supported in single supply and dual
supply devices.
• Added a statement in PLL Specifications for Intel MAX 10 Single Supply Device table: For V36 package, the PLL
specification is based on single supply devices.
• Added Internal Oscillator Specifications from Intel MAX 10 Clocking and PLL User Guide.
• Added UFM specifications for serial interface.
• Updated total harmonic distortion (THD) specifications as follows:
— Single supply devices: Updated from 65 dB to –65 dB
— Dual supply devices: Updated from 70 dB to –70 dB (updated from 65 dB to –65 dB for dual function pin)
• Added condition for On-Chip Temperature Sensor—Absolute accuracy parameter in ADC Performance Specifications for
Intel MAX 10 Dual Supply Devices table. The condition is: with 64 samples averaging.
• Updated the description in Periphery Performance Specifications to mention that proper timing closure is required in
design.
• Updated HSIODR and fHSCLK specifications for x10 and x7 modes in True LVDS Transmitter Timing Specifications for Intel
MAX 10 Dual Supply Devices.
• Added specifications for low-speed I/O performance pin sampling window in LVDS Receiver Timing Specifications for Intel
MAX 10 Single Supply Devices table: Max = 900 ps for –C7, –I7, –A7, and –C8 speed grades.
• Added tRU_nCONFIG and tRU_nRSTIMER specifications for different devices in Remote System Upgrade Circuitry Timing
Specifications for Intel MAX 10 Devices table.
• Removed the word "internal oscillator" in User Watchdog Timer Specifications for Intel MAX 10 Devices table to avoid
confusion.
• Added IOE programmable delay specifications.
September 2014 2014.09.22 Initial release.
Intel® MAX® 10 FPGA Device Datasheet
M10-DATASHEET | 2018.06.29
Intel® MAX® 10 FPGA Device Datasheet
72
