AD7685BCP - Analog Devices, Inc.

REV. Pr H

Preliminary Technical Data

PRELIMINARY TECHNICAL DATA

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

AD7685*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2004

16-BIT, 250kSPS PulSAR

ADC in ␮SO/CSP

FUNCTIONAL BLOCK DIAGRAM

SDO

GND

OVDD

REF

IN-

SWITCHED

CAP DAC

AD7685

IN+

SCK

CONTROL

LOGIC

CNV

CLOCK

SDI

VDD

FEATURES

16-bit Resolution with No Missing Codes

Throughput: 250kSPS

INL: ⴞⴞ

ⴞⴞ

ⴞ1LSB Typ, ⴞⴞ

ⴞⴞ

ⴞ3LSB Max (ⴞⴞ

ⴞⴞ

ⴞ0.0046 % of FSR)

S/(N+D): 90dB Typ @ 20kHz

THD: –106dB Typ @ 20kHz

Pseudo-Differential Analog input range:

0V to VREF with VREF up to VDD

No Pipeline Delay

Single Supply Operation 2V to 5.5V with

1.8V/2.5V/3V/5V logic interface

Daisy Chain Multiple ADCs and Busy Indicator

Serial Interface SPI/QSPI/␮Wire/DSP compatible

Typical Power Dissipation:

2.25mW @ 3V/100kSPS, 13mW @ 5V/250ksps,

1.8␮W @ 2.5V/100SPS

Stand-by current: 1 nA Typ

10-pin Package: ␮-SOIC ( ␮-SO8 size ) and

CSP ( 3mm x 3mm same space as SOT-23 )

Pin-for-Pin Compatible with the AD7686, AD7687,

AD7688

APPLICATIONS

Battery Powered Equipment

Data Acquisition

Instrumentation

Medical Instruments

Process Control

GENERAL DESCRIPTION

The AD7685 is a 16-bit, 250kSPS, charge redistribution

successive-approximation, Analog-to-Digital Converter

which operates from a single power supply, VDD, be-

tween 2V to 5.5V. It contains a very low power high-speed

16-bit sampling ADC with no missing codes, an internal

conversion clock and a versatile serial interface port. The

part also contains a low noise, wide bandwidth, very short

aperture delay track/hold circuit. On the CNV rising

edge, it samples an analog input IN+ between 0V to REF

with respect to a ground sense IN-. The reference voltage

REF is applied externally and can be set up to the supply

voltage.

Its power scales linearly with throughput.

The SPI compatible serial interface also features the abil-

ity, using the SDI input, to “Daisy chain” several ADCs

on a single 3 wire bus and provides an optional Busy indi-

cator. It is compatible with 1.8V, 2.5V, 3V or 5V logic

using the separate supply OVDD.

The AD7685 is housed in a 10-lead ␮SOIC or 10-lead

CSP (Chip Scale package) with operation specified from

–40°C to +85°C.

*Patent pending.

␮␮

␮SO, CSP/SOT23 16 Bit PulSAR ADC

Type 100 kSPS 250 kSPS 500 kSPS

True AD7684 AD7687 AD7688

Differential

Pseudo AD7683 AD7685 AD7686

Differential

Unipolar AD7680

PRELIMINARY TECHNICAL DATA

REV. Pr H –2–

AD7685–SPECIFICATIONS

Parameter Conditions Min Typ Max Unit

RESOLUTION 16 Bits

ANALOG INPUT

Voltage Range IN+ - IN- 0 VREF V

Absolute Input Voltage I N + –0.1 VDD + 0.3 V

IN- –0.1 TBD V

Analog Input CMRR fIN = TBD kHz T B D d B

Leakage Current at 25 ⴗC acquisition phase T B D nA

Input Impedance See Analog Input Section

DC ACCURACY

No Missing Codes 16 Bits

Differential Linearity Error – 1 ±0.7 +TBD LSB1

Integral Linearity Error – 3 ± 1 + 3 L S B

Transition Noise REF = VDD = 5V 0.7 L S B

Gain Error2, TMIN to TMAX ±TBD % of FSR

Gain Error Temperature Drift ±TBD ppm/°C

Offset Error2, TMIN to TMAX high bandwidth ±TBD ±TBD LSB

Offset Temperature Drift ±TBD ppm/°C

Power Supply Sensitivity VDD = VDD ± 5% ±TBD LSB

THROUGHPUT

Conversion rate 4µs

0 250 kSPS

Transient Response Full-Scale Step 1.5 µ s

AC ACCURACY

Signal-to-Noise fIN = 20 kHz, VREF=5V 88 90 dB3

Spurious Free Dynamic Range fIN = 20 kHz 106 d B

Total Harmonic Distortion fIN = 20 kHz –106 TB D dB

Signal-to-(Noise+Distortion) fIN = 20 kHz, VREF=5V 88 90 dB

IN = 20 kHz,–60 dB Input 3 0 d B

Intermodulation Distortion

Second Order Terms T B D d B

Third Order Terms TBD dB

REFERENCE

Voltage Range 0.5 VDD+0.3 V

Load Current 250kSPS, VIN+-VIN- = VREF/2 TBD µA

SAMPLING DYNAMICS

–3 dB Input Bandwidth Low Bandwidth 2 M H z

High Bandwidth 9 M H z

Aperture Delay TBD ns

Aperture Jitter T B D ps rms

DIGITAL INPUTS

Logic Levels

VIL – 0 . 3 0.3 * OVDD V

VIH 0.7 * OVDD OVDD + 0.3 V

IIL –1 +1 µA

IIH –1 +1 µA

DIGITAL OUTPUTS

Data Format Serial 16-Bits Straight Binary

Pipeline Delay Conversion Results Available Immediately

After Completed Conversion

VOL ISINK = 500 µA 0.4 V

VOH ISOURCE = –500 µA OVDD – 0.3 V

NOTES

LSB means Least Significant Bit. With the 5 V input range, one LSB is 76.3 µV.

See Definition of Specifications section. These specifications do include full temperature range variation but do not include the error contribution

from the external reference.

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.

Specifications subject to change without notice.

( VDD = 2.3V to 5.5 V, OVDD = 2.3V to VDD, VREF = VDD, TA = -40ⴗⴗ

ⴗⴗ

ⴗC to +85ⴗⴗ

ⴗⴗ

ⴗC, unless

otherwise noted.)

PRELIMINARY TECHNICAL DATA

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–3–

AD7685

( VDD = 2.3V to 5.5 V, OVDD = 2.3V to VDD, VREF = VDD, TA = -40ⴗⴗ

ⴗⴗ

ⴗC to +85ⴗⴗ

ⴗⴗ

ⴗC, unless otherwise noted.)

Parameter Conditions Min Typ Max Unit

POWER SUPPLIES

VDD Specified Performance 2 . 3 5 . 5 V

OVDD Specified Performance 2.3 VDD + 0.3 V

VDD Range 2 5.5 V

OVDD Range 1.8 5.5 V

Operating Current 250 kSPS Throughput

V D D VDD = 5V T B D m A

OVDD OVDD = 3.3V T B D µ A

Standby Current4,5 VDD and OVDD = 5V, 25°C 1 T B D nA

Power Dissipation VDD= 2.5V, 100SPS Throughput41.8 µ W

VDD= 3V, 100kSPS Throughput 2.25 T B D m W

VDD= 5V, 250kSPS Throughput 1 3 T B D m W

TEMPERATURE RANGE6

Specified Performance TMIN to TMAX –40 +85 °C

NOTES

With all digital inputs forced to OVDD or GND as required.

During acquisition phase.

Contact Analog Devices for extended temperature range.

Specifications subject to change without notice.

PRELIMINARY TECHNICAL DATA

REV. Pr H –4–

AD7685–SPECIFICATIONS

NOTES

Specifications subject to change without notice.

TIMING SPECIFICATIONS

Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data available t

CONV

1.1 2.5 µs

Acquisition Time t

ACQ

1.5 µs

Time Between Conversions t

CYC

4µs

CNV Pulse width ( CS mode ) t

CNVH

5ns

SCK Period t

SCK

15 ns

SCK Low Time t

SCKH

7ns

SCK High Time t

SCKL

7ns

SCK Falling Edge to Data remains Valid t

HSDO

5ns

SCK Falling Edge to Data Valid delay t

DSDO

OVDD above 4.75V 13 ns

OVDD above 3V 20 ns

OVDD above 2.7V 27 ns

OVDD above 2.3V TBD ns

CNV or SDI Low to SDO D15 MSB Valid (CS mode) t

OVDD above 4.75V 15 ns

OVDD above 2.7V 30 ns

OVDD above 2.3V TBD ns

CNV or SDI High or last SCK Falling Edge

to SDO High Impedance (CS mode) t

DIS

30 ns

SDI valid Setup Time from CNV rising edge (CS mode) t

SSDICNV

8ns

SDI valid Hold Time from CNV rising edge (CS mode) t

HSDICNV

0ns

SCK valid Setup Time from CNV rising edge (Chain mode) t

SSCKCNV

8ns

SCK valid Hold Time from CNV rising edge (Chain mode) t

HSCKCNV

5ns

SDI valid Setup Time from SCK falling edge (Chain mode) t

SSDISCK

8ns

SDI valid Hold Time from SCK falling edge (Chain mode) t

HSDISCK

0ns

SDI High to SDO High (Chain mode with Busy indicator) t

DSDOSDI

OVDD above 4.75V 15 ns

OVDD above 2.7V 30 ns

OVDD above 2.3V TBD ns

(–40OC to +85OC, VDD = 4.5 V to 5.5V, OVDD = 2.3 V to 5.5 V, unless otherwise stated)

PRELIMINARY TECHNICAL DATA

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–5–

AD7685

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD7685 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high-energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of

functionality.

ABSOLUTE MAXIMUM RATINGS

Analog Inputs

IN+

, IN-, REF, . . . . . . GND –0.3 V to VDD + 0.3 V

Supply Voltages

VDD, OVDD to GND . . . . . . . . . . . . . . . . -0.3 V to 7 V

VDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 V

Digital Inputs to GND . . . . . . –0.3 V to OVDD + 0.3 V

Digital Outputs to GND . . . . –0.3 V to OVDD + 0.3 V

Storage Temperature Range . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Thermal Impedance . . . . . . . . . . 200°C/W (␮SOIC-10)

Thermal Impedance . . . . . . . . . . . 44°C/W (␮SOIC-10)

TBD°C/W (CSP-10)

Lead Temperature Range

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only; functional operation of the device

at these or any other conditions above those indicated in the operational section of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

See Analog Input section.

AD7685 PIN CONFIGURATION

10-Lead ␮SOIC and 10-Lead CSP

OVDD

SDI

SCK

SDO

CNV

REF

VDD

IN+

IN-

GND

AD7685

To SDO

IOL

50pF

IOH

+1.4V

500µA

Figure 1. Load Circuit for Digital Interface Timing.

30% OVDD

70% OVDD

2V or OVDD-0.5V

0.8V or 0.5V

2V or OVDD-0.5V

DELAY

Note

: 2V if OVDD above 2.5V, OVDD-0.5V if OVDD below 2.5V.

Note

: 0.8V if OVDD above 2.5V, 0.5V if OVDD below 2.5V.

Figure 2. Voltage Reference Levels for Timing.

WARNING!

ING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Model Temperature Range Package Description Package Option Brand

AD7685BRM –40°C to +85°C ␮SOIC-10 RM-10 C01

AD7685BRMRL7 –40°C to +85°C ␮SOIC-10 RM-10 (reel) C01

AD7685BCP –40°C to +85°C CSP-10 C01

EVAL-AD7685CB1Evaluation Board

EVAL-CONTROL BRD22Controller Board

EVAL-CONTROL BRD32Controller Board

NOTES

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration

purposes.

These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

PRELIMINARY TECHNICAL DATA

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AD7685

–6–

Pin # Mnemonic Function

1 R E F A I Reference Input Voltage. The REF range is from 0.5V to VDD. It is referred to the

GND pin. This pin should be decoupled closely to the pin with a 10␮F capacitor.

2 V D D P Power Supply.

3 I N + A I Analog Input. It is referred to IN-. The voltage range, i.e. the difference between IN+

and IN-, is 0V to VREF.

4 I N - A I Analog Input Ground Sense. To be connected to the analog ground plane or to a remote

sense ground.

5 G N D P Power Supply Ground.

6 C N V D I Convert Input. This input has multiple functions. On its leading edge, it initiates the

conversions and selects the interface mode of the part, Chain or CS mode. In CS mode, it

enables the SDO pin when low. In Chain mode, the data should be read when CNV is

high.

7 S D O D O Serial Data Output. The conversion result is ouput on this pin. It is synchronized to SCK.

8 S C K D I Serial Data Clock Input. When the part is selected, the conversion result is shifted out by

this clock.

9 S D I D I Serial Data Input. This input provides multiple features. It selects the interface mode of

the ADC as follows:

Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is

used as a data input to daisy chain the conversion results of two or more ADCs onto a

single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK

cycles.

CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI

or CNV can enable the serial output signals when low and if SDI or CNV is low when the

conversion is complete, the busy indicator feature is enabled.

10 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host

interface (1.8V, 2.5V, 3V or 5V).

NOTES

AI = Analog Input

DI = Digital Input

DO = Digital Output

P = Power

PIN FUNCTION DESCRIPTIONS

PRELIMINARY TECHNICAL DATA

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AD7685

–7–

DEFINITION OF SPECIFICATIONS

INTEGRAL NONLINEARITY ERROR (INL)

Linearity error refers to the deviation of each individual

code from a line drawn from “negative full scale” through

“positive full scale”. The point used as “negative full

scale” occurs 1/2 LSB before the first code transition.

“Positive full scale” is defined as a level 1 1/2 LSB beyond

the last code transition. The deviation is measured from the

middle of each code to the true straight line (figure 4).

DIFFERENTIAL NONLINEARITY ERROR (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differ-

ential nonlinearity is the maximum deviation from this

ideal value. It is often specified in terms of resolution for

which no missing codes are guaranteed.

OFFSET ERROR

The first transition should occur at a level 1/2 LSB above

analog ground (38.1 ␮V for the

0 V to 5

V range). The

offset error is the deviation of the actual transition from

that point.

GAIN ERROR

The last transition (from 111 . . . 10 to 111 . . . 11)

should occur for an analog voltage 1 1/2 LSB below the

nominal full scale (4.999886 V for the

0 V to 5

V range).

The gain error is the deviation of the actual level of the

last transition from the ideal level after the offset has been

adjusted out.

SPURIOUS FREE DYNAMIC RANGE (SFDR)

The difference, in decibels (dB), between the rms ampli-

tude of the input signal and the peak spurious signal.

EFFECTIVE NUMBER OF BITS (ENOB)

ENOB is a measurement of the resolution with a sine

wave input. It is related to S/(N+D) by the following for-

mula:

ENOB = (S/[N+D]

– 1.76)/6.02)

and is expressed in bits.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first five har-

monic components to the rms value of a full-scale input

signal and is expressed in dB.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the actual input signal

to the rms sum of all other spectral components below the

Nyquist frequency, excluding harmonics and dc. The

value for SNR is expressed in dB.

SIGNAL TO (NOISE + DISTORTION) RATIO

(S/[N+D])

S/(N+D) is the ratio of the rms value of the actual input

signal to the rms sum of all other spectral components

below the Nyquist frequency, including harmonics but

excluding dc. The value for S/(N+D) is expressed in dB.

APERTURE DELAY

Aperture delay is a measure of the acquisition performance

and is the time between the rising edge of the CNV input

and when the input signal is held for a conversion.

TRANSIENT RESPONSE

The time required for the AD7685 to accurately acquire

its input after a full-scale step function was applied.

PRELIMINARY TECHNICAL DATA

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AD7685

–8–

CIRCUIT INFORMATION

The AD7685 is a fast, low-power, single-supply, precise

16-bit analog-to-digital converter (ADC) using a succes-

sive approximation architecture.

The AD7685 is capable of converting 250,000 samples

per second (250kSPS) and powers down between conver-

sions. When operating at 100SPS, for example, it

consumes typically 1.8␮W with a 2.5V supply, ideal for

battery-powered applications.

The AD7685 provides the user with an on-chip track/hold

and does not exhibit any pipeline delay or latency, making

it ideal for multiple multiplexed channel applications.

The AD7685 can be operated from a single 2V to 5.5V

supply, specified from 2.3V to 5.5V, and can be interfaced

to either 5 V or 3.3 V or 2.5 V or 1.8V digital logic. It is

housed in a 10-lead ␮SO or a tiny 10-lead CSP (chip

scale package) that combines space savings and allows

flexible configurations.

It is pin-for-pin-compatible with the AD7686, AD7687

and AD7688.

CONVERTER OPERATION

The AD7685 is a successive approximation ADC based on

a charge redistribution DAC. Figure 3 shows the simpli-

fied schematic of the ADC. The capacitive DAC consists

of two identical arrays of 16 binary weighted capacitors

which are connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to

the comparator’s input are connected to GND via SW+

and SW-. All independent switches are connected to the

analog inputs. Thus, the capacitor arrays are used as sam-

pling capacitors and acquire the analog signal on the IN+

and IN- inputs. When the acquisition phase is complete

and the CNV input goes high, a conversion phase is initi-

ated. When the conversion phase begins, SW+

and SW-

are opened first. The two capacitor arrays are then discon-

nected from the inputs and connected to the GND input.

Therefore, the differential voltage between the inputs IN+

and IN- captured at the end of the acquisition phase is

SW+

MSB

32,768C 16,384C 4C 2C C C

IN+

LSB

COMP

SW-

CONTROL

LOGIC

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

REF

GND

MSB

32,768C 16,384C 4C 2C C C

IN -

LSB

Figure 3. ADC Simplified Schematic

applied to the comparator inputs, causing the comparator

to become unbalanced. By switching each element of the

capacitor array between GND or REF, the comparator

input varies by binary weighted voltage steps (V

REF

/2,

REF

/4 . . . V

REF

/65536). The control logic toggles these

switches, starting with the MSB, in order to bring the

comparator back into a balanced condition. After the

completion of this process, the part returns to the acquisi-

tion phase and the control logic generates the ADC output

code and a BUSY signal indicator.

Because the AD7685 has an on-board conversion clock,

the serial clock SCK is not required for the conversion

process.

PRELIMINARY TECHNICAL DATA

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AD7685

–9–

Transfer Functions

The ideal transfer characteristic for the AD7685 is shown

in Figure 4 and Table I.

000...000

000...001

000...010

111...101

111...110

111...111

ADC CODE - Straight Binary

ANALOG INPUT

+FS-1.5 LSB

+FS-1 LSB

-FS+1 LSB-FS

-FS+0.5 LSB

Figure 4. ADC Ideal Transfer Function

Table I. Output Codes and Ideal Input Voltages

escription Analog Digital Output Code

Input Hexa

REF

= 5V

FSR –1 LSB 4.999924 V FFFF

Midscale + 1 LSB 2.500076 V 8001

Midscale 2.5 V 8000

Midscale – 1 LSB 2.499924V 7FFF

–FSR + 1 LSB 76.3µV 0001

–FSR 0 V 0000

NOTES

This is also the code for an overranged analog input (V

IN+

– V

IN-

above V

REF

– V

GND

This is also the code for an underranged analog input (V

IN+

– V

IN-

below V

GND

PRELIMINARY TECHNICAL DATA

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AD7685

–10–

DIGITAL INTERFACE

Though the AD7685 has a reduced number of pins, it

offers flexibility in its serial interface modes:

The AD7685, when in “CS mode”, is compatible with

SPI, QSPI digital hosts and DSPs (e.g.Blackfin ADSP-

BF53x or ADSP-219x). This interface can use either 3 or

4 wires. A three wire interface using the CNV, SCK and

SDO signals, minimizes wiring connections useful, for

instance, in isolated applications. A four wire interface

using the SDI, CNV, SCK and SDO signals allows CNV,

which initiates the conversions, to be independent of the

readback timing (SDI). This is useful in low jitter sam-

pling or simultaneous sampling applications.

The AD7685, when in “Chain mode”, provides a “daisy

chain” feature using the SDI input for cascading multiple

ADCs on a single data line similar to a shift register.

The mode in which the part operates depends on the SDI

level when the CNV rising edge occurs. The CS mode is

selected if SDI is high and the chain mode is selected if

SDI is low. The SDI hold time is such that when SDI and

CNV are connected together, the chain mode is always

selected.

In either mode, the AD7685 offers the flexibility to op-

tionally force a start bit in front of the data bits. This start

bit can be used as a busy signal indicator to interrupt the

digital host and trigger the data reading. Otherwise, with-

out a busy indicator, the user must time out the maximum

conversion time prior to readback.

The busy indicator feature is enabled as follows:

In CS mode, if CNV or SDI is low when the ADC con-

version ends (figure 8 and 12).

In Chain mode, if SCK is high during the CNV rising

edge (figure 16).

SDO D15 D14 D13 D1 D0

tDIS

SCK 1 2 3 14 15 16

tSCK

tSCKL

tSCKH

tHSDO

tDSDO

CNV

tEN

CONVERSIONACQUISITION

tCONV

tCYC

tACQ

ACQUISITION

SDI = 1

tCNVH

Figure 6.

mode 3 wires, no busy indicator serial interface timing ( SDI high ).

CSCS

CS MODE 3 wires, no Busy indicator

This mode is usually used when a single AD7685 is con-

nected to an SPI compatible digital host. The connection

diagram is shown in figure 5 and the corresponding tim-

ing is given in figure 6.

With SDI tied to OVDD, a rising edge on CNV initiates

a conversion, selects the CS mode and forces SDO to

high impedance. Once a conversion is initiated, it will

continue to completion irrespective of the state of CNV.

For instance, it could be useful to bring CNV low to se-

lect other SPI devices such as analog multiplexers but

CNV must be returned high before the minimum conver-

sion time and held high until the maximum conversion

time to avoid the generation of the busy signal indicator.

When the conversion is complete, the AD7685 enters the

acquisition phase and powers down. When CNV goes low,

the MSB is output onto SDO. The remaining data bits

are then clocked by subsequent SCK falling edges. The

data is valid on both SCK edges. Although the rising edge

can be used to capture the data, a digital host also using

the SCK falling edge will allow a faster reading rate pro-

vided it has an acceptable hold time. After the 16th SCK

falling edge or when CNV goes high, whichever is earlier,

SDO returns to high impedance.

CNV

SCK

SDOSDI DATA IN

CLK

CONVERT

OVDD

Digital Host

AD7685

Figure 5.

mode 3 wires, no busy indicator connection

diagram ( SDI high ).

PRELIMINARY TECHNICAL DATA

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–11–

SDO D15 D14 D1 D0

tDIS

SCK 1 2 3 15 16 17

tSCK

tSCKL

tSCKH

tHSDO

tDSDO

CNV

CONVERSIONACQUISITION

tCONV

tCYC

tCNVH

tACQ

ACQUISITION

SDI = 1

Figure 8.

mode 3 wires with busy indicator serial interface timing ( SDI high ).

CSCS

CS MODE 3 wires with Busy indicator

This mode is usually used when a single AD7685 is con-

nected to an SPI compatible digital host having an

interrupt input.

The connection diagram is shown in figure 7 and the cor-

responding timing is given in figure 8.

With SDI tied to OVDD, a rising edge on CNV initiates

a conversion, selects the CS mode and forces SDO to

high impedance. SDO is maintained in high impedance

until the completion of the conversion irrespective of the

state of CNV. Prior to the minimum conversion time,

CNV could be used to select other SPI devices such as

analog multiplexers but CNV must be returned low before

the minimum conversion time and held low until the

maximum conversion time to guarantee the generation of

the busy signal indicator. When the conversion is com-

plete, SDO goes from high impedance to low. With a

pull-up on the SDO line, this transition can be used as an

interrupt signal to initiate the data reading controlled by

the digital host. The AD7685 then enters the acquisition

phase and powers down. The data bits are then clocked

out, MSB first, by subsequent SCK falling edges. The

data is valid on both SCK edges. Although the rising edge

can be used to capture the data, a digital host also using

the SCK falling edge will allow a faster reading rate pro-

vided it has an acceptable hold time. After the optional

17th SCK falling edge or when CNV goes high whichever

is earlier, SDO returns to high impedance.

IRQ

CNV

SCK

SDOSDI DATA IN

CLK

CONVERT

OVDD

47k⍀OVDD

Digital Host

AD7685

Figure 7.

mode 3 wires with busy indicator connection

diagram ( SDI high ).

PRELIMINARY TECHNICAL DATA

REV. Pr H

AD7685

–12–

CNV

SCK

SDOSDI

DATA IN

CLK

CONVERT

Digital Host

AD7685

CNV

SCK

SDOSDI

AD7685

CS1

CS2

Figure 9.

mode 4 wires, no busy indicator connection diagram.

SDO D15 D14 D13 D1 D0

tDIS

SCK 123 30 31 32

tHSDO

tDSDO

tEN

CONVERSIONACQUISITION

tCONV

tCYC

tACQ

ACQUISITION

SDI(CS1)

CNV

tSSDICNV

tHSDICNV

14 15

tSCK

tSCKL

tSCKH

D0 D15 D14

17 1816

SDI(CS2)

Figure 10.

mode 4 wires, no busy indicator serial interfacetiming.

CSCS

CS MODE 4 wires, no Busy indicator

This mode is usually used when multiple AD7685’s are

connected to an SPI compatible digital host.

A connection diagram example using two AD7685’s is

shown in figure 9 and the corresponding timing is given in

figure 10.

With SDI high, a rising edge on CNV initiates a conver-

sion, selects the CS mode and forces SDO to high

impedance. In this mode, CNV must be held high during

the conversion phase and the subsequent data readback (if

SDI and CNV are low, SDO is driven low). Prior to the

minimum conversion time, SDI could be used to select

other SPI devices, such as analog multiplexers but SDI

must be returned high before the minimum conversion

time and held high until the maximum conversion time to

avoid the generation of the busy signal indicator. When

the conversion is complete, the AD7685 enters the acqui-

sition phase and powers down. Each ADC result can be

read by bringing low its SDI input which consequently

outputs the MSB onto SDO. The remaining data bits are

then clocked by subsequent SCK falling edges. The data

is valid on both SCK edges. Although the rising edge can

be used to capture the data, a digital host also using the

SCK falling edge will allow a faster reading rate provided

it has an acceptable hold time. After the 16th SCK falling

edge or when SDI goes high whichever is earlier, SDO

returns to high impedance and another AD7685 can be

read.

PRELIMINARY TECHNICAL DATA

REV. Pr H

AD7685

–13–

SDO

D15 D14 D1 D0

DIS

SCK

1 2 3 15 16 17

SCK

SCKL

SCKH

HSDO

DSDO

CONVERSIONACQUISITION

CONV

CYC

ACQ

ACQUISITION

SDI

CNV

SSDICNV

HSDICNV

Figure 12.

mode 4 wires with busy indicator serial interface timing.

CSCS

CS MODE 4 wires with Busy indicator

This mode is usually used when a single AD7685 is con-

nected to an SPI compatible digital host having an

interrupt input and it is desired to keep CNV, used to

sample the analog input, independent of the signal used to

select the data reading. This requirement is particularly

important in applications where low jitter on CNV is de-

sired.

The connection diagram is shown in figure 11 and the

corresponding timing is given in figure 12.

With SDI high, a rising edge on CNV initiates a conver-

sion, selects the CS mode and forces SDO to high

impedance. In this mode, CNV must be held high during

the conversion phase and the subsequent data readback (if

SDI and CNV are low, SDO is driven low). Prior to the

minimum conversion time, SDI could be used to select

other SPI devices, such as analog multiplexers but SDI

must be returned low before the minimum conversion

time and held low until the maximum conversion time to

guarantee the generation of the busy signal indicator.

When the conversion is complete, SDO goes from high

impedance to low. With a pull-up on SDO line, this tran-

sition can be used as an interrupt signal to intiate the data

readback controlled by the digital host. The AD7685 then

enters the acquisition phase and powers down. The data

bits are then clocked out, MSB first, by subsequent SCK

falling edges. The data is valid on both SCK edges. Al-

though the rising edge can be used to capture the data, a

digital also host using the SCK falling edge will allow a

faster reading rate provided it has an acceptable hold time.

After the optional 17th SCK falling edge or SDI going

high, whichever is earlier, the SDO returns to high im-

pedance.

CNV

SCK

SDOSDI DATA IN

CLK

CONVERT

OVDD

47k⍀

Digital Host

AD7685

CS1

IRQ

Figure 11.

mode 4 wires with busy indicator connection

diagram .

PRELIMINARY TECHNICAL DATA

REV. Pr H

AD7685

–14–

CNV

SCK

SDOSDI DATA IN

CLK

CONVERT

Digital Host

AD7685

CNV

SCK

SDOSDI

AD7685

Figure 13. Chain mode, no busy indicator connection diagram .

SDOA = SDIB

DA15 DA14 DA13

SCK

1 2 3 30 31 32

SSDISCK

HSDISC

CONVERSIONACQUISITION

CONV

CYC

ACQ

ACQUISITION

CNV

DA1

14 15

SCK

SCKL

SCKH

DA0

17 1816

SDIA = 0

SDOB

DB15 DB14 DB13 DA1D

A0DB1 DB0D

A15 DA14

HSDO

DSDO

SSCKCNV

HSCKCNV

Figure 14. Chain mode, no busy indicator Serial InterfaceTiming.

Chain MODE, no Busy indicator

This mode can be used to “daisy-chain” multiple

AD7685’s on a 3 wire serial interface. This feature is

useful for reducing component count and wiring connec-

tions e.g. in isolated multiconverter applications or for

systems with a limited interfacing capacity. Data readback

is analogous to clocking a shift register.

A connection diagram example using two AD7685’s is

shown in figure 13 and the corresponding timing is given

in figure 14.

When SDI and CNV are low, SDO is driven low. With

SCK low, a rising edge on CNV initiates a conversion,

selects Chain mode and disables the busy indicator. In this

mode, CNV is held high during the conversion phase and

the subsequent data readback. When the conversion is

complete, the MSB is output onto SDO and the AD7685

enters the acquisition phase and powers down. The re-

maining data bits stored in the internal shift register are

then clocked by subsequent SCK falling edges. For each

ADC, SDI feeds the input of the internal shift register and

is clocked by the SCK falling edge. Each ADC in the

chain output its data MSB first, and 16*N clocks are re-

quired to readback the N ADCs. The data is valid on both

SCK edges. Although the rising edge can be used to cap-

ture the data, a digital host also using the SCK falling

edge will allow a faster reading rate and, consequently

more AD7685s in the chain provided the digital host has

an acceptable hold time. The maximum conversion rate

may be reduced due to the total readback time. For in-

stance, with a 5ns digital host set-up time and 5V

interface, up to five AD7685’s running at a conversion

rate of 250 kSPS can be daisy-chained on a 3 wire port.

PRELIMINARY TECHNICAL DATA

REV. Pr H

AD7685

–15–

CNV

SCK

SDOSDI DATA IN

CLK

CONVERT

Digital Host

AD7685

CNV

SCK

SDOSDI

AD7685

A C

IRQ

CNV

SCK

SDOSDI

AD7685

Figure 15. Chain mode with busy indicator connection diagram .

SDOA = SDIB

DA15 DA14 DA13

SCK

123 35 47 48

CONVERSIONACQUISITION

CONV

CYC

ACQ

ACQUISITION

CNV = SDIA

DA1

415

SCK

SCKH

SCKL

DA0

17 3416

SDOB = SDIC

DB15 DB14 DB13 DA1D

A0DB1 DB0D

A15 DA14

SSDISCK

HSDISC

HSDO

DSDO

SDOC

DC15 DC14 DC13 DA1D

A0DC1 DC0D

A15 DA14

19 31 3218 33

DB1D

B0DB15 DB14

DSDOSDI

SSCKCNV

HSCKCNV

Figure 16. Chain mode with busy indicator serial interface timing.

Chain MODE with Busy indicator

This mode can also be used to “daisy-chain” multiple

AD7685’s on a 3 wire serial interface while providing a

busy indicator. This feature is useful for reducing compo-

nent count and wiring connections e.g. in isolated

multiconverter applications or for systems with a limited

interfacing capacity. Data readback is analogous to clock-

ing a shift register.

A connection diagram example using three AD7685’s is

shown in figure 15 and the corresponding timing is given

in figure 16.

When SDI and CNV are low, SDO is driven low. With

SCK high, a rising edge on CNV initiates a conversion,

selects Chain mode and enables the busy indicator feature.

In this mode, CNV is held high during the conversion

phase and the subsequent data readback. When all ADCs

in the chain have completed their conversions, the “near-

end” ADC ( ADC C in figure 15 ) SDO will be driven

high. This transition on SDO can be used as a busy indi-

cator to trigger the data readback controlled by the digital

host. The AD7685 then enters the acquisition phase and

powers down. The data bits stored in the internal shift

SCK falling edges. For each ADC, SDI feeds the input of

the internal shift register and is clocked by the SCK fall-

ing edge. Each ADC in the chain outputs its data MSB

first, and 16*N +1 clocks are required to readback the N

ADCs. Although the rising edge can be used to capture

the data, a digital host also using the SCK falling edge

will allow a faster reading rate and, consequently more

AD7685s in the chain provided the digital host has an

acceptable hold time. For instance, with a 5ns digital host

set-up time and 5V interface, up to five AD7685’s running

at a conversion rate of 250 kSPS can be daisy-chained to a

single 3 wire port.

PRELIMINARY TECHNICAL DATA

REV. Pr H

AD7685

–16–

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

10-Lead ␮SOIC

(RM-10)

0.011 (0.28)

0.003 (0.08)

0.120 (3.05)

0.112 (2.84)

0.022 (0.56)

0.021 (0.53)

6˚

0˚

10 6

0.0197 (0.50) BSC

0.124 (3.15)

0.112 (2.84)

0.124 (3.15)

0.112 (2.84)

0.199 (5.05)

0.187 (4.75)

PIN 1

0.122 (3.10)

0.110 (2.79)

0.006 (0.15)

0.002 (0.05)

0.016 (0.41)

0.006 (0.15)

0.038 (0.97)

0.030 (0.76)

SEATING

PLANE

0.043 (1.09)

0.037 (0.94)

10-Lead CSP

(CP-10)

Dimensions shown in mm.

3.00

BSC SQ

INDEX

AREA

TOP VIEW

1.50

BCS SQ

0.20 R

1.00

0.90

0.80 0.05 MAX

0.02 NOM

SEATING

PLANE 0.30

0.23

0.18

0.20 REF

1.00 MAX

0.65 TYP

1.74

1.64

1.49

2.48

2.38

2.23

10 6

0.50 BSC 0.50

0.40

0.30

0.23

EXPOSED PAD

(BOTTOM VIEW)