Rev. 0.6 11/12 Copyright © 2012 by Silicon Labo ratories Si537x-EVB
Si537x-EVB
Si537X-EVB EVALUATION BOARD USER’S GUIDE
Description
The Si5374/75/76 Any Frequency Precision Clocks are
based on Silicon Labs 3rd-generation DSPLL
technology, which provides any-frequency synthesis in
a highly integrated PLL solution that eliminates the need
for external VCXO and loop filter components. The
devices have excellent phase noise and jitter
performance. All of the devices support 350 fs RMS
jitter generatio n across the 12 kHz to 20 MH z jitter filter
bandwidth. For all devices, the DSPLL loop bandwidth
is digitally programmable, providing jitter performance
optimization at the application level. These devices are
ideal for providing clock multiplication/clock division and
jitter attenuation in mid-range and high-performance
timing applications where printed circuit board real
estate is at a premium.
Features
The Si537x-EVB includes the following:
CD with documentation and EVB software including
the Si537x_DSPLLsim configuration software utility.
EVB circuit board
Si537x-EVB User’s Guide (this document)
Functional Block Diagram
Control, monitor
D
C
B
A
Level
Translate CPLD
Si530
MCU EEPROM
Serial #Regulator
USB
3.3 V
I2C
SPI
OSC Ext Ref
Si537x
I2C
Si537x-EVB
2 Rev. 0.6
1. Introduction
The Si537x-EVB provides a platform for evaluating Silicon Labs’ Si5374, Si5375, and Si5376 Any Frequency
Precision Clocks. These devices are jitter attenuating quad DSPLLs that are microprocessor controlled using an
I2C interface. The Si5374 and the Si5376 have eight clock inputs and 8 clock outputs, whereas the Si5375 has 4
clock inputs and 4 clock outputs. The Si5 374 has the added feature of lower loop BW than the Si5375 and Si5376.
Figure 1. Si537x-EVB
Table 1. Si537x Selection Summary
Device # Input/
Output
Clocks
Frequency Range DSPLL Loop
Bandwidth
Range
Hitless Switching
VCO Freeze
Free Run
Digital H old
Package
Input Output
Si5374 8/8 2 kHz–710 MHz 2 kHz–808 MHz 4–525 Hz 10x10 mm
80-PBGA
Si5375 4/4 2 kHz–710 MHz 2 kHz–808 MHz 60 Hz–8.4 kHz  10x10 mm
80-PBGA
Si5376 8/8 2 kHz–710 MHz 2 kHz–808 MHz 60 Hz–8.4 kHz 10x10 mm
80-PBGA
Si537x-EVB
Rev. 0.6 3
2. Applications
The Si5374/75/76 Any Frequency Precision Clocks offer a comprehensive feature set, including any frequency
synthesis, jitter attenuation, fully integrated loop filter , multiple clock input s, multiple clock output s, alarm and st atus
outputs, hitless switching between multiple input clocks, programmable output clock format (LVPECL, LVDS, CML,
CMOS), and output phase adjustment between all output clocks. For more details, consult the Silicon Labs timing
products website at www.silabs.com/timing.
The Si537x-EVB has a Silicon Labs MCU (C8051F430) that supports USB communications with a PC host. The
Si5374/75/76 devices are controlled and monitored through the I2C serial port. A CPLD is connected to the MCU
and stores pin configuration data and reads the device status pins. The MCU communicates to the Si537x device
using I2C through a voltage level translator. However, the user has the option of bypassing the MCU and controlling
the devices from an external serial device. On-board termination is included so that the user can evaluate either
single-ended or differential as well as ac or dc coupled clock inputs and outputs. A separate DUT (device under
test) power supply con nector is include d. LEDs are provided for conven ient monitor of key st atus signals. The user
can select between a number of reference oscillator options, including external sources and various on-board
options.
For more detailed information about the app lications of these devices, please see their respective data shee ts.
3. Si5374/75/76-EVB Quick Start
For more detailed information about these devices, see their respective data sheets.
Si537x-EVB
4 Rev. 0.6
4. Functional Description
The Si537x-EVB and software allows for a complete and simple evaluation of the functions, features, and
performance of the Si5374/75/76 Any Frequency Precision Clocks. For the following material, refer to the
schematics in section “7. Schematics.”
4.1. Block Diagram
Figure 2. Si537x-EVB Block Diagram
Figure 2 is a block diagram of the evaluation board and it is helpful to refer to this diagram. The MCU
communicates to the host PC over a USB connection. The MCU controls and monitors the Si537x pins through the
CPLD, which provides level translation between the MCU and the Si537x. I2C level translation is provided
separately. A number of different options are provided for the required Si537x external reference oscillator.
4.2. Si537x Device
To minimize noise and crosstalk, the Si537x device has separate and filtered VDD supplies. Two-pin jumper plug s
(J16, J17, J25, and J33) are provided so that the distinct power supplies can be monitored.
4.3. Input Clocks
The input clocks are all located at the edge of the board. For each clock input pair, each input is ac terminated with
50 to ground. With this configuration, single ended inputs can be implemented by simply leaving the unused
clock input disconnected. If low frequency clock inputs are in use, the reactance of the 100 nf capacitors (C12,
C13, C14, etc.) can become significant and they should be replaced with 0 resistors. In some circumstances, the
ac termination should be re moved and r epla ced. CMOS in puts are typically best terminated by using series source
termination at the output of the CMOS driver and completely removin g all of the on-board input termination.
Regardless of the termination scheme in use, a scope should be used to verify that none of the clock input
specifications found in the data sheet are being violated.
Control, monitor
D
C
B
A
Level
Translate CPLD
Si530
MCU EEPROM
Serial #Regulator
USB
3.3 V
I2C
SPI
OSC Ext Ref
Si537x
I2C
Si537x-EVB
Rev. 0.6 5
4.4. Output clocks
The output clocks all use vertical mount SMA connectors and are ac coupled. There may be circumstances (e.g.,
CMOS outpu ts) for which the 100 n F capacitors should be repl aced wit h 0 resistors. Pads for resistors between
the two halves of the outputs are provided for CMOS outputs so that the outputs can be put in parallel for greater
drive strength.
4.5. OSC Reference Source
The Si537x requires a low-jitter reference on it s OSC_P and OSC_N input pins. To provide a clock sou rce, the user
has a number of different opt ion s:
1. The factory default configuration is a 121.109 MHz Si530 crystal oscillator (XO). For this configuration
install C78 and C81 (in the silkscreen XO box on the top of the board), remove C97 and C101 (in the INT
silkscreen box on th e bottom of the boar d), and remo ve C77 and C80 (in the silkscreen box EXT on the top
of the board). J50 should be removed and J60 should select the desired XO supply voltage of 3.3 V by
jumpering J60.2 to J60.3.
2. There are provisions for three different XO oscillator packages in industry standard pinouts: 5x7 mm,
3.2x5 mm, and 3.2x2.5 mm. If any of these are used, be sure to install C78 and C81 (in the silkscreen XO
box on the top of the board), remove C97 and C101 (in the INT silkscreen box on the bottom of the board),
and remove C77 and C8 0 (in the silkscree n box EXT on the top of the bo ard). J50 should be removed and
J60 should select the desired XO supply voltage of either the Si537x VDD or 3.3 V.
3. An off-board, external reference oscillator may be used instead of the Si530 XO. If this is desired, C98 and
C102 (in the CKIN silkscreen box on the bottom of the board), C101 and C97 (in the INT silkscreen box on
the bottom of the b oard), a nd C78 and C81 (in the silkscre en XO box on the to p of the board) sh ould all b e
removed and C77 and C80 (in the EXT silkscreen box on the top of the board) should be installed. If this
mode is selected, the clock input should be applied to J64 and J66. Both J50 and J60 should be removed
so that the other references sources are not powered and do not add noise.
4. A PCB footprint for a reference Si5326 is included on the EVB. If it is installed, the Si5326 is initialized by
the MCU and EEPROM so that it powers up with an output that is 114.285 MHz based on its crystal, X1.
The output of the Si5326 can be mo nitored at J65 and J67 and can be changed to most any frequency
using DSPLLsim . Free run at 114.285 MHz is the factory default Si5326 frequency plan. If a reference
OSC frequency in the
37–41 MHz band is to be used, be sure to set the RATE register (reg 2) for all of the DSPLLs to 0101.
For options 2 and 4 above, an external OSC reference XO in the 37–41 MHz frequency band can also be used.
With this approach, the output jitter will be higher by an amount that is illustrated in “AN591: Crystal Selection for
the Si5315 and Si5317,” Figures 3 and 4. It will also be necessary to create an Si537xDSPLLsim frequency plan
with the appropriate RATE_REG (at addr 2) setting of 0001.
It is also possible to have the reference Si5326 lock onto an external clock source instead of locking to its
114.285 MHz crystal in free run mode. If this mode is desir e d, ins tall C98 and C102 (in th e CKIN silkscreen box on
the bottom of the board) and then load the appropriate frequency plan into the reference Si5326 using DSPLLsim.
The external clock source is connected to J64 and J66. If the Si5326 is being used, J50 should be installed and
J60 should be remo ve d.
Though they will result in slightly lower performance, single ended reference clock inputs can be connected to J66,
with the unused J64 connected to ground. In all cases, when a single ended reference oscillator is in use, C53
(located close to the Si537x) should be installed.
Si537x-EVB
6 Rev. 0.6
4.6. CPLD
The CPLD provides various functions including level translation and the buffering of monitor/control of signals for
the Si537x DUT and the Si5326 reference source. Examples are the LOL, IRQ, and CS_CA signals from the
Si537x as well as the SPI port connection to the reference Si5326.
4.7. MCU
The MCU is the intermediary between the PC host and the Si537x DUT. The host’s USB port prov ides power for
the MCU and the LEDs through a 3.3 V regulator (U17). U6 provides I2C level translation to the DUT VDD voltage
level. U2 is an EEPROM that is used to initialize the reference Si5326. J51 is an I2C serial port connector by which
an external I 2C master can control the on-board Si537x or by which the on-board MCU can control an Si537x that
resides on a external target board.
4.8. Power and LEDs
J4 is the main Si537x power connector. Remote sensing for the power supply is provided by J3. DUT current can
be monitored by removing R1 and connecting to J7. U10 and U11 are buffers that are used to drive the LEDs. The
status outputs are available at J44/45.
Si537x-EVB
Rev. 0.6 7
5. Connectors and LEDs
Figure 3. Connectors, Top, and Bottom Views
J51 can be used as an attachment point for controlling the Si537x DUT from an external I2C master or to u se the
MCU to control an Si537x DUT that resides on an external target board.
To control the on-board Si537x from an external I2C master, disconnect the cable from the USB connector (J61),
thereby depriving the EVB of its 5 V power source. A lack of 3.3 V power will disable the U6 level translator (by
virtue of U6.8) so that the MCU will be isolated from the external I2C bus that should be ap plie d to J51.
To control an external Si537 x from the on-board MCU, the on-board Si537x must be held in reset so that it does not
assert either of the two I2C bus signals. This can be done by opening the Si537x Register Programmer and going
to the Options pull down menu on the top toolbar and selecting "Switch to External Control Mode.”
Top Bottom
J44, J45, status
J51, ext I2C
XO caps
J60, XO pwr
EXT caps
J50, Ref pwr
U1
INT cap s CKIN caps
Si537x-EVB
8 Rev. 0.6
J45 is used to make external connections to status signals:
Table 2. External I2C
J51 Name Comment
J51.1 SDA serial data
J51.3 SCL serial clock
J51.9 DUT_RST_L DUT reset
Table 3. Status
J45 Name Comment
J45.27 DUT_PWR +2.5 or 1.8 V
J45.25 REF_LOL
J45.23 IRQ_D
J45.21 IRQ_C
J45.19 IRQ_B
J45.17 IRQ_A
J45.15 CS_CA_D
J45.13 CS_CA_C
J45.11 CS_CA_B
J45.9 CS_CA_A
J45.7 LOL_D
J45.5 LOL_C
J45.3 LOL_B
J45.1 LOL_A
Si537x-EVB
Rev. 0.6 9
The LEDs are used to quickly determine the board status:
Table 4. LED Descriptions
LED Color Label
D17 yellow CS_CA_D
D16 yellow CS_CA_C
D15 yellow CS_CA_B
D14 yellow CS_CA_A
D13 red LOL_D
D12 red LOL_C
D11 red LOL_B
D10 red LOL_A
D9 red IRQ_D
D8 red IRQ_C
D7 red IRQ_B
D6 red IRQ_A
D5 green MCU_2
D4 green MCU_1
D3 red REF_LOL
D2 green 3.3 V
D1 green DUT_PWR
Si537x-EVB
10 Rev. 0.6
6. EVB Software Installation
The release notes and the procedure for installing the EVB software can be found on the release CD included with
the EVB. These items can also be downloaded from the Silabs web site: www.silabs.com/timing. Follow the links
for 4-PLL Jitter att en u at or s, an d loo k un de r the Tools tab.
Program Description
Si537x_DSPLLsim Provides the high level control of the Si537x device. It has the frequency planning wizard
as well as control of the pins in an organized, intuitive manner. Register maps and other
configuration files can be saved and opened.
Setting Utility This application allows for quick read/write access to each control word of the Si537x
device. It can save and open text files.
Register Prgmr Provides a low-level, hex register read/write capability on a byte basis (as opposed to
control word). Register map files can be opened and saved in its batch mode.
Register Viewer Displays the current register map data in a table format sorted by register address. Can
save and print the register map.
Si537x-EVB
Rev. 0.6 11
7. Schematics
VDD_D
VDD_B VDD_C
VDD_DVDD_A
DUT_PWR DUT_PWR
SDA
CKOUT1N_A
CS_CA_A
CKIN2P_A
CKIN2N_A CKOUT2N_A
CKOUT2P_A
CKIN1P_B
CKIN1N_B
CKOUT1P_A
CKOUT1N_B
CKOUT1P_B
LOL_A
CKIN2P_B
CKIN2N_B CKOUT2N_B
CKOUT2P_B
CKOUT1P_C
CKOUT1N_C
CKOUT2N_C
CKOUT2P_C
CKIN1P_C
CKIN1N_C
CKIN2P_C
CKIN2N_C
CKOUT1N_D
CKOUT1P_D
CKIN1N_D
CKIN1P_D
CKIN2P_D
CKIN2N_D
CKOUT2P_D
CKOUT2N_D
OSC_P
IRQ_A
OSC_N
LOL_B
IRQ_B
IRQ_C
LOL_C
IRQ_D
LOL_D
CS_CA_B
CS_CA_C
CKIN1P_A
CKIN1N_A
CS_CA_D
SCL
RSTD_L
RSTC_L
RSTB_L
RSTA_L
+
C119
220UF
NOPOP
+
C119
220UF
NOPOP
12
C17
10UF_805
C17
10UF_805
1
2
J16
NOPOP
A
J16
NOPOP
A
1 2
L3
Ferrite
L3
Ferrite
VddA1 C1
VddA2 B5
VddB2 A7
Gnd13
G1
Gnd1
B2
Gnd14
H2
Gnd15
J2
Gnd2
A3
Gnd3
B3
Gnd16
G2
Gnd4
E4
Gnd5
C8
Gnd9
H7
Gnd10
J7
Gnd6
A8
Gnd7
B8
CKIN1P_A
C2
CKIN1N_A
D2
CKIN2P_A
C3
CKOUT1P_A B1
CKOUT1N_A 2A
CKOUT2P_A A5
CKOUT2N_A A4
LOL_A E2
IRQ_A B4
RSTL_A
D4
OSC_P E5
OSC_N E6
CS_CA_A
D1
SCL
G5
SDA
G6
CKIN2N_A
D3
VddC1 F5
VddD1 F3
VddD2 J3
VddA3 C4
VddD3 E3
VddB1 D5
Gnd11
H8
Gnd8
C9
Gnd12
H9
VddB3 D7
VddC2 E7
VddC3 G9
CKIN2N_B
C6
CKIN1N_B
B6
CKIN1P_B
B7
CKIN2P_B
C7
CS_CA_B
A6
CKOUT1P_B A9
CKOUT1N_B B9
LOL_B C5
CKOUT2P_B E9
IRQ_B D8
CKOUT2N_B D9
CS_CA_C
F9
CKIN2P_C
G7
CKIN2N_C
F7
CKIN1P_C
G8
CKIN1N_C
F8
LOL_C E8
CKOUT2P_C J5
IRQ_C H6
CKOUT2N_C J6
CKOUT1N_C J8
CKOUT1P_C J9
CKIN1N_D
H4
CKIN2N_D
G4
CKIN1P_D
H3
CKIN2P_D
G3
CS_CA_D
J4
CKOUT1P_D J1
LOL_D H5
CKOUT1N_D H1
CKOUT2P_D E1
CKOUT2N_D F1
IRQ_D F2
RSTL_B
D6
RSTL_C
F6
RSTL_D
F4
A
B
C
D
U1 Si537x
A
B
C
D
U1 Si537x
C29
100N
C29
100N C44
100N
C44
100N
C115
100N
402
C115
100N
402
C45
100N
C45
100N
+
C116
220UF
NOPOP
+
C116
220UF
NOPOP
1
2
J17
NOPOP
B
J17
NOPOP
B
C113
100N
402
C113
100N
402
R3149.9 R3149.9
C19
100N
C19
100N
1 2
L4
Ferrite
L4
Ferrite
C27
100N
C27
100N
C53
100N
402
NOPOP
C53
100N
402
NOPOP
+
C117
220UF
NOPOP
+
C117
220UF
NOPOP
C112
100N
402
C112
100N
402
12
L2
Ferrite
L2
Ferrite
R3049.9 R3049.9
1
2
J25
NOPOP
C
J25
NOPOP
C
C28
100N
C28
100N
12
L1
Ferrite
L1
Ferrite
R2949.9 R2949.9
C114
100N
402
C114
100N
402
+
C118
220UF
NOPOP
+
C118
220UF
NOPOP
12
C18
10UF_805
C18
10UF_805
C20
100N
C20
100N
12
C31
10UF_805
C31
10UF_805
C30
100N
C30
100N
R3249.9 R3249.9
1
2
J33
NOPOP
D
J33
NOPOP
D
12
C43
10UF_805
C43
10UF_805
Figure 4. Si537x
Si537x-EVB
12 Rev. 0.6
Figure 5. Clock Inputs
Figure 6. Clock Outputs
CKIN2P_A
CKIN2N_A
CKIN1P_B
CKIN1N_B
CKIN2P_B
CKIN2N_B
CKIN1P_C
CKIN1N_C
CKIN2P_C
CKIN2N_C
CKIN1N_D
CKIN1P_D
CKIN2P_D
CKIN2N_D
CKIN1P_A
CKIN1N_A
CKIN1_A+
CKIN1_A-
CKIN2_A+
CKIN2_A-
CKIN1_B+
CKIN1_B-
CKIN2_B+
CKIN2_B-
CKIN2_C+
CKIN2_C-
CKIN1_D+
CKIN1_D-
CKIN2_D+
CKIN2_D-
CKIN1_C+
CKIN1_C-
Do not populate
for Si5375-EVB
1
3
2
J48
SMA_EDGE
J48
SMA_EDGE
R2849.9 R2849.9
R1149.9 R1149.9
C9100N C9100N
C32
10NF
C32
10NF C35
10NF
C35
10NF
C24
10NF
C24
10NF
C16100N C16100N
C1100N C1100N
R2749.9 R2749.9
R1649.9 R1649.9
R849.9 R849.9
C22
10NF
C22
10NF
1
3
2
J26
SMA_EDGE
J26
SMA_EDGE
1
3
2
J34
SMA_EDGE
J34
SMA_EDGE
C59100N C59100N
R1449.9 R1449.9
R1749.9 R1749.9
R949.9 R949.9
R1549.9 R1549.9
C14100N C14100N
C52100N C52100N
C25
10NF
C25
10NF
1
3
2
J5
SMA_EDGE
J5
SMA_EDGE
C4100N C4100N
1
3
2
J13
SMA_EDGE
J13
SMA_EDGE
C65100N C65100N
1
3
2
J1
SMA_EDGE
J1
SMA_EDGE
C46
10NF
C46
10NF
C57
10NF
C57
10NF
C54
10NF
C54
10NF
C42100N C42100N
R1949.9 R1949.9
C2100N C2100N
C33
10NF
C33
10NF C34
10NF
C34
10NF
C23
10NF
C23
10NF
1
3
2
J14
SMA_EDGE
J14
SMA_EDGE
1
3
2
J18
SMA_EDGE
J18
SMA_EDGE
1
3
2
J23
SMA_EDGE
J23
SMA_EDGE
R2149.9 R2149.9
1
3
2
J46
SMA_EDGE
J46
SMA_EDGE
R2649.9 R2649.9
1
3
2
J55
SMA_EDGE
J55
SMA_EDGE
C69100N C69100N
1
3
2
J35
SMA_EDGE
J35
SMA_EDGE
1
3
2
J6
SMA_EDGE
J6
SMA_EDGE
R2549.9 R2549.9
1
3
2
J31
SMA_EDGE
J31
SMA_EDGE
1
3
2
J2
SMA_EDGE
J2
SMA_EDGE
C21
10NF
C21
10NF
C15100N C15100N
C36100N C36100N
C60100N C60100N
R749.9 R749.9
C39
10NF
C39
10NF
C26
10NF
C26
10NF
R649.9 R649.9
C56
10NF
C56
10NF
C47100N C47100N C55
10NF
C55
10NF
R1049.9 R1049.9
C3100N C3100N 1
3
2
J56
SMA_EDGE
J56
SMA_EDGE
CKOUT2N_A
CKOUT2P_A
CKOUT1N_B
CKOUT1P_B
CKOUT2N_B
CKOUT2P_B
CKOUT1P_C
CKOUT1N_C
CKOUT2N_C
CKOUT2P_C
CKOUT1N_D
CKOUT1P_D
CKOUT2P_D
CKOUT2N_D
CKOUT1N_A
CKOUT1P_A
CKOUT1_C+
CKOUT1_C-
CKOUT2_C-
CKOUT1_D-
CKOUT1_D+
CKOUT2_D-
CKOUT2_D+
CKOUT1_A-
CKOUT1_A+
CKOUT2_A-
CKOUT2_A+
CKOUT1_B-
CKOUT1_B+
CKOUT2_B-
CKOUT2_B+
CKOUT2_C+
Do not populate
for Si5375-EVB
R18
0 ohm
NOPOP
R18
0 ohm
NOPOP
J29
SMA_VERT
J29
SMA_VERT
1
3
2
4
5
C51
100N
C51
100N
J12
SMA_VERT
J12
SMA_VERT
1
3
2
4
5
C41
100N
C41
100N
R5
0 ohm
NOPOP
R5
0 ohm
NOPOP
J28
SMA_VERT
J28
SMA_VERT
1
3
2
4
5
C12
100N
C12
100N
R22
0 ohm
NOPOP
R22
0 ohm
NOPOP
C40
100N
C40
100N
J37
SMA_VERT
J37
SMA_VERT
1
3
2
4
5
C37
100N
C37
100N
C8
100N
C8
100N
J22
SMA_VERT
J22
SMA_VERT
1
3
2
4
5
J11
SMA_VERT
J11
SMA_VERT
1
3
2
4
5
C48
100N
C48
100N
R4
0 ohm
NOPOP
R4
0 ohm
NOPOP
C11
100N
C11
100N
C7
100N
C7
100N
J21
SMA_VERT
J21
SMA_VERT
1
3
2
4
5
J10
SMA_VERT
J10
SMA_VERT
1
3
2
4
5
R3
0 ohm
NOPOP
R3
0 ohm
NOPOP
J9
SMA_VERT
J9
SMA_VERT
1
3
2
4
5
C10
100N
C10
100N
R20
0 ohm
NOPOP
R20
0 ohm
NOPOP
J39
SMA_VERT
J39
SMA_VERT
1
3
2
4
5
C6
100N
C6
100N
C50
100N
C50
100N
J20
SMA_VERT
J20
SMA_VERT
1
3
2
4
5
R2
0 ohm
NOPOP
R2
0 ohm
NOPOP
C13
100N
C13
100N
J30
SMA_VERT
J30
SMA_VERT
1
3
2
4
5
J19
SMA_VERT
J19
SMA_VERT
1
3
2
4
5
C38
100N
C38
100N
J27
SMA_VERT
J27
SMA_VERT
1
3
2
4
5
R23
0 ohm
NOPOP
R23
0 ohm
NOPOP
J38
SMA_VERT
J38
SMA_VERT
1
3
2
4
5
J36
SMA_VERT
J36
SMA_VERT
1
3
2
4
5
C5
100N
C5
100N
C49
100N
C49
100N
Si537x-EVB
Rev. 0.6 13
5()B&.287B1
5()B&.287B3
5()B&.,1B3
5()B&.,1B1
5()B3
5()B9''
;2B3:5
5()B1
26&B'87B3:5
93
93 '87B3:5
6&/.
5()B66B/
5()B/2/
26&B3
26&B1
026,
5()B567B/
0,62
EXT_REF+
EXT_REF-
REF_OUT+
REF_OUT-
CKIN
EXT
INT XO
121.109 MHz
-
XO_PWR
-
XO_PWR
5

5

2(
*1'
9''
287
8
;2E\P
8
;2E\P
/ )HUULWH/ )HUULWH
5
&
1
12323
&
1
12323
&
1)
&
1)
7373 5
RKP
5
RKP
5
N
5
N
5

5

-
60$B('*(
-
60$B('*(
GND
;
0+]
GND
;
0+]
&
1
&
1
-
60$B('*(
-
60$B('*(
7373
5
N
5
N
&
1
12323
&
1
12323
/ )HUULWH
/ )HUULWH
&
1)
&
1)
&
1
&
1
&
1
&
1
&112323 &112323
&
1
12323
&
1
12323
1&
2(
*QG
9GG
&ON
&ON
8
6L
8
6L
&112323 &112323
&1 &1
&
8)
&
8)
2(
1&
*1'
9''
&/.
&/.
8
6L
123238
6L
12323
9''
9'' 
*1'
*1'

&.,1

&.,1

&.,1B

&.,1B

5DWH 
5DWH 
;$
;%
&.287 
&.287 
&.287 
&.287 
'%/B%<
 ,17B&%
&%
&.6(/&.B$&79 
567
/2/ 
$8726(/
&02'(

6'$B6'2B%:6(/

6&/B6&/.B%:6(/

)547%/
6',B)546(/

$B66B)546(/

$B)546(/

$B)546(/

6)287 
6)287 
,1&

'(&

*1'

9'' 
Si532x
8 12323
Si532x
8 12323
-
REF_PWR
-
REF_PWR
5
N
12323
5
N
12323
&
1
12323
&
1
12323
&
1
&
1
&
1
&
1
-
60$B('*(
-
60$B('*(
&
1
&
1
&
8)
&
8)
7373
5
& 1& 1
-
60$B('*(
-
60$B('*(
5RKP 5RKP
5

5

Figure 7. Reference Oscillators
Si537x-EVB
14 Rev. 0.6
DUT_PWR +3.3V
1.8V
Trig1
Trig2
Trig3
install exactly one resistor:
code
E Si5374: install R58
D Si5375: install R60
B Si5376: install R61
125
26
50
5175
76
100
CPLD
CLK
LS
MS
V1P8
TMS
TDO
TCK
VCCAUX
TDI
RST_L
CPLD_DUT_PWR
V3P3
DUT_PWR
V3P3
REG_ADR0
REG_ADR1
REG_ADR2
REG_ADR3
SS_L
MOSI
SCLK
MISO
REF_SS_L
REG_ADR4
REF_LOL
REF_RST_L
RSTA_L
CS_CA_A
IRQ_D
LOL_A
LOL_B
LOL_C
LOL_D
IRQ_C
IRQ_B
IRQ_A
CS_CA_B
CS_CA_C
CS_CA_D
CPLD_RST_L
LED_CS_CA_D
LED_CS_CA_C
LED_CS_CA_B
LED_CS_CA_A
LED_LOL_D
LED_LOL_C
LED_LOL_B
LED_LOL_A
LED_IRQ_C
LED_IRQ_D
LED_IRQ_A
LED_IRQ_B
CMND_DONE
DUT_PWR_LRSTB_L
RSTC_L
RSTD_L
C61
10NF
C61
10NF
R8010 R8010
R490 ohm R490 ohm
C66
1UF
C66
1UF
C73
100N
C73
100N
R36
0 ohm
R36
0 ohm
+
C71
33UF
+
C71
33UF
J52
NOPOP
J52
NOPOP
1
2
3
4
5
6
C83
100N
C83
100N
R47
10
R47
10
C85
1UF
C85
1UF
C62
10NF
C62
10NF
R58
0 ohm
R58
0 ohm
U12A
XC2C128
U12A
XC2C128
GND1 21
GND2 25
GND3 31
GND4 62
GND5 69
GND7 84
GND8 100
GND6 75
VCC1
26
VCC2
57
VCCIO1-1
20
VCCIO1-2
38
VCCIO1-3
51
VCCIO2-1
88
VCCIO2-2
98
R60
0 ohm
NOPOP
R60
0 ohm
NOPOP
R61
0 ohm
NOPOP
R61
0 ohm
NOPOP
R62
0 ohm
NOPOP
R62
0 ohm
NOPOP
R89
66.5
R89
66.5
R8110 R8110
R7410 R7410
TP3TP3
1
2
R50
R10x4
R50
R10x4
1 8
2 7
3 6
4 5
R57
R10Kx4
R57
R10Kx4
18
27
36
45
C99
1UF
C99
1UF
J53 NOPOP
J53 NOPOP
1
2
3
4
J49NOPOP J49NOPO P
1
2
3
R90
0 ohm
R90
0 ohm
U12B
XC2C128
U12B
XC2C128
TCK
48
TDI
45
TDO
83
TMS
47
VCCAUX
5
+
C70
33UF
+
C70
33UF
R79
113
R79
113
C82
10NF
C82
10NF
J43
NOPOP
J43
NOPOP
1
2
3
4
C96
1UF
C96
1UF
C72
10NF
C72
10NF
R4410 R4410
C74
100N
C74
100N
C75
10NF
C75
10NF
J63
SMT
JTAG
J63
SMT
JTAG
1
2
3
4
5
6
TP4TP4
1
2
C63
10NF
C63
10NF
TP1TP1
1
2
Bank 1Bank 2
U12C
XC2C128
Bank 1Bank 2
U12C
XC2C128
FN5_M4_GCK1 23
FN5_M6_GCK0 22
FN6_M2_CDRST 24
FN6_M4_GCK2 27
FN6_M12_DGE 28
FN6_M14 29
FN6_M16 30
FN7_M5 19
FN7_M6 18
FN7_M11 17
FN7_M12 16
FN7_M13 15
FN7_M14 14
FN8_M6 32
FN8_M11 33
FN8_M12 34
FN8_M13 35
FN8_M14 36
FN8_M15 37
FN13_M2 53
FN13_M4 54
FN13_M6 55
FN13_M13 56
FN14_M1 52
FN14_M3 50
FN14_M5 49
FN14_M14 46
FN14_M15 44
FN15_M11 58
FN15_M12 59
FN15_M13 60
FN15_M14 61
FN15_M15 63
FN15_M16 64
FN16_M5 43
FN16_M6 42
FN16_M11 41
FN16_M12 40
FN16_M13 39
FN1_M3_GSR
99
FN1_M6
97
FN1_M12
96
FN1_M13
95
FN1_M14
94
FN2_M1_GTS2
1
FN2_M3_GTS3
2
FN2_M5_GTS0
3
FN2_M12_GTS1
4
FN2_M14
6
FN2_M15
7
FN3_M5
93
FN3_M12
92
FN3_M14
91
FN3_M16
90
FN4_M1
8
FN4_M2
9
FN4_M3
10
FN4_M5
11
FN4_M6
12
FN4_M13
13
FN9_M1
78
FN9_M2
79
FN9_M4
80
FN9_M6
81
FN9_M12
82
FN10_M1
77
FN10_M2
76
FN10_M3
74
FN10_M4
73
FN10_M5
72
FN10_M6
71
FN10_M12
70
FN11_M11
85
FN11_M12
86
FN11_M13
87
FN11_M14
89
FN12_M11
68
FN12_M13
67
FN12_M14
66
FN12_M15
65
J54 NOPOP
LOL
J54 NOPOP
LOL
1
2
3
4
J47
NOPOP
J47
NOPOP
1
2
3
4
5
6
Vreg
U3
TPS76201
Vreg
U3
TPS76201
In
1
Gnd
2
EN
3
FB 4
Out 5
Figure 8. CPLD
Si537x-EVB
Rev. 0.6 15
Figure 9. MCU
Si537x-EVB
16 Rev. 0.6
V3P3
V3P3
DUT_PWR
DUT_PWR
V3P3
LED_LOL_C
LED_LOL_D
LED_CS_CA_A
LED_CS_CA_B
LED_CS_CA_D
LED_CS_CA_C
LED_LOL_B
LED_LOL_A
LED_IRQ_B
LED_IRQ_C
LED_IRQ_D
LED_IRQ_A
LED_CS_CA_D
LED_CS_CA_B
LED_CS_CA_A
LED_CS_CA_C
LED_LOL_B
LED_LOL_D
LED_LOL_C
LED_LOL_A
MCU_LED1
MCU_LED2
REF_LOL
LED_IRQ_B
LED_IRQ_A
LED_IRQ_C
LED_IRQ_D
REF_LOL
DUT_PWR_L
GND
DUT_PWR
DUT Power
ground
pins
mounting holes
Status
measure DUT
voltage, currrent
1612
Place resistors
next to U1
+S
-S
3M unshrouded header:
2380-6121TG
Digikey: 2380-6121TG-ND
C94
100N
C94
100N
1 8
2 7
3 6
4 5
R72
R150x4
R72
R150x4
2 1
A
C
D3 Red
REF_LOL
A
C
D3 Red
REF_LOL
1
H1
#4
H1
#4
1
H5
#4
H5
#4
1
2 3
Q1
BSS138
Q1
BSS138
1 2
AC
D17 Yel
CS_CA_D
AC
D17 Yel
CS_CA_D
IN7
9IN6
8IN5
7IN4
6IN3
5IN2
4IN1
3IN0
2
O7 11
O6 12
O5 13
O4 14
Q3 15
O2 16
O1 17
O0 18
Vcc 20
GND
10
OE1
1
OE2
19
Buffer
U11
74LCX541
Buffer
U11
74LCX541
1 8
2 7
3 6
4 5
R71
R150x4
R71
R150x4
2 1
A
C
D11 Red
LOL_B
A
C
D11 Red
LOL_B
1
H3
#4
H3
#4
1 2
A
C
D4 Grn
MCU_1
A
C
D4 Grn
MCU_1
12
34
56
78
910
1112
1314
J45
14_M_Header
J45
14_M_Header
1
2
*
*
J4
Phoenix_2_screw
*
*
J4
Phoenix_2_screw
1 8
2 7
3 6
4 5
R68
R150x4
R68
R150x4
12
A
C
D1Grn
DUT_PWR
A
C
D1Grn
DUT_PWR
1 2
A
C
D5 Grn
MCU_2
A
C
D5 Grn
MCU_2
1J24J24
IN7
9IN6
8IN5
7IN4
6IN3
5IN2
4IN1
3IN0
2
O7 11
O6 12
O5 13
O4 14
Q3 15
O2 16
O1 17
O0 18
Vcc 20
GND
10
OE1
1
OE2
19
Buffer
U10
74LCX541
Buffer
U10
74LCX541
1
2
3
J3
SENSE
J3
SENSE
2 1
A
C
D12 Red
LOL_C
A
C
D12 Red
LOL_C
2 1
A
C
D7 Red
IRQ_B
A
C
D7 Red
IRQ_B
1 2
L6 Ferrite
L6 Ferrite
1 2
A
C
D2 Grn
3.3V
A
C
D2 Grn
3.3V
1J57J57
R130 ohm R130 ohm
2 1
A
C
D8 Red
IRQ_C
A
C
D8 Red
IRQ_C
2 1
A
C
D10 Red
LOL_A
A
C
D10 Red
LOL_A
R75
10k
R75
10k
R96 10k
R96 10k
C93
100N
C93
100N
12
34
56
78
910
1112
1314
J44
14_M_Header
J44
14_M_Header
1J32J32
C95
100N
C95
100N
1J15J15
2 1
A
C
D13 Red
LOL_D
A
C
D13 Red
LOL_D
2 1
A
C
D9 Red
IRQ_D
A
C
D9 Red
IRQ_D
1 8
2 7
3 6
4 5
R66
R150x4
R66
R150x4
1J40J40
1J42J42
+
C91
220UF
+
C91
220UF
1 2
AC
D14 Yel
CS_CA_A
AC
D14 Yel
CS_CA_A
1
H4
#4
H4
#4
1
2
J7 NOPOP
DUT_PWR
J7 NOPOP
DUT_PWR
R35100 R35100
R73150 R73150
1 2
AC
D15 Yel
CS_CA_B
AC
D15 Yel
CS_CA_B
+
C92
33UF
+
C92
33UF
1J41J41
R10 ohm R10 ohm
1J8J8
1
H2
#4
H2
#4
R69
10k
R69
10k
R67
10k
R67
10k
R120 ohm R120 ohm
1 2
AC
D16 Yel
CS_CA_C
AC
D16 Yel
CS_CA_C
R70
10k
R70
10k
2 1
A
C
D6 Red
IRQ_A
A
C
D6 Red
IRQ_A
1J58J58
Figure 10. Power and LEDs
Si537x-EVB
Rev. 0.6 17
8. Bill of Materials
Table 5. Si537x-EVB Bill of Materials
Item Qty Reference Part Mfgr Mfr Part Num BOM Digikey Footprint
1 62 C1,C2,C3,C4,
C5,C6,C7,C8,
C9,C10,C11,
C12,C13,C14,
C15,C16,C19,
C20,C27,C28,
C29,C30,C36,
C37,C38,C40,
C41,C42,C44,
C45,C47,C48,
C49,C50,C51,
C52,C58,C59,
C60,C64,C65,
C67,C69,C73,
C74,C83,C86,
C88,C93,C94,
C95,C97,C100,
C101,C103,
C104,C105,
C106,C107,
C109,C110,C111
100N Venkel C0603X7R160-104KNE 603
2 4 C17,C18,C31,C43 10UF_805 Venkel C0805Y5V6R3106ZN 805
3 24 C21,C22,C23,C24,
C25,C26,C32,C33,
C34,C35,C39,C46,
C54,C55,C56,C57,
C61,C62,C63,C72,
C75,C76,C82,C84
10NF Venkel C0603X7R160-103KNE 603
5 8 C66,C68,C79,C85,
C87,C96,C99,C108 1UF Venkel C0603X7R6R3-105KNE 603
6 3 C70,C89,C90 33UF Venkel TA006TCM336MBR 3528
7 2 C71,C92 33UF Venkel TA0006TCM336MBR 3528
9 1 C91 220UF Kemet T494B227M004AT 399-4631-1-ND SM_C_3528_21
10 4 D1,D2,D4,D5 Grn Panasonic LN1371G P491CT-ND LED_gull
11 9 D3,D6,D7,D8,D9,
D10,D11, Red Lumex LN1271RAL P493CT-ND LED_gull
D12,D13
12 4 D14,D15,D16,D17 Yel Panasonic LN1471YTR P11125CT-ND LED_gull
13 1 D18 BAT54S Fairchild BAT54S BAT54SFSCT-
ND SOT23
Si537x-EVB
18 Rev. 0.6
16 20 J1,J2,J5,J6,J13,J14
,J18,J23,J26,J31,J
34,J35,J46,J48,J55
,J56,J64,J65,J66,J
67
SMA_EDGE Johnson 142-0701-801 J502-ND SMA_EDGE_
p062
17 2 J3,J60 Jmpr_3pin 3pin_p1pitch
18 1 J4 Phoenix_2_
screw Phoenix MKDSN 1.5/2-5.08 277-1247-ND Phoenix2pinM_
p2pitch
20 9 J8,J15,J24,J32,J40
,
J41,J42,J57,J58
Jmpr_1pin 1pin_p1pitch
21 16 J9,J10,J11,J12,J19,
J20,J21,J22,J27,J2
8,J29,J30,J36,J37,
J38,J39
SMA_VERT Johnson 142-0701-211 J494-ND SMA_VERT
23 2 J44,J45 unshrouded
_Header 3M 2380-6121TG 2380-6121TG-ND 28pin thru hole
header
26 1 J50 Jmpr_2pin
27 2 J51,J62 10_M_Head
er_SMT Samtec HTST-105-01-lm-dv-a 10pinMdualHea
der_p1pitch_smt
28 1 J61 USB FCI 61729-0010BLF 609-1039-ND USB_typeB
29 1 J63 SMT Sullins GZC36SABN-M30 S1033-36-ND 6pin_m_smt
30 6 L1,L2,L3,L4,L5,L7 Ferrite Venkel FBC1206-471H 1206
31 1 L6 Ferrite Steward HI1612X560R-10 1612
32 3 Q1,Q2,Q3 BSS138 On Semi BSS138LT1G BSS138LT10SCT
-ND SOT23
33 14 R1,R12,R13,R29,
R30,R31,R32,R34,
R36,R37,R38,R49,
R61,R77,R87, R90,
R23,R62,R85,R92
0Venkel CR0603-16W-000T 603
35 25 R6,R7,R8,R9,R10,
R11,R14,R15,R16,
R17,R19,R21,R25,
R26,R27,R28,R43,
R48,R51,R52,R53,
R54,R55,R56,R64
49.9 Venkel CR0603-16W-49R9FT 603
37 4 R33,R42,R65,R76 1K Venkel CR0603-16W-1001FT 603
38 1 R35, R86, R94 100 Venkel CR0603-16W-1000FT 603
Table 5. Si537x-EVB Bill of Materials (Continued)
Item Qty Reference Part Mfgr Mfr Part Num BOM Digikey Footprint
Si537x-EVB
Rev. 0.6 19
39 13 R39,R41,R45,R46,
R57,R59,R67,R69,
R70,R75,R78,R84,
R88
10k Venkel CR603-16W-1002FT 603
40 7 R40,R44,R47,R63,
R74,R80,R81 10 Venkel CR0603-16W-10R0FT 603
41 1 R50 R10x4 Panasonic EXB-38V100JV Y9100CT-ND 1206x4
42 4 R66,R68,R71,R72 R150x4 Panasonic EXB-38V151JV Y9151CT-ND 1206x4
43 1 R73 150 Venkel CR0603-16W-1500FT 603
44 1 R79 113 Venkel CR0603-16W-1130FT 603
45 2 R82,R91 4.99K Venkel CR0603-16W-4991FT 603
46 2 R83,R93 1.5K Venkel CR0603-16W-1501FT 603
48 1 R89 66.5 Venkel CR0603-16W-66R5FT 603
49 1 SW1 NO Mountain
Switch 101-0161-EV 101-
0161(mouser) 4pin Switch
51 1 U1 Si537x Silicon
Labs Si537x 10x10 mm BGA
52 1 U2 M95040 ST Micro M95040-WMN6P SOIC-8
53 1 U3 TPS76201 TI TPS76201DBVT 296-11013-1-ND SOT23-5
56 1 U6 PCA9306 TI PCA9306DCTR-ND 296-18509-1-ND SM8
57 1 U7 Si530_2.5V
PECL Silicon
Labs 530EB121M109DG 5x7 mm
59 1 U9 DS2411 Maxim/
Dallas DS2411P TSOC-6
60 2 U10,U11 74LCX541 Fairchild 74LCX541MTC_NL TC74LCX541FTF
CT-ND TSSOP-20
61 1 U12 XC2C128 Xilinx XC2C128-7VQG100I VQG100
63 1 U14 Si8051F340 Silicon
Labs C8051F340-GQ TQFP-48
64 2 U15,U16 SN65220 TI SN65220DBVT 296-9694-1-ND SOT23-6
65 1 U17 FAN1540B Fairchild FAN1540BPMX FAN1540BMPXC
T-ND MLP6
66 1 X1 114.285 MH
zTXC 7MA1400014 xtal_3p2by2p5
4 spacer SPC Tech-
nology 2397
4 screw Richco NSS-4-4-01
4 1 C53 10NF Venkel C0603X7R160-103KNE NOPOP 603
8 6 C77,C78,C80,C81,
C98,C102 100N Venkel C0603X7R160-104KNE NOPOP 603
Table 5. Si537x-EVB Bill of Materials (Continued)
Item Qty Reference Part Mfgr Mfr Part Num BOM Digikey Footprint
Si537x-EVB
20 Rev. 0.6
14 2 D19,D20 BAT54S Fairchild BAT54S NOPOP BAT54SFSCT-
ND SOT23
19 5 J7,J16,J17,J25,J33 Jmpr_2pin NOPOP
22 3 J43,J53,J54 Jmpr_4pin NOPOP 4pin_p1pitch
24 2 J47,J52 Jmpr_6pin NOPOP 6pin_p1pitch
25 2 J49,J59 Jmpr_3pin NOPOP 3pin_p1pitch
34 14 R2,R3,R4,R5,R18,
R20,R22, 0 ohm Venkel CR0603-16W- 000T
Note: install R58 for
Si5374-EVB, install R60
for Si5375-EVB
NOPOP 603
36 1 R24 1K Venkel CR0603-16W-1001FT NOPOP 603
50 8 TP1,TP2,TP3,TP4,
TP5,TP6, test_points none none NOPOP
TP7,TP8
54 1 U4 Si5326 Silicon
Labs Si5326C-C-GM NOPOP QFN-36
55 1 U5 LTC4311 LinearTech LTC4311ISC6#TRMPBF NOPOP LTC4311CSC6#T
RMPBFCT-ND SC70
58 1 U8 Si500 Silicon
Labs NOPOP 3x5 mm_6pin
62 1 U13 XO, 3.2 by
2.5 Pericom FKB420001 NOPOP 3x2 mm
67 1 — heatsink Aavid
Thermalloy 375324B00035G NOPOP 10x10 mm
Table 5. Si537x-EVB Bill of Materials (Continued)
Item Qty Reference Part Mfgr Mfr Part Num BOM Digikey Footprint
Si537x-EVB
Rev. 0.6 21
9. Layout
Contact Silicon Labs to obtain the Allegro Board file.
Si537x-EVB
22 Rev. 0.6
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
Various changes to accommodate 1.8 V operation.
Revision 0.3 to Revision 0.4
Removed software installation instructions and
directed reader to refer to release CD or download
from Silicon Labs web site.
Revision 0.4 to Revision 0.5
Changed U7 to LVPECL, part number
Si530EB121M109G.
Installed 100 resistors at R94 and R86.
Revision 0.5 to Revision 0.6
Added Si5376.
Updated " Descrip tio n" on page 1.
Si537x-EVB
Rev. 0.6 23
NOTES:
Disclaimer
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using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific
device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories
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