74HC/HCT390 MSI DUAL DECADE RIPPLE COUNTER FEATURES @ Two BCD decade or bi-quinary TYPICAL counters SYMBOL | PARAMETER CONDITIONS UNIT One package can be configured HC HcT to divide-by-2, 4,5, 10, 20, 25, propagation delay 50 or 100 nCPq to nO 14 18 ns Two master reset inputs to clear teye/ nCPy to nQy C) = 150F 15 19 nas each decade counter individually tPLH nCP; to nQg ye . BV 23 | 26 | ns Output capability: standard nCPy to ndg cc 15 19 | ns icc category: MSI OMR to On 16 | 18 jns f maximum clock frequency GENERAL DESCRIPTION max nCBq, nCP 66 | 61 | MHz The 74HC/HCT390 are high-speed Cy input capacitance 3.5 3.5 pF Si-gate CMOS devices and are pin compatible with low power Schottky power dissipation TTLILSTTL). They are specified in Spo capacitance per counter notes | and 2 20 21 pF compliance with JEDEC standard no. 7A. The 74HC/HCT390 are dual 4-bit decade ripple counters divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections are normally used in a BCD decade or bi-quinary configuration, since they share a common master reset input (nMR). (f the two master reset inguts (IMR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clocks (nPg and nCP 1) of each section allow tipple counter or frequency division applications of divide-by-2, 4, 5, 10, 20, 25, 50 or 100. (continued on next page} GND = 0 V; Tamb = 25C; ty = t = 6 ns Notes 1. Cpo is used to determine the dynamic power dissipation {Pp in yW): Pp =Cpp x Vcc x fi + (CL x VCC? x fp) where: fj = input frequency in MHz Ct. = output load capacitance in pF fo = output frequency in MHz Vcc = supply voltage in V Z(CL x Voc? x fg) = sum of outputs 2. For HC the condition is Vj = GND to Vcc For HCT the condition is Vj = GNO to Vcc 1.5 V PACKAGE OUTLINES SEE PACKAGE INFORMATION SECTION 169 [| U 16] Voc ime [2 | 5] 2CFq 109 [3 | fia} 2m 1&8, fa 13] 20g iia 380 = 102 (6 | 1] 2a, 103 [7] fia} 242 cup [8 | rs] 293 3293775 Fig. 1 Pin configuration. Up olv2 3 73 OWS jy} 5 115 Qyacey * ant, ct 6 1Qof 3,13 ape ama CTR 4 eteo 4.12 ncry #5 ndybig yy . : IB Div2 13 902} 6.10 Divs u 2146 nMR Oj 79 0 Bn, cr? PO rz9ay76e 1 2 }2 7293777 Fig. 2 Logic symbol. Fig. 3 IEC lagic symbol. December 1990 63774HC/HCT390 MSI 118 oCPy 22 7Qq/ 3,13 COUNTER 412 [ACP o nOr]s.u +5 72/6, to 21a tamer counter |nag}z g 7293778 Fig. 4 Functional diagram. PIN DESCRIPTION | | PIN NO. ' SYMBOL NAME AND FUNCTION 11,15 | 1CPo, 2CPo clock input divide-by-2 section (HIGH-to-LOW, | edge-triggerea} 2,14 1MR, 2MR asynchronous master reset inputs (active HIGH) 3,5, 8,7 " 109 to 103 flip-flop outputs | 4,12 1TP;, 207, clock input divide-by-5 section (HIGH-to-LOW, edge triggered) 8 | GND ground (0 V} 13,11, 10,9 20g to 203 flip-flop outputs 16 | Veco positive supply voltage BCD COUNT SEQUENCE FOR 1/2 THE 390 BI-QUINARY COUNT SEQUENCE FOR 1/2 THE 330 OUTPUTS OUTPUTS COUNT COUNT Qp | A | O2 As Qo) 91 | Q2 | 93 0 L i 0 L Lf ode 1 H L Lak 1 L Hf} L 2 L H |] LOL 2 L L Ho} L 3 H Ho} bale 3 L H | H EL 4 L L H | L 4 L L L H 5 H L H L 5 H L L L 6 L H H L 6 H H L L 7 H H Hoy k 7 H L H L 8 L L L H 8 H H H L 9 H L tL oH 9 H L L H Note Note Output Qg connected to nCPy with counter input on nChg, H = HIGH voltage level L = LOW voltage level Output Q3 connected to nChg with counter input on nCPy. GENERAL DESCRIPTION Each section is triggered by the HiGH-to- LOW transition of the clock inputs (nTPp and nCP 4). For BCD decade operation, the nOg output is connected to the nCPy input of the divide-by-5 section. For bi-quinary decade operation, the nQ3 output is connected to the nCPg input and nd becomes the decade output. The master reset inputs (1MR and 2MR) are active HIGH asynchronous inputs to each decade counter which operates on the portion of the counter identified by the ''1" and "2" prefixes in the pin configuration. A HIGH level on the nMR input overrides the clocks and sets the four outputs LOW. 638 January 1986Dual! decade ripple counter 74HC/HCT390 MSI &, 9 cP cP -_ 2293779.) ogfo<] Fig. 5 Logic diagram (one counter}. March 1988 63974HC/HCT390 MSI OC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Qutput capability: standard \oc category: MSI AC CHARACTERISTICS FOR 74HC GND = OV; t, = te= 6 ns;C_ = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Veco | WAVEFORMS +25 40 to +85 | 40 to +125 Vv min. |typ.| max. | min.| max. | min, | max. 47 | 145 180 220 2.0 TPHL/ | Propagation delay 17 | 29 36 44 [ns | 45 | Fig.6 tPLH nCPg to nQg 14 | 25 3 38 8.0 50 | 155 195 236 2.0 tPHL/ propagation delay 18 | 31 39 47 | ns 45 | Fig.6 'PLH mCP; to nQy 14 | 26 33 40 6.0 74 | 210 265 315 2.0 teHL/ | propagation delay 27 | a2 53 63 |ns | 45 | Fig.6 LH | CPs to nO 22 | 36 45 54 6.0 | ; 60 | 155 195 235 2.0 'PHL/ =| Propagation delay 18 | 31 39 47 | ns 45 | Fig.6 *PLH nGP1 to ng 14 | 26 33 40 6.0 ; 52 | 165 205 250 2.0 PHL propagation delay 19 | 33 4 50 | ns 45 | Fig.? n 15 | 28 35 43 6.0 uns 19 | 75 95 110 2.0 ae output transition time 7 15 19 22 ns 45 Fig. 6 TLH 6 | 13 16 19 6.0 ; go | 19 100 | 120 2.0 Ww Cone sea 16 4/7 20 24 ns 45 | Fig 6 armel 1416 7 20 6.0 go | 28 105 130 2.0 tw master reset pulsewidth 147 | 10 2 26 ns 45 | Fig.7 14 18 18 22 6.0 75 | 22 95 110 2.0 1 ti trem eR to nce 15 8 19 22 ns 45 | Fig. 7 n 13. |6 16 19 6.0 maximum clock puise 6.0 | 20 48 4.0 2.0 fax frequency 30 (| 60 24 20 MHz | 4.5 Fig. 6 nCBo, nCPy 35 (| 71 28 24 6.0 40 March 1988Dual decade ripple counter 74HC/HCT390 MsI DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter HCMOS family characteristics, section Family specifications. Output capability: standard tec category: MSI Note to HCT types The value of additional quiescent supply current (Alec) for a unit load of 1 is given in the family specifications. To determine Alcg per input, muitiply this value by the unit load coefficient shawn in the table below. UNIT LOAD INPUT COEFFICIENT ncPg 0.45 nCP1, nMR 0.60 AC CHARACTERISTICS FOR 74HCT GND = OV; t, = te = 6 ns;C,_ = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL | PARAMETER UNIT | Veo | WAVEFORMS +25 40 to +85 | --40 to +125 Vv min, | typ. | max. | min. | max, | min, | max. tpHL/ propagation delay . tPLH ncPq to ng 21 | 34 43 51 ns 45 Fig. 6 teHL/ propagation delay . LH nCP, to nQy 22 | 38 48 57 ns 4.5 Fig. 6 tpHL! propagation delay . tPLH ncP to nQy 30 | 51 64 77 ns 45 Fig. 6 teHL/ Propagation delay . tPLH ncPy to nO3 22 | 38 48 57 ns 45 Fig. 6 Propagation delay ; tpHL nMR to nQ, 21 | 36 45 54 ns 4.5 | Fig.7 trHt/ output transition time 7 15 19 22 ns 45 Fig. 6 'TLH clock pulse width . tw nPop, nCPy 18 8 23 27 ns 4.5 Fig. 6 master reset pulse width . tw HIGH 7 10 21 26 ns 4.5 | Fig.7 removal time i tram nMR to ncP,, 156 #18 19 22 ns 4.5 Fig. 7 maximum clock pulse fmax frequency 27 (55 22 18 MHz | 45 | Fig. 6 nCPo, nCPy March 1988 64174HC/HCT390 AC WAVEFORMS nMR INPUT CP, INPUT nCP, (NPUT Vag tt! nQ, OUTPUT Vagit! 7293781 STH et be aot Me OTH Fig. 6 Waveforms showing the clock (nTP,,) to output (nQ,,) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. RH ay nQ, OUTPUT Vy it! 7293780.1 Fig. 7 Waveforms showing the master reset (nMR) pulse width, the master reset to output (nQ,) propagation delays and the master reset to clock (nCP,,) removal time. Note to AC waveforms (1) HC : Vay = 50%; Vy = GNO to Vcc. HCT: Vy = 1.3 V; Vy = GND to 3V. 642 January 1986