11100E–ATARM–24-Jul-13
Description
The Atmel SAM4S series is a member of a family of Flash microcontrollers based on
the high-performance 32-bit ARM® Cortex®-M4 RISC processor. It operates at a
maximum speed of 120 MHz and features up to 2048 Kbytes of Flash, with optional
dual-bank implementation and cache memory, and up to 160 Kbytes of SRAM. The
peripheral set includes a full-speed USB Device port with embedded transceiver, a
high-speed MCI for SDIO/SD/MMC, an External Bus Interface featuring a Static
Memory Controller to connect to SRAM, PSRAM, NOR Flash, LCD Module and NAND
Flash, two USARTs, two UARTs, two TWIs, three SPI, one I2S, as well as one PWM
timer, two three-channel general-purpose 16-bit timers (with stepper motor and
quadrature decoder logic support), one RTC, one 12-bit ADC, one 12-bit DAC and one
analog comparator.
The SAM4S series is ready for capacitive touch thanks to the Atmel QTouch ® library,
offering an easy way to implement buttons, wheels and sliders.
The SAM4S device is a medium-range general-purpose microcontroller with the best
ratio in terms of reduced power consumption, processing power and peripheral set.
This enables the SAM4S to sustain a wide range of applications including consumer,
industrial control, and PC peripherals.
It operates from 1.62V to 3.6V.
The SAM4S series is pin-to-pin compatible with the SAM3N, SAM3S series (64- and
100-pin versions), SAM4N and SAM7S legacy series (64-pin versions).
1. Features
Core
ARM Cortex-M4 with 2 Kbytes of cache running at up to 120 MHz
Memory Protection Unit (MPU)
DSP Instruction Set
Thumb®-2 instruction set
Pin-to-pin compatible with SAM3N, SAM3S (64- and 100- pin versions), SAM4N
and SAM7S legacy products (64-pin version)
Memories
Up to 2048 Kbytes embedded Flash with optional dual-bank and cache
memory
Up to 160 Kbytes embedded SRAM
ARM-based Flash MCU
SAM4S Series
DATASHEET
2
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines
8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash support
System
Embedded voltage regulator for single supply operation
Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with failure detection and optional low-
power 32.768 kHz for RTC or device clock
RTC with Gregorian and Persian calendar mode, waveform generation in low-power modes
RTC clock calibration circuitry for 32.768 kHz crystal frequency compensation
High-precision 8/12 MHz factory-trimmed internal RC oscillator with 4 MHz default frequency for device
startup. In-application trimming access for frequency adjustment.
Slow clock internal RC oscillator as permanent low-power mode device clock
Two PLLs up to 240 MHz for device clock and for USB
Temperature sensor
Up to 22 Peripheral DMA (PDC) Channels
Low-Power Modes
Sleep and backup modes, down to 1 μA in backup mode
Ultra low-power RTC
Peripherals
USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-chip transceiver.
Up to two USARTs with ISO7816, IrDA®, RS-485, SPI, Manchester and Modem Mode
Two 2-wire UARTs
Up to two Two-Wire Interface modules (I2C-compatible), one SPI, one Serial Synchronous Controller (I2S),
one high-speed Multimedia Card Interface (SDIO/SD Card/MMC)
Two three-channel 16-bit Timer/Counters with capture, waveform, compare and PWM mode. Quadrature
decoder logic and 2-bit Gray up/down counter for stepper motor
4-channel 16-bit PWM with complementary output, fault input, 12-bit dead time generator counter for motor
control
32-bit Real-time Timer and RTC with calendar, alarm and 32 kHz trimming features
Up to 16-channel, 1Msps ADC with differential input mode and programmable gain stage and auto
calibration
One 2-channel 12-bit 1Msps DAC
One Analog Comparator with flexible input selection, selectable input hysteresis
32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
Write-Protected registers
I/O
Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and
on-die series resistor termination
Three 32-bit Parallel Input/Output Controllers, Peripheral DMA-assisted Parallel Capture Mode
Packages
100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm/100-ball VFBGA, 7 x 7
mm, pitch 0.65 mm
64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-lead QFN 9x9 mm, pitch 0.5 mm/ 64-ball WLCSP, 4.42 x 3.42
mm, pitch 0.4 mm
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SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
1.1 Configuration Summary
The SAM4S series devices differ in memory size, package and features. Table 1-1 summarizes the configurations of the
device family.
Notes: 1. One channel is reserved for internal temperature sensor.
2. Full Modem support on USART1.
Table 1-1. Configuration Summary
Feature SAM4SD32C SAM4SD32B SAM4SD16C SAM4SD16B SAM4SA16C SAM4SA16B SAM4S16C SAM4S16B SAM4S8C SAM4S8B
Flash 2 x 1024
Kbytes 2 x 1024
Kbytes 2 x 512
Kbytes 2 x 512
Kbytes 1024 Kbytes 1024 Kbytes 1024 Kbytes 1024
Kbytes 512 Kbytes 512 Kbytes
SRAM 160 Kbytes 160 Kbytes 160 Kbytes 160 Kbytes 160 Kbytes 160 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes
HCACHE 2KBytes 2KBytes 2KBytes 2KBytes 2KBytes 2KBytes - - - -
Package LQFP 100
TFBGA 100
VFBGA 100
LQFP 64
QFN 64
LQFP 100
TFBGA 100
VFBGA 100
LQFP 64
QFN 64
LQFP 100
TFBGA 100
VFBGA 100
LQFP 64
QFN 64
LQFP 100
TFBGA 100
VFBGA 100
LQFP 64
QFN 64
WLCSP 64
LQFP 100
TFBGA 100
VFBGA 100
LQFP 64
QFN 64
WLCSP 64
Number of
PIOs 79 47 79 47 79 47 79 47 79 47
External
Bus
Interface
8-bit data,
4chip selects,
24-bit address -8-bit data,
4chip selects,
24-bit address -8-bit data,
4chip selects,
24-bit address -8-bit data,
4chip selects,
24-bit address -
8-bit data,
4chip selects,
24-bit
address
-
12-bit
ADC 16 ch.(1) 11 ch.(1) 16 ch.(1) 11 ch.(1) 16 ch.(1) 11 ch.(1) 16 ch.(1) 11 ch.(1) 16 ch.(1) 11 ch.(1)
12-bit
DAC 2 ch. 2 ch. 2 ch. 2 ch. 2 ch. 2 ch. 2 ch. 2 ch. 2 ch. 2 ch.
Timer
Counter
Channels 6363636363
PDC
Channels 22 22 22 22 22 22 22 22 22 22
USART/
UART 2/2(2) 2/2(2) 2/2(2) 2/2(2) 2/2(2) 2/2(2) 2/2(2) 2/2(2) 2/2(2) 2/2(2)
HSMCI 1 port
4 bits 1 port
4 bits 1 port
4 bits 1 port
4 bits 1 port
4 bits 1 port
4 bits 1 port
4 bits 1 port
4 bits 1 port
4 bits 1 port
4 bits
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SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
2. Block Diagram
Figure 2-1. SAM4S16/S8 100-pin version Block Diagram
PLLA
Sys tem C ontroller
WDT
RTT
Osc 32 kHz
SUPC
RSTC
8 GPBREG
3-20 MHz
Osc
POR
RTC
RC 32 kHz
SM
RC Osc
12/8/4 MHz
I/D S
MPU
N
V
I
C
4-layer AHB Bus Matrix Fmax 120 MHz
ADC Ch.
PLLB
PMC
PIOA / PIOB / PIOC
WKUP[15:0]
PIO
External Bus
Interface
D[7:0]
PIODC[7:0]
A[0:23]
A21/NANDALE
A22/NANDCLE
NCS0
NCS1
NCS2
NCS3
NRD
NWE
NANDOE
NANDWE
NWAIT
High Speed MCI
DATRG PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
DAC0
DAC1
Timer Counter B
Timer Counter A
TC[3..5]
TC[0..2]
TIOA[3:5]
TIOB[3:5]
TCLK[3:5]
AD[0..14]
RXD1
TXD1
USART1
USART0
UART1
UART0
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
NAND Flash
Logic
TWCK0
TWD0
TWD1
URXD0
UTXD0
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
TWCK1
ADVREF
TIOB[0:2]
TCLK[0:2]
PWMH[0:3]
PWML[0:3]
PWMFI0
ADTRG
TIOA[0:2]
TST
PCK0-PCK2
XIN
NRST
VDDCORE
XOUT
RTCOUT0
RTCOUT1
XIN32
XOUT32
ERASE
VDDPLL
VDDIO
12-bit DAC
Temp. Sensor
PWM
12-bit ADC
TWI0
TWI1
SPI
SSC
PIO
Static Memory
Controller
Analog
Comparator
CRC Unit
Peripheral
Bridge
2668
Bytes
FIFO
USB 2.0
Full
Speed
Transceiver
NPCS0
PIODCCLK
PIODCEN1
PIODCEN2
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
MCDA[0..3]
MCCDA
MCCK
TF
TK
TD
RD
RK
RF
DDP
DDM
ADVREF
ROM
16 Kbytes
FLASH
1024 Kbytes
512 Kbytes
Flash
Unique
Identifier
User
Signature
TDI
TDO
TMS/SWDIO
TCK/SWCLK
JTAGSEL
Voltage
Regulator
VDDIN
VDDOUT
Cortex-M4 Processor
Fmax 120 MHz
In-Circuit Emulator
JTAG & Serial Wire
24-Bit
SysTick Counter
DSP
SRAM
128 Kbytes
Real Time
Events
5
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 2-2. SAM4S16/S8 64-pin version Block Diagram
PLLA
Sys tem C ontroller
WDT
RTT
Osc 32 kHz
SUPC
RSTC
8 GPBREG
3-20 MHz
Osc
POR
RTC
RC 32 kHz
SM
RC Osc
12/8/4 MHz
I/D S
MPU
N
V
I
C
4-layer AHB Bus Matrix Fmax 120 MHz
ADC Ch.
PLLB
PMC
PIOA / PIOB
PIODC[7:0]
High Speed MCI
DATRG PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
DAC0
DAC1
Timer Counter A
TC[0..2]
AD[0..9]
RXD1
TXD1
USART1
USART0
UART1
UART0
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
TWCK0
TWD0
TWD1
URXD0
UTXD0
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
TWCK1
ADVREF
TIOB[0:2]
TCLK[0:2]
PWMH[0:3]
PWML[0:3]
PWMFI0
ADTRG
TIOA[0:2]
TST
PCK0-PCK2
XIN
NRST
VDDCORE
XOUT
RTCOUT0
RTCOUT1
XIN32
XOUT32
ERASE
VDDPLL
VDDIO
12-bit DAC
Temp. Sensor
PWM
12-bit ADC
TWI0
TWI1
SPI
SSC
PIO
Analog
Comparator
CRC Unit
Peripheral
Bridge
2668
Bytes
FIFO
USB 2.0
Full
Speed
Transceiver
NPCS0
PIODCCLK
PIODCEN1
PIODCEN2
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
MCDA[0..3]
MCCDA
MCCK
TF
TK
TD
RD
RK
RF
DDP
DDM
ADVREF
TDI
TDO
TMS/SWDIO
TCK/SWCLK
JTAGSEL
Voltage
Regulator
VDDIN
VDDOUT
Cortex-M4 Processor
Fmax 120 MHz
In-Circuit Emulator
JTAG & Serial Wire
24-Bit
SysTick Counter
PIO
PIO
DSP
ROM
16 Kbytes
FLASH
1024 Kbytes
512 Kbytes
Flash
Unique
Identifier
User
Signature
SRAM
128 Kbytes
Real Time
Events
WKUP[15:0]
6
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 2-3. SAM4SD32/SD16/SA16 100-pin version Block Diagram
PLLA
TST
PCK0-PCK2
XIN
NRST
VDDCORE
XOUT
WDT
RTT
OSC 32k
XIN32
XOUT32
SUPC
RSTC
8 GPBREG
3-20 MHz
Osc.
POR
RTC
RC 32k
SM
RC
12/8/4 M
ERASE
TDI
TDO
TMS/SWDIO
TCK/SWCLK
JTAGSEL
ID
Voltage
Regulator
VDDIN
VDDOUT
SPI
TC[0..2]
DAC
ADVREF PDC
NPCS0
PIODCCLK
PIODCEN1
PIODCEN2
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
MCDA[0..3]
MCCDA
MCCK
TCLK[0:2]
Temp. Sensor
PDC
TWI0 PDC
TWD0
PWM
PDC
TF
TK
TD
RD
RK
RF
DDP
DDM
MPU
N
V
I
C
24-Bit
SysTick Counter
4-layer AHB Bus Matrix Fmax 120 MHz
TWI1 PDC
TWCK1
TWD1
PWMH[0:3]
PWML[0:3]
PWMFI0
PDC
UART0
UART1
URXD0
UTXD0
URXD1
UTXD1
SSC
Peripheral
Bridge
PDC
PIO
PDC
PDC
2668
Bytes
FIFO
USB 2.0
Full
Speed
VDDPLL
VDDIO
PDC
RXD0
TXD0 USART0
SCK0
RTS0
CTS0
Analog
Comparator
CRC Unit
ADC
Transceiver
PLLB
In-Circuit Emulator
JTAG & Serial Wire Flash
Unique
Identifier
PMC
PIOA / PIOB / PIOC
ADTRG
Cortex-M4 Processor
Fmax 120 MHz
Timer Counter A
Timer Counter B
TWCK0
FLASH
2*1024 KBytes
2*512 KBytes
1024 KBytes
SRAM
160 KBytes ROM
16 KBytes
RTCOUT1
RTCOUT0
DSP
CMCC
(2 KB cache)
PIO
External Bus
Interface D[7:0]
PIODC[7:0]
A[0:23]
A21/NANDALE
A22/NANDCLE
NCS0
NCS1
NCS2
NCS3
NRD
NWE
NANDOE
NANDWE
NWAIT
High Speed MCI
PDC
DATRG PDC
DAC0
DAC1
TC[3..5]
TIOA[3:5]
TIOB[3:5]
TIOA[0:2]
TIOB[0:2]
TCLK[3:5]
AD[0..14]
PDC
RXD1
TXD1
USART1
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
NAND Flash
Logic
Static Memory
Controller
ADC
DAC
Temp Sensor
ADVREF
Real Time
Events
WKUP[15:0]
7
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 2-4. SAM4SD32/SD16/SA16 64-pin version Block Diagram
PLLA
Sys tem C ontroller
WDT
RTT
Osc 32 kHz
SUPC
RSTC
8 GPBREG
3-20 MHz
Osc
POR
RTC
RC 32 kHz
SM
RC Osc
12/8/4 MHz
MPU
N
V
I
C
4-layer AHB Bus Matrix Fmax 120 MHz
ADC Ch.
PLLB
PMC
PIOA / PIOB
WKUP[15:0]
PIODC[7:
0
High Speed MCI
DATRG PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
DAC0
DAC1
Timer Counter A
TC[0..2]
AD[0..9]
RXD1
TXD1
USART1
USART0
UART1
UART0
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
TWCK0
TWD0
TWD1
URXD0
UTXD0
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
TWCK1
ADVREF
TIOB[0:2]
TCLK[0:2]
PWMH[0:3]
PWML[0:3]
PWMFI0
ADTRG
TIOA[0:2]
TST
PCK0-PCK2
XIN
NRST
VDDCORE
XOUT
RTCOUT0
RTCOUT1
XIN32
XOUT32
ERASE
VDDPLL
VDDIO
12-bit DAC
Temp. Sensor
PWM
12-bit ADC
TWI0
TWI1
SPI
SSC
PIO
Analog
Comparator
CRC Unit
Peripheral
Bridge
2668
Bytes
FIFO
USB 2.0
Full
Speed
Transceiver
NPCS0
PIODCCL
K
PIODCEN
PIODCEN
2
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
MCDA[0..
3
MCCDA
MCCK
TF
TK
TD
RD
RK
RF
DDP
DDM
ADVREF
Flash
Unique
Identifier
TDI
TDO
TMS/SWDIO
TCK/SWCLK
JTAGSEL
Voltage
Regulator
VDDIN
VDDOUT
Cortex-M4 Processor
Fmax 120 MHz
In-Circuit Emulator
JTAG & Serial Wire
24-Bit
SysTick Counter
PIO
PIO
DSP
ROM
16 KBytes
ID
FLASH
2*1024 KBytes
2*512 KBytes
1024 KBytes
SRAM
160 KBytes
CMCC
(2 KB cache)
Real Time
Events
8
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
3. Signal Description
Table 3-1 gives details on signal names classified by peripheral.
Table 3-1. Signal Description List
Signal Name Function Type Active
Level Voltage
reference Comments
Power Supplies
VDDIO Peripherals I/O Lines and USB transceiver
Power Supply Power 1.62V to 3.6V
VDDIN Voltage Regulator Input, ADC, DAC and
Analog Comparator Power Supply Power 1.62V to 3.6V(4)
VDDOUT Voltage Regulator Output Power 1.2V Output
VDDPLL Oscillator and PLL Power Supply Power 1.08 V to 1.32V
VDDCORE Power the core, the embedded memories
and the peripherals Power 1.08V to 1.32V
GND Ground Ground
Clocks, Oscillators and PLLs
XIN Main Oscillator Input Input
VDDIO
Reset State:
- PIO Input
- Internal Pull-up disabled
- Schmitt Trigger enabled(1)
XOUT Main Oscillator Output Output
XIN32 Slow Clock Oscillator Input Input
XOUT32 Slow Clock Oscillator Output Output
PCK0 - PCK2 Programmable Clock Output Output
Reset State:
- PIO Input
- Internal Pull-up enabled
- Schmitt Trigger enabled(1)
Real Time Clock
RTCOUT0 Programmable RTC waveform output Output
VDDIO
Reset State:
- PIO Input
- Internal Pull-up enabled
- Schmitt Trigger enabled(1)
RTCOUT1 Programmable RTC waveform output Output
Serial Wire/JTAG Debug Port - SWJ-DP
TCK/SWCLK Test Clock/Serial Wire Clock Input
VDDIO
Reset State:
- SWJ-DP Mode
- Internal pull-up disabled(5)
- Schmitt Trigger enabled(1)
TDI Test Data In Input
TDO/TRACESWO Test Data Out / Trace Asynchronous Data
Out Output
TMS/SWDIO Test Mode Select /Serial Wire
Input/Output Input / I/O
JTAGSEL JTAG Selection Input High Permanent Internal
pull-down
9
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Flash Memory
ERASE Flash and NVM Configuration Bits Erase
Command Input High VDDIO
Reset State:
- Erase Input
- Internal pull-down enabled
- Schmitt Trigger enabled(1)
Reset/Test
NRST Synchronous Microcontroller Reset I/O Low VDDIO
Permanent Internal
pull-up
TST Test Select Input Permanent Internal
pull-down
Wake-up
WKUP[15:0] Wake-up Inputs Input
Universal Asynchronous Receiver Transceiver - UARTx
URXDx UART Receive Data Input
UTXDx UART Transmit Data Output
PIO Controller - PIOA - PIOB - PIOC
PA0 - PA31 Parallel IO Controller A I/O
VDDIO
Reset State:
- PIO or System IOs(2)
- Internal pull-up enabled
- Schmitt Trigger enabled(1)
PB0 - PB14 Parallel IO Controller B I/O
PC0 - PC31 Parallel IO Controller C I/O
PIO Controller - Parallel Capture Mode
PIODC0-PIODC7 Parallel Capture Mode Data Input
VDDIOPIODCCLK Parallel Capture Mode Clock Input
PIODCEN1-2 Parallel Capture Mode Enable Input
External Bus Interface
D0 - D7 Data Bus I/O
A0 - A23 Address Bus Output
NWAIT External Wait Signal Input Low
Static Memory Controller - SMC
NCS0 - NCS3 Chip Select Lines Output Low
NRD Read Signal Output Low
NWE Write Enable Output Low
NAND Flash Logic
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
High Speed Multimedia Card Interface - HSMCI
MCCK Multimedia Card Clock I/O
MCCDA Multimedia Card Slot A Command I/O
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Voltage
reference Comments
10
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
MCDA0 - MCDA3 Multimedia Card Slot A Data I/O
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx USARTx Serial Clock I/O
TXDx USARTx Transmit Data I/O
RXDx USARTx Receive Data Input
RTSx USARTx Request To Send Output
CTSx USARTx Clear To Send Input
DTR1 USART1 Data Terminal Ready I/O
DSR1 USART1 Data Set Ready Input
DCD1 USART1 Data Carrier Detect Output
RI1 USART1 Ring Indicator Input
Synchronous Serial Controller - SSC
TD SSC Transmit Data Output
RD SSC Receive Data Input
TK SSC Transmit Clock I/O
RK SSC Receive Clock I/O
TF SSC Transmit Frame Sync I/O
RF SSC Receive Frame Sync I/O
Timer/Counter - TC
TCLKx TC Channel x External Clock Input Input
TIOAx TC Channel x I/O Line A I/O
TIOBx TC Channel x I/O Line B I/O
Pulse Width Modulation Controller- PWMC
PWMHx PWM Waveform Output High for channel x Output
PWMLx PWM Waveform Output Low for channel x Output
only output in
complementary mode
when dead time insertion is
enabled.
PWMFI0 PWM Fault Input Input
Serial Peripheral Interface - SPI
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
SPCK SPI Serial Clock I/O
SPI_NPCS0 SPI Peripheral Chip Select 0 I/O Low
SPI_NPCS1 -
SPI_NPCS3 SPI Peripheral Chip Select Output Low
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Voltage
reference Comments
11
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Note: 1. Schmitt Triggers can be disabled through PIO registers.
2. Some PIO lines are shared with System I/Os.
3. Refer to USB Section of the product Electrical Characteristics for information on Pull-down value in USB Mode.
4. See “Typical Powering Schematics” Section for restrictions on voltage range of Analog Cells.
5. TDO pin is set in input mode when the Cortex-M4 Core is not in debug mode. Thus the internal pull-up corresponding
to this PIO line must be enabled to avoid current consumption due to floating input
Two-Wire Interface- TWI
TWDx TWIx Two-wire Serial Data I/O
TWCKx TWIx Two-wire Serial Clock I/O
Analog
ADVREF ADC, DAC and Analog Comparator
Reference Analog
12-bit Analog-to-Digital Converter - ADC
AD0-AD14 Analog Inputs Analog,
Digital
ADTRG ADC Trigger Input VDDIO
12-bit Digital-to-Analog Converter - DAC
DAC0 - DAC1 Analog output Analog,
Digital
DACTRG DAC Trigger Input VDDIO
Fast Flash Programming Interface - FFPI
PGMEN0-
PGMEN2 Programming Enabling Input VDDIO
PGMM0-PGMM3 Programming Mode Input
VDDIO
PGMD0-PGMD15 Programming Data I/O
PGMRDY Programming Ready Output High
PGMNVALID Data Direction Output Low
PGMNOE Programming Read Input Low
PGMCK Programming Clock Input
PGMNCMD Programming Command Input Low
USB Full Speed Device
DDM USB Full Speed Data - Analog,
Digital VDDIO Reset State:
- USB Mode
- Internal Pull-down(3)
DDP USB Full Speed Data +
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Voltage
reference Comments
12
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
4. Package and Pinout
SAM4S devices are pin-to-pin compatible with SAM3N, SAM3S products in 64- and 100-pin versions, and AT91SAM7S
legacy products in 64-pin versions.
4.1 SAM4SD32/SD16/SA16/S16/S8C Package and Pinout
4.1.1 100-lead LQFP Package Outline
Figure 4-1. Orientation of the 100-lead LQFP Package
4.1.2 100-ball TFBGA Package Outline
The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 9 x 9 x 1.1 mm.
Figure 4-2 shows the orientation of the 100-ball TFBGA Package.
Figure 4-2. Orientation of the 100-ball TFBGA Package
125
26
50
5175
76
100
1
3
4
5
6
7
8
9
10
2
ABCDEFGHJK
TOP VIEW
BALL A1
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SAM4S [DATASHEET]
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4.1.3 100-ball VFBGA Package Outline
Figure 4-3. Orientation of the 100-ball VFBGA Package
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SAM4S [DATASHEET]
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4.1.4 100-lead LQFP Pinout
Table 4-1. SAM4SD32/SD16/SA16/S16/S8C 100-lead LQFP Pinout
1 ADVREF 26 GND 51 TDI/PB4 76 TDO/TRACESWO/
PB5
2 GND 27 VDDIO 52 PA6/PGMNOE 77 JTAGSEL
3 PB0/AD4 28 PA16/PGMD4 53 PA5/PGMRDY 78 PC18
4 PC29/AD13 29 PC7 54 PC28 79 TMS/SWDIO/PB6
5 PB1/AD5 30 PA15/PGMD3 55 PA4/PGMNCMD 80 PC19
6 PC30/AD14 31 PA14/PGMD2 56 VDDCORE 81 PA31
7 PB2/AD6 32 PC6 57 PA27/PGMD15 82 PC20
8 PC31 33 PA13/PGMD1 58 PC8 83 TCK/SWCLK/PB7
9 PB3/AD7 34 PA24/PGMD12 59 PA28 84 PC21
10 VDDIN 35 PC5 60 NRST 85 VDDCORE
11 VDDOUT 36 VDDCORE 61 TST 86 PC22
12 PA17/PGMD5/
AD0 37 PC4 62 PC9 87 ERASE/PB12
13 PC26 38 PA25/PGMD13 63 PA29 88 DDM/PB10
14 PA18/PGMD6/
AD1 39 PA26/PGMD14 64 PA30 89 DDP/PB11
15 PA21/PGMD9/
AD8 40 PC3 65 PC10 90 PC23
16 VDDCORE 41 PA12/PGMD0 66 PA3 91 VDDIO
17 PC27 42 PA11/PGMM3 67 PA2/PGMEN2 92 PC24
18 PA19/PGMD7/
AD2 43 PC2 68 PC11 93 PB13/DAC0
19 PC15/AD11 44 PA10/PGMM2 69 VDDIO 94 PC25
20 PA22/PGMD10/
AD9 45 GND 70 GND 95 GND
21 PC13/AD10 46 PA9/PGMM1 71 PC14 96 PB8/XOUT
22 PA23/PGMD11 47 PC1 72 PA1/PGMEN1 97 PB9/PGMCK/XIN
23 PC12/AD12 48 PA8/XOUT32/
PGMM0 73 PC16 98 VDDIO
24 PA20/PGMD8/
AD3 49 PA7/XIN32/
PGMNVALID 74 PA0/PGMEN0 99 PB14/DAC1
25 PC0 50 VDDIO 75 PC17 100 VDDPLL
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4.1.5 100-ball TFBGA Pinout
Table 4-2. SAM4SD32/SD16/SA16/S16/S8 100-ball TFBGA Pinout
A1 PB1/AD5 C6 TCK/SWCLK/PB7 F1 PA18/PGMD6/
AD1 H6 PC4
A2 PC29 C7 PC16 F2 PC26 H7 PA11/PGMM3
A3 VDDIO C8 PA1/PGMEN1 F3 VDDOUT H8 PC1
A4 PB9/PGMCK/XIN C9 PC17 F4 GND H9 PA6/PGMNOE
A5 PB8/XOUT C10 PA0/PGMEN0 F5 VDDIO H10 TDI/PB4
A6 PB13/DAC0 D1 PB3/AD7 F6 PA27/PGMD15 J1 PC15/AD11
A7 DDP/PB11 D2 PB0/AD4 F7 PC8 J2 PC0
A8 DDM/PB10 D3 PC24 F8 PA28 J3 PA16/PGMD4
A9 TMS/SWDIO/PB6 D4 PC22 F9 TST J4 PC6
A10 JTAGSEL D5 GND F10 PC9 J5 PA24/PGMD12
B1 PC30 D6 GND G1 PA21/PGMD9/AD8 J6 PA25/PGMD13
B2 ADVREF D7 VDDCORE G2 PC27 J7 PA10/PGMM2
B3 GNDANA D8 PA2/PGMEN2 G3 PA15/PGMD3 J8 GND
B4 PB14/DAC1 D9 PC11 G4 VDDCORE J9 VDDCORE
B5 PC21 D10 PC14 G5 VDDCORE J10 VDDIO
B6 PC20 E1 PA17/PGMD5/
AD0 G6 PA26/PGMD14 K1 PA22/PGMD10/
AD9
B7 PA31 E2 PC31 G7 PA12/PGMD0 K2 PC13/AD10
B8 PC19 E3 VDDIN G8 PC28 K3 PC12/AD12
B9 PC18 E4 GND G9 PA4/PGMNCMD K4 PA20/PGMD8/
AD3
B10 TDO/TRACESWO/
PB5 E5 GND G10 PA5/PGMRDY K5 PC5
C1 PB2/AD6 E6 NRST H1 PA19/PGMD7/
AD2 K6 PC3
C2 VDDPLL E7 PA29/AD13 H2 PA23/PGMD11 K7 PC2
C3 PC25 E8 PA30/AD14 H3 PC7 K8 PA9/PGMM1
C4 PC23 E9 PC10 H4 PA14/PGMD2 K9 PA8/XOUT32/
PGMM0
C5 ERASE/PB12 E10 PA3 H5 PA13/PGMD1 K10 PA7/XIN32/
PGMNVALID
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4.1.6 100-ball VFBGA Pinout
Table 4-3. SAM4SD32/SD16/SA16/S16/S8 100-ball VFBGA Pinout
A1 ADVREF C6 PC9 F1 VDDOUT H6 PA12/PGMD0
A2 VDDPLL C7 TMS/SWDIO/PB6 F2 PA18/PGMD6/
AD1 H7 PA9/PGMM1
A3 PB9/PGMCK/XIN C8 PA1/PGMEN1 F3 PA17/PGMD5/
AD0 H8 VDDCORE
A4 PB8/XOUT C9 PA0/PGMEN0 F4 GND H9 PA6/PGMNOE
A5 JTAGSEL C10 PC16 F5 GND H10 PA5/PGMRDY
A6 DDP/PB11 D1 PB1/AD5 F6 PC26 J1 PA20/AD3
A7 DDM/PB10 D2 PC30 F7 PA4/PGMNCMD J2 PC12/AD12
A8 PC20 D3 PC31 F8 PA28 J3 PA16/PGMD4
A9 PC19 D4 PC22 F9 TST J4 PC6
A10 TDO/TRACESWO/
PB5 D5 PC5 F10 PC8 J5 PA24
B1 GNDANA D6 PA29/AD13 G1 PC15/AD11 J6 PA25
B2 PC25 D7 PA30/AD14 G2 PA19/PGMD7/
AD2 J7 PA11/PGMM3
B3 PB14/DAC1 D8 GND G3 PA21/AD8 J8 VDDCORE
B4 PB13/DAC0 D9 PC14 G4 PA15/PGMD3 J9 VDDCORE
B5 PC23 D10 PC11 G5 PC3 J10 TDI/PB4
B6 PC21 E1 VDDIN G6 PA10/PGMM2 K1 PA23
B7 TCK/SWCLK/PB7 E2 PB3/AD7 G7 PC1 K2 PC0
B8 PA31 E3 PB2/AD6 G8 PC28 K3 PC7
B9 PC18 E4 GND G9 NRST K4 PA13/PGMD1
B10 PC17 E5 GND G10 PA27 K5 PA26
C1 PB0/AD4 E6 GND H1 PC13/AD10 K6 PC2
C2 PC29 E7 VDDIO H2 PA22/AD9 K7 VDDIO
C3 PC24 E8 PC10 H3 PC27 K8 VDDIO
C4 ERASE/PB12 E9 PA2/PGMEN2 H4 PA14/PGMD2 K9 PA8/XOUT32/
PGMM0
C5 VDDCORE E10 PA3 H5 PC4 K10 PA7/XIN32/
PGMNVALID
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4.2 SAM4SD32/SD16/SA16/S16/S8 Package and Pinout
4.2.1 64-lead LQFP Package Outline
Figure 4-4. Orientation of the 64-lead LQFP Package
4.2.2 64-lead QFN Package Outline
Figure 4-5. Orientation of the 64-lead QFN Package
4.2.3 64-ball WLCSP Package Outline
Figure 4-6. Orientation of the 64-ball WLCSP Package
33
49
48
32
17
16
1
64
1
16 17 32 33
48
4964
T OP VIEW
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4.2.4 64-lead LQFP and QFN Pinout
Note: The bottom pad of the QFN package must be connected to ground.
Table 4-4. 64-pin SAM4SD32/SD16/SA16/S16/S8 Pinout
1 ADVREF 17 GND 33 TDI/PB4 49 TDO/TRACESWO/
PB5
2 GND 18 VDDIO 34 PA6/PGMNOE 50 JTAGSEL
3 PB0/AD4 19 PA16/PGMD4 35 PA5/PGMRDY 51 TMS/SWDIO/PB6
4 PB1/AD5 20 PA15/PGMD3 36 PA4/PGMNCMD 52 PA31
5 PB2/AD6 21 PA14/PGMD2 37 PA27/PGMD15 53 TCK/SWCLK/PB7
6 PB3/AD7 22 PA13/PGMD1 38 PA28 54 VDDCORE
7 VDDIN 23 PA24/PGMD12 39 NRST 55 ERASE/PB12
8 VDDOUT 24 VDDCORE 40 TST 56 DDM/PB10
9PA17/PGMD5/
AD025 PA25/PGMD13 41 PA29 57 DDP/PB11
10 PA18/PGMD6/
AD1 26 PA26/PGMD14 42 PA30 58 VDDIO
11 PA21/PGMD9/
AD8 27 PA12/PGMD0 43 PA3 59 PB13/DAC0
12 VDDCORE 28 PA11/PGMM3 44 PA2/PGMEN2 60 GND
13 PA19/PGMD7/
AD2 29 PA10/PGMM2 45 VDDIO 61 XOUT/PB8
14 PA22/PGMD10/
AD9 30 PA9/PGMM1 46 GND 62 XIN/PGMCK/PB9
15 PA23/PGMD11 31 PA8/XOUT32/
PGMM0 47 PA1/PGMEN1 63 PB14/DAC1
16 PA20/PGMD8/
AD3 32 PA7/XIN32/
PGMNVALID 48 PA0/PGMEN0 64 VDDPLL
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4.2.5 64-ball WLCSP Pinout
Table 4-5. 64-ball WLCSP Pinout
A1 PA31 C1 GND E1 PA29 G1 PA5
A2 PB7 C2 PA1 E2 TST G2 PA6
A3 VDDCORE C3 PA0 E3 NRST G3 PA9
A4 PB10 C4 PB12 E4 PA28 G4 PA11
A5 VDDIO C5 ADVREF E5 PA25 G5 VDDCORE
A6 GND C6 PB3 E6 PA23 G6 PA14
A7 PB9 C7 PB1 E7 PA18 G7 PA20
A8 PB14 C8 PB0 E8 VDDIN G8 PA19
B1 PB5 D1 VDDIO F1 PA27 H1 PA7
B2 JTAGSEL D2 PA3 F2 VDDCORE H2 PA8
B3 PB6 D3 PA30 F3 PA4 H3 PA10
B4 PB11 D4 PA2 F4 PB4 H4 PA12
B5 PB13 D5 PA13 F5 PA26 H5 PA24
B6 VDDPLL D6 PA21 F6 PA16 H6 PA15
B7 PB8 D7 PA17 F7 PA22 H7 VDDIO
B8 GND D8 PB2 F8 VDDOUT H8 GND
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5. Power Considerations
5.1 Power Supplies
The SAM4S has several types of power supply pins:
VDDCORE pins: Power the core, the first flash rail and the embedded memories and peripherals. Voltage ranges
from 1.08V to 1.32V.
VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers), the second flash rail, USB transceiver, Backup
part, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62V to 3.6V.
VDDIN pin: Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply. Voltage ranges from
1.62V to 3.6V.
VDDPLL pin: Powers the PLLA, PLLB, the Fast RC and the 3 to 20 MHz oscillator. Voltage ranges from 1.08V to
1.32V.
5.2 Voltage Regulator
The SAM4S embeds a voltage regulator that is managed by the Supply Controller.
This internal regulator is designed to supply the internal core of SAM4S It features two operating modes:
In Normal mode, the voltage regulator consumes less than 500 μA static current and draws 80 mA of output
current. Internal adaptive biasing adjusts the regulator quiescent current depending on the required load current.
In Wait Mode quiescent current is only 5 μA.
In Backup mode, the voltage regulator consumes less than 1μA while its output (VDDOUT) is driven internally to
GND. The default output voltage is 1.20V and the start-up time to reach Normal mode is less than 300 μs.
For adequate input and output power supply decoupling/bypassing, refer to the “Voltage Regulator” section in the
“Electrical Characteristics” section of the datasheet.
5.3 Typical Powering Schematics
The SAM4S supports a 1.62V-3.6V single supply mode. The internal regulator input is connected to the source and its
output feeds VDDCORE. Figure 5-1 below shows the power schematics.
As VDDIN powers the voltage regulator, the ADC, DAC and the analog comparator, when the user does not want to use
the embedded voltage regulator, it can be disabled by software via the SUPC (note that this is different from Backup
mode).
Figure 5-1. Single Supply
Note: Restrictions
For USB, VDDIO needs to be greater than 3.0V.
Main Supply
(1.62V-3.6V) ADC, DAC
Analog Comp.
USB
Transceivers.
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDIO
VDDPLL
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For ADC, VDDIN needs to be greater than 2.0V.
For DAC, VDDIN needs to be greater than 2.4V.
Figure 5-2. Core Externally Supplied
Note: Restrictions
For USB, VDDIO needs to be greater than 3.0V.
For ADC, VDDIN needs to be greater than 2.0V.
For DAC, VDDIN needs to be greater than 2.4V.
Figure 5-3 below provides an example of the powering scheme when using a backup battery. Since the PIO state is
preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the PIO line
at low level (PIO is input, pull-up enabled after backup reset). External wake-up of the system can be from a push button
or any signal. See Section 5.6 “Wake-up Sources” for further details.
Figure 5-3. Backup Battery
Main Supply
(1.62V-3.6V)
Can be the
same supply
VDDCORE Supply
(1.08V-1.32V)
ADC, DAC, Analog
Comparator Supply
(2.0V-3.6V)
ADC, DAC
Analog Comp.
USB
Transceivers.
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDIO
VDDPLL
ADC, DAC
Analog Comp.
USB
Transceivers.
VDDIN
Voltage
Regulator
3.3V
LDO
Backup
Battery +
-
ON/OFF
IN OUT VDDOUT
Main Supply
VDDCORE
ADC, DAC, Analog
Comparator Supply
(2.0V-3.6V)
VDDIO
VDDPLL
PIOx (Output)
WAKEUPx
External wakeup signal
Note: The two diodes provide a “switchover circuit”(for illustration purpose)
between the backup battery and the main supply when the system is put in
backup mode.
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5.4 Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator
or the PLLA. The Power Management Controller can be used to adapt the frequency and to disable the peripheral clocks.
5.5 Low-power Modes
The SAM4S has the following low-power modes: backup mode, wait mode and sleep mode.
Note: The Wait For Event instruction (WFE) of the Cortex-M4 core can be used to enter any of the low-power modes, how-
ever, this may add complexity in the design of application state machines. This is due to the fact that the WFE
instruction goes along with an event flag of the Cortex core (cannot be managed by the software application). The
event flag can be set by interrupts, a debug event or an event signal from another processor. Since it is possible for an
interrupt to occur just before the execution of WFE, WFE takes into account events that happened in the past. As a
result, WFE prevents the device from entering wait mode if an interrupt event has occurred.
Atmel has made provision to avoid using the WFE instruction. The workarounds to ease application design are as fol-
lows:
- For backup mode, switch off the voltage regulator and configure the VROFF bit in the Supply Controller Control Reg-
ister (SUPC_CR).
- For wait mode, configure the WAITMODE bit in the PMC Clock Generator Main Oscillator Register of the Power Man-
agement Controller (PMC)
- For sleep mode, use the Wait for Interrupt (WFI) instruction.
Complete information is available in Table 5-1 “Low-power Mode Configuration Summary".
5.5.1 Backup Mode
The purpose of backup mode is to achieve the lowest power consumption possible in a system which is performing
periodic wake-ups to perform tasks but not requiring fast startup time. Total current consumption is 1 μA typical (VDDIO
= 1.8 V to 25°).
The Supply Controller, zero-power power-on reset, RTT, RTC, backup registers and 32 kHz oscillator (RC or crystal
oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off.
The SAM4S can be awakened from this mode using the WKUP0-15 pins, the supply monitor (SM), the RTT or RTC
wake-up event.
Backup mode is entered by writing a 1 to the VROFF bit of the Supply Controller Control Register (SUPC_CR) (A key is
needed to write the VROFF bit, refer to the Supply Controller SUPC section of the product datasheet) and with the
SLEEPDEEP bit in the Cortex-M4 System Control Register set to 1. (See the power management description in the ARM
Cortex-M4 Processor section of the product datasheet).
To enter backup mode using the VROFF bit:
Write a 1 to the VROFF bit of SUPC_CR.
To enter backup mode using the WFE instruction:
Write a 1 to the SLEEPDEEP bit of the Cortex-M4 processor.
Execute the WFE instruction of the processor.
In both cases, exit from backup mode happens if one of the following enable wake up events occurs:
WKUPEN0-15 pins (level transition, configurable debouncing)
Supply Monitor alarm
RTC alarm
RTT alarm
5.5.2 Wait Mode
The purpose of wait mode is to achieve very low power consumption while maintaining the whole device in a powered
state for a startup time of less than 10 μs. Current consumption in wait mode is typically 32 μA (total current
consumption) if the internal voltage regulator is used.
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In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and
memories power supplies are still powered. From this mode, a fast start up is available.
This mode is entered by setting the WAITMODE bit to 1 in the CKGR_MOR register in conjunction with FLPM = 0 or
FLPM = 1 bits of the PMC_FSMR register or by the WFE instruction.
The Cortex-M4 is able to handle external or internal events in order to wake-up the core. This is done by configuring the
external lines WUP0-15 as fast startup wake-up pins (refer to Section 5.7 “Fast Start-up”). RTC or RTT Alarm and USB
wake-up events can be used to wake up the CPU.
To enter wait mode with WAITMODE bit:
Select the 4/8/12 MHz fast RC oscillator as Main Clock.
Set the FLPM field in the PMC Fast Startup Mode Register (PMC_FSMR).
Set Flash Wait State at 0.
Set the WAITMODE bit = 1 in PMC Main Oscillator Register (CKGR_MOR).
Wait for Master Clock Ready MCKRDY = 1 in the PMC Status Register (PMC_SR).
To enter wait mode with WFE:
Select the 4/8/12 MHz fast RC oscillator as Main Clock.
Set the FLPM field in the PMC Fast Startup Mode Register (PMC_FSMR).
Set Flash Wait State at 0.
Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR).
Execute the Wait-For-Event (WFE) instruction of the processor.
In both cases, depending on the value of the field Flash Low Power Mode (FLPM), the Flash enters three different
modes:
FLPM = 0 in Standby mode (Low consumption)
FLPM = 1 in Deep power-down mode (Extra low consumption)
FLPM = 2 in Idle mode. Memory ready for Read access
Table 5-1 summarizes the power consumption, wake-up time and system state in wait mode.
5.5.3 Sleep Mode
The purpose of sleep mode is to optimize power consumption of the device versus response time. In this mode, only the
core clock is stopped. The peripheral clocks can be enabled. The current consumption in this mode is application
dependent.
This mode is entered via Wait for Interrupt (WFI) or WFE instructions.
The processor can be awakened from an interrupt if the WFI instruction of the Cortex-M4 is used or from an event if the
WFE instruction is used.
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5.5.4 Low-power Mode Summary Table
The modes detailed above are the main low-power modes. Each part can be set to on or off separately and wake up
sources can be individually configured. Table 5-1 below shows a summary of the configurations of the low-power modes.
Notes: 1. The external loads on PIOs are not taken into account in the calculation.
2. Supply Monitor current consumption is not included.
3. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the 4/8/12
MHz fast RC oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up time is defined as the time
taken for wake up until the first instruction is fetched.
4. Total consumption 1 μA typ to 1.8V on VDDIO to 25°C.
5. 20.4 μA on VDDCORE, 32.2 μA for total current consumption.
6. Depends on MCK frequency.
7. Depends on MCK frequency. In this mode, the core is supplied but some peripherals can be clocked.
Table 5-1. Low-power Mode Configuration Summary
Mode
SUPC,
32 kHz Osc,
RTC, RTT
Backup
Registers,
POR
(Backup
Region) Regulator
Core
Memory
Peripherals Mode Entry Potential Wake Up
Sources
Core at
Wake
Up
PIO State
while in Low
Power Mode
PIO State
at Wake
Up
Consumption
(1) (2) Wake-up
Time(3)
Backup
Mode ON OFF OFF
(Not powered)
VROFF = 1
or
WFE +
SLEEPDEEP = 1
WUP0-15 pins
SM alarm
RTC alarm
RTT alarm
Reset Previous state
saved
PIOA &
PIOB &
PIOC
Inputs with
pull ups
1 μA typ(4) < 1 ms
Wait Mode
w/Flash in
Standby
Mode
ON ON Powered
(Not clocked)
WAITMODE = 1
+ FLPM = 0
or
WFE +
SLEEPDEEP = 0
+ LPM = 1
+ FLPM = 0
Any Event from:
Fast startup through
WUP0-15 pins
RTC alarm
RTT alarm
USB wake-up
Clocked
back Previous state
saved Unchange
d32.2 μA(5) < 10 μs
Wait Mode
w/Flash in
Deep Power
Down Mode
ON ON Powered
(Not clocked)
WAITMODE = 1
+ FLPM = 1
or
WFE +
SLEEPDEEP = 0
+ LPM = 1
+ FLPM = 1
Any Event from:
Fast startup through
WUP0-15 pins
RTC alarm
RTT alarm
USB wake-up
Clocked
back Previous state
saved Unchange
d27.6 μA< 100 μs
Sleep Mode ON ON Powered(6)
(Not clocked)
WFE
or
WFI +
SLEEPDEEP = 0
+ LPM = 0
Entry mode =WFI
Interrupt Only;
Entry mode =WFE
Any Enabled Interrupt
and/or Any Event
from:
Fast start-up through
WUP0-15 pins
RTC alarm
RTT alarm
USB wake-up
Clocked
back Previous state
saved Unchange
d(7) (7)
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5.6 Wake-up Sources
The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller
performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they are not
already enabled.
Figure 5-4. Wake-up Source
WKUP15
WKUPEN15
WKUPT15
WKUPEN1
WKUPEN0
Debouncer
SLCK
WKUPDBC
WKUPS
RTCEN
rtc_alarm
SMEN
sm_out
Core
Supply
Restart
WKUPIS0
WKUPIS1
WKUPIS15
Falling/Rising
Edge
Detector
WKUPT0
Falling/Rising
Edge
Detector
WKUPT1
Falling/Rising
Edge
Detector
WKUP0
WKUP1
RTTEN
rtt_alarm
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5.7 Fast Start-up
The SAM4S allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start-up can
occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + USB + RTC + RTT).
The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast start-up signal to the Power
Management Controller. As soon as the fast start-up signal is asserted, the PMC automatically restarts the embedded
4/8/12 MHz Fast RC oscillator, switches the master clock on this 4 MHz clock and reenables the processor clock.
Figure 5-5. Fast Start-up Sources
fast_restart
WKUP15
FSTT15
FSTP15
WKUP1
FSTT1
FSTP1
WKUP0
FSTT0
FSTP0
RTTAL
RTCAL
USBAL
RTT Alarm
RTC Alarm
USB Alarm
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6. Input/Output Lines
The SAM4S has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs
can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used
whether in I/O mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or
analog inputs.
6.1 General Purpose I/O Lines
GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such as pull-up or pull-down,
input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. Programming of these
modes is performed independently for each I/O line through the PIO controller user interface. For more details, refer to
the product “PIO Controller” section.
Some GPIOs can have alternate function as analog input. When the GPIO is set in analog mode, all digital features of
the I/O are disabled.
The input/output buffers of the PIO lines are supplied through VDDIO power supply rail.
The SAM4S embeds high speed pads able to handle up to 70 MHz for HSMCI (MCK/2), 70 MHz for SPI clock lines and
46 MHz on other lines. See the “AC Characteristics” sub-section of the product Electrical Characteristics. Typical pull-up
and pull-down value is 100 kΩ for all I/Os.
Each I/O line also embeds an ODT (On-Die Termination), (see Figure 6-1 below). It consists of an internal series resistor
termination scheme for impedance matching between the driver output (SAM4S) and the PCB trace impedance
preventing signal reflection. The series resistor helps to reduce IOs switching current (di/dt) thereby reducing in turn,
EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between devices or
between boards. In conclusion ODT helps diminish signal integrity issues.
Figure 6-1. On-Die Termination
6.2 System I/O Lines
System I/O lines are pins used by oscillators, test mode, reset and JTAG to name but a few. Described below in Table 6-
1are the SAM4S system I/O lines shared with PIO lines.
These pins are software configurable as general purpose I/O or system pins. At startup the default function of these pins
is always used.
PCB Trace
Z0 ~ 50 Ohms
Receiver
SAM4 Driver with
Rodt
Zout ~ 10 Ohms
Z0 ~ Zout + Rodt
ODT
36 Ohms Typ.
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Notes: 1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before
the user application sets PB12 into PIO mode,
2. In the product Datasheet Refer to: “Slow Clock Generator” of the “Supply Controller” section.
3. In the product Datasheet Refer to: “3 to 20 MHZ Crystal Oscillator” information in the “PMC” section.
6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on a standard 20-pin JTAG
connector defined by ARM. For more details about voltage reference and reset state, refer to Table 3-1 on page 8.
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Please refer to the
“Debug and Test” Section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port is not
needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general IO mode is
performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad for pull-up,
triggers, debouncing and glitch filters is possible regardless of the mode.
The JTAG pin and PA7 pin are used to select the JTAG Boundary Scan when asserted JTAGSEL at a high level and
PA7 at low level. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected
for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it must
provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and enables the
SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used
with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, please refer to the “Debug and
Test” Section.
6.3 Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM4S
series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected
for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface (FFPI) section. For
more on the manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet.
Table 6-1. System I/O Configuration Pin List.
SYSTEM_IO
bit number Default function
after reset Other function Constraints for
normal start Configuration
12 ERASE PB12 Low Level at startup(1)
In Matrix User Interface Registers
(Refer to the System I/O
Configuration Register in the “Bus
Matrix” section of the datasheet.)
10 DDM PB10 -
11 DDP PB11 -
7 TCK/SWCLK PB7 -
6 TMS/SWDIO PB6 -
5 TDO/TRACESWO PB5 -
4 TDI PB4 -
- PA7 XIN32 - See footnote (2) below
- PA8 XOUT32 -
- PB9 XIN - See footnote (3) below
- PB8 XOUT -
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6.4 NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal
to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the
peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset
pulse and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up
resistor to VDDIO of about 100 kΩ. By default, the NRST pin is configured as an input.
6.5 ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read as
logic level 1). It integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left unconnected for normal
operations.
This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high during less than 100
ms, it is not taken into account. The pin must be tied high during more than 220 ms to perform a Flash erase operation.
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured as a
PIO pin. If the ERASE pin is used as a standard I/O, startup level of this pin must be low to prevent unwanted erasing.
Refer to Section 11.2 “Peripheral Signal Multiplexing on I/O Lines” on page 42. Al so, if the ER ASE pi n is used as a
standard I/O output, asserting the pin to low does not erase the Flash.
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7. Product Mapping
Figure 7-1. SAM4S Product Mapping
Address memory space
Code
1 MByte
bit band
region
1 MByte
bit band
1 MByte
bit band
regiion
0x00000000
SRAM
0x20000000
0x20100000
0x20400000
0x22000000
0x24000000
offset
ID
peripheral
block
Code
Boot Memory
0x00000000
0x00400000
0x00800000
Reserved
0x00C00000
0x1FFFFFFF
Peripherals
HSMCI 18
0x40000000
SSC 22
0x40004000
SPI 21
0x40008000
0x4000C000
TC0 TC0
0x40010000
23
TC0 TC1
+0x40
24
TC0 TC2
+0x80
25
TC1 TC3
0x40014000
26
TC1 TC4
+0x40
27
TC1 TC5
+0x80
28
TWI0 19
0x40018000
TWI1 20
0x4001C000
PWM 31
0x40020000
USART0
USART1
14
0x40024000
15
0x40028000
0x4002C000
Reserved
Reserved
0x40030000
UDP 33
0x40034000
ADC 29
0x40038000
DACC 30
0x4003C000
ACC 34
0x40040000
CRCCU 35
0x40044000
0x40048000
System Controller
0x400E0000
0x400E2600
0x40100000
0x42000000
0x43FFFFFF
0x60000000
External RAM
SMC Chip Select 0
0x60000000
SMC Chip Select 1
Undefined
32 MBytes
bit band alias
0x61000000
SMC Chip Select 2
0x62000000
SMC Chip Select 3
0x63000000
0x64000000
0x9FFFFFFF
System Controller
SMC 10
0x400E0000
MATRIX
0x400E0200
PMC 5
0x400E0400
UART0
UART1
8
0x400E0600
CHIPID
0x400E0740
9
0x400E0800
EFC 6
0x400E0A00
0x400E0C00
PIOA 11
0x400E0E00
PIOB 12
0x400E1000
PIOC 13
0x400E1200
RSTC
0x400E1400
1
SUPC
+0x10
RTT
+0x30
3
WDT
+0x50
4
RTC
+0x60
2
GPBR
+0x90
0x400E1600
0x4007FFFF
Internal Flash
Internal ROM
Reserved
Peripherals
External SRAM
0x60000000
0xA0000000
System
0xE0000000
0xFFFFFFFF
Reserved
Reserved
EFC1
Reserved
Reserved
Reserved
Reserved
32 MBytes
bit band alias
Reserved
Undefined
0x40000000
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8. Memories
8.1 Embedded Memories
8.1.1 Internal SRAM
The SAM4SD32 device (2x1024 Kbytes) embeds a total of 160-Kbytes high-speed SRAM.
The SAM4SD16 device (2x512KBytes)embeds a total of 160-Kbytes high-speed SRAM.
The SAM4SA16 device (1024 Kbytes) embeds a total of 160-Kbytes high-speed SRAM.
The SAM4S16 device (1024 Kbytes) embeds a total of 128-Kbytes high-speed SRAM.
The SAM4S8 device (512 Kbytes) embeds a total of 128-Kbytes high-speed SRAM.
The SRAM is accessible over System Cortex-M4 bus at address 0x2000 0000.
The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 to 0x23FF FFFF.
8.1.2 Internal ROM
The SAM4S embeds an Internal ROM, which contains the SAM Boot Assistant (SAM-BA®), In Application Programming
routines (IAP) and Fast Flash Programming Interface (FFPI).
At any time, the ROM is mapped at address 0x0080 0000.
8.1.3 Embedded Flash
8.1.3.1 Flash Overview
The memory is organized in sectors. Each sector has a size of 64 KBytes. The first sector of 64 KBytes is divided into 3
smaller sectors.
The three smaller sectors are organized to consist of 2 sectors of 8 KBytes and 1 sector of 48 KBytes. Refer to Figure 8-
1, "Global Flash Organization" below.
Figure 8-1. Global Flash Organization
Small Sector 0
8 KBytes
Small Sector 1
8 KBytes
Larger Sector
48 KBytes
Sector 164 KBytes
64 KBytes Sector n
Sector 0
Sector size Sector name
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Each Sector is organized in pages of 512 Bytes.
For sector 0:
The smaller sector 0 has 16 pages of 512Bytes
The smaller sector 1 has 16 pages of 512 Bytes
The larger sector has 96 pages of 512 Bytes
From Sector 1 to n:
The rest of the array is composed of 64-KByte sectors of 128 pages, each page of 512 bytes. Refer to Figure 8-2, "Flash
Sector Organization" below.
Figure 8-2. Flash Sector Organization
Flash size varies by product:
SAM4S8/S16: the Flash size is 512 KBytes
Internal Flash address is 0x0040_0000
SAM4SD16/SA16: the Flash size is 2 x 512 KBytes
Internal Flash0 address is 0x0040_0000
Internal Flash1 address is 0x0048_0000
SAM4SD32: the Flash size is 2 x 1024 KBytes
Internal Flash0 address is 0x0040_0000
Internal Flash1 address is 0x0050_0000
Refer to Figure 8-3, "Flash Size" below for the organization of the Flash following its size.
Sector 0
Sector 1
Smaller sector 0
Smaller sector 1
Larger sector
A sector size is 64 KBytes
16 pages of 512 Bytes
16 pages of 512 Bytes
96 pages of 512 Bytes
128 pages of 512 Bytes
Sector n 128 pages of 512 Bytes
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Figure 8-3. Flash Size
Erasing the memory can be performed as follows:
On a 512-byte page inside a sector, of 8K Bytes
Note: EWP and EWPL commands can be only used in 8 KBytes sectors.
On a 4-Kbyte Block inside a sector of 8 KBytes/48 Kbytes/64 KBytes
Note: Erase Page commands can be only used with FARG[1:0] = 1
On a sector of 8 KBytes/48 KBytes/64 KBytes
Note: Erase Page commands can be only used with FARG[1:0] = 2
On chip
The Write commands of the Flash cannot be used under 330 kHz.
8.1.3.2 Enhanced Embedded Flash Controller
The Enhanced Embedded Flash Controller manages accesses performed by the masters of the system. It enables
reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB.
The Enhanced Embedded Flash Controller ensures the interface of the Flash block.
It manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands.
One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash
organization, thus making the software generic.
8.1.3.3 Flash Speed
The user needs to set the number of wait states depending on the frequency used:
For more details, refer to the “AC Characteristics” sub-section of the product “Electrical Characteristics”.
8.1.3.4 Lock Regions
Several lock bits are used to protect write and erase operations on lock regions. A lock region is composed of several
consecutive pages, and each lock region has its associated lock bit.
2 * 8 KBytes
1 * 48 KBytes
15 * 64 KBytes
2 * 8 KBytes
1 * 48 KBytes
7 * 64 KBytes
2 * 8 KBytes
1 * 48 KBytes
3 * 64 KBytes
Flash 1 MBytes Flash 512 KBytes Flash 256 KBytes
Table 8-1. Lock Bit Number
Product Number of Lock Bits Lock Region Size
SAM4SD32 256 (128 + 128) 8 Kbytes
SAM4SD16 128 (64 + 64) 8 Kbytes
SAM4S16/SA16 128 8 Kbytes
SAM4S8 64 8 Kbytes
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If a locked-region’s erase or program command occurs, the command is aborted and the EEFC triggers an interrupt.
The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables the
protection. The command “Clear Lock Bit” unlocks the lock region.
Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.
8.1.3.5 Security Bit Feature
The SAM4SD32 and SAM4SD16 feature 2 security bits, the SAM4S16/SA16/S8 feature a security bit, based on a
specific General Purpose NVM bit (GPNVM bit 0). When one of the security bits is enabled, any access to the Flash,
SRAM, Core Registers and Internal Peripherals either through the ICE interface or through the Fast Flash Programming
Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.
This security bit can only be enabled, through the command “Set General Purpose NVM Bit 0” of the EEFC User
Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is
performed. When the security bit is deactivated, all accesses to the Flash, SRAM, Core registers, Internal Peripherals
are permitted.
It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.
As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is
safer to connect it directly to GND for the final application.
8.1.3.6 Calibration Bits
NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and
cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
8.1.3.7 Unique Identifier
Each device integrates its own 128-bit unique identifier. These bits are factory configured and cannot be changed by the
user. The ERASE pin has no effect on the unique identifier.
8.1.3.8 User Signature
Each part contains a User Signature of 512 bytes. It can be used by the user to store user information such as trimming,
keys, etc., that the customer does not want to be erased by asserting the ERASE pin or by software ERASE command.
Read, write and erase of this area is allowed.
8.1.3.9 Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through a multiplexed fully-handshaked parallel
port. It allows gang programming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.
8.1.3.10SAM-BA Boot
The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory.
The SAM-BA Boot Assistant supports serial communication via the UART and USB.
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0.
8.1.3.11GPNVM Bits
The SAM4S16 features two GPNVM bits. These bits can be cleared or set respectively through the commands “Clear
GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.
The Flash of the SAM4S8 is composed of 512 Kbytes in a single bank.
The SAM4SA16/SD32/SD16 features 3 GPNVM bits (GPNVM from Flash0) that can be cleared or set respectively
through the "Clear GPNVM Bit" and "Set GPNVM Bit" commands of the EEFC0 User Interface. The GPNVM bits of the
SAM4SA16/SD16/SD32 are only available on FLash0. There is no GPNVM bit on Flash1. The GPNVM0 is the security
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bit. The GPNVM1 is used to select the boot mode (boot always at 0x00) on ROM or FLASH. The SAM4SD32/16 embeds
an additional GPNVM bit: GPNVM2. This GPNVM bit is used only to swap the Flash0 and Flash1. If GPNVM bit 2 is:
ENABLE: the Flash1 is mapped at address 0x0040_0000 (Flash1 and Flash0 are continuous). DISABLE: the Flash0 is
mapped at address 0x0040_0000 (Flash0 and Flash1 are continuous).
8.1.4 Boot Strategies
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed via
GPNVM.
A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash.
The GPNVM bit can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set
General-purpose NVM Bit” of the EEFC User Interface.
Setting GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE clears
the GPNVM Bit 1 and thus selects the boot from the ROM by default.
Setting the GPNVM Bit 2 selects bank 1, clearing it selects the boot from bank 0. Asserting ERASE clears the GPNVM
Bit 2 and thus selects the boot from bank 0 by default.
8.2 External Memories
The SAM4S features one External Bus Interface to provide an interface to a wide range of external memories and to any
parallel peripheral.
8.2.1 Static Memory Controller
16-Mbyte Address Space per Chip Select
8- bit Data Bus
Word, Halfword, Byte Transfers
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
Programmable Data Float Time per Chip Select
External Wait Request
Automatic Switch to Slow Clock Mode
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
NAND Flash additional logic supporting NAND Flash with Multiplexed Data/Address buses
Hardware Configurable number of chip selects from 1 to 4
Programmable timing on a per chip select basis
Table 8-2. General-purpose Non volatile Memory Bits
GPNVMBit[#] Function
0 Security bit
1 Boot mode selection
2 Flash selection (Flash 0 or Flash 1)
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9. Real Time Event Management
The events generated by peripherals are designed to be directly routed to peripherals managing/using these events
without processor intervention. Peripherals receiving events contain logic by which to select the one required.
9.1 Embedded Characteristics
Timers, PWM, IO peripherals generate event triggers which are directly routed to event managers such as ADC or
DACC, for example, to start measurement/conversion without processor intervention.
UART, USART, SPI, TWI, SSC, PWM, HSMCI, ADC, DACC, PIO also generate event triggers directly connected
to Peripheral DMA Controller (PDC) for data transfer without processor intervention.
Parallel capture logic is directly embedded in PIO and generates trigger event to Peripheral DMA Controller to
capture data without processor intervention.
PWM security events (faults) are in combinational form and directly routed from event generators (ADC, ACC,
PMC, TIMER) to PWM module.
PMC security event (clock failure detection) can be programmed to switch the MCK on reliable main RC internal
clock without processor intervention.
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9.2 Real Time Event Mapping List
Table 9-1. Real Time Event Mapping List
Event Generator Event Manager Function
IO (WKUP0/1) General Purpose Backup Register
(GPBR) Security / Immediate GPBR clear (asynchronous) on
Tamper detection through WKUP0/1 IO pins.
Power Management Controller
(PMC) PMC Safety / Automatic Switch to Reliable Main RC oscillator
in case of Main Crystal Clock Failure
PMC Pulse Width Modulation(PWM) Safety / Puts the PWM Outputs in Safe Mode (Main
Crystal Clock Failure Detection)
Analog Comparator Controller
(ACC) PWM Safety / Puts the PWM Outputs in Safe Mode
(Overcurrent sensor, ...)
Analog-to-Digital Converter (ADC) PWM Safety / Puts the PWM Outputs in Safe Mode
(Overspeed,Overcurrent detection ...)
Timer Counter (TC) PWM Safety / Puts the PWM Outputs in Safe Mode
(Overspeed detection through TIMER Quadrature
Decoder)
IO PWM Safety / Puts the PWM Outputs in Safe Mode (General
Purpose Fault Inputs)
IO Parallel Capture (PC) PC is embedded in PIO (Capture Image from Sensor
directly to System Memory)
IO (ADTRG) ADC Trigger for measurement. Selection in ADC module
TC Output 0 ADC Trigger for measurement. Selection in ADC module
TC Output 1 ADC Trigger for measurement. Selection in ADC module
TC Output 2 ADC Trigger for measurement. Selection in ADC module
PWM Event Line 0 ADC Trigger for measurement. PWM contains a
programmable delay for this trigger.
PWM Event Line 1 ADC Trigger for measurement. PWM contains a
programmable delay for this trigger.
IO (DATRG) DACC (Digital-Analog Converter
Controller) Trigger for conversion. Selection in DAC module
TC Output 0 DACC Trigger for conversion. Selection in DAC module
TC Output 1 DACC Trigger for conversion. Selection in DAC module
TC Output 2 DACC Trigger for conversion. Selection in DAC module
PWM Event Line 0 DACC Trigger for conversion. Selection in DAC module
PWM Event Line 1 DACC Trigger for conversion. Selection in DAC module
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Figure 10-1. System Controller Block Diagram
Software Controlled
Voltage Regulator
Matrix
SRAM
Watchdog
Timer
Cortex-M4
Flash
Peripherals
Peripheral
Bridge
Zero-Power
Power-on Reset
Supply
Monitor
(Backup)
RTC
Power
Management
Controller
Embedded
32 kHz RC
Oscillator
Xtal 32 kHz
Oscillator
Supply
Controller
Brownout
Detector
(Core)
Reset
Controller
Backup Power Supply
Core Power Supply
PLLA
vr_on
vr_mode
ON
out
rtc_alarm
SLCK rtc_nreset
proc_nreset
periph_nreset
ice_nreset
Master Clock
MCK
SLCK
NRST
MAINCK
FSTT0 - FSTT15
XIN32
XOUT32
osc32k_xtal_en
Slow Clock
SLCK
osc32k_rc_en
VDDIO
VDDCORE
VDDOUT
ADVREF
ADx
WKUP0 - WKUP15
bod_core_on
lcore_brown_out
RTT
rtt_alarm
SLCK rtt_nreset
XIN
XOUT
VDDIO
VDDIN
PIOx
USB
Transeivers
VDDIO
DDP
DDM
MAINCK
DAC Analog
Circuitry
DACx
PLLB PLLBCK
PLLACK
Embedded
12 / 8 / 4 MHz
RC
Oscillator
Main Clock
MAINCK
SLCK
3 - 20 MHz
XTAL Oscillator
VDDIO
XTALSEL
General Purpose
Backup Registers
vddcore_nreset
vddcore_nreset
PIOA/B/C
Input/Output Buffers
ADC Analog
Circuitry
Analog
Comparator
FSTT0 - FSTT15 are possible Fast Startup sources, generated by WKUP0 - WKUP15 pins,
but are not physical pins.
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10.1 System Controller and Peripheral Mapping
Refer to Figure 7-1, "SAM4S Product Mapping".
All the peripherals are in the bit band region and are mapped in the bit band alias region.
10.2 Power-on-Reset, Brownout and Supply Monitor
The SAM4S embeds three features to monitor, warn and/or reset the chip:
• Power-on-Reset on VDDIO
• Brownout Detector on VDDCORE
• Supply Monitor on VDDIO
10.2.1 Power-on-Reset
The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but also during power down.
If VDDIO goes below the threshold voltage, the entire chip is reset. For more information, refer to the Electrical
Characteristics section of the datasheet.
10.2.2 Brownout Detector on VDDCORE
The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by software through the Supply
Controller (SUPC_MR). It is especially recommended to disable it during low-power modes such as wait or sleep modes.
If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more information, refer to the
Supply Controller (SUPC) and Electrical Characteristics sections of the datasheet.
10.2.3 Supply Monitor on VDDIO
The Supply Monitor monitors VDDIO. It is not active by default. It can be activated by software and is fully programmable
with 16 steps for the threshold (between 1.6V to 3.4V). It is controlled by the Supply Controller (SUPC). A sample mode
is possible. It allows to divide the supply monitor power consumption by a factor of up to 2048. For more information,
refer to the SUPC and Electrical Characteristics sections of the datasheet.
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11. Peripherals
11.1 Peripheral Identifiers
Table 11-1 defines the Peripheral Identifiers of the SAM4S. A peripheral identifier is required for the control of the
peripheral interrupt with the Nested Vectored Interrupt Controller and control of the peripheral clock with the Power
Management Controller.
Table 11-1. Peripheral Identifiers
Instance ID Instance Name NVIC Interrupt PMC
Clock Control Instance Description
0 SUPC X Supply Controller
1 RSTC X Reset Controller
2 RTC X Real Time Clock
3 RTT X Real Time Timer
4 WDT X Watchdog Timer
5 PMC X Power Management Controller
6 EEFC0 X Enhanced Embedded Flash Controller 0
7 EEFC1 - Enhanced Embedded Flash Controller 1
8 UART0 X X UART 0
9 UART1 X X UART 1
10 SMC - X Static Memory Controller
11 PIOA X X Parallel I/O Controller A
12 PIOB X X Parallel I/O Controller B
13 PIOC X X Parallel I/O Controller C
14 USART0 X X USART 0
15 USART1 X X USART 1
16 - - - Reserved
17 - - - Reserved
18 HSMCI X X Multimedia Card Interface
19 TWI0 X X Two Wire Interface 0
20 TWI1 X X Two Wire Interface 1
21 SPI X X Serial Peripheral Interface
22 SSC X X Synchronous Serial Controller
23 TC0 X X Timer/Counter 0
24 TC1 X X Timer/Counter 1
25 TC2 X X Timer/Counter 2
26 TC3 X X Timer/Counter 3
27 TC4 X X Timer/Counter 4
28 TC5 X X Timer/Counter 5
29 ADC X X Analog To Digital Converter
30 DACC X X Digital To Analog Converter
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11.2 Peripheral Signal Multiplexing on I/O Lines
The SAM4S features 2 PIO controllers on 64-pin versions (PIOA and PIOB) or 3 PIO controllers on the 100-pin version
(PIOA, PIOB and PIOC), that multiplex the I/O lines of the peripheral set.
The SAM4S 64-pin and 100-pin PIO Controllers control up to 32 lines. Each line can be assigned to one of three
peripheral functions: A, B or C. The multiplexing tables in the following paragraphs define how the I/O lines of the
peripherals A, B and C are multiplexed on the PIO Controllers. The column “Comments” has been inserted in this table
for the user’s own comments; it may be used to track how pins are defined in an application.
Note that some peripheral functions which are output only, might be duplicated within the tables.
31 PWM X X Pulse Width Modulation
32 CRCCU X X CRC Calculation Unit
33 ACC X X Analog Comparator
34 UDP X X USB Device Port
Table 11-1. Peripheral Identifiers (Continued)
Instance ID Instance Name NVIC Interrupt PMC
Clock Control Instance Description
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11.2.1 PIO Controller A Multiplexing
Table 11-2. Multiplexing on PIO Controller A (PIOA)
I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comments
PA0 PWMH0 TIOA0 A17 WKUP0
PA1 PWMH1 TIOB0 A18 WKUP1
PA2 PWMH2 SCK0 DATRG WKUP2
PA3 TWD0 NPCS3
PA4 TWCK0 TCLK0 WKUP3
PA5 RXD0 NPCS3 WKUP4
PA6 TXD0 PCK0
PA7 RTS0 PWMH3 XIN32
PA8 CTS0 ADTRG WKUP5 XOUT32
PA9 URXD0 NPCS1 PWMFI0 WKUP6
PA10 UTXD0 NPCS2
PA11 NPCS0 PWMH0 WKUP7
PA12 MISO PWMH1
PA13 MOSI PWMH2
PA14 SPCK PWMH3 WKUP8
PA15 TF TIOA1 PWML3 WKUP14/PIODCEN1
PA16 TK TIOB1 PWML2 WKUP15/PIODCEN2
PA17 TD PCK1 PWMH3 AD0
PA18 RD PCK2 A14 AD1
PA19 RK PWML0 A15 AD2/WKUP9
PA20 RF PWML1 A16 AD3/WKUP10
PA21 RXD1 PCK1 AD8 64/100 pins versions
PA22 TXD1 NPCS3 NCS2 AD9 64/100 pins versions
PA23 SCK1 PWMH0 A19 PIODCCLK 64/100 pins versions
PA24 RTS1 PWMH1 A20 PIODC0 64/100 pins versions
PA25 CTS1 PWMH2 A23 PIODC1 64/100 pins versions
PA26 DCD1 TIOA2 MCDA2 PIODC2 64/100 pins versions
PA27 DTR1 TIOB2 MCDA3 PIODC3 64/100 pins versions
PA28 DSR1 TCLK1 MCCDA PIODC4 64/100 pins versions
PA29 RI1 TCLK2 MCCK PIODC5 64/100 pins versions
PA30 PWML2 NPCS2 MCDA0 WKUP11/PIODC6 64/100 pins versions
PA31 NPCS1 PCK2 MCDA1 PIODC7 64/100 pins versions
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11.2.2 PIO Controller B Multiplexing
Table 11-3. Multiplexing on PIO Controller B (PIOB)
I/O
Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comments
PB0 PWMH0 AD4/RTCOUT0
PB1 PWMH1 AD5/RTCOUT1
PB2 URXD1 NPCS2 AD6/WKUP12
PB3 UTXD1 PCK2 AD7
PB4 TWD1 PWMH2 TDI
PB5 TWCK1 PWML0 WKUP13 TDO/TRACESWO
PB6 TMS/SWDIO
PB7 TCK/SWCLK
PB8 XOUT
PB9 XIN
PB10 DDM
PB11 DDP
PB12 PWML1 ERASE
PB13 PWML2 PCK0 DAC0 64/100 pins versions
PB14 NPCS1 PWMH3 DAC1 64/100 pins versions
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11.2.3 PIO Controller C Multiplexing
Table 11-4. Multiplexing on PIO Controller C (PIOC)
I/O Line Peripheral A Peripheral B Peripheral C Extra
Function System
Function Comments
PC0 D0 PWML0 100 pin version
PC1 D1 PWML1 100 pin version
PC2 D2 PWML2 100 pin version
PC3 D3 PWML3 100 pin version
PC4 D4 NPCS1 100 pin version
PC5 D5 100 pin version
PC6 D6 100 pin version
PC7 D7 100 pin version
PC8 NWE 100 pin version
PC9 NANDOE 100 pin version
PC10 NANDWE 100 pin version
PC11 NRD 100 pin version
PC12 NCS3 AD12 100 pin version
PC13 NWAIT PWML0 AD10 100 pin version
PC14 NCS0 100 pin version
PC15 NCS1 PWML1 AD11 100 pin version
PC16 A21/NANDALE 100 pin version
PC17 A22/NANDCLE 100 pin version
PC18 A0 PWMH0 100 pin version
PC19 A1 PWMH1 100 pin version
PC20 A2 PWMH2 100 pin version
PC21 A3 PWMH3 100 pin version
PC22 A4 PWML3 100 pin version
PC23 A5 TIOA3 100 pin version
PC24 A6 TIOB3 100 pin version
PC25 A7 TCLK3 100 pin version
PC26 A8 TIOA4 100 pin version
PC27 A9 TIOB4 100 pin version
PC28 A10 TCLK4 100 pin version
PC29 A11 TIOA5 AD13 100 pin version
PC30 A12 TIOB5 AD14 100 pin version
PC31 A13 TCLK5 100 pin version
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12. ARM Cortex-M4
12.1 Description
The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers
significant benefits to developers, including outstanding processing performance combined with fast interrupt handling,
enhanced system debug with extensive breakpoint and trace capabilities, efficient processor core, system and
memories, ultra-low power consumption with integrated sleep modes, and platform security robustness, with integrated
memory protection unit (MPU).
The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture,
making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an
efficient instruction set and extensively optimized design, providing high-end processing hardware including a range of
single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated
hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements tightly-coupled system
components that reduce processor area while significantly improving interrupt handling and system debug capabilities.
The Cortex-M4 processor implements a version of the Thumb® instruction set based on Thumb-2 technology, ensuring
high code density and reduced program memory requirements. The Cortex-M4 instruction set provides the exceptional
performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.
The Cortex-M4 processor closely integrates a configurable NVIC, to deliver industry-leading interrupt performance. The
NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels. The tight integration of the
processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt
latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-
multiple operations. Interrupt handlers do not require wrapping in assembler code, removing any code overhead from the
ISRs. A tail-chain optimization also significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that
enables the entire device to be rapidly powered down while still retaining program state.
12.1.1 System Level Interface
The Cortex-M4 processor provides multiple interfaces using AMBA® technology to provide high speed, low latency
memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables faster
peripheral controls, system spinlocks and thread-safe Boolean data handling.
The Cortex-M4 processor has a Memory Protection Unit (MPU) that provides fine grain memory control, enabling
applications to utilize multiple privilege levels, separating and protecting code, data and stack on a task-by-task basis.
Such requirements are becoming critical in many embedded applications such as automotive.
12.1.2 Integrated Configurable Debug
The Cortex-M4 processor implements a complete hardware debug solution. This provides high system visibility of the
processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for
microcontrollers and other small package devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data watchpoints and a
profiling unit. To enable simple and cost-effective profiling of the system events these generate, a Serial Wire Viewer
(SWV) can export a stream of software-generated messages, data trace, and profiling information through a single pin.
The Flash Patch and Breakpoint Unit (FPB) provides up to 8 hardware breakpoint comparators that debuggers can use.
The comparators in the FPB also provide remap functions of up to 8 words in the program code in the CODE memory
region. This enables applications stored on a non-erasable, ROM-based microcontroller to be patched if a small
programmable memory, for example flash, is available in the device. During initialization, the application in ROM detects,
from the programmable memory, whether a patch is required. If a patch is required, the application programs the FPB to
remap a number of addresses. When those addresses are accessed, the accesses are redirected to a remap table
specified in the FPB configuration, which means the program in the non-modifiable ROM can be patched.
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12.2 Embedded Characteristics
Tight integration of system peripherals reduces area and development costs
Thumb instruction set combines high code density with 32-bit performance
Code-patch ability for ROM system updates
Power control optimization of system components
Integrated sleep modes for low power consumption
Fast code execution permits slower processor clock or increases sleep mode time
Hardware division and fast digital-signal-processing oriented multiply accumulate
Saturating arithmetic for signal processing
Deterministic, high-performance interrupt handling for time-critical applications
Memory Protection Unit (MPU) for safety-critical applications
Extensive debug and trace capabilities:
Serial Wire Debug and Serial Wire Trace reduce the number of pins required for debugging, tracing, and
code profiling.
12.3 Block Diagram
Figure 12-1. Typical Cortex-M4 Implementation
NVIC
Debug
Access
Port Memory
Protection Unit
Serial
Wire
Viewer
Bus Matrix
Code
Interface SRAM and
Peripheral Interface
Data
Watchpoints
Flash
Patch
Cortex-M4
Processor
Processor
Core
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12.4 Cortex-M4 Models
12.4.1 Programmers Model
This section describes the Cortex-M4 programmers model. In addition to the individual core register descriptions, it
contains information about the processor modes and privilege levels for software execution and stacks.
12.4.1.1Processor Modes and Privilege Levels for Software Execution
The processor modes are:
Thread mode
Used to execute application software. The processor enters the Thread mode when it comes out of reset.
Handler mode
Used to handle exceptions. The processor returns to the Thread mode when it has finished exception processing.
The privilege levels for software execution are:
Unprivileged
The software:
Has limited access to the MSR and MRS instructions, and cannot use the CPS instruction
Cannot access the System Timer, NVIC, or System Control Block
Might have a restricted access to memory or peripherals.
Unprivileged software executes at the unprivileged level.
Privileged
The software can use all the instructions and has access to all resources. Privileged software executes at the
privileged level.
In Thread mode, the CONTROL register controls whether the software execution is privileged or unprivileged, see
“CONTROL Register” . In Handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level for software execution in
Thread mode. Unprivileged software can use the SVC instruction to make a supervisor call to transfer control to
privileged software.
12.4.1.2Stacks
The processor uses a full descending stack. This means the stack pointer holds the address of the last stacked item in
memory When the processor pushes a new item onto the stack, it decrements the stack pointer and then writes the item
to the new memory location. The processor implements two stacks, the main stack and the process stack, with a pointer
for each held in independent registers, see “Stack Pointer” .
In Thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack, see
“CONTROL Register” .
In Handler mode, the processor always uses the main stack.
The options for processor operations are:
Note: 1. See “CONTROL Register” .
Table 12-1. Summary of processor mode, execution privilege level, and stack use options
Processor
Mode Used to
Execute Privilege Level for
Software Execution Stack Used
Thread Applications Privileged or
unprivileged (1) Main stack or
process stack(1)
Handler Exception
handlers Always privileged Main stack
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12.4.1.3Core Registers
Figure 12-2. Processor Core Registers
Notes: 1. Describes access type during program execution in thread mode and Handler mode. Debug access can differ.
2. An entry of Either means privileged and unprivileged software can access the register.
SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R4
R2
R10
R11
R12
R8
R9
Low registers
High registers
MSP‡
PSP‡
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
Stack Pointer
Link Register
Program Counter
Program status register
Exception mask registers
CONTROL register
Special registers
‡Banked version of SP
Table 12-2. Core Processor Registers
Register Name Access(1) Required
Privilege(2) Reset
General-purpose registers R0-R12 Read-write Either Unknown
Stack Pointer MSP Read-write Privileged See description
Stack Pointer PSP Read-write Either Unknown
Link Register LR Read-write Either 0xFFFFFFFF
Program Counter PC Read-write Either See description
Program Status Register PSR Read-write Privileged
0x01000000
Application Program Status Register APSR Read-write Either 0x00000000
Interrupt Program Status Register IPSR Read-only Privileged 0x00000000
Execution Program Status Register EPSR Read-only Privileged 0x01000000
Priority Mask Register PRIMASK Read-write Privileged 0x00000000
Fault Mask Register FAULTMASK Read-write Privileged 0x00000000
Base Priority Mask Register BASEPRI Read-write Privileged 0x00000000
CONTROL register CONTROL Read-write Privileged 0x00000000
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12.4.1.4General-purpose Registers
R0-R12 are 32-bit general-purpose registers for data operations.
12.4.1.5Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indicates the stack pointer to
use:
0 = Main Stack Pointer (MSP). This is the reset value.
1 = Process Stack Pointer (PSP).
On reset, the processor loads the MSP with the value from address
0x00000000
.
12.4.1.6Link Register
The Link Register (LR) is register R14. It stores the return information for subroutines, function calls, and exceptions. On
reset, the processor loads the LR value
0xFFFFFFFF
.
12.4.1.7Program Counter
The Program Counter (PC) is register R15. It contains the current program address. On reset, the processor loads the
PC with the value of the reset vector, which is at address 0x00000004. Bit[0] of the value is loaded into the EPSR T-bit at
reset and must be 1.
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12.4.1.8Program Status Register
Name: PSR
Access: Read-write
Reset: 0x000000000
The Program Status Register (PSR) combines:
•Application Program Status Register (APSR)
•Interrupt Program Status Register (IPSR)
•Execution Program Status Register (EPSR).
These registers are mutually exclusive bitfields in the 32-bit PSR.
The PSR register accesses these registers individually or as a combination of any two or all three registers, using the register
name as an argument to the MSR or MRS instructions. For example:
• Read of all the registers using PSR with the MRS instruction
• Write to the APSR N, Z, C, V and Q bits using APSR_nzcvq with the MSR instruction.
The PSR combinations and attributes are:
Notes: 1. The processor ignores writes to the IPSR bits.
2. Reads of the EPSR bits return zero, and the processor ignores writes to these bits
See the instruction descriptions “MRS” and “MSR” for more information about how to access the program status registers.
31 30 29 28 27 26 25 24
N Z C V Q ICI/IT T
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
ICI/IT – ISR_NUMBER
76543210
ISR_NUMBER
Name Access Combination
PSR Read-write(1)(2) APSR, EPSR, and IPSR
IEPSR Read-only EPSR and IPSR
IAPSR Read-write(1) APSR and IPSR
EAPSR Read-write(2) APSR and EPSR
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12.4.1.9 Application Program Status Register
Name: APSR
Access: Read-write
Reset: 0x000000000
The APSR contains the current state of the condition flags from previous instruction executions.
• N: Negative Flag
0: Operation result was positive, zero, greater than, or equal
1: Operation result was negative or less than.
• Z: Zero Flag
0: Operation result was not zero
1: Operation result was zero.
• C: Carry or Borrow Flag
Carry or borrow flag:
0: Add operation did not result in a carry bit or subtract operation resulted in a borrow bit
1: Add operation resulted in a carry bit or subtract operation did not result in a borrow bit.
• V: Overflow Flag
0: Operation did not result in an overflow
1: Operation resulted in an overflow.
• Q: DSP Overflow and Saturation Flag
Sticky saturation flag:
0: Indicates that saturation has not occurred since reset or since the bit was last cleared to zero
1: Indicates when an
SSAT
or
USAT
instruction results in saturation.
This bit is cleared to zero by software using an
MRS
instruction.
• GE[19:16]: Greater Than or Equal Flags
See “SEL” for more information.
31 30 29 28 27 26 25 24
NZCVQ –
23 22 21 20 19 18 17 16
– GE[3:0]
15 14 13 12 11 10 9 8
–
76543210
–
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12.4.1.10Interrupt Program Status Register
Name: IPSR
Access: Read-write
Reset: 0x000000000
The IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
• ISR_NUMBER: Number of the Current Exception
0 = Thread mode
1 = Reserved
2 = NMI
3 = Hard fault
4 = Memory management fault
5 = Bus fault
6 = Usage fault
7-10 = Reserved
11 = SVCall
12 = Reserved for Debug
13 = Reserved
14 = PendSV
15 = SysTick
16 = IRQ0
50 = IRQ34
See “Exception Types” for more information.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
– ISR_NUMBER
76543210
ISR_NUMBER
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12.4.1.11 Execution Program Status Register
Name: EPSR
Access: Read-write
Reset: 0x000000000
The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the Interruptible-
Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write
the EPSR using the MSR instruction in the application software are ignored. Fault handlers can examine the EPSR value in the
stacked PSR to indicate the operation that is at fault. See “Exception Entry and Return”
• ICI: Interruptible-continuable Instruction
When an interrupt occurs during the execution of an LDM, STM, PUSH, POP, VLDM, VSTM, VPUSH,
or VPOP instruction, the processor:
– Stops the load multiple or store multiple instruction operation temporarily
– Stores the next register operand in the multiple operation to EPSR bits[15:12].
After servicing the interrupt, the processor:
– Returns to the register pointed to by bits[15:12]
– Resumes the execution of the multiple load or store instruction.
When the EPSR holds the ICI execution state, bits[26:25,11:10] are zero.
• IT: If-Then Instruction
Indicates the execution state bits of the
IT
instruction.
The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The con-
ditions for the instructions are either all the same, or some can be the inverse of others. See “IT” for more information.
• T: Thumb State
The Cortex-M4 processor only supports the execution of instructions in Thumb state. The following can clear the T bit to 0:
– Instructions BLX, BX and POP{PC}
– Restoration from the stacked xPSR value on an exception return
– Bit[0] of the vector value on an exception entry or reset.
Attempting to execute instructions when the T bit is 0 results in a fault or lockup. See “Lockup” for more information.
31 30 29 28 27 26 25 24
– ICI/IT T
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
ICI/IT –
76543210
–
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12.4.1.12Exception Mask Registers
The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might
impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value
of PRIMASK or FAULTMASK. See “MRS” , “MSR” , and “CPS” for more information.
12.4.1.13Priority Mask Register
Name: PRIMASK
Access: Read-write
Reset: 0x000000000
The PRIMASK register prevents the activation of all exceptions with a configurable priority.
• PRIMASK
0: No effect
1: Prevents the activation of all exceptions with a configurable priority.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– PRIMASK
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12.4.1.14Fault Mask Register
Name: FAULTMASK
Access: Read-write
Reset: 0x000000000
The FAULTMASK register prevents the activation of all exceptions except for Non-Maskable Interrupt (NMI).
• FAULTMASK
0: No effect.
1: Prevents the activation of all exceptions except for NMI.
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except the NMI handler.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– FAULTMASK
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12.4.1.15Base Priority Mask Register
Name: BASEPRI
Access: Read-write
Reset: 0x000000000
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it pre-
vents the activation of all exceptions with same or lower priority level as the BASEPRI value.
• BASEPRI
Priority mask bits:
0x0000
= No effect.
Nonzero = Defines the base priority for exception processing.
The processor does not process any exception with a priority value greater than or equal to BASEPRI.
This field is similar to the priority fields in the interrupt priority registers. The processor implements only bits[7:4] of this field,
bits[3:0] read as zero and ignore writes. See “Interrupt Priority Registers” for more information. Remember that higher priority
field values correspond to lower exception priorities.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
BASEPRI
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12.4.1.16CONTROL Register
Name: CONTROL
Access: Read-write
Reset: 0x000000000
The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread
mode.
• SPSEL: Active Stack Pointer
Defines the current stack:
0: MSP is the current stack pointer.
1: PSP is the current stack pointer.
In Handler mode, this bit reads as zero and ignores writes. The Cortex-M4 updates this bit automatically on exception return.
• nPRIV: Thread Mode Privilege Level
Defines the Thread mode privilege level:
0: Privileged.
1: Unprivileged.
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack pointer bit of the CONTROL reg-
ister when in Handler mode. The exception entry and return mechanisms update the CONTROL register based on the
EXC_RETURN value.
In an OS environment, ARM recommends that threads running in Thread mode use the process stack, and the kernel and excep-
tion handlers use the main stack.
By default, the Thread mode uses the MSP. To switch the stack pointer used in Thread mode to the PSP, either:
• Use the MSR instruction to set the Active stack pointer bit to 1, see “MSR” ,or
• Perform an exception return to Thread mode with the appropriate EXC_RETURN value, see Table 12-10.
Note: When changing the stack pointer, the software must use an ISB instruction immediately after the MSR instruction.
This ensures that instructions after the ISB execute using the new stack pointer. See “ISB” .
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– – SPSEL nPRIV
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12.4.1.17Exceptions and Interrupts
The Cortex-M4 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt
Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The
processor uses the Handler mode to handle all exceptions except for reset. See “Exception Entry” and “Exception
Return” for more information.
The NVIC registers control interrupt handling. See “Nested Vectored Interrupt Controller (NVIC)” for more information.
12.4.1.18Data Types
The processor supports the following data types:
32-bit words
16-bit halfwords
8-bit bytes
The processor manages all data memory accesses as little-endian. Instruction memory and Private Peripheral Bus
(PPB) accesses are always little-endian. See “Memory Regions, Types and Attributes” for more information.
12.4.1.19 Cortex Microcontroller Software Interface Standard (CMSIS)
For a Cortex-M4 microcontroller system, the Cortex Microcontroller Software Interface Standard (CMSIS) defines:
A common way to:
Access peripheral registers
Define exception vectors
The names of:
The registers of the core peripherals
The core exception vectors
A device-independent interface for RTOS kernels, including a debug channel.
The CMSIS includes address definitions and data structures for the core peripherals in the Cortex-M4 processor.
The CMSIS simplifies the software development by enabling the reuse of template code and the combination of CMSIS-
compliant software components from various middleware vendors. Software vendors can expand the CMSIS to include
their peripheral definitions and access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short descriptions of the CMSIS functions
that address the processor core and the core peripherals.
Note: This document uses the register short names defined by the CMSIS. In a few cases, these differ from the archi-
tectural short names that might be used in other documents.
The following sections give more information about the CMSIS:
Section 12.5.3 ”Power Management Programming Hints”
Section 12.6.2 ”CMSIS Functions”
Section 12.8.2.1 ”NVIC Programming Hints” .
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12.4.2 Memory Model
This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The
processor has a fixed memory map that provides up to 4GB of addressable memory.
Figure 12-3. Memory Map
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to bit data, see
“Bit-banding” .
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral registers.
This memory mapping is generic to ARM Cortex-M4 products. To get the specific memory mapping of this product, refer
to the Memories section of the datasheet.
12.4.2.1Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region has a defined
memory type, and some regions have additional memory attributes. The memory type and attributes determine the
behavior of accesses to the region.
Vendor-specific
memory
External device
External RAM
Peripheral
SRAM
Code
0xFFFFFFFF
Private peripheral
bus
0xE0100000
0xE00FFFFF
0x9FFFFFFF
0xA0000000
0x5FFFFFFF
0x60000000
0x3FFFFFFF
0x40000000
0x1FFFFFFF
0x20000000
0x00000000
0x40000000
32 MB Bit band alias
0x400FFFFF
0x42000000
0x43FFFFFF
1 MB Bit Band region
32 MB Bit band alias
0x20000000
0x200FFFFF
0x22000000
0x23FFFFFF
1.0GB
1.0GB
0.5GB
0.5GB
0.5GB
0xDFFFFFFF
0xE0000000
1.0MB
511MB
1 MB Bit Band region
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Memory Types
Normal
The processor can re-order transactions for efficiency, or perform speculative reads.
Device
The processor preserves transaction order relative to other transactions to Device or Strongly-ordered memory.
Strongly-ordered
The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a
write to Device memory, but must not buffer a write to Strongly-ordered memory.
Additional Memory Attributes
Shareable
For a shareable memory region, the memory system provides data synchronization between bus masters in a
system with multiple bus masters, for example, a processor with a DMA controller.
Strongly-ordered memory is always shareable.
If multiple bus masters can access a non-shareable memory region, the software must ensure data coherency
between the bus masters.
Execute Never (XN)
Means the processor prevents instruction accesses. A fault exception is generated only on execution of an
instruction executed from an XN region.
12.4.2.2Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that
the order in which the accesses complete matches the program order of the instructions, providing this does not affect
the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses
completing in program order, the software must insert a memory barrier instruction between the memory access
instructions, see “Software Ordering of Memory Accesses” .
However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered memory. For
two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of the memory
accesses is described below.
Where:
– Means that the memory system does not guarantee the ordering of the accesses.
< Means that accesses are observed in program order, that is, A1 is always observed
before A2.
Table 12-3. Ordering of the Memory Accesses Caused by Two Instructions
A2 Normal
Access
Device Access Strongly-
ordered
Access
A1 Non-shareable Shareable
Normal Access – – – –
Device access, non-
shareable –<–<
Device access, shareable – – < <
Strongly-ordered access – < < <
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12.4.2.3Behavior of Memory Accesses
The behavior of accesses to each region in the memory map is:
Note: 1. See “Memory Regions, Types and Attributes” for more information.
The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends that programs always use
the Code region. This is because the processor has separate buses that enable instruction fetches and data accesses to
occur simultaneously.
The MPU can override the default memory access behavior described in this section. For more information, see “Memory
Protection Unit (MPU)” .
Additional Memory Access Constraints For Shared Memory
When a system includes shared memory, some memory regions have additional access constraints, and some regions
are subdivided, as Table 12-5 shows:
Table 12-4. Memory Access Behavior
Address Range Memory Region Memory
Type XN Description
0x00000000 - 0x1FFFFFFF Code Normal(1) -Executable region for program code. Data can also be
put here.
0x20000000 - 0x3FFFFFFF SRAM Normal (1) -Executable region for data. Code can also be put here.
This region includes bit band and bit band alias areas,
see Table 12-6.
0x40000000 - 0x5FFFFFFF Peripheral Device (1) XN This region includes bit band and bit band alias areas,
see Table 12-6.
0x60000000 - 0x9FFFFFFF External RAM Normal (1) - Executable region for data.
0xA0000000 - 0xDFFFFFFF External device Device (1) XN External Device memory
0xE0000000 - 0xE00FFFFF Private Peripheral Bus Strongly-
ordered (1) XN This region includes the NVIC, System timer, and
system control block.
0xE0100000 - 0xFFFFFFFF Reserved Device (1) XN Reserved
Table 12-5. Memory Region Shareability Policies
Address Range Memory Region Memory Type Shareability
0x00000000
-
0x1FFFFFFF
Code Normal (1) -(2)
0x20000000
-
0x3FFFFFFF
SRAM Normal (1) -(2)
0x40000000
-
0x5FFFFFFF
Peripheral Device
(1) -
0x60000000
-
0x7FFFFFFF
External RAM Normal (1) -WBWA (2)
0x80000000
-
0x9FFFFFFF
WT (2)
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Notes: 1. See “Memory Regions, Types and Attributes” for more information.
2. WT = Write through, no write allocate. WBWA = Write back, write allocate. See the “Glossary” for more
information.
Instruction Prefetch and Branch Prediction
The Cortex-M4 processor:
Prefetches instructions ahead of execution
Speculatively prefetches from branch target addresses.
12.4.2.4Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the corresponding memory
transactions. This is because:
The processor can reorder some memory accesses to improve efficiency, providing this does not affect the
behavior of the instruction sequence.
The processor has multiple bus interfaces
Memory or devices in the memory map have different wait states
Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” describes the cases where the memory system guarantees the order
of memory accesses. Otherwise, if the order of memory accesses is critical, the software must include memory barrier
instructions to force that ordering. The processor provides the following memory barrier instructions:
DMB
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent
memory transactions. See “DMB” .
DSB
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before
subsequent instructions execute. See “DSB” .
ISB
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is
recognizable by subsequent instructions. See “ISB” .
MPU Programming
Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by
subsequent instructions.
12.4.2.5Bit-banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions
occupy the lowest 1 MB of the SRAM and peripheral memory regions.
The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions:
0xA0000000
-
0xBFFFFFFF
External device Device (1) Shareable (1)
-
0xC0000000
-
0xDFFFFFFF
Non-shareable (1)
0xE0000000
-
0xE00FFFFF
Private Peripheral
Bus Strongly- ordered(1) Shareable (1) -
0xE0100000
-
0xFFFFFFFF
Vendor-specific
device Device (1) --
Table 12-5. Memory Region Shareability Policies (Continued)
Address Range Memory Region Memory Type Shareability
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Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band region, as shown in Table 12-6.
Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit-band region, as shown in Table 12-
7.
Notes: 1. A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or periph-
eral bit-band region.
2. Bit-band accesses can use byte, halfword, or word transfers. The bit-band transfer size matches the transfer
size of the instruction making the bit-band access.
The following formula shows how the alias region maps onto the bit-band region:
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_addr = bit_band_base + bit_word_offset
where:
Bit_word_offset
is the position of the target bit in the bit-band memory region.
Bit_word_addr
is the address of the word in the alias memory region that maps to the targeted bit.
Bit_band_base
is the starting address of the alias region.
Byte_offset
is the number of the byte in the bit-band region that contains the targeted bit.
Bit_number
is the bit position, 0-7, of the targeted bit.
Figure 12-4 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band
region:
The alias word at
0x23FFFFE0
maps to bit[0] of the bit-band byte at
0x200FFFFF
:
0x23FFFFE0
=
0x22000000
+
(
0xFFFFF
*32) + (0*4).
The alias word at
0x23FFFFFC
maps to bit[7] of the bit-band byte at
0x200FFFFF
:
0x23FFFFFC
=
0x22000000
+
(
0xFFFFF
*32) + (7*4).
The alias word at
0x22000000
maps to bit[0] of the bit-band byte at
0x20000000
:
0x22000000
=
0x22000000
+ (0*32) + (0
*4).
The alias word at
0x2200001C
maps to bit[7] of the bit-band byte at
0x20000000
:
0x2200001C
=
0x22000000
+ (0*32) +
(7*4).
Table 12-6. SRAM Memory Bit-banding Regions
Address
Range Memory
Region Instruction and Data Accesses
0x20000000-
0x200FFFFF SRAM bit-band
region
Direct accesses to this memory range behave as SRAM
memory accesses, but this region is also bit-addressable
through bit-band alias.
0x22000000-
0x23FFFFFF SRAM bit-band alias Data accesses to this region are remapped to bit-band
region. A write operation is performed as read-modify-
write. Instruction accesses are not remapped.
Table 12-7. Peripheral Memory Bit-banding Regions
Address
Range Memory
Region Instruction and Data Accesses
0x40000000-
0x400FFFFF Peripheral bit-band
alias
Direct accesses to this memory range behave as
peripheral memory accesses, but this region is also bit-
addressable through bit-band alias.
0x42000000-
0x43FFFFFF Peripheral bit-band
region
Data accesses to this region are remapped to bit-band
region. A write operation is performed as read-modify-
write. Instruction accesses are not permitted.
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Figure 12-4. Bit-band Mapping
Directly Accessing an Alias Region
Writing to a word in the alias region updates a single bit in the bit-band region.
Bit[0] of the value written to a word in the alias region determines the value written to the targeted bit in the bit-band
region. Writing a value with bit[0] set to 1 writes a 1 to the bit-band bit, and writing a value with bit[0] set to 0 writes a 0 to
the bit-band bit.
Bits[31:1] of the alias word have no effect on the bit-band bit. Writing
0x01
has the same effect as writing
0xFF
. Writing
0x00
has the same effect as writing
0x0E
.
Reading a word in the alias region:
0x00000000
indicates that the targeted bit in the bit-band region is set to 0
0x00000001
indicates that the targeted bit in the bit-band region is set to 1
Directly Accessing a Bit-band Region
“Behavior of Memory Accesses” describes the behavior of direct byte, halfword, or word accesses to the bit-band
regions.
12.4.2.6Memory Endianness
The processor views memory as a linear collection of bytes numbered in ascending order from zero. For example, bytes
0-3 hold the first stored word, and bytes 4-7 hold the second stored word. “Little-endian Format” describes how words of
data are stored in memory.
Little-endian Format
In little-endian format, the processor stores the least significant byte of a word at the lowest-numbered byte, and the most
significant byte at the highest-numbered byte. For example:
0x23FFFFE4
0x22000004
0x23FFFFE00x23FFFFE80x23FFFFEC0x23FFFFF00x23FFFFF40x23FFFFF80x23FFFFFC
0x220000000x220000140x220000180x2200001C 0x220000080x22000010 0x2200000C
32 MB alias region
0
7 0
07
0x200000000x200000010x200000020x20000003
6 5 4 3 2 1 07 6 5 4 3 2 1 7 6 5 4 3 2 1 07 6 5 4 3 2 1
07 6 5 4 3 2 1 6 5 4 3 2 107 6 5 4 3 2 1 07 6 5 4 3 2 1
0x200FFFFC0x200FFFFD0x200FFFFE0x200FFFFF
1 MB SRAM bit-band region
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Figure 12-5. Little-endian Format
12.4.2.7Synchronization Primitives
The Cortex-M4 instruction set includes pairs of synchronization primitives. These provide a non-blocking mechanism that
a thread or process can use to obtain exclusive access to a memory location. The software can use them to perform a
guaranteed read-modify-write memory update sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
A Load-exclusive Instruction, used to read the value of a memory location, requesting exclusive access to that location.
A Store-Exclusive instruction, used to attempt to write to the same memory location, returning a status bit to a register. If
this bit is:
0: It indicates that the thread or process gained exclusive access to the memory, and the write succeeds,
1: It indicates that the thread or process did not gain exclusive access to the memory, and no write is performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
The word instructions LDREX and STREX
The halfword instructions LDREXH and STREXH
The byte instructions LDREXB and STREXB.
The software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, the software must:
1. Use a Load-Exclusive instruction to read the value of the location.
2. Update the value, as required.
3. Use a Store-Exclusive instruction to attempt to write the new value back to the memory location
4. Test the returned status bit. If this bit is:
0: The read-modify-write completed successfully.
1: No write was performed. This indicates that the value returned at step 1 might be out of date. The software must
retry the read-modify-write sequence.
The software can use the synchronization primitives to implement a semaphore as follows:
1. Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free.
2. If the semaphore is free, use a Store-Exclusive instruction to write the claim value to the semaphore address.
3. If the returned status bit from step 2 indicates that the Store-Exclusive instruction succeeded then the software has
claimed the semaphore. However, if the Store-Exclusive instruction failed, another process might have claimed the
semaphore after the software performed the first step.
The Cortex-M4 includes an exclusive access monitor, that tags the fact that the processor has executed a Load-
Exclusive instruction. If the processor is part of a multiprocessor system, the system also globally tags the memory
locations addressed by exclusive accesses by each processor.
Memory Register
Address
A
A+1
lsbyte
msbyte
A+2
A+3
07
B0B1B3 B2
31 24 23 16 15 8 7 0
B0
B1
B2
B3
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The processor removes its exclusive access tag if:
It executes a CLREX instruction
It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
An exception occurs. This means that the processor can resolve semaphore conflicts between different threads.
In a multiprocessor implementation:
Executing a CLREX instruction removes only the local exclusive access tag for the processor
Executing a Store-Exclusive instruction, or an exception, removes the local exclusive access tags, and all global
exclusive access tags for the processor.
For more information about the synchronization primitive instructions, see “LDREX and STREX” and “CLREX” .
12.4.2.8Programming Hints for the Synchronization Primitives
ISO/IEC C cannot directly generate the exclusive access instructions. CMSIS provides intrinsic functions for generation
of these instructions:
The actual exclusive access instruction generated depends on the data type of the pointer passed to the intrinsic
function. For example, the following C code generates the required LDREXB operation:
__ldrex((volatile char *) 0xFF);
Table 12-8. CMSIS Functions for Exclusive Access Instructions
Instruction CMSIS Function
LDREX uint32_t __LDREXW (uint32_t *addr)
LDREXH uint16_t __LDREXH (uint16_t *addr)
LDREXB uint8_t __LDREXB (uint8_t *addr)
STREX uint32_t __STREXW (uint32_t value, uint32_t *addr)
STREXH uint32_t __STREXH (uint16_t value, uint16_t *addr)
STREXB uint32_t __STREXB (uint8_t value, uint8_t *addr)
CLREX void __CLREX (void)
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12.4.3 Exception Model
This section describes the exception model.
12.4.3.1Exception States
Each exception is in one of the following states:
Inactive
The exception is not active and not pending.
Pending
The exception is waiting to be serviced by the processor.
An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending.
Active
An exception is being serviced by the processor but has not completed.
An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the
active state.
Active and Pending
The exception is being serviced by the processor and there is a pending exception from the same source.
12.4.3.2Exception Types
The exception types are:
Reset
Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When
reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is
deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as
privileged execution in Thread mode.
Non Maskable Interrupt (NMI)
A non maskable interrupt (NMI) can be signalled by a peripheral or triggered by software. This is the highest priority
exception other than reset. It is permanently enabled and has a fixed priority of -2.
NMIs cannot be:
Masked or prevented from activation by any other exception.
Preempted by any exception other than Reset.
Hard Fault
A hard fault is an exception that occurs because of an error during exception processing, or because an exception
cannot be managed by any other exception mechanism. Hard Faults have a fixed priority of -1, meaning they have higher
priority than any exception with configurable priority.
Memory Management Fault (MemManage)
A Memory Management Fault is an exception that occurs because of a memory protection related fault. The MPU or the
fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault is
used to abort instruction accesses to Execute Never (XN) memory regions, even if the MPU is disabled.
Bus Fault
A Bus Fault is an exception that occurs because of a memory related fault for an instruction or data memory transaction.
This might be from an error detected on a bus in the memory system.
Usage Fault
A Usage Fault is an exception that occurs because of a fault related to an instruction execution. This includes:
An undefined instruction
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An illegal unaligned access
An invalid state on instruction execution
An error on exception return.
The following can cause a Usage Fault when the core is configured to report them:
An unaligned address on word and halfword memory access
A division by zero.
SVCall
A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can
use SVC instructions to access OS kernel functions and device drivers.
PendSV
PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching
when no other exception is active.
SysTick
A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate a
SysTick exception. In an OS environment, the processor can use this exception as system tick.
Interrupt (IRQ)
A interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are
asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor.
Notes: 1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions
other than interrupts. The IPSR returns the Exception number, see “Interrupt Program Status Register” .
2. See “Vector Table” for more information
3. See “System Handler Priority Registers”
4. See “Interrupt Priority Registers”
5. Increasing in steps of 4.
Table 12-9. Properties of the Different Exception Types
Exception
Number (1) Irq Number (1) Exception Type Priority Vector Address
or Offset (2) Activation
1 - Reset -3, the highest 0x00000004 Asynchronous
2 -14 NMI -2 0x00000008 Asynchronous
3 -13 Hard fault -1 0x0000000C -
4 -12 Memory
management fault Configurable (3) 0x00000010 Synchronous
5 -11 Bus fault Configurable (3) 0x00000014 Synchronous when
precise, asynchronous
when imprecise
6 -10 Usage fault Configurable (3) 0x00000018 Synchronous
7-10 - - - Reserved -
11 -5 SVCall Configurable (3) 0x0000002C Synchronous
12-13 - - - Reserved -
14 -2 PendSV Configurable (3) 0x00000038 Asynchronous
15 -1 SysTick Configurable (3) 0x0000003C Asynchronous
16 and above 0 and above Interrupt (IRQ) Configurable(4) 0x00000040 and
above (5) Asynchronous
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For an asynchronous exception, other than reset, the processor can execute another instruction between when the
exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 12-9 shows as having configurable priority, see:
“System Handler Control and State Register”
“Interrupt Clear-enable Registers” .
For more information about hard faults, memory management faults, bus faults, and usage faults, see “Fault Handling” .
12.4.3.3Exception Handlers
The processor handles exceptions using:
Interrupt Service Routines (ISRs)
Interrupts IRQ0 to IRQ34 are the exceptions handled by ISRs.
Fault Handlers
Hard fault, memory management fault, usage fault, bus fault are fault exceptions handled by the fault handlers.
System Handlers
NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions that are handled by system
handlers.
12.4.3.4Vector Table
The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for
all exception handlers. Figure 12-6 shows the order of the exception vectors in the vector table. The least-significant bit
of each vector must be 1, indicating that the exception handler is Thumb code.
Figure 12-6. Vector Table
Initial SP value
Reset
Hard fault
NMI
Memory management fault
Usage fault
Bus fault
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
Reserved
SVCall
PendSV
Reserved for Debug
SysTick
IRQ0
Reserved
0x002C
0x0038
0x003C
0x0040
OffsetException number
2
3
4
5
6
11
12
14
15
16
18
13
7
10
1
Vector
.
.
.
8
9
IRQ1
IRQ2
0x0044
IRQ239
17 0x0048
0x004C
255
.
.
.
.
.
.
0x03FC
IRQ number
-14
-13
-12
-11
-10
-5
-2
-1
0
2
1
239
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On system reset, the vector table is fixed at address
0x00000000
. Privileged software can write to the SCB_VTOR register
to relocate the vector table start address to a different memory location, in the range
0x00000080
to
0x3FFFFF80
, see
“Vector Table Offset Register” .
12.4.3.5Exception Priorities
As Table 12-9 shows, all exceptions have an associated priority, with:
A lower priority value indicating a higher priority
Configurable priorities for all exceptions except Reset, Hard fault and NMI.
If the software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0. For
information about configuring exception priorities see “System Handler Priority Registers” , and “Interrupt Priority
Registers” .
Note: Configurable priority values are in the range 0-15. This means that the Reset, Hard fault, and NMI exceptions,
with fixed negative priority values, always have higher priority than any other exception.
For example, assigning a higher priority value to IRQ[0] and a lower priority value to IRQ[1] means that IRQ[1] has higher
priority than IRQ[0]. If both IRQ[1] and IRQ[0] are asserted, IRQ[1] is processed before IRQ[0].
If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes
precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed
before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception
occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted,
irrespective of the exception number. However, the status of the new interrupt changes to pending.
12.4.3.6Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This divides each interrupt
priority register entry into two fields:
An upper field that defines the group priority
A lower field that defines a subpriority within the group.
Only the group priority determines preemption of interrupt exceptions. When the processor is executing an interrupt
exception handler, another interrupt with the same group priority as the interrupt being handled does not preempt the
handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order in which they are
processed. If multiple pending interrupts have the same group priority and subpriority, the interrupt with the lowest IRQ
number is processed first.
For information about splitting the interrupt priority fields into group priority and subpriority, see “Application Interrupt and
Reset Control Register” .
12.4.3.7Exception Entry and Return
Descriptions of exception handling use the following terms:
Preemption
When the processor is executing an exception handler, an exception can preempt the exception handler if its priority is
higher than the priority of the exception being handled. See “Interrupt Priority Grouping” for more information about
preemption by an interrupt.
When one exception preempts another, the exceptions are called nested exceptions. See “Exception Entry” more
information.
Return
This occurs when the exception handler is completed, and:
There is no pending exception with sufficient priority to be serviced
The completed exception handler was not handling a late-arriving exception.
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The processor pops the stack and restores the processor state to the state it had before the interrupt occurred. See
“Exception Return” for more information.
Tail-chaining
This mechanism speeds up exception servicing. On completion of an exception handler, if there is a pending exception
that meets the requirements for exception entry, the stack pop is skipped and control transfers to the new exception
handler.
Late-arriving
This mechanism speeds up preemption. If a higher priority exception occurs during state saving for a previous exception,
the processor switches to handle the higher priority exception and initiates the vector fetch for that exception. State
saving is not affected by late arrival because the state saved is the same for both exceptions. Therefore the state saving
continues uninterrupted. The processor can accept a late arriving exception until the first instruction of the exception
handler of the original exception enters the execute stage of the processor. On return from the exception handler of the
late-arriving exception, the normal tail-chaining rules apply.
Exception Entry
An Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread
mode, or the new exception is of a higher priority than the exception being handled, in which case the new exception
preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means that the exception has more priority than any limits set by the mask registers, see “Exception
Mask Registers” . An exception with less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor
pushes information onto the current stack. This operation is referred as stacking and the structure of eight data words is
referred to as stack frame.
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Figure 12-7. Exception Stack Frame
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame. The alignment of the stack
frame is controlled via the STKALIGN bit of the Configuration Control Register (CCR).
The stack frame includes the return address. This is the address of the next instruction in the interrupted program. This
value is restored to the PC at exception return so that the interrupted program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the exception handler start address
from the vector table. When stacking is complete, the processor starts executing the exception handler. At the same
time, the processor writes an EXC_RETURN value to the LR. This indicates which stack pointer corresponds to the stack
frame and what operation mode the processor was in before the entry occurred.
If no higher priority exception occurs during the exception entry, the processor starts executing the exception handler and
automatically changes the status of the corresponding pending interrupt to active.
If another higher priority exception occurs during the exception entry, the processor starts executing the exception
handler for this exception and does not change the pending status of the earlier exception. This is the late arrival case.
Exception Return
An Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load
the EXC_RETURN value into the PC:
An LDM or POP instruction that loads the PC
An LDR instruction with the PC as the destination.
A BX instruction using any register.
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to
detect when the processor has completed an exception handler. The lowest five bits of this value provide information on
Pre-IRQ top of stack
xPSR
PC
LR
R12
R3
R2
R1
R0
{aligner}
IRQ top of stack
Decreasing
memory
address
xPSR
PC
LR
R12
R3
R2
R1
R0
S7
S6
S5
S4
S3
S2
S1
S0
S9
S8
FPSCR
S15
S14
S13
S12
S11
S10
{aligner}
IRQ top of stack
...
Exception frame with
floating-point storage Exception frame without
floating-point storage
Pre-IRQ top of stack
...
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the return stack and processor mode. Table 12-10 shows the EXC_RETURN values with a description of the exception
return behavior.
All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
12.4.3.8Fault Handling
Faults are a subset of the exceptions, see “Exception Model” . The following generate a fault:
A bus error on:
An instruction fetch or vector table load
A data access
An internally-detected error such as an undefined instruction
An attempt to execute an instruction from a memory region marked as Non-Executable (XN).
A privilege violation or an attempt to access an unmanaged region causing an MPU fault.
Fault Types
Table 12-11 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the
register bit that indicates that the fault has occurred. See “Configurable Fault Status Register” for more information about
the fault status registers.
Table 12-10. Exception Return Behavior
EXC_RETURN[31:0] Description
0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state
from the MSP and execution uses MSP after return.
0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from
MSP and execution uses MSP after return.
0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from
the PSP and execution uses PSP after return.
Table 12-11. Faults
Fault Handler Bit Name Fault Status Register
Bus error on a vector read Hard fault VECTTBL “Hard Fault Status Register”
Fault escalated to a hard fault FORCED
MPU or default memory map mismatch:
Memory
management
fault
--
on instruction access IACCVIOL
“MMFSR: Memory Management Fault
Status Subregister”
on data access DACCVIOL(2)
during exception stacking MSTKERR
during exception unstacking MUNSKERR
during lazy floating-point state preservation MLSPERR
Bus error:
Bus fault
--
during exception stacking STKERR
“BFSR: Bus Fault Status Subregister”
during exception unstacking UNSTKERR
during instruction prefetch IBUSERR
during lazy floating-point state preservation LSPERR
Precise data bus error PRECISERR
Imprecise data bus error IMPRECISERR
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Notes: 1. Occurs on an access to an XN region even if the processor does not include an MPU or the MPU is disabled.
2. Attempt to use an instruction set other than the Thumb instruction set, or return to a non load/store-multiple instruction
with ICI continuation.
Fault Escalation and Hard Faults
All faults exceptions except for hard fault have configurable exception priority, see “System Handler Priority Registers” .
The software can disable the execution of the handlers for these faults, see “System Handler Control and State Register”
.Usually, the exception priority, together with the values of the exception mask registers, determines whether the
processor enters the fault handler, and whether a fault handler can preempt another fault handler, as described in
“Exception Model” .
In some situations, a fault with configurable priority is treated as a hard fault. This is called priority escalation, and the
fault is described as escalated to hard fault. Escalation to hard fault occurs when:
A fault handler causes the same kind of fault as the one it is servicing. This escalation to hard fault occurs because
a fault handler cannot preempt itself; it must have the same priority as the current priority level.
A fault handler causes a fault with the same or lower priority as the fault it is servicing. This is because the handler
for the new fault cannot preempt the currently executing fault handler.
An exception handler causes a fault for which the priority is the same as or lower than the currently executing
exception.
A fault occurs and the handler for that fault is not enabled.
If a bus fault occurs during a stack push when entering a bus fault handler, the bus fault does not escalate to a hard fault.
This means that if a corrupted stack causes a fault, the fault handler executes even though the stack push for the handler
failed. The fault handler operates but the stack contents are corrupted.
Note: Only Reset and NMI can preempt the fixed priority hard fault. A hard fault can preempt any exception other than
Reset, NMI, or another hard fault.
Fault Status Registers and Fault Address Registers
The fault status registers indicate the cause of a fault. For bus faults and memory management faults, the fault address
register indicates the address accessed by the operation that caused the fault, as shown in Table 12-12.
Attempt to access a coprocessor
Usage fault
NOCP
“UFSR: Usage Fault Status Subregister”
Undefined instruction UNDEFINSTR
Attempt to enter an invalid instruction set state (1) INVSTATE
Invalid EXC_RETURN value INVPC
Illegal unaligned load or store UNALIGNED
Divide By 0 DIVBYZERO
Table 12-11. Faults (Continued)
Fault Handler Bit Name Fault Status Register
Table 12-12. Fault Status and Fault Address Registers
Handler Status Register
Name Address
Register Name Register Description
Hard fault SCB_HFSR - “Hard Fault Status Register”
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Lockup
The processor enters a lockup state if a hard fault occurs when executing the NMI or hard fault handlers. When the
processor is in lockup state, it does not execute any instructions. The processor remains in lockup state until either:
It is reset
An NMI occurs
It is halted by a debugger.
Note: If the lockup state occurs from the NMI handler, a subsequent NMI does not cause the processor to leave the
lockup state.
Memory
management fault MMFSR SCB_MMFAR “MMFSR: Memory Management Fault
Status Subregister”
“MemManage Fault Address Register”
Bus fault BFSR SCB_BFAR “BFSR: Bus Fault Status Subregister”
“Bus Fault Address Register”
Usage fault UFSR - “UFSR: Usage Fault Status
Subregister”
Table 12-12. Fault Status and Fault Address Registers (Continued)
Handler Status Register
Name Address
Register Name Register Description
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12.5 Power Management
The Cortex-M4 processor sleep modes reduce the power consumption:
Sleep mode stops the processor clock
Deep sleep mode stops the system clock and switches off the PLL and flash memory.
The SLEEPDEEP bit of the SCR selects which sleep mode is used; see “System Control Register” .
This section describes the mechanisms for entering sleep mode, and the conditions for waking up from sleep mode.
12.5.1 Entering Sleep Mode
This section describes the mechanisms software can use to put the processor into sleep mode.
The system can generate spurious wakeup events, for example a debug operation wakes up the processor. Therefore,
the software must be able to put the processor back into sleep mode after such an event. A program might have an idle
loop to put the processor back to sleep mode.
12.5.1.1Wait for Interrupt
The wait for interrupt instruction, WFI, causes immediate entry to sleep mode. When the processor executes a WFI
instruction it stops executing instructions and enters sleep mode. See “WFI” for more information.
12.5.1.2Sleep-on-exit
If the SLEEPONEXIT bit of the SCR is set to 1 when the processor completes the execution of an exception handler, it
returns to Thread mode and immediately enters sleep mode. Use this mechanism in applications that only require the
processor to run when an exception occurs.
12.5.2 Wakeup from Sleep Mode
The conditions for the processor to wake up depend on the mechanism that cause it to enter sleep mode.
12.5.2.1Wakeup from WFI or Sleep-on-exit
Normally, the processor wakes up only when it detects an exception with sufficient priority to cause exception entry.
Some embedded systems might have to execute system restore tasks after the processor wakes up, and before it
executes an interrupt handler. To achieve this, set the PRIMASK bit to 1 and the FAULTMASK bit to 0. If an interrupt
arrives that is enabled and has a higher priority than the current exception priority, the processor wakes up but does not
execute the interrupt handler until the processor sets PRIMASK to zero. For more information about PRIMASK and
FAULTMASK, see “Exception Mask Registers” .
12.5.3 Power Management Programming Hints
ISO/IEC C cannot directly generate the WFI and WFE instructions. The CMSIS provides the following functions for these
instructions:
void __WFI(void) // Wait for Interrupt
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12.6 Cortex-M4 Instruction Set
12.6.1 Instruction Set Summary
The processor implements a version of the Thumb instruction set. Table 12-13 lists the supported instructions.
Angle brackets, <>, enclose alternative forms of the operand
Braces, {}, enclose optional operands
The Operands column is not exhaustive
Op2 is a flexible second operand that can be either a register or a constant
Most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Table 12-13. Cortex-M4 Instructions
Mnemonic Operands Description Flags
ADC, ADCS {Rd,} Rn, Op2 Add with Carry N,Z,C,V
ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V
ADD, ADDW {Rd,} Rn, #imm12 Add N,Z,C,V
ADR Rd, label Load PC-relative address -
AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C
ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right N,Z,C
B label Branch -
BFC Rd, #lsb, #width Bit Field Clear -
BFI Rd, Rn, #lsb, #width Bit Field Insert -
BIC, BICS {Rd,} Rn, Op2 Bit Clear N,Z,C
BKPT #imm Breakpoint -
BL label Branch with Link -
BLX Rm Branch indirect with Link -
BX Rm Branch indirect -
CBNZ Rn, label Compare and Branch if Non Zero -
CBZ Rn, label Compare and Branch if Zero -
CLREX - Clear Exclusive -
CLZ Rd, Rm Count leading zeros -
CMN Rn, Op2 Compare Negative N,Z,C,V
CMP Rn, Op2 Compare N,Z,C,V
CPSID i Change Processor State, Disable Interrupts -
CPSIE i Change Processor State, Enable Interrupts -
DMB - Data Memory Barrier -
DSB - Data Synchronization Barrier -
EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C
ISB - Instruction Synchronization Barrier -
IT - If-Then condition block -
LDM Rn{!}, reglist Load Multiple registers, increment after -
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LDMDB, LDMEA Rn{!}, reglist Load Multiple registers, decrement before -
LDMFD, LDMIA Rn{!}, reglist Load Multiple registers, increment after -
LDR Rt, [Rn, #offset] Load Register with word -
LDRB, LDRBT Rt, [Rn, #offset] Load Register with byte -
LDRD Rt, Rt2, [Rn, #offset] Load Register with two bytes -
LDREX Rt, [Rn, #offset] Load Register Exclusive -
LDREXB Rt, [Rn] Load Register Exclusive with byte -
LDREXH Rt, [Rn] Load Register Exclusive with halfword -
LDRH, LDRHT Rt, [Rn, #offset] Load Register with halfword -
LDRSB, DRSBT Rt, [Rn, #offset] Load Register with signed byte -
LDRSH, LDRSHT Rt, [Rn, #offset] Load Register with signed halfword -
LDRT Rt, [Rn, #offset] Load Register with word -
LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left N,Z,C
LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right N,Z,C
MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result -
MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result -
MOV, MOVS Rd, Op2 Move N,Z,C
MOVT Rd, #imm16 Move Top -
MOVW, MOV Rd, #imm16 Move 16-bit constant N,Z,C
MRS Rd, spec_reg Move from special register to general register -
MSR spec_reg, Rm Move from general register to special register N,Z,C,V
MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z
MVN, MVNS Rd, Op2 Move NOT N,Z,C
NOP - No Operation -
ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N,Z,C
ORR, ORRS {Rd,} Rn, Op2 Logical OR N,Z,C
PKHTB, PKHBT {Rd,} Rn, Rm, Op2 Pack Halfword -
POP reglist Pop registers from stack -
PUSH reglist Push registers onto stack -
QADD {Rd,} Rn, Rm Saturating double and Add Q
QADD16 {Rd,} Rn, Rm Saturating Add 16 -
QADD8 {Rd,} Rn, Rm Saturating Add 8 -
QASX {Rd,} Rn, Rm Saturating Add and Subtract with Exchange -
QDADD {Rd,} Rn, Rm Saturating Add Q
QDSUB {Rd,} Rn, Rm Saturating double and Subtract Q
QSAX {Rd,} Rn, Rm Saturating Subtract and Add with Exchange -
QSUB {Rd,} Rn, Rm Saturating Subtract Q
Table 12-13. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
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QSUB16 {Rd,} Rn, Rm Saturating Subtract 16 -
QSUB8 {Rd,} Rn, Rm Saturating Subtract 8 -
RBIT Rd, Rn Reverse Bits -
REV Rd, Rn Reverse byte order in a word -
REV16 Rd, Rn Reverse byte order in each halfword -
REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend -
ROR, RORS Rd, Rm, <Rs|#n> Rotate Right N,Z,C
RRX, RRXS Rd, Rm Rotate Right with Extend N,Z,C
RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract N,Z,C,V
SADD16 {Rd,} Rn, Rm Signed Add 16 GE
SADD8 {Rd,} Rn, Rm Signed Add 8 and Subtract with Exchange GE
SASX {Rd,} Rn, Rm Signed Add GE
SBC, SBCS {Rd,} Rn, Op2 Subtract with Carry N,Z,C,V
SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract -
SDIV {Rd,} Rn, Rm Signed Divide -
SEL {Rd,} Rn, Rm Select bytes -
SEV - Send Event -
SHADD16 {Rd,} Rn, Rm Signed Halving Add 16 -
SHADD8 {Rd,} Rn, Rm Signed Halving Add 8 -
SHASX {Rd,} Rn, Rm Signed Halving Add and Subtract with Exchange -
SHSAX {Rd,} Rn, Rm Signed Halving Subtract and Add with Exchange -
SHSUB16 {Rd,} Rn, Rm Signed Halving Subtract 16 -
SHSUB8 {Rd,} Rn, Rm Signed Halving Subtract 8 -
SMLABB, SMLABT,
SMLATB, SMLATT Rd, Rn, Rm, Ra Signed Multiply Accumulate Long (halfwords) Q
SMLAD, SMLADX Rd, Rn, Rm, Ra Signed Multiply Accumulate Dual Q
SMLAL RdLo, RdHi, Rn, Rm Signed Multiply with Accumulate (32 x 32 + 64), 64-bit result -
SMLALBB, SMLALBT,
SMLALTB, SMLALTT RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long, halfwords -
SMLALD, SMLALDX RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long Dual -
SMLAWB, SMLAWT Rd, Rn, Rm, Ra Signed Multiply Accumulate, word by halfword Q
SMLSD Rd, Rn, Rm, Ra Signed Multiply Subtract Dual Q
SMLSLD RdLo, RdHi, Rn, Rm Signed Multiply Subtract Long Dual
SMMLA Rd, Rn, Rm, Ra Signed Most significant word Multiply Accumulate -
SMMLS, SMMLR Rd, Rn, Rm, Ra Signed Most significant word Multiply Subtract -
SMMUL, SMMULR {Rd,} Rn, Rm Signed Most significant word Multiply -
SMUAD {Rd,} Rn, Rm Signed dual Multiply Add Q
Table 12-13. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
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SMULBB, SMULBT
SMULTB, SMULTT {Rd,} Rn, Rm Signed Multiply (halfwords) -
SMULL RdLo, RdHi, Rn, Rm Signed Multiply (32 x 32), 64-bit result -
SMULWB, SMULWT {Rd,} Rn, Rm Signed Multiply word by halfword -
SMUSD, SMUSDX {Rd,} Rn, Rm Signed dual Multiply Subtract -
SSAT Rd, #n, Rm {,shift #s} Signed Saturate Q
SSAT16 Rd, #n, Rm Signed Saturate 16 Q
SSAX {Rd,} Rn, Rm Signed Subtract and Add with Exchange GE
SSUB16 {Rd,} Rn, Rm Signed Subtract 16 -
SSUB8 {Rd,} Rn, Rm Signed Subtract 8 -
STM Rn{!}, reglist Store Multiple registers, increment after -
STMDB, STMEA Rn{!}, reglist Store Multiple registers, decrement before -
STMFD, STMIA Rn{!}, reglist Store Multiple registers, increment after -
STR Rt, [Rn, #offset] Store Register word -
STRB, STRBT Rt, [Rn, #offset] Store Register byte -
STRD Rt, Rt2, [Rn, #offset] Store Register two words -
STREX Rd, Rt, [Rn, #offset] Store Register Exclusive -
STREXB Rd, Rt, [Rn] Store Register Exclusive byte -
STREXH Rd, Rt, [Rn] Store Register Exclusive halfword -
STRH, STRHT Rt, [Rn, #offset] Store Register halfword -
STRT Rt, [Rn, #offset] Store Register word -
SUB, SUBS {Rd,} Rn, Op2 Subtract N,Z,C,V
SUB, SUBW {Rd,} Rn, #imm12 Subtract N,Z,C,V
SVC #imm Supervisor Call -
SXTAB {Rd,} Rn, Rm,{,ROR #} Extend 8 bits to 32 and add -
SXTAB16 {Rd,} Rn, Rm,{,ROR #} Dual extend 8 bits to 16 and add -
SXTAH {Rd,} Rn, Rm,{,ROR #} Extend 16 bits to 32 and add -
SXTB16 {Rd,} Rm {,ROR #n} Signed Extend Byte 16 -
SXTB {Rd,} Rm {,ROR #n} Sign extend a byte -
SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword -
TBB [Rn, Rm] Table Branch Byte -
TBH [Rn, Rm, LSL #1] Table Branch Halfword -
TEQ Rn, Op2 Test Equivalence N,Z,C
TST Rn, Op2 Test N,Z,C
UADD16 {Rd,} Rn, Rm Unsigned Add 16 GE
UADD8 {Rd,} Rn, Rm Unsigned Add 8 GE
USAX {Rd,} Rn, Rm Unsigned Subtract and Add with Exchange GE
Table 12-13. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
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UHADD16 {Rd,} Rn, Rm Unsigned Halving Add 16 -
UHADD8 {Rd,} Rn, Rm Unsigned Halving Add 8 -
UHASX {Rd,} Rn, Rm Unsigned Halving Add and Subtract with Exchange -
UHSAX {Rd,} Rn, Rm Unsigned Halving Subtract and Add with Exchange -
UHSUB16 {Rd,} Rn, Rm Unsigned Halving Subtract 16 -
UHSUB8 {Rd,} Rn, Rm Unsigned Halving Subtract 8 -
UBFX Rd, Rn, #lsb, #width Unsigned Bit Field Extract -
UDIV {Rd,} Rn, Rm Unsigned Divide -
UMAAL RdLo, RdHi, Rn, Rm Unsigned Multiply Accumulate Accumulate Long (32 x 32 + 32 +32),
64-bit result -
UMLAL RdLo, RdHi, Rn, Rm Unsigned Multiply with Accumulate
(32 x 32 + 64), 64-bit result -
UMULL RdLo, RdHi, Rn, Rm Unsigned Multiply (32 x 32), 64-bit result -
UQADD16 {Rd,} Rn, Rm Unsigned Saturating Add 16 -
UQADD8 {Rd,} Rn, Rm Unsigned Saturating Add 8 -
UQASX {Rd,} Rn, Rm Unsigned Saturating Add and Subtract with Exchange -
UQSAX {Rd,} Rn, Rm Unsigned Saturating Subtract and Add with Exchange -
UQSUB16 {Rd,} Rn, Rm Unsigned Saturating Subtract 16 -
UQSUB8 {Rd,} Rn, Rm Unsigned Saturating Subtract 8 -
USAD8 {Rd,} Rn, Rm Unsigned Sum of Absolute Differences -
USADA8 {Rd,} Rn, Rm, Ra Unsigned Sum of Absolute Differences and Accumulate -
USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q
USAT16 Rd, #n, Rm Unsigned Saturate 16 Q
UASX {Rd,} Rn, Rm Unsigned Add and Subtract with Exchange GE
USUB16 {Rd,} Rn, Rm Unsigned Subtract 16 GE
USUB8 {Rd,} Rn, Rm Unsigned Subtract 8 GE
UXTAB {Rd,} Rn, Rm,{,ROR #} Rotate, extend 8 bits to 32 and Add -
UXTAB16 {Rd,} Rn, Rm,{,ROR #} Rotate, dual extend 8 bits to 16 and Add -
UXTAH {Rd,} Rn, Rm,{,ROR #} Rotate, unsigned extend and Add Halfword -
UXTB {Rd,} Rm {,ROR #n} Zero extend a byte -
UXTB16 {Rd,} Rm {,ROR #n} Unsigned Extend Byte 16 -
UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword -
VABS.F32 Sd, Sm Floating-point Absolute -
VADD.F32 {Sd,} Sn, Sm Floating-point Add -
VCMP.F32 Sd, <Sm | #0.0> Compare two floating-point registers, or one floating-point register
and zero FPSCR
VCMPE.F32 Sd, <Sm | #0.0> Compare two floating-point registers, or one floating-point register
and zero with Invalid Operation check FPSCR
Table 12-13. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
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VCVT.S32.F32 Sd, Sm Convert between floating-point and integer -
VCVT.S16.F32 Sd, Sd, #fbits Convert between floating-point and fixed point -
VCVTR.S32.F32 Sd, Sm Convert between floating-point and integer with rounding -
VCVT<B|H>.F32.F16 Sd, Sm Converts half-precision value to single-precision -
VCVTT<B|T>.F32.F16 Sd, Sm Converts single-precision register to half-precision -
VDIV.F32 {Sd,} Sn, Sm Floating-point Divide -
VFMA.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Accumulate -
VFNMA.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Accumulate -
VFMS.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Subtract -
VFNMS.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Subtract -
VLDM.F<32|64> Rn{!}, list Load Multiple extension registers -
VLDR.F<32|64> <Dd|Sd>, [Rn] Load an extension register from memory -
VLMA.F32 {Sd,} Sn, Sm Floating-point Multiply Accumulate -
VLMS.F32 {Sd,} Sn, Sm Floating-point Multiply Subtract -
VMOV.F32 Sd, #imm Floating-point Move immediate -
VMOV Sd, Sm Floating-point Move register -
VMOV Sn, Rt Copy ARM core register to single precision -
VMOV Sm, Sm1, Rt, Rt2 Copy 2 ARM core registers to 2 single precision -
VMOV Dd[x], Rt Copy ARM core register to scalar -
VMOV Rt, Dn[x] Copy scalar to ARM core register -
VMRS Rt, FPSCR Move FPSCR to ARM core register or APSR N,Z,C,V
VMSR FPSCR, Rt Move to FPSCR from ARM Core register FPSCR
VMUL.F32 {Sd,} Sn, Sm Floating-point Multiply -
VNEG.F32 Sd, Sm Floating-point Negate -
VNMLA.F32 Sd, Sn, Sm Floating-point Multiply and Add -
VNMLS.F32 Sd, Sn, Sm Floating-point Multiply and Subtract -
VNMUL {Sd,} Sn, Sm Floating-point Multiply -
VPOP list Pop extension registers -
VPUSH list Push extension registers -
VSQRT.F32 Sd, Sm Calculates floating-point Square Root -
VSTM Rn{!}, list Floating-point register Store Multiple -
VSTR.F<32|64> Sd, [Rn] Stores an extension register to memory -
VSUB.F<32|64> {Sd,} Sn, Sm Floating-point Subtract -
WFI - Wait For Interrupt -
Table 12-13. Cortex-M4 Instructions (Continued)
Mnemonic Operands Description Flags
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12.6.2 CMSIS Functions
ISO/IEC cannot directly access some Cortex-M4 instructions. This section describes intrinsic functions that can generate
these instructions, provided by the CMIS and that might be provided by a C compiler. If a C compiler does not support an
appropriate intrinsic function, the user might have to use inline assembler to access some instructions.
The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C code cannot directly access:
The CMSIS also provides a number of functions for accessing the special registers using MRS and MSR instructions:
Table 12-14. CMSIS Functions to Generate some Cortex-M4 Instructions
Instruction CMSIS Function
CPSIE I void __enable_irq(void)
CPSID I void __disable_irq(void)
CPSIE F void __enable_fault_irq(void)
CPSID F void __disable_fault_irq(void)
ISB void __ISB(void)
DSB void __DSB(void)
DMB void __DMB(void)
REV uint32_t __REV(uint32_t int value)
REV16 uint32_t __REV16(uint32_t int value)
REVSH uint32_t __REVSH(uint32_t int value)
RBIT uint32_t __RBIT(uint32_t int value)
SEV void __SEV(void)
WFI void __WFI(void)
Table 12-15. CMSIS Intrinsic Functions to Access the Special Registers
Special Register Access CMSIS Function
PRIMASK Read uint32_t __get_PRIMASK (void)
Write void __set_PRIMASK (uint32_t value)
FAULTMASK Read uint32_t __get_FAULTMASK (void)
Write void __set_FAULTMASK (uint32_t value)
BASEPRI Read uint32_t __get_BASEPRI (void)
Write void __set_BASEPRI (uint32_t value)
CONTROL Read uint32_t __get_CONTROL (void)
Write void __set_CONTROL (uint32_t value)
MSP Read uint32_t __get_MSP (void)
Write void __set_MSP (uint32_t TopOfMainStack)
PSP Read uint32_t __get_PSP (void)
Write void __set_PSP (uint32_t TopOfProcStack)
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12.6.3 Instruction Descriptions
12.6.3.1Operands
An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on
the operands and often store the result in a destination register. When there is a destination register in the instruction, it
is usually specified before the operands.
Operands in some instructions are flexible, can either be a register or a constant. See “Flexible Second Operand” .
12.6.3.2Restrictions when Using PC or SP
Many instructions have restrictions on whether the Program Counter (PC) or Stack Pointer (SP) for the operands or
destination register can be used. See instruction descriptions for more information.
Note: Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must be 1 for correct exe-
cution, because this bit indicates the required instruction set, and the Cortex-M4 processor only supports Thumb
instructions.
12.6.3.3Flexible Second Operand
Many general data processing instructions have a flexible second operand. This is shown as Operand2 in the
descriptions of the syntax of each instruction.
Operand2 can be a:
“Constant”
“Register with Optional Shift”
Constant
Specify an Operand2 constant in the form:
#constant
where constant can be:
Any constant that can be produced by shifting an 8-bit value left by any number of bits within a 32-bit word
Any constant of the form 0x00XY00XY
Any constant of the form 0xXY00XY00
Any constant of the form 0xXYXYXYXY.
Note: In the constants shown above, X and Y are hexadecimal digits.
In addition, in a small number of instructions, constant can take a wider range of values. These are described in the
individual instruction descriptions.
When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or
TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by
shifting an 8-bit value. These instructions do not affect the carry flag if Operand2 is any other constant.
Instruction Substitution
The assembler might be able to produce an equivalent instruction in cases where the user specifies a constant that is not
permitted. For example, an assembler might assemble the instruction CMP
Rd
, #0xFFFFFFFE as the equivalent
instruction CMN Rd, #0x2.
Register with Optional Shift
Specify an Operand2 register in the form:
Rm {, shift}
where:
Rm is the register holding the data for the second operand.
shift is an optional shift to be applied to Rm. It can be one of:
ASR #narithmetic shift right n bits, 1 ≤ n ≤ 32.
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LSL #nlogical shift left n bits, 1 ≤ n ≤ 31.
LSR #nlogical shift right n bits, 1 ≤ n ≤ 32.
ROR #nrotate right n bits, 1 ≤ n ≤ 31.
RRX rotate right one bit, with extend.
- if omitted, no shift occurs, equivalent to LSL #0.
If the user omits the shift, or specifies LSL #0, the instruction uses the value in Rm.
If the user specifies a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the instruction.
However, the contents in the register Rm remains unchanged. Specifying a register with shift also updates the carry flag
when used with certain instructions. For information on the shift operations and how they affect the carry flag, see
“Flexible Second Operand”
12.6.3.4Shift Operations
Register shift operations move the bits in a register left or right by a specified number of bits, the shift length . Register
shift can be performed:
Directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a destination register
During the calculation of Operand2 by the instructions that specify the second operand as a register with shift. See
“Flexible Second Operand” . The result is used by the instruction.
The permitted shift lengths depend on the shift type and the instruction. If the shift length is 0, no shift occurs. Register
shift operations update the carry flag except when the specified shift length is 0. The following sub-sections describe the
various shift operations and how they affect the carry flag. In these descriptions, Rm is the register containing the value
to be shifted, and n is the shift length.
ASR
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register, Rm, to the right by n places, into the right-hand
32-n bits of the result. And it copies the original bit[31] of the register into the left-hand n bits of the result. See Figure 12-
8.
The ASR #n operation can be used to divide the value in the register Rm by 2n, with the result being rounded towards
negative-infinity.
When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS,
ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm.
If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
Figure 12-8. ASR #3
LSR
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand
32-n bits of the result. And it sets the left-hand n bits of the result to 0. See Figure 12-9.
The LSR #n operation can be used to divide the value in the register Rm by 2n, if the value is regarded as an unsigned
integer.
When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS,
ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm.
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If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 12-9. LSR #3
LSL
Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n
bits of the result; and it sets the right-hand n bits of the result to 0. See Figure 12-10.
The LSL #n operation can be used to multiply the value in the register Rm by 2n, if the value is regarded as an unsigned
integer or a two’s complement signed integer. Overflow can occur without warning.
When the instruction is LSLS or when LSL #n, with non-zero n, is used in Operand2 with the instructions MOVS, MVNS,
ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[32-n], of the
register Rm. These instructions do not affect the carry flag when used with LSL #0.
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 12-10.LSL #3
ROR
Rotate right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into the right-hand 32-n
bits of the result; and it moves the right-hand n bits of the register into the left-hand n bits of the result. See Figure 12-11.
When the instruction is RORS or when ROR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS,
ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[n-1], of the register Rm.
If n is 32, then the value of the result is same as the value in Rm, and if the carry flag is updated, it is updated to
bit[31] of Rm.
ROR with shift length, n, more than 32 is the same as ROR with shift length n-32.
Figure 12-11.ROR #3
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RRX
Rotate right with extend moves the bits of the register Rm to the right by one bit; and it copies the carry flag into bit[31] of
the result. See Figure 12-12.
When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS,
ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm.
Figure 12-12.RRX
12.6.3.5Address Alignment
An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word access,
or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned.
The Cortex-M4 processor supports unaligned access only for the following instructions:
LDR, LDRT
LDRH, LDRHT
LDRSH, LDRSHT
STR, STRT
STRH, STRHT
All other load and store instructions generate a usage fault exception if they perform an unaligned access, and therefore
their accesses must be address-aligned. For more information about usage faults, see “Fault Handling” .
Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support
unaligned accesses. Therefore, ARM recommends that programmers ensure that accesses are aligned. To avoid
accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control Register to
trap all unaligned accesses, see “Configuration and Control Register” .
12.6.3.6PC-relative Expressions
A PC-relative expression or label is a symbol that represents the address of an instruction or literal data. It is represented
in the instruction as the PC value plus or minus a numeric offset. The assembler calculates the required offset from the
label and the address of the current instruction. If the offset is too big, the assembler produces an error.
For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus 4 bytes.
For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4 bytes,
with bit[1] of the result cleared to 0 to make it word-aligned.
Your assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a number,
or an expression of the form [PC, #number].
12.6.3.7Conditional Execution
Most data processing instructions can optionally update the condition flags in the Application Program Status Register
(APSR) according to the result of the operation, see “Application Program Status Register” . Some instructions update all
flags, and some only update a subset. If a flag is not updated, the original value is preserved. See the instruction
descriptions for the flags they affect.
An instruction can be executed conditionally, based on the condition flags set in another instruction, either:
Immediately after the instruction that updated the flags
After any number of intervening instructions that have not updated the flags.
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Conditional execution is available by using conditional branches or by adding condition code suffixes to instructions. See
Table 12-16 for a list of the suffixes to add to instructions to make them conditional instructions. The condition code suffix
enables the processor to test a condition based on the flags. If the condition test of a conditional instruction fails, the
instruction:
Does not execute
Does not write any value to its destination register
Does not affect any of the flags
Does not generate any exception.
Conditional instructions, except for conditional branches, must be inside an If-Then instruction block. See “IT” for more
information and restrictions when using the IT instruction. Depending on the vendor, the assembler might automatically
insert an IT instruction if there are conditional instructions outside the IT block.
The CBZ and CBNZ instructions are used to compare the value of a register against zero and branch on the result.
This section describes:
“Condition Flags”
“Condition Code Suffixes” .
Condition Flags
The APSR contains the following condition flags:
N Set to 1 when the result of the operation was negative, cleared to 0 otherwise.
Z Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
C Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.
V Set to 1 when the operation caused overflow, cleared to 0 otherwise.
For more information about the APSR, see “Program Status Register” .
A carry occurs:
If the result of an addition is greater than or equal to 232
If the result of a subtraction is positive or zero
As the result of an inline barrel shifter operation in a move or logical instruction.
An overflow occurs when the sign of the result, in bit[31], does not match the sign of the result, had the operation been
performed at infinite precision, for example:
If adding two negative values results in a positive value
If adding two positive values results in a negative value
If subtracting a positive value from a negative value generates a positive value
If subtracting a negative value from a positive value generates a negative value.
The Compare operations are identical to subtracting, for CMP, or adding, for CMN, except that the result is discarded.
See the instruction descriptions for more information.
Note: Most instructions update the status flags only if the S suffix is specified. See the instruction descriptions for more
information.
Condition Code Suffixes
The instructions that can be conditional have an optional condition code, shown in syntax descriptions as {cond}.
Conditional execution requires a preceding IT instruction. An instruction with a condition code is only executed if the
condition code flags in the APSR meet the specified condition. Table 12-16 shows the condition codes to use.
A conditional execution can be used with the IT instruction to reduce the number of branch instructions in code.
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Table 12-16 also shows the relationship between condition code suffixes and the N, Z, C, and V flags.
Absolute Value
The example below shows the use of a conditional instruction to find the absolute value of a number. R0 = ABS(R1).
MOVS R0, R1 ; R0 = R1, setting flags
IT MI ; IT instruction for the negative condition
RSBMI R0, R1, #0 ; If negative, R0 = -R1
Compare and Update Value
The example below shows the use of conditional instructions to update the value of R4 if the signed values R0 is greater
than R1 and R2 is greater than R3.
CMP R0, R1 ; Compare R0 and R1, setting flags
ITT GT ; IT instruction for the two GT conditions
CMPGT R2, R3 ; If 'greater than', compare R2 and R3, setting flags
MOVGT R4, R5 ; If still 'greater than', do R4 = R5
12.6.3.8Instruction Width Selection
There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the operands
and destination register specified. For some of these instructions, the user can force a specific instruction size by using
an instruction width suffix. The .W suffix forces a 32-bit instruction encoding. The .N suffix forces a 16-bit instruction
encoding.
If the user specifies an instruction width suffix and the assembler cannot generate an instruction encoding of the
requested width, it generates an error.
Note: In some cases, it might be necessary to specify the .W suffix, for example if the operand is the label of an
instruction or literal data, as in the case of branch instructions. This is because the assembler might not automat-
ically generate the right size encoding.
Table 12-16. Condition Code Suffixes
Suffix Flags Meaning
EQ Z = 1 Equal
NE Z = 0 Not equal
CS or
HS C = 1 Higher or same, unsigned ≥
CC or
LO C = 0 Lower, unsigned <
MI N = 1 Negative
PL N = 0 Positive or zero
VS V = 1 Overflow
VC V = 0 No overflow
HI C = 1 and Z = 0 Higher, unsigned >
LS C = 0 or Z = 1 Lower or same, unsigned ≤
GE N = V Greater than or equal, signed ≥
LT N != V Less than, signed <
GT Z = 0 and N = V Greater than, signed >
LE Z = 1 and N != V Less than or equal, signed ≤
AL Can have any
value Always. This is the default when no suffix is
specified.
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To use an instruction width suffix, place it immediately after the instruction mnemonic and condition code, if any. The
example below shows instructions with the instruction width suffix.
BCS.W label ; creates a 32-bit instruction even for a short
; branch
ADDS.W R0, R0, R1 ; creates a 32-bit instruction even though the same
; operation can be done by a 16-bit instruction
12.6.4 Memory Access Instructions
The table below shows the memory access instructions:
Table 12-17. Memory Access Instructions
Mnemonic Description
ADR Load PC-relative address
CLREX Clear Exclusive
LDM{mode} Load Multiple registers
LDR{type} Load Register using immediate offset
LDR{type} Load Register using register offset
LDR{type}T Load Register with unprivileged access
LDR Load Register using PC-relative address
LDRD Load Register Dual
LDREX{type} Load Register Exclusive
POP Pop registers from stack
PUSH Push registers onto stack
STM{mode} Store Multiple registers
STR{type} Store Register using immediate offset
STR{type} Store Register using register offset
STR{type}T Store Register with unprivileged access
STREX{type} Store Register Exclusive
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12.6.4.1ADR
Load PC-relative address.
Syntax ADR{cond} Rd, label
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
label is a PC-relative expression. See “PC-relative Expressions” .
Operation
ADR determines the address by adding an immediate value to the PC, and writes the result to the destination register.
ADR produces position-independent code, because the address is PC-relative.
If ADR is used to generate a target address for a BX or BLX instruction, ensure that bit[0] of the address generated is set
to 1 for correct execution.
Values of label must be within the range of −4095 to +4095 from the address in the PC.
Note: The user might have to use the .W suffix to get the maximum offset range or to generate addresses that are not
word-aligned. See “Instruction Width Selection” .
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
ADR R1, TextMessage ; Write address value of a location labelled as
; TextMessage to R1
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12.6.4.2LDR and STR, Immediate Offset
Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.
Syntax op{type}{cond} Rt, [Rn {, #offset}] ; immediate offset
op{type}{cond} Rt, [Rn, #offset]! ; pre-indexed
op{type}{cond} Rt, [Rn], #offset ; post-indexed
opD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset, two words
opD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, two words
opD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, two words
where:
op is one of:
LDR Load Register.
STR Store Register.
type is one of:
B unsigned byte, zero extend to 32 bits on loads.
SB signed byte, sign extend to 32 bits (LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits (LDR only).
- omit, for word.
cond is an optional condition code, see “Conditional Execution” .
Rt is the register to load or store.
Rn is the register on which the memory address is based.
offset is an offset from Rn. If offset is omitted, the address is the contents of Rn.
Rt2 is the additional register to load or store for two-word operations.
Operation
LDR instructions load one or two registers with a value from memory.
STR instructions store one or two register values to memory.
Load and store instructions with immediate offset can use the following addressing modes:
Offset Addressing
The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the
address for the memory access. The register Rn is unaltered. The assembly language syntax for this mode is:
[Rn, #offset]
Pre-indexed Addressing
The offset value is added to or subtracted from the address obtained from the register Rn. The result is used as the
address for the memory access and written back into the register Rn. The assembly language syntax for this mode is:
[Rn, #offset]!
Post-indexed Addressing
The address obtained from the register Rn is used as the address for the memory access. The offset value is added to or
subtracted from the address, and written back into the register Rn. The assembly language syntax for this mode is:
[Rn], #offset
The value to load or store can be a byte, halfword, word, or two words. Bytes and halfwords can either be signed or
unsigned. See “Address Alignment” .
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The table below shows the ranges of offset for immediate, pre-indexed and post-indexed forms.
Restrictions
For load instructions:
Rt can be SP or PC for word loads only
Rt must be different from Rt2 for two-word loads
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution
A branch occurs to the address created by changing bit[0] of the loaded value to 0
If the instruction is conditional, it must be the last instruction in the IT block.
For store instructions:
Rt can be SP for word stores only
Rt must not be PC
Rn must not be PC
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
Condition Flags
These instructions do not change the flags.
Examples
LDR R8, [R10] ; Loads R8 from the address in R10.
LDRNE R2, [R5, #960]! ; Loads (conditionally) R2 from a word
; 960 bytes above the address in R5, and
; increments R5 by 960.
STR R2, [R9,#const-struc] ; const-struc is an expression evaluating
; to a constant in the range 0-4095.
STRH R3, [R4], #4 ; Store R3 as halfword data into address in
; R4, then increment R4 by 4
LDRD R8, R9, [R3, #0x20] ; Load R8 from a word 32 bytes above the
; address in R3, and load R9 from a word 36
; bytes above the address in R3
STRD R0, R1, [R8], #-16 ; Store R0 to address in R8, and store R1 to
; a word 4 bytes above the address in R8,
; and then decrement R8 by 16.
12.6.4.3LDR and STR, Register Offset
Load and Store with register offset.
Syntax op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
where:
op is one of:
Table 12-18. Offset Ranges
Instruction Type Immediate Offset Pre-indexed Post-indexed
Word, halfword, signed
halfword, byte, or signed byte -255 to 4095 -255 to 255 -255 to 255
Two words multiple of 4 in the
range -1020 to
1020
multiple of 4 in the
range -1020 to
1020
multiple of 4 in the
range -1020 to 1020
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LDR Load Register.
STR Store Register.
type is one of:
B unsigned byte, zero extend to 32 bits on loads.
SB signed byte, sign extend to 32 bits (LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits (LDR only).
- omit, for word.
cond is an optional condition code, see “Conditional Execution” .
Rt is the register to load or store.
Rn is the register on which the memory address is based.
Rm is a register containing a value to be used as the offset.
LSL #nis an optional shift, with n in the range 0 to 3.
Operation
LDR instructions load a register with a value from memory.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the register
Rm and can be shifted left by up to 3 bits using LSL.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be
signed or unsigned. See “Address Alignment” .
Restrictions
In these instructions:
Rn must not be PC
Rm must not be SP and must not be PC
Rt can be SP only for word loads and word stores
Rt can be PC only for word loads.
When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
STR R0, [R5, R1] ; Store value of R0 into an address equal to
; sum of R5 and R1
LDRSB R0, [R5, R1, LSL #1] ; Read byte value from an address equal to
; sum of R5 and two times R1, sign extended it
; to a word value and put it in R0
STR R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1
; and four times R2
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12.6.4.4LDR and STR, Unprivileged
Load and Store with unprivileged access.
Syntax op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset
where:
op is one of:
LDR Load Register.
STR Store Register.
type is one of:
B unsigned byte, zero extend to 32 bits on loads.
SB signed byte, sign extend to 32 bits (LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits (LDR only).
- omit, for word.
cond is an optional condition code, see “Conditional Execution” .
Rt is the register to load or store.
Rn is the register on which the memory address is based.
offset is an offset from Rn and can be 0 to 255.
If offset is omitted, the address is the value in Rn.
Operation
These load and store instructions perform the same function as the memory access instructions with immediate offset,
see “LDR and STR, Immediate Offset” . The difference is that these instructions have only unprivileged access even
when used in privileged software.
When used in unprivileged software, these instructions behave in exactly the same way as normal memory access
instructions with immediate offset.
Restrictions
In these instructions:
Rn must not be PC
Rt must not be SP and must not be PC.
Condition Flags
These instructions do not change the flags.
Examples
STRBTEQ R4, [R7] ; Conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
LDRHT R2, [R2, #8] ; Load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access
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12.6.4.5LDR, PC-relative
Load register from memory.
Syntax LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label ; Load two words
where:
type is one of:
B unsigned byte, zero extend to 32 bits.
SB signed byte, sign extend to 32 bits.
H unsigned halfword, zero extend to 32 bits.
SH signed halfword, sign extend to 32 bits.
- omit, for word.
cond is an optional condition code, see “Conditional Execution” .
Rt is the register to load or store.
Rt2 is the second register to load or store.
label is a PC-relative expression. See “PC-relative Expressions” .
Operation
LDR loads a register with a value from a PC-relative memory address. The memory address is specified by a label or by
an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be
signed or unsigned. See “Address Alignment” .
label must be within a limited range of the current instruction. The table below shows the possible offsets between label
and the PC.
The user might have to use the .W suffix to get the maximum offset range. See “Instruction Width Selection” .
Restrictions
In these instructions:
Rt can be SP or PC only for word loads
Rt2 must not be SP and must not be PC
Rt must be different from Rt2.
Table 12-19. Offset Ranges
Instruction Type Offset Range
Word, halfword, signed halfword, byte, signed byte -4095 to 4095
Two words -1020 to 1020
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When Rt is PC in a word load instruction:
Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
LDR R0, LookUpTable ; Load R0 with a word of data from an address
; labelled as LookUpTable
LDRSB R7, localdata ; Load a byte value from an address labelled
; as localdata, sign extend it to a word
; value, and put it in R7
12.6.4.6LDM and STM
Load and Store Multiple registers.
Syntax op{addr_mode}{cond} Rn{!}, reglist
where:
op is one of:
LDM Load Multiple registers.
STM Store Multiple registers.
addr_mode is any one of the following:
IA Increment address After each access. This is the default.
DB Decrement address Before each access.
cond is an optional condition code, see “Conditional Execution” .
Rn is the register on which the memory addresses are based.
! is an optional writeback suffix.
If ! is present, the final address, that is loaded from or stored to, is written back into Rn.
reglist is a list of one or more registers to be loaded or stored, enclosed in braces. It
can contain register ranges. It must be comma separated if it contains more
than one register or register range, see “Examples” .
LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full Descending stacks.
LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending stacks.
STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto Empty Ascending stacks.
STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending stacks
Operation
LDM instructions load the registers in reglist with word values from memory addresses based on Rn.
STM instructions store the word values in the registers in reglist to memory addresses based on Rn.
For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the accesses are at 4-byte
intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of registers in reglist. The accesses happens in order
of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest
number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4 * ( n-1) is
written back to Rn.
For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging
from Rn to Rn - 4 * ( n-1), where n is the number of registers in reglist. The accesses happen in order of decreasing
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register numbers, with the highest numbered register using the highest memory address and the lowest number register
using the lowest memory address. If the writeback suffix is specified, the value of Rn - 4 * (n-1) is written back to Rn.
The PUSH and POP instructions can be expressed in this form. See “PUSH and POP” for details.
Restrictions
In these instructions:
Rn must not be PC
reglist must not contain SP
In any STM instruction, reglist must not contain PC
In any LDM instruction, reglist must not contain PC if it contains LR
reglist must not contain Rn if the writeback suffix is specified.
When PC is in reglist in an LDM instruction:
Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-aligned
address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
LDM R8,{R0,R2,R9} ; LDMIA is a synonym for LDM
STMDB R1!,{R3-R6,R11,R12}
Incorrect Examples
STM R5!,{R5,R4,R9} ; Value stored for R5 is unpredictable
LDM R2, {} ; There must be at least one register in the list
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12.6.4.7PUSH and POP
Push registers onto, and pop registers off a full-descending stack.
Syntax PUSH{cond} reglist
POP{cond} reglist
where:
cond is an optional condition code, see “Conditional Execution” .
reglist is a non-empty list of registers, enclosed in braces. It can contain register
ranges. It must be comma separated if it contains more than one register or
register range.
PUSH and POP are synonyms for STMDB and LDM (or LDMIA) with the memory addresses for the access based on SP,
and with the final address for the access written back to the SP. PUSH and POP are the preferred mnemonics in these
cases.
Operation
PUSH stores registers on the stack in order of decreasing the register numbers, with the highest numbered register using
the highest memory address and the lowest numbered register using the lowest memory address.
POP loads registers from the stack in order of increasing register numbers, with the lowest numbered register using the
lowest memory address and the highest numbered register using the highest memory address.
See “LDM and STM” for more information.
Restrictions
In these instructions:
reglist must not contain SP
For the PUSH instruction, reglist must not contain PC
For the POP instruction, reglist must not contain PC if it contains LR.
When PC is in reglist in a POP instruction:
Bit[0] of the value loaded to the PC must be 1 for correct execution, and a branch occurs to this halfword-aligned
address
If the instruction is conditional, it must be the last instruction in the IT block.
Condition Flags
These instructions do not change the flags.
Examples
PUSH {R0,R4-R7}
PUSH {R2,LR}
POP {R0,R10,PC}
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12.6.4.8LDREX and STREX
Load and Store Register Exclusive.
Syntax LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register for the returned status.
Rt is the register to load or store.
Rn is the register on which the memory address is based.
offset is an optional offset applied to the value in Rn.
If offset is omitted, the address is the value in Rn.
Operation
LDREX, LDREXB, and LDREXH load a word, byte, and halfword respectively from a memory address.
STREX, STREXB, and STREXH attempt to store a word, byte, and halfword respectively to a memory address. The
address used in any Store-Exclusive instruction must be the same as the address in the most recently executed Load-
exclusive instruction. The value stored by the Store-Exclusive instruction must also have the same data size as the value
loaded by the preceding Load-exclusive instruction. This means software must always use a Load-exclusive instruction
and a matching Store-Exclusive instruction to perform a synchronization operation, see “Synchronization Primitives” .
If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it does not perform the store, it
writes 1 to its destination register. If the Store-Exclusive instruction writes 0 to the destination register, it is guaranteed
that no other process in the system has accessed the memory location between the Load-exclusive and Store-Exclusive
instructions.
For reasons of performance, keep the number of instructions between corresponding Load-Exclusive and Store-
Exclusive instruction to a minimum.
The result of executing a Store-Exclusive instruction to an address that is different from that used in the preceding Load-
Exclusive instruction is unpredictable.
Restrictions
In these instructions:
Do not use PC
Do not use SP for Rd and Rt
For STREX, Rd must be different from both Rt and Rn
The value of offset must be a multiple of four in the range 0-1020.
Condition Flags
These instructions do not change the flags.
Examples
MOV R1, #0x1 ; Initialize the ‘lock taken’ value try
LDREX R0, [LockAddr] ; Load the lock value
CMP R0, #0 ; Is the lock free?
ITT EQ ; IT instruction for STREXEQ and CMPEQ
STREXEQ R0, R1, [LockAddr] ; Try and claim the lock
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CMPEQ R0, #0 ; Did this succeed?
BNE try ; No – try again
.... ; Yes – we have the lock
12.6.4.9CLREX
Clear Exclusive.
Syntax CLREX{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
Use CLREX to make the next STREX, STREXB, or STREXH instruction write 1 to its destination register and fail to
perform the store. It is useful in exception handler code to force the failure of the store exclusive if the exception occurs
between a load exclusive instruction and the matching store exclusive instruction in a synchronization operation.
See “Synchronization Primitives” for more information.
Condition Flags
These instructions do not change the flags.
Examples
CLREX
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12.6.5 General Data Processing Instructions
The table below shows the data processing instructions:
Table 12-20. Data Processing Instructions
Mnemonic Description
ADC Add with Carry
ADD Add
ADDW Add
AND Logical AND
ASR Arithmetic Shift Right
BIC Bit Clear
CLZ Count leading zeros
CMN Compare Negative
CMP Compare
EOR Exclusive OR
LSL Logical Shift Left
LSR Logical Shift Right
MOV Move
MOVT Move Top
MOVW Move 16-bit constant
MVN Move NOT
ORN Logical OR NOT
ORR Logical OR
RBIT Reverse Bits
REV Reverse byte order in a word
REV16 Reverse byte order in each halfword
REVSH Reverse byte order in bottom halfword and sign extend
ROR Rotate Right
RRX Rotate Right with Extend
RSB Reverse Subtract
SADD16 Signed Add 16
SADD8 Signed Add 8
SASX Signed Add and Subtract with Exchange
SSAX Signed Subtract and Add with Exchange
SBC Subtract with Carry
SHADD16 Signed Halving Add 16
SHADD8 Signed Halving Add 8
SHASX Signed Halving Add and Subtract with Exchange
SHSAX Signed Halving Subtract and Add with Exchange
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SHSUB16 Signed Halving Subtract 16
SHSUB8 Signed Halving Subtract 8
SSUB16 Signed Subtract 16
SSUB8 Signed Subtract 8
SUB Subtract
SUBW Subtract
TEQ Test Equivalence
TST Test
UADD16 Unsigned Add 16
UADD8 Unsigned Add 8
UASX Unsigned Add and Subtract with Exchange
USAX Unsigned Subtract and Add with Exchange
UHADD16 Unsigned Halving Add 16
UHADD8 Unsigned Halving Add 8
UHASX Unsigned Halving Add and Subtract with Exchange
UHSAX Unsigned Halving Subtract and Add with Exchange
UHSUB16 Unsigned Halving Subtract 16
UHSUB8 Unsigned Halving Subtract 8
USAD8 Unsigned Sum of Absolute Differences
USADA8 Unsigned Sum of Absolute Differences and Accumulate
USUB16 Unsigned Subtract 16
USUB8 Unsigned Subtract 8
Table 12-20. Data Processing Instructions (Continued)
Mnemonic Description
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12.6.5.1ADD, ADC, SUB, SBC, and RSB
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
Syntax op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only
where:
op is one of:
ADD Add.
ADC Add with Carry.
SUB Subtract.
SBC Subtract with Carry.
RSB Reverse Subtract.
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation,
see “Conditional Execution” .
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register. If Rd is omitted, the destination register is Rn.
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options.
imm12 is any value in the range 0-4095.
Operation
The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.
The ADC instruction adds the values in Rn and Operand2, together with the carry flag.
The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is reduced
by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide range of
options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see Multiword arithmetic examples on.
See also “ADR” .
Note: ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the SUB syntax
that uses the imm12 operand.
Restrictions
In these instructions:
Operand2 must not be SP and must not be PC
Rd can be SP only in ADD and SUB, and only with the additional restrictions:
Rn must also be SP
Any shift in Operand2 must be limited to a maximum of 3 bits using LSL
Rn can be SP only in ADD and SUB
Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:
The user must not specify the S suffix
Rm must not be PC and must not be SP
If the instruction is conditional, it must be the last instruction in the IT block
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With the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and SUB, and only with
the additional restrictions:
The user must not specify the S suffix
The second operand must be a constant in the range 0 to 4095.
Note: When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 0b00 before
performing the calculation, making the base address for the calculation word-aligned.
Note: To generate the address of an instruction, the constant based on the value of the PC must be
adjusted. ARM recommends to use the ADR instruction instead of ADD or SUB with Rn equal to the PC,
because the assembler automatically calculates the correct constant for the ADR instruction.
When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
Bit[0] of the value written to the PC is ignored
A branch occurs to the address created by forcing bit[0] of that value to 0.
Condition Flags
If
S
is specified, these instructions update the N, Z, C and V flags according to the result.
Examples
ADD R2, R1, R3 ; Sets the flags on the result
SUBS R8, R6, #240 ; Subtracts contents of R4 from 1280
RSB R4, R4, #1280 ; Only executed if C flag set and Z
ADCHI R11, R0, R3 ; flag clear.
Multiword Arithmetic Examples
The example below shows two instructions that add a 64-bit integer contained in R2 and R3 to another 64-bit integer
contained in R0 and R1, and place the result in R4 and R5.
64-bit Addition Example
ADDS R4, R0, R2 ; add the least significant words
ADC R5, R1, R3 ; add the most significant words with carry
Multiword values do not have to use consecutive registers. The example below shows instructions that subtract a 96-bit
integer contained in R9, R1, and R11 from another contained in R6, R2, and R8. The example stores the result in R6, R9,
and R2.
96-bit Subtraction Example
SUBS R6, R6, R9 ; subtract the least significant words
SBCS R9, R2, R1 ; subtract the middle words with carry
SBC R2, R8, R11 ; subtract the most significant words with carry
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12.6.5.2AND, ORR, EOR, BIC, and ORN
Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.
Syntax op{S}{cond} {Rd,} Rn, Operand2
where:
op is one of:
AND logical AND.
ORR
logical OR, or bit set.
EOR
logical Exclusive OR.
BIC
logical AND NOT, or bit clear.
ORN
logical OR NOT.
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation,
see “Conditional Execution” .
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options
Operation
The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn and
Operand2.
The BIC instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the
value of Operand2.
The ORN instruction performs an OR operation on the bits in Rn with the complements of the corresponding bits in the
value of Operand2.
Restrictions
Do not use SP and do not use PC.
Condition Flags
If
S
is specified, these instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
Examples
AND R9, R2, #0xFF00
ORREQ R2, R0, R5
ANDS R9, R8, #0x19
EORS R7, R11, #0x18181818
BIC R0, R1, #0xab
ORN R7, R11, R14, ROR #4
ORNS R7, R11, R14, ASR #32
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12.6.5.3ASR, LSL, LSR, ROR, and RRX
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.
Syntax op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
where:
op is one of:
ASR Arithmetic Shift Right.
LSL Logical Shift Left.
LSR Logical Shift Right.
ROR Rotate Right.
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation,
see “Conditional Execution” .
Rd is the destination register.
Rm is the register holding the value to be shifted.
Rs is the register holding the shift length to apply to the value in Rm. Only the least
significant byte is used and can be in the range 0 to 255.
n is the shift length. The range of shift length depends on the instruction:
ASR shift length from 1 to 32
LSL shift length from 0 to 31
LSR shift length from 1 to 32
ROR shift length from 0 to 31
MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0.
Operation
ASR, LSL, LSR, and ROR move the bits in the register Rm to the left or right by the number of places specified by
constant n or register Rs.
RRX moves the bits in register Rm to the right by 1.
In all these instructions, the result is written to Rd, but the value in register Rm remains unchanged. For details on what
result is generated by the different instructions, see “Shift Operations” .
Restrictions
Do not use SP and do not use PC.
Condition Flags
If
S
is specified:
These instructions update the N and Z flags according to the result
The C flag is updated to the last bit shifted out, except when the shift length is 0, see “Shift Operations” .
Examples
ASR R7, R8, #9 ; Arithmetic shift right by 9 bits
SLS R1, R2, #3 ; Logical shift left by 3 bits with flag update
LSR R4, R5, #6 ; Logical shift right by 6 bits
ROR R4, R5, R6 ; Rotate right by the value in the bottom byte of R6
RRX R4, R5 ; Rotate right with extend.
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12.6.5.4CLZ
Count Leading Zeros.
Syntax CLZ{cond} Rd, Rm
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rm is the operand register.
Operation
The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd. The result value
is 32 if no bits are set and zero if bit[31] is set.
Restrictions
Do not use SP and do not use PC.
Condition Flags
This instruction does not change the flags.
Examples
CLZ R4,R9
CLZNE R2,R3
12.6.5.5CMP and CMN
Compare and Compare Negative.
Syntax CMP{cond} Rn, Operand2
CMN{cond} Rn, Operand2
where:
cond is an optional condition code, see “Conditional Execution” .
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options
Operation
These instructions compare the value in a register with Operand2. They update the condition flags on the result, but do
not write the result to a register.
The CMP instruction subtracts the value of Operand2 f rom th e valu e in Rn. This is the same as a SUBS instruction,
except that the result is discarded.
The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an ADDS instruction, except that
the result is discarded.
Restrictions
In these instructions:
Do not use PC
Operand2 must not be SP.
Condition Flags
These instructions update the N, Z, C and V flags according to the result.
Examples
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CMP R2, R9
CMN R0, #6400
CMPGT SP, R7, LSL #2
12.6.5.6MOV and MVN
Move and Move NOT.
Syntax MOV{S}{cond} Rd, Operand2
MOV{cond} Rd, #imm16
MVN{S}{cond} Rd, Operand2
where:
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation,
see “Conditional Execution” .
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options
imm16 is any value in the range 0-65535.
Operation
The MOV instruction copies the value of Operand2 into Rd.
When Operand2 in a MOV instruction is a register with a shift other than LSL #0, the preferred syntax is the
corresponding shift instruction:
ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n
LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #n if n != 0
LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n
ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n
RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX.
Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift instructions:
MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs
See “ASR, LSL, LSR, ROR, and RRX” .
The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and places the
result into Rd.
The MOVW instruction provides the same function as MOV, but is restricted to using the imm16 operand.
Restrictions
SP and PC only can be used in the MOV instruction, with the following restrictions:
The second operand must be a register without shift
The S suffix must not be specified.
When Rd is PC in a MOV instruction:
Bit[0] of the value written to the PC is ignored
A branch occurs to the address created by forcing bit[0] of that value to 0.
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Though it is possible to use MOV as a branch instruction, ARM strongly recommends the use of a BX or BLX instruction
to branch for software portability to the ARM instruction set.
Condition Flags
If S is specified, these instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
Examples
MOVS R11, #0x000B ; Write value of 0x000B to
R11, flags get updated
MOV R1, #0xFA05 ; Write value of 0xFA05 to
R1, flags are not updated
MOVS R10, R12 ; Write value in R12 to R10,
flags get updated
MOV R3, #23 ; Write value of 23 to R3
MOV R8, SP ; Write value of stack pointer to R8
MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
; to the R2 and update flags.
12.6.5.7MOVT
Move Top.
Syntax MOVT{cond} Rd, #imm16
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
imm16 is a 16-bit immediate constant.
Operation
MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write does
not affect Rd[15:0].
The MOV, MOVT instruction pair enables to generate any 32-bit constant.
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
MOVT R3, #0xF123 ; Write 0xF123 to upper halfword of R3, lower halfword
; and APSR are unchanged.
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12.6.5.8REV, REV16, REVSH, and RBIT
Reverse bytes and Reverse bits.
Syntax op{cond} Rd, Rn
where:
op is any of:
REV Reverse byte order in a word.
REV16 Reverse byte order in each halfword independently.
REVSH Reverse byte order in the bottom halfword, and sign extend to 32 bits.
RBIT Reverse the bit order in a 32-bit word.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the register holding the operand.
Operation
Use these instructions to change endianness of data:
REV converts either:
32-bit big-endian data into little-endian data
32-bit little-endian data into big-endian data.
REV16 converts either:
16-bit big-endian data into little-endian data
16-bit little-endian data into big-endian data.
REVSH converts either:
16-bit signed big-endian data into 32-bit signed little-endian data
16-bit signed little-endian data into 32-bit signed big-endian data.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
REV R3, R7; Reverse byte order of value in R7 and write it to R3
REV16 R0, R0; Reverse byte order of each 16-bit halfword in R0
REVSH R0, R5; Reverse Signed Halfword
REVHS R3, R7; Reverse with Higher or Same condition
RBIT R7, R8; Reverse bit order of value in R8 and write the result to R7.
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12.6.5.9SADD16 and SADD8
Signed Add 16 and Signed Add 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
SADD16 Performs two 16-bit signed integer additions.
SADD8 Performs four 8-bit signed integer additions.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the first register holding the operand.
Rm is the second register holding the operand.
Operation
Use these instructions to perform a halfword or byte add in parallel:
The SADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Writes the result in the corresponding halfwords of the destination register.
The SADD8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
Writes the result in the corresponding bytes of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SADD16 R1, R0 ; Adds the halfwords in R0 to the corresponding
; halfwords of R1 and writes to corresponding halfword
; of R1.
SADD8 R4, R0, R5 ; Adds bytes of R0 to the corresponding byte in R5 and
; writes to the corresponding byte in R4.
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12.6.5.10SHADD16 and SHADD8
Signed Halving Add 16 and Signed Halving Add 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
SHADD16 Signed Halving Add 16.
SHADD8 Signed Halving Add 8.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the first operand register.
Rm is the second operand register.
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the destination
register:
The SHADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the halfword results in the destination register.
The SHADDB8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the byte results in the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SHADD16 R1, R0 ; Adds halfwords in R0 to corresponding halfword of R1
; and writes halved result to corresponding halfword in
; R1
SHADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and
; writes halved result to corresponding byte in R4.
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12.6.5.11SHASX and SHSAX
Signed Halving Add and Subtract with Exchange and Signed Halving Subtract and Add with Exchange.
Syntax op{cond} {Rd}, Rn, Rm
where:
op is any of:
SHASX Add and Subtract with Exchange and Halving.
SHSAX Subtract and Add with Exchange and Halving.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn, Rm are registers holding the first and second operands.
Operation
The SHASX instruction:
1. Adds the top halfword of the first operand with the bottom halfword of the second operand.
2. Writes the halfword result of the addition to the top halfword of the destination register, shifted by one bit to the
right causing a divide by two, or halving.
3. Subtracts the top halfword of the second operand from the bottom highword of the first operand.
4. Writes the halfword result of the division in the bottom halfword of the destination register, shifted by one bit to the
right causing a divide by two, or halving.
The SHSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2. Writes the halfword result of the addition to the bottom halfword of the destination register, shifted by one bit to the
right causing a divide by two, or halving.
3. Adds the bottom halfword of the first operand with the top halfword of the second operand.
4. Writes the halfword result of the division in the top halfword of the destination register, shifted by one bit to the right
causing a divide by two, or halving.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SHASX R7, R4, R2 ; Adds top halfword of R4 to bottom halfword of R2
; and writes halved result to top halfword of R7
; Subtracts top halfword of R2 from bottom halfword of
; R4 and writes halved result to bottom halfword of R7
SHSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword
; of R3 and writes halved result to top halfword of R0
; Adds top halfword of R5 to bottom halfword of R3 and
; writes halved result to bottom halfword of R0.
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12.6.5.12SHSUB16 and SHSUB8
Signed Halving Subtract 16 and Signed Halving Subtract 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
SHSUB16 Signed Halving Subtract 16.
SHSUB8 Signed Halving Subtract 8.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the first operand register.
Rm is the second operand register.
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the destination
register:
The SHSUB16 instruction:
1. Subtracts each halfword of the second operand from the corresponding halfwords of the first operand.
2. Shuffles the result by one bit to the right, halving the data.
3. Writes the halved halfword results in the destination register.
The SHSUBB8 instruction:
1. Subtracts each byte of the second operand from the corresponding byte of the first operand,
2. Shuffles the result by one bit to the right, halving the data,
3. Writes the corresponding signed byte results in the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SHSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword
; of R1 and writes to corresponding halfword of R1
SHSUB8 R4, R0, R5 ; Subtracts bytes of R0 from corresponding byte in R5,
; and writes to corresponding byte in R4.
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12.6.5.13SSUB16 and SSUB8
Signed Subtract 16 and Signed Subtract 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
SSUB16 Performs two 16-bit signed integer subtractions.
SSUB8 Performs four 8-bit signed integer subtractions.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the first operand register.
Rm is the second operand register.
Operation
Use these instructions to change endianness of data:
The SSUB16 instruction:
1. Subtracts each halfword from the second operand from the corresponding halfword of the first operand
2. Writes the difference result of two signed halfwords in the corresponding halfword of the destination register.
The SSUB8 instruction:
1. Subtracts each byte of the second operand from the corresponding byte of the first operand
2. Writes the difference result of four signed bytes in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword
; of R1 and writes to corresponding halfword of R1
SSUB8 R4, R0, R5 ; Subtracts bytes of R5 from corresponding byte in
; R0, and writes to corresponding byte of R4.
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12.6.5.14SASX and SSAX
Signed Add and Subtract with Exchange and Signed Subtract and Add with Exchange.
Syntax op{cond} {Rd}, Rm, Rn
where:
op is any of:
SASX Signed Add and Subtract with Exchange.
SSAX Signed Subtract and Add with Exchange.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn, Rm are registers holding the first and second operands.
Operation
The SASX instruction:
1. Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand.
2. Writes the signed result of the addition to the top halfword of the destination register.
3. Subtracts the signed bottom halfword of the second operand from the top signed highword of the first operand.
4. Writes the signed result of the subtraction to the bottom halfword of the destination register.
The SSAX instruction:
1. Subtracts the signed bottom halfword of the second operand from the top signed highword of the first operand.
2. Writes the signed result of the addition to the bottom halfword of the destination register.
3. Adds the signed top halfword of the first operand with the signed bottom halfword of the second operand.
4. Writes the signed result of the subtraction to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SASX R0, R4, R5 ; Adds top halfword of R4 to bottom halfword of R5 and
; writes to top halfword of R0
; Subtracts bottom halfword of R5 from top halfword of R4
; and writes to bottom halfword of R0
SSAX R7, R3, R2 ; Subtracts top halfword of R2 from bottom halfword of R3
; and writes to bottom halfword of R7
; Adds top halfword of R3 with bottom halfword of R2 and
; writes to top halfword of R7.
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12.6.5.15TST and TEQ
Test bits and Test Equivalence.
Syntax TST{cond} Rn, Operand2
TEQ{cond} Rn, Operand2
where
cond is an optional condition code, see “Conditional Execution” .
Rn is the register holding the first operand.
Operand2 is a flexible second operand. See “Flexible Second Operand” for details of the
options
Operation
These instructions test the value in a register against Operand2. They update the condition flags based on the result, but
do not write the result to a register.
The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2. This is the same as
the ANDS instruction, except that it discards the result.
To test whether a bit of Rn is 0 or 1, use the TST instruction with an Operand2 constant that has that bit set to 1 and all
other bits cleared to 0.
The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2. This is the
same as the EORS instruction, except that it discards the result.
Use the TEQ instruction to test if two values are equal without affecting the V or C flags.
TEQ is also useful for testing the sign of a value. After the comparison, the N flag is the logical Exclusive OR of the sign
bits of the two operands.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions:
Update the N and Z flags according to the result
Can update the C flag during the calculation of Operand2, see “Flexible Second Operand”
Do not affect the V flag.
Examples
TST R0, #0x3F8 ; Perform bitwise AND of R0 value to 0x3F8,
; APSR is updated but result is discarded
TEQEQ R10, R9 ; Conditionally test if value in R10 is equal to
; value in R9, APSR is updated but result is discarded.
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12.6.5.16UADD16 and UADD8
Unsigned Add 16 and Unsigned Add 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
UADD16 Performs two 16-bit unsigned integer additions.
UADD8 Performs four 8-bit unsigned integer additions.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the first register holding the operand.
Rm is the second register holding the operand.
Operation
Use these instructions to add 16- and 8-bit unsigned data:
The UADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Writes the unsigned result in the corresponding halfwords of the destination register.
The UADD16 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2. Writes the unsigned result in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
UADD16 R1, R0 ; Adds halfwords in R0 to corresponding halfword of R1,
; writes to corresponding halfword of R1
UADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and
; writes to corresponding byte in R4.
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12.6.5.17UASX and USAX
Add and Subtract with Exchange and Subtract and Add with Exchange.
Syntax op{cond} {Rd}, Rn, Rm
where:
op is one of:
UASX Add and Subtract with Exchange.
USAX Subtract and Add with Exchange.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn, Rm are registers holding the first and second operands.
Operation
The UASX instruction:
1. Subtracts the top halfword of the second operand from the bottom halfword of the first operand.
2. Writes the unsigned result from the subtraction to the bottom halfword of the destination register.
3. Adds the top halfword of the first operand with the bottom halfword of the second operand.
4. Writes the unsigned result of the addition to the top halfword of the destination register.
The USAX instruction:
1. Adds the bottom halfword of the first operand with the top halfword of the second operand.
2. Writes the unsigned result of the addition to the bottom halfword of the destination register.
3. Subtracts the bottom halfword of the second operand from the top halfword of the first operand.
4. Writes the unsigned result from the subtraction to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UASX R0, R4, R5 ; Adds top halfword of R4 to bottom halfword of R5 and
; writes to top halfword of R0
; Subtracts bottom halfword of R5 from top halfword of R0
; and writes to bottom halfword of R0
USAX R7, R3, R2 ; Subtracts top halfword of R2 from bottom halfword of R3
; and writes to bottom halfword of R7
; Adds top halfword of R3 to bottom halfword of R2 and
; writes to top halfword of R7.
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12.6.5.18UHADD16 and UHADD8
Unsigned Halving Add 16 and Unsigned Halving Add 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
UHADD16 Unsigned Halving Add 16.
UHADD8 Unsigned Halving Add 8.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the register holding the first operand.
Rm is the register holding the second operand.
Operation
Use these instructions to add 16- and 8-bit data and then to halve the result befo re writing the result to the destination
register:
The UHADD16 instruction:
1. Adds each halfword from the first operand to the corresponding halfword of the second operand.
2. Shuffles the halfword result by one bit to the right, halving the data.
3. Writes the unsigned results to the corresponding halfword in the destination register.
The UHADD8 instruction:
1. Adds each byte of the first operand to the corresponding byte of the second operand.
2. Shuffles the byte result by one bit to the right, halving the data.
3. Writes the unsigned results in the corresponding byte in the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
UHADD16 R7, R3 ; Adds halfwords in R7 to corresponding halfword of R3
; and writes halved result to corresponding halfword
; in R7
UHADD8 R4, R0, R5 ; Adds bytes of R0 to corresponding byte in R5 and
; writes halved result to corresponding byte in R4.
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12.6.5.19UHASX and UHSAX
Unsigned Halving Add and Subtract with Exchange and Unsigned Halving Subtract and Add with Exchange.
Syntax op{cond} {Rd}, Rn, Rm
where:
op is one of:
UHASX Add and Subtract with Exchange and Halving.
UHSAX Subtract and Add with Exchange and Halving.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn, Rm are registers holding the first and second operands.
Operation
The UHASX instruction:
1. Adds the top halfword of the first operand with the bottom halfword of the second operand.
2. Shifts the result by one bit to the right causing a divide by two, or halving.
3. Writes the halfword result of the addition to the top halfword of the destination register.
4. Subtracts the top halfword of the second operand from the bottom highword of the first operand.
5. Shifts the result by one bit to the right causing a divide by two, or halving.
6. Writes the halfword result of the division in the bottom halfword of the destination register.
The UHSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2. Shifts the result by one bit to the right causing a divide by two, or halving.
3. Writes the halfword result of the subtraction in the top halfword of the destination register.
4. Adds the bottom halfword of the first operand with the top halfword of the second operand.
5. Shifts the result by one bit to the right causing a divide by two, or halving.
6. Writes the halfword result of the addition to the bottom halfword of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UHASX R7, R4, R2 ; Adds top halfword of R4 with bottom halfword of R2
; and writes halved result to top halfword of R7
; Subtracts top halfword of R2 from bottom halfword of
; R7 and writes halved result to bottom halfword of R7
UHSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of
; R3 and writes halved result to top halfword of R0
; Adds top halfword of R5 to bottom halfword of R3 and
; writes halved result to bottom halfword of R0.
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12.6.5.20UHSUB16 and UHSUB8
Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8
Syntax op{cond}{Rd,} Rn, Rm
where:
op is any of:
UHSUB16 Performs two unsigned 16-bit integer additions, halves the results,
and writes the results to the destination register.
UHSUB8 Performs four unsigned 8-bit integer additions, halves the results, and
writes the results to the destination register.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the first register holding the operand.
Rm is the second register holding the operand.
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing the result to the destination
register:
The UHSUB16 instruction:
1. Subtracts each halfword of the second operand from the corresponding halfword of the first operand.
2. Shuffles each halfword result to the right by one bit, halving the data.
3. Writes each unsigned halfword result to the corresponding halfwords in the destination register.
The UHSUB8 instruction:
1. Subtracts each byte of second operand from the corresponding byte of the first operand.
2. Shuffles each byte result by one bit to the right, halving the data.
3. Writes the unsigned byte results to the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
UHSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword of
; R1 and writes halved result to corresponding halfword in R1
UHSUB8 R4, R0, R5 ; Subtracts bytes of R5 from corresponding byte in R0 and
; writes halved result to corresponding byte in R4.
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12.6.5.21SEL
Select Bytes. Selects each byte of its result from either its first operand or its second operand, according to the values of
the GE flags.
Syntax SEL{<c>}{<q>} {<Rd>,} <Rn>, <Rm>
where:
c, q are standard assembler syntax fields.
Rd is the destination register.
Rn is the first register holding the operand.
Rm is the second register holding the operand.
Operation
The
SEL
instruction:
1. Reads the value of each bit of APSR.GE.
2. Depending on the value of APSR.GE, assigns the destination register the value of either the first or second oper-
and register.
Restrictions
None.
Condition Flags
These instructions do not change the flags.
Examples
SADD16 R0, R1, R2 ; Set GE bits based on result
SEL R0, R0, R3 ; Select bytes from R0 or R3, based on GE.
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12.6.5.22USAD8
Unsigned Sum of Absolute Differences
Syntax USAD8{cond}{Rd,} Rn, Rm
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the first operand register.
Rm is the second operand register.
Operation
The USAD8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register.
2. Adds the absolute values of the differences together.
3. Writes the result to the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
USAD8 R1, R4, R0 ; Subtracts each byte in R0 from corresponding byte of R4
; adds the differences and writes to R1
USAD8 R0, R5 ; Subtracts bytes of R5 from corresponding byte in R0,
; adds the differences and writes to R0.
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12.6.5.23USADA8
Unsigned Sum of Absolute Differences and Accumulate
Syntax USADA8{cond}{Rd,} Rn, Rm, Ra
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the first operand register.
Rm is the second operand register.
Ra is the register that contains the accumulation value.
Operation
The USADA8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register.
2. Adds the unsigned absolute differences together.
3. Adds the accumulation value to the sum of the absolute differences.
4. Writes the result to the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
USADA8 R1, R0, R6 ; Subtracts bytes in R0 from corresponding halfword of R1
; adds differences, adds value of R6, writes to R1
USADA8 R4, R0, R5, R2 ; Subtracts bytes of R5 from corresponding byte in R0
; adds differences, adds value of R2 writes to R4.
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12.6.5.24USUB16 and USUB8
Unsigned Subtract 16 and Unsigned Subtract 8
Syntax op{cond}{Rd,} Rn, Rm
where
op is any of:
USUB16 Unsigned Subtract 16.
USUB8 Unsigned Subtract 8.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the first operand register.
Rm is the second operand register.
Operation
Use these instructions to subtract 16-bit and 8-bit data before writing the result to the destination register:
The USUB16 instruction:
1. Subtracts each halfword from the second operand register from the corresponding halfword of the first operand
register.
2. Writes the unsigned result in the corresponding halfwords of the destination register.
The USUB8 instruction:
1. Subtracts each byte of the second operand register from the corresponding byte of the first operand register.
2. Writes the unsigned byte result in the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
USUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding halfword of R1
; and writes to corresponding halfword in R1USUB8 R4, R0, R5
; Subtracts bytes of R5 from corresponding byte in R0 and
; writes to the corresponding byte in R4.
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12.6.6 Multiply and Divide Instructions
The table below shows the multiply and divide instructions:
Table 12-21. Multiply and Divide Instructions
Mnemonic Description
MLA Multiply with Accumulate, 32-bit result
MLS Multiply and Subtract, 32-bit result
MUL Multiply, 32-bit result
SDIV Signed Divide
SMLA[B,T] Signed Multiply Accumulate (halfwords)
SMLAD
,
SMLADX
Signed Multiply Accumulate Dual
SMLAL Signed Multiply with Accumulate (32x32+64), 64-bit result
SMLAL[B,T]
Signed Multiply Accumulate Long (halfwords)
SMLALD
,
SMLALDX
Signed Multiply Accumulate Long Dual
SMLAW[B|T] Signed Multiply Accumulate (word by halfword)
SMLSD Signed Multiply Subtract Dual
SMLSLD Signed Multiply Subtract Long Dual
SMMLA Signed Most Significant Word Multiply Accumulate
SMMLS
,
SMMLSR
Signed Most Significant Word Multiply Subtract
SMUAD, SMUADX Signed Dual Multiply Add
SMUL[B,T] Signed Multiply (word by halfword)
SMMUL
,
SMMULR
Signed Most Significant Word Multiply
SMULL Signed Multiply (32x32), 64-bit result
SMULWB, SMULWT Signed Multiply (word by halfword)
SMUSD, SMUSDX Signed Dual Multiply Subtract
UDIV Unsigned Divide
UMAAL Unsigned Multiply Accumulate Accumulate Long
(32x32+32+32), 64-bit result
UMLAL Unsigned Multiply with Accumulate (32x32+64), 64-bit result
UMULL Unsigned Multiply (32x32), 64-bit result
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12.6.6.1MUL, MLA, and MLS
Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and producing a 32-bit result.
Syntax MUL{S}{cond} {Rd,} Rn, Rm ; Multiply
MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate
MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract
where:
cond is an optional condition code, see “Conditional Execution” .
S is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation,
see “Conditional Execution” .
Rd is the destination register. If Rd is omitted, the destination register is Rn.
Rn, Rm are registers holding the values to be multiplied.
Ra is a register holding the value to be added or subtracted from.
Operation
The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the result in Rd.
The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least significant 32
bits of the result in Rd.
The MLS instruction multiplies the values from Rn and Rm, subtracts the product from the value from Ra, and places the
least significant 32 bits of the result in Rd.
The results of these instructions do not depend on whether the operands are signed or unsigned.
Restrictions
In these instructions, do not use SP and do not use PC.
If the S suffix is used with the MUL instruction:
Rd, Rn, and Rm must all be in the range R0 to R7
Rd must be the same as Rm
The cond suffix must not be used.
Condition Flags
If S is specified, the MUL instruction:
Updates the N and Z flags according to the result
Does not affect the C and V flags.
Examples
MUL R10, R2, R5 ; Multiply, R10 = R2 x R5
MLA R10, R2, R1, R5 ; Multiply with accumulate, R10 = (R2 x R1) + R5
MULS R0, R2, R2 ; Multiply with flag update, R0 = R2 x R2
MULLT R2, R3, R2 ; Conditionally multiply, R2 = R3 x R2
MLS R4, R5, R6, R7 ; Multiply with subtract, R4 = R7 - (R5 x R6)
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12.6.6.2UMULL, UMAAL, UMLAL
Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result.
Syntax op{cond} RdLo, RdHi, Rn, Rm
where:
op is one of:
UMULL Unsigned Long Multiply.
UMAAL Unsigned Long Multiply with Accumulate Accumulate.
UMLAL Unsigned Long Multiply, with Accumulate.
cond is an optional condition code, see “Conditional Execution” .
RdHi, RdLo are the destination registers. For UMAAL, UMLAL and UMLAL they also hold
the accumulating value.
Rn, Rm are registers holding the first and second operands.
Operation
These instructions interpret the values from Rn and Rm as unsigned 32-bit integers.
The UMULL instruction:
Multiplies the two unsigned integers in the first and second operands.
Writes the least significant 32 bits of the result in RdLo.
Writes the most significant 32 bits of the result in RdHi.
The UMAAL instruction:
Multiplies the two unsigned 32-bit integers in the first and second operands.
Adds the unsigned 32-bit integer in RdHi to the 64-bit result of the multiplication.
Adds the unsigned 32-bit integer in RdLo to the 64-bit result of the addition.
Writes the top 32-bits of the result to RdHi.
Writes the lower 32-bits of the result to RdLo.
The UMLAL instruction:
Multiplies the two unsigned integers in the first and second operands.
Adds the 64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo.
Writes the result back to RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UMULL R0, R4, R5, R6 ; Multiplies R5 and R6, writes the top 32 bits to R4
; and the bottom 32 bits to R0
UMAAL R3, R6, R2, R7 ; Multiplies R2 and R7, adds R6, adds R3, writes the
; top 32 bits to R6, and the bottom 32 bits to R3
UMLAL R2, R1, R3, R5 ; Multiplies R5 and R3, adds R1:R2, writes to R1:R2.
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12.6.6.3SMLA and SMLAW
Signed Multiply Accumulate (halfwords).
Syntax op{XY}{cond} Rd, Rn, Rm
op{Y}{cond} Rd, Rn, Rm, Ra
where:
op is one of:
SMLA Signed Multiply Accumulate Long (halfwords).
X and Y specifies which half of the source registers Rn and Rm are used as the
first and second multiply operand.
If X is B, then the bottom halfword, bits [15:0], of Rn is used.
If X is T, then the top halfword, bits [31:16], of Rn is used.
If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used
SMLAW Signed Multiply Accumulate (word by halfword).
Y specifies which half of the source register Rm is used as the second multiply
operand.
If Y is T, then the top halfword, bits [31:16] of Rm is used.
If Y is B, then the bottom halfword, bits [15:0] of Rm is used.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register. If Rd is omitted, the destination register is Rn.
Rn, Rm are registers holding the values to be multiplied.
Ra is a register holding the value to be added or subtracted from.
Operation
The SMALBB, SMLABT, SMLATB, SMLATT instructions:
Multiplies the specified signed halfword, top or bottom, values from Rn and Rm.
Adds the value in Ra to the resulting 32-bit product.
Writes the result of the multiplication and addition in Rd.
The non-specified halfwords of the source registers are ignored.
The SMLAWB and SMLAWT instructions:
Multiply the 32-bit signed values in Rn with:
The top signed halfword of Rm, T instruction suffix.
The bottom signed halfword of Rm, B instruction suffix.
Add the 32-bit signed value in Ra to the top 32 bits of the 48-bit product
Writes the result of the multiplication and addition in Rd.
The bottom 16 bits of the 48-bit product are ignored.
If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the APSR. No overflow
can occur during the multiplication.
Restrictions
In these instructions, do not use SP and do not use PC.
Condition Flags
If an overflow is detected, the
Q
flag is set.
Examples
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SMLABB R5, R6, R4, R1 ; Multiplies bottom halfwords of R6 and R4, adds
; R1 and writes to R5
SMLATB R5, R6, R4, R1 ; Multiplies top halfword of R6 with bottom halfword
; of R4, adds R1 and writes to R5
SMLATT R5, R6, R4, R1 ; Multiplies top halfwords of R6 and R4, adds
; R1 and writes the sum to R5
SMLABT R5, R6, R4, R1 ; Multiplies bottom halfword of R6 with top halfword
; of R4, adds R1 and writes to R5
SMLABT R4, R3, R2 ; Multiplies bottom halfword of R4 with top halfword of
; R3, adds R2 and writes to R4
SMLAWB R10, R2, R5, R3 ; Multiplies R2 with bottom halfword of R5, adds
; R3 to the result and writes top 32-bits to R10
SMLAWT R10, R2, R1, R5 ; Multiplies R2 with top halfword of R1, adds R5
; and writes top 32-bits to R10.
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12.6.6.4SMLAD
Signed Multiply Accumulate Long Dual
Syntax op{X}{cond} Rd, Rn, Rm, Ra ;
where:
op is one of:
SMLAD Signed Multiply Accumulate Dual.
SMLADX Signed Multiply Accumulate Dual Reverse.
X specifies which halfword of the source register Rn is used as the multiply
operand.
If X is omitted, the multiplications are bottom × bottom and top × top.
If X is present, the multiplications are bottom × top and top × bottom.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the first operand register holding the values to be multiplied.
Rm the second operand register.
Ra is the accumulate value.
Operation
The SMLAD and SMLADX instructions regard the two operands as four halfword 16-bit values. The SMLAD and
SMLADX instructions:
If X is not present, multiply the top signed halfword value in Rn with the top signed halfword of Rm and the bottom
signed halfword values in Rn with the bottom signed halfword of Rm.
Or if X is present, multiply the top signed halfword value in Rn with the bottom signed halfword of Rm and the
bottom signed halfword values in Rn with the top signed halfword of Rm.
Add both multiplication results to the signed 32-bit value in Ra.
Writes the 32-bit signed result of the multiplication and addition to Rd.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SMLAD R10, R2, R1, R5 ; Multiplies two halfword values in R2 with
; corresponding halfwords in R1, adds R5 and
; writes to R10
SMLALDX R0, R2, R4, R6 ; Multiplies top halfword of R2 with bottom
; halfword of R4, multiplies bottom halfword of R2
; with top halfword of R4, adds R6 and writes to
; R0.
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12.6.6.5SMLAL and SMLALD
Signed Multiply Accumulate Long, Signed Multiply Accumulate Long (halfwords) and Signed Multiply Accumulate Long
Dual.
Syntax op{cond} RdLo, RdHi, Rn, Rm
op{XY}{cond} RdLo, RdHi, Rn, Rm
op{X}{cond} RdLo, RdHi, Rn, Rm
where:
op is one of:
MLAL Signed Multiply Accumulate Long.
SMLAL Signed Multiply Accumulate Long (halfwords, X and Y).
X and Y specify which halfword of the source registers Rn and Rm are used as
the first and second multiply operand:
If X is B, then the bottom halfword, bits [15:0], of Rn is used.
If X is T, then the top halfword, bits [31:16], of Rn is used.
If Y is B, then the bottom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used.
SMLALD Signed Multiply Accumulate Long Dual.
SMLALDX Signed Multiply Accumulate Long Dual Reversed.
If the X is omitted, the multiplications are bottom × bottom and top × top.
If X is present, the multiplications are bottom × top and top × bottom.
cond is an optional condition code, see “Conditional Execution” .
RdHi, RdLo are the destination registers.
RdLo is the lower 32 bits and RdHi is the upper 32 bits of the 64-bit integer.
For SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD and SMLA
LDX, they also hold the accumulating value.
Rn, Rm are registers holding the first and second operands.
Operation
The SMLAL instruction:
Multiplies the two’s complement signed word values from Rn and Rm.
Adds the 64-bit value in RdLo and RdHi to the resulting 64-bit product.
Writes the 64-bit result of the multiplication and addition in RdLo and RdHi.
The SMLALBB, SMLALBT, SMLALTB and SMLALTT instructions:
Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm.
Adds the resulting sign-extended 32-bit product to the 64-bit value in RdLo and RdHi.
Writes the 64-bit result of the multiplication and addition in RdLo and RdHi.
The non-specified halfwords of the source registers are ignored.
The SMLALD and SMLALDX instructions interpret the values from Rn and Rm as four halfword two’s complement signed
16-bit integers. These instructions:
If X is not present, multiply the top signed halfword value of Rn with the top signed halfword of Rm and the bottom
signed halfword values of Rn with the bottom signed halfword of Rm.
Or if X is present, multiply the top signed halfword value of Rn with the bottom signed halfword of Rm and the
bottom signed halfword values of Rn with the top signed halfword of Rm.
Add the two multiplication results to the signed 64-bit value in RdLo and RdHi to create the resulting 64-bit product.
Write the 64-bit product in RdLo and RdHi.
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Restrictions
In these instructions:
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SMLAL R4, R5, R3, R8 ; Multiplies R3 and R8, adds R5:R4 and writes to
; R5:R4
SMLALBT R2, R1, R6, R7 ; Multiplies bottom halfword of R6 with top
; halfword of R7, sign extends to 32-bit, adds
; R1:R2 and writes to R1:R2
SMLALTB R2, R1, R6, R7 ; Multiplies top halfword of R6 with bottom
; halfword of R7,sign extends to 32-bit, adds R1:R2
; and writes to R1:R2
SMLALD R6, R8, R5, R1 ; Multiplies top halfwords in R5 and R1 and bottom
; halfwords of R5 and R1, adds R8:R6 and writes to
; R8:R6
SMLALDX R6, R8, R5, R1 ; Multiplies top halfword in R5 with bottom
; halfword of R1, and bottom halfword of R5 with
; top halfword of R1, adds R8:R6 and writes to
; R8:R6.
12.6.6.6SMLSD and SMLSLD
Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual
Syntax op{X}{cond} Rd, Rn, Rm, Ra
where:
op is one of:
SMLSD Signed Multiply Subtract Dual.
SMLSDX Signed Multiply Subtract Dual Reversed.
SMLSLD Signed Multiply Subtract Long Dual.
SMLSLDX Signed Multiply Subtract Long Dual Reversed.
SMLAW Signed Multiply Accumulate (word by halfword).
If X is present, the multiplications are bottom × top and top × bottom.
If the X is omitted, the multiplications are bottom × bottom and top × top.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn, Rm are registers holding the first and second operands.
Ra is the register holding the accumulate value.
Operation
The SMLSD instruction interprets the values from the first and second operands as four signed halfwords. This
instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit halfword multiplications.
Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
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Adds the signed accumulate value to the result of the subtraction.
Writes the result of the addition to the destination register.
The SMLSLD instruction interprets the values from Rn and Rm as four signed halfwords.
This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit halfword multiplications.
Subtracts the result of the upper halfword multiplication from the result of the lower halfword multiplication.
Adds the 64-bit value in RdHi and RdLo to the result of the subtraction.
Writes the 64-bit result of the addition to the RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or
subtraction.
For the Thumb instruction set, these instructions do not affect the condition code flags.
Examples
SMLSD R0, R4, R5, R6 ; Multiplies bottom halfword of R4 with bottom
; halfword of R5, multiplies top halfword of R4
; with top halfword of R5, subtracts second from
; first, adds R6, writes to R0
SMLSDX R1, R3, R2, R0 ; Multiplies bottom halfword of R3 with top
; halfword of R2, multiplies top halfword of R3
; with bottom halfword of R2, subtracts second from
; first, adds R0, writes to R1
SMLSLD R3, R6, R2, R7 ; Multiplies bottom halfword of R6 with bottom
; halfword of R2, multiplies top halfword of R6
; with top halfword of R2, subtracts second from
; first, adds R6:R3, writes to R6:R3
SMLSLDX R3, R6, R2, R7 ; Multiplies bottom halfword of R6 with top
; halfword of R2, multiplies top halfword of R6
; with bottom halfword of R2, subtracts second from
; first, adds R6:R3, writes to R6:R3.
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12.6.6.7SMMLA and SMMLS
Signed Most Significant Word Multiply Accumulate and Signed Most Significant Word Multiply Subtract
Syntax op{R}{cond} Rd, Rn, Rm, Ra
where:
op is one of:
SMMLA Signed Most Significant Word Multiply Accumulate.
SMMLS Signed Most Significant Word Multiply Subtract.
If the X is omitted, the multiplications are bottom × bottom and top × top.
R is a rounding error flag. If R is specified, the result is rounded instead of being
truncated. In this case the constant 0x80000000 is added to the product before
the high word is extracted.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn, Rm are registers holding the first and second multiply operands.
Ra is the register holding the accumulate value.
Operation
The SMMLA instruction interprets the values from Rn and Rm as signed 32-bit words.
The SMMLA instruction:
Multiplies the values in Rn and Rm.
Optionally rounds the result by adding 0x80000000.
Extracts the most significant 32 bits of the result.
Adds the value of Ra to the signed extracted value.
Writes the result of the addition in Rd.
The SMMLS instruction interprets the values from Rn and Rm as signed 32-bit words.
The SMMLS instruction:
Multiplies the values in Rn and Rm.
Optionally rounds the result by adding 0x80000000.
Extracts the most significant 32 bits of the result.
Subtracts the extracted value of the result from the value in Ra.
Writes the result of the subtraction in Rd.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the condition code flags.
Examples
SMMLA R0, R4, R5, R6 ; Multiplies R4 and R5, extracts top 32 bits, adds
; R6, truncates and writes to R0
SMMLAR R6, R2, R1, R4 ; Multiplies R2 and R1, extracts top 32 bits, adds
; R4, rounds and writes to R6
SMMLSR R3, R6, R2, R7 ; Multiplies R6 and R2, extracts top 32 bits,
; subtracts R7, rounds and writes to R3
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SMMLS R4, R5, R3, R8 ; Multiplies R5 and R3, extracts top 32 bits,
; subtracts R8, truncates and writes to R4.
12.6.6.8SMMUL
Signed Most Significant Word Multiply
Syntax op{R}{cond} Rd, Rn, Rm
where:
op is one of:
SMMUL Signed Most Significant Word Multiply.
R is a rounding error flag. If R is specified, the result is rounded instead of being
truncated. In this case the constant 0x80000000 is added to the product before
the high word is extracted.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn, Rm are registers holding the first and second operands.
Operation
The SMMUL instruction interprets the values from Rn and Rm as two’s complement 32-bit signed integers. The SMMUL
instruction:
Multiplies the values from Rn and Rm.
Optionally rounds the result, otherwise truncates the result.
Writes the most significant signed 32 bits of the result in Rd.
Restrictions
In this instruction:
do not use SP and do not use PC.
Condition Flags
This instruction does not affect the condition code flags.
Examples
SMULL R0, R4, R5 ; Multiplies R4 and R5, truncates top 32 bits
; and writes to R0
SMULLR R6, R2 ; Multiplies R6 and R2, rounds the top 32 bits
; and writes to R6.
12.6.6.9SMUAD and SMUSD
Signed Dual Multiply Add and Signed Dual Multiply Subtract
Syntax op{X}{cond} Rd, Rn, Rm
where:
op is one of:
SMUAD Signed Dual Multiply Add.
SMUADX Signed Dual Multiply Add Reversed.
SMUSD Signed Dual Multiply Subtract.
SMUSDX Signed Dual Multiply Subtract Reversed.
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If X is present, the multiplications are bottom × top and top × bottom.
If the X is omitted, the multiplications are bottom × bottom and top × top.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn, Rm are registers holding the first and second operands.
Operation
The SMUAD instruction interprets the values from the first and second operands as two signed halfwords in each
operand. This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit multiplications.
Adds the two multiplication results together.
Writes the result of the addition to the destination register.
The SMUSD instruction interprets the values from the first and second operands as two’s complement signed integers.
This instruction:
Optionally rotates the halfwords of the second operand.
Performs two signed 16 × 16-bit multiplications.
Subtracts the result of the top halfword multiplication from the result of the bottom halfword multiplication.
Writes the result of the subtraction to the destination register.
Restrictions
In these instructions:
Do not use SP and do not use PC.
Condition Flags
Sets the Q flag if the addition overflows. The multiplications cannot overflow.
Examples
SMUAD R0, R4, R5 ; Multiplies bottom halfword of R4 with the bottom
; halfword of R5, adds multiplication of top halfword
; of R4 with top halfword of R5, writes to R0
SMUADX R3, R7, R4 ; Multiplies bottom halfword of R7 with top halfword
; of R4, adds multiplication of top halfword of R7
; with bottom halfword of R4, writes to R3
SMUSD R3, R6, R2 ; Multiplies bottom halfword of R4 with bottom halfword
; of R6, subtracts multiplication of top halfword of R6
; with top halfword of R3, writes to R3
SMUSDX R4, R5, R3 ; Multiplies bottom halfword of R5 with top halfword of
; R3, subtracts multiplication of top halfword of R5
; with bottom halfword of R3, writes to R4.
12.6.6.10SMUL and SMULW
Signed Multiply (halfwords) and Signed Multiply (word by halfword)
Syntax op{XY}{cond} Rd,Rn, Rm
op{Y}{cond} Rd. Rn, Rm
For SMULXY only:
op is one of:
SMUL{XY} Signed Multiply (halfwords).
X and Y specify which halfword of the source registers Rn and Rm is used as
the first and second multiply operand.
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If X is B, then the bottom halfword, bits [15:0] of Rn is used.
If X is T, then the top halfword, bits [31:16] of Rn is used.If Y is B, then the bot
tom halfword, bits [15:0], of Rm is used.
If Y is T, then the top halfword, bits [31:16], of Rm is used.
SMULW{Y} Signed Multiply (word by halfword).
Y specifies which halfword of the source register Rm is used as the second mul
tiply operand.
If Y is B, then the bottom halfword (bits [15:0]) of Rm is used.
If Y is T, then the top halfword (bits [31:16]) of Rm is used.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn, Rm are registers holding the first and second operands.
Operation
The SMULBB, SMULTB, SMULBT and SMULTT instructions interprets the values from Rn and Rm as four signed 16-bit
integers. These instructions:
Multiplies the specified signed halfword, Top or Bottom, values from Rn and Rm.
Writes the 32-bit result of the multiplication in Rd.
The SMULWT and SMULWB instructions interprets the values from Rn as a 32-bit signed integer and Rm as two
halfword 16-bit signed integers. These instructions:
Multiplies the first operand and the top, T suffix, or the bottom, B suffix, halfword of the second operand.
Writes the signed most significant 32 bits of the 48-bit result in the destination register.
Restrictions
In these instructions:
Do not use SP and do not use PC.
RdHi and RdLo must be different registers.
Examples
SMULBT R0, R4, R5 ; Multiplies the bottom halfword of R4 with the
; top halfword of R5, multiplies results and
; writes to R0
SMULBB R0, R4, R5 ; Multiplies the bottom halfword of R4 with the
; bottom halfword of R5, multiplies results and
; writes to R0
SMULTT R0, R4, R5 ; Multiplies the top halfword of R4 with the top
; halfword of R5, multiplies results and writes
; to R0
SMULTB R0, R4, R5 ; Multiplies the top halfword of R4 with the
; bottom halfword of R5, multiplies results and
; and writes to R0
SMULWT R4, R5, R3 ; Multiplies R5 with the top halfword of R3,
; extracts top 32 bits and writes to R4
SMULWB R4, R5, R3 ; Multiplies R5 with the bottom halfword of R3,
; extracts top 32 bits and writes to R4.
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12.6.6.11UMULL, UMLAL, SMULL, and SMLAL
Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and producing a 64-bit result.
Syntax op{cond} RdLo, RdHi, Rn, Rm
where:
op is one of:
UMULL Unsigned Long Multiply.
UMLAL Unsigned Long Multiply, with Accumulate.
SMULL Signed Long Multiply.
SMLAL Signed Long Multiply, with Accumulate.
cond is an optional condition code, see “Conditional Execution” .
RdHi, RdLo are the destination registers. For UMLAL and SMLAL they also hold the accu
mulating value.
Rn, Rm are registers holding the operands.
Operation
The UMULL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers and
places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.
The UMLAL instruction interprets the values from Rn and Rm as unsigned integers. It multiplies these integers, adds the
64-bit result to the 64-bit unsigned integer contained in RdHi and RdLo, and writes the result back to RdHi and RdLo.
The SMULL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these
integers and places the least significant 32 bits of the result in RdLo, and the most significant 32 bits of the result in RdHi.
The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these
integers, adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo, a nd writ es the re sult ba ck to
RdHi and RdLo.
Restrictions
In these instructions:
Do not use SP and do not use PC
RdHi and RdLo must be different registers.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UMULL R0, R4, R5, R6 ; Unsigned (R4,R0) = R5 x R6
SMLAL R4, R5, R3, R8 ; Signed (R5,R4) = (R5,R4) + R3 x R8
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12.6.6.12SDIV and UDIV
Signed Divide and Unsigned Divide.
Syntax SDIV{cond} {Rd,} Rn, Rm
UDIV{cond} {Rd,} Rn, Rm
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register. If Rd is omitted, the destination register is Rn.
Rn is the register holding the value to be divided.
Rm is a register holding the divisor.
Operation
SDIV performs a signed integer division of the value in Rn by the value in Rm.
UDIV performs an unsigned integer division of the value in Rn by the value in Rm.
For both instructions, if the value in Rn is not divisible by the value in Rm, the result is rounded towards zero.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not change the flags.
Examples
SDIV R0, R2, R4 ; Signed divide, R0 = R2/R4
UDIV R8, R8, R1 ; Unsigned divide, R8 = R8/R1
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12.6.7 Saturating Instructions
The table below shows the saturating instructions:
For signed n-bit saturation, this means that:
If the value to be saturated is less than -2n-1, the result returned is -2n-1
If the value to be saturated is greater than 2n-1-1, the result returned is 2n-1-1
Otherwise, the result returned is the same as the value to be saturated.
For unsigned n-bit saturation, this means that:
If the value to be saturated is less than 0, the result returned is 0
If the value to be saturated is greater than 2n-1, the result returned is 2n-1
Otherwise, the result returned is the same as the value to be saturated.
If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the instruction
sets the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. To clear the Q flag to 0, the
MSR
instruction
must be used; see “MSR” .
To read the state of the Q flag, the
MRS
instruction must be used; see “MRS” .
Table 12-22. Saturating Instructions
Mnemonic Description
SSAT Signed Saturate
SSAT16 Signed Saturate Halfword
USAT Unsigned Saturate
USAT16 Unsigned Saturate Halfword
QADD Saturating Add
QSUB Saturating Subtract
QSUB16 Saturating Subtract 16
QASX Saturating Add and Subtract with Exchange
QSAX Saturating Subtract and Add with Exchange
QDADD Saturating Double and Add
QDSUB Saturating Double and Subtract
UQADD16 Unsigned Saturating Add 16
UQADD8 Unsigned Saturating Add 8
UQASX Unsigned Saturating Add and Subtract with Exchange
UQSAX Unsigned Saturating Subtract and Add with Exchange
UQSUB16 Unsigned Saturating Subtract 16
UQSUB8 Unsigned Saturating Subtract 8
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12.6.7.1SSAT and USAT
Signed Saturate and Unsigned Saturate to any bit position, with optional shift before saturating.
Syntax op{cond} Rd, #n, Rm {, shift #s}
where:
op is one of:
SSAT Saturates a signed value to a signed range.
USAT Saturates a signed value to an unsigned range.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
n specifies the bit position to saturate to:
n ranges from 1 n ranges from 0 to 31 for USAT.
to 32 for SSAT
Rm is the register containing the value to saturate.
shift #s is an optional shift applied to Rm before saturating. It must be one of the
following:
ASR #s where s is in the range 1 to 31.
LSL #s where s is in the range 0 to 31.
Operation
These instructions saturate to a signed or unsigned n-bit value.
The
SSAT
instruction applies the specified shift, then saturates to the signed range -2n–1 £ x £ 2n–1-1.
The
USAT
instruction applies the specified shift, then saturates to the unsigned range 0 £ x £ 2n-1.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
Examples
SSAT R7, #16, R7, LSL #4 ; Logical shift left value in R7 by 4, then
; saturate it as a signed 16-bit value and
; write it back to R7
USATNE R0, #7, R5 ; Conditionally saturate value in R5 as an
; unsigned 7 bit value and write it to R0.
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12.6.7.2SSAT16 and USAT16
Signed Saturate and Unsigned Saturate to any bit position for two halfwords.
Syntax op{cond} Rd, #n, Rm
where:
op is one of:
SSAT16 Saturates a signed halfword value to a signed range.
USAT16 Saturates a signed halfword value to an unsigned range.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
n specifies the bit position to saturate to:
n ranges from 1 n ranges from 0 to 15 for USAT.
to 16 for SSAT
Rm is the register containing the value to saturate.
Operation
The SSAT16 instruction:
Saturates two signed 16-bit halfword values of the register with the value to saturate from selected by the bit position in n.
Writes the results as two signed 16-bit halfwords to the destination register.
The USAT16 instruction:
Saturates two unsigned 16-bit halfword values of the register with the value to saturate from selected by the bit position
in n.
Writes the results as two unsigned halfwords in the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
Examples
SSAT16 R7, #9, R2 ; Saturates the top and bottom highwords of R2
; as 9-bit values, writes to corresponding halfword
; of R7
USAT16NE R0, #13, R5 ; Conditionally saturates the top and bottom
; halfwords of R5 as 13-bit values, writes to
; corresponding halfword of R0.
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12.6.7.3QADD and QSUB
Saturating Add and Saturating Subtract, signed.
Syntax op{cond} {Rd}, Rn, Rm
op{cond} {Rd}, Rn, Rm
where:
op is one of:
QADD Saturating 32-bit add.
QADD8 Saturating four 8-bit integer additions.
QADD16 Saturating two 16-bit integer additions.
QSUB Saturating 32-bit subtraction.
QSUB8 Saturating four 8-bit integer subtraction.
QSUB16 Saturating two 16-bit integer subtraction.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn, Rm are registers holding the first and second operands.
Operation
These instructions add or subtract two, four or eight values from the first and second operands and then writes a signed
saturated value in the destination register.
The QADD and QSUB instructions apply the specified add or subtract, and then saturate the result to the signed range -
2n–1 £ x £ 2n–1-1, where x is given by the number of bits applied in the instruction, 32, 16 or 8.
If the returned result is different from the value to be saturated, it is called saturation. If saturation occurs, the QADD and
QSUB instructions set the Q flag to 1 in the APSR. Otherwise, it leaves the Q flag unchanged. The 8-bit and 16-bit QADD
and QSUB instructions always leave the Q flag unchanged.
To clear the Q flag to 0, the MSR instruction must be used; see “MSR” .
To read the state of the Q flag, the MRS instruction must be used; see “MRS” .
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.
Examples
QADD16 R7, R4, R2 ; Adds halfwords of R4 with corresponding halfword of
; R2, saturates to 16 bits and writes to
; corresponding halfword of R7
QADD8 R3, R1, R6 ; Adds bytes of R1 to the corresponding bytes of R6,
; saturates to 8 bits and writes to corresponding
; byte of R3
QSUB16 R4, R2, R3 ; Subtracts halfwords of R3 from corresponding
; halfword of R2, saturates to 16 bits, writes to
; corresponding halfword of R4
QSUB8 R4, R2, R5 ; Subtracts bytes of R5 from the corresponding byte
; in R2, saturates to 8 bits, writes to corresponding
; byte of R4.
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12.6.7.4QASX and QSAX
Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, signed.
Syntax op{cond} {Rd}, Rm, Rn
where:
op is one of:
QASX Add and Subtract with Exchange and Saturate.
QSAX Subtract and Add with Exchange and Saturate.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn, Rm are registers holding the first and second operands.
Operation
The QASX instruction:
1. Adds the top halfword of the source operand with the bottom halfword of the second operand.
2. Subtracts the top halfword of the second operand from the bottom highword of the first operand.
3. Saturates the result of the subtraction and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where x
equals 16, to the bottom halfword of the destination register.
4. Saturates the results of the sum and writes a 16-bit signed integer in the range
–215 ≤ x ≤ 215 – 1, where x equals 16, to the top halfword of the destination register.
The QSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2. Adds the bottom halfword of the source operand with the top halfword of the second operand.
3. Saturates the results of the sum and writes a 16-bit signed integer in the range
–215 ≤ x ≤ 215 – 1, where
x
equals 16, to the bottom halfword of the destination register.
4. Saturates the result of the subtraction and writes a 16-bit signed integer in the range –215 ≤ x ≤ 215 – 1, where
x
equals 16, to the top halfword of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
QASX R7, R4, R2 ; Adds top halfword of R4 to bottom halfword of R2,
; saturates to 16 bits, writes to top halfword of R7
; Subtracts top highword of R2 from bottom halfword of
; R4, saturates to 16 bits and writes to bottom halfword
; of R7
QSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of
; R3, saturates to 16 bits, writes to top halfword of R0
; Adds bottom halfword of R3 to top halfword of R5,
; saturates to 16 bits, writes to bottom halfword of R0.
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12.6.7.5QDADD and QDSUB
Saturating Double and Add and Saturating Double and Subtract, signed.
Syntax op{cond} {Rd}, Rm, Rn
where:
op is one of:
QDADD Saturating Double and Add.
QDSUB Saturating Double and Subtract.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rm, Rn are registers holding the first and second operands.
Operation
The QDADD instruction:
Doubles the second operand value.
Adds the result of the doubling to the signed saturated value in the first operand.
Writes the result to the destination register.
The QDSUB instruction:
Doubles the second operand value.
Subtracts the doubled value from the signed saturated value in the first operand.
Writes the result to the destination register.
Both the doubling and the addition or subtraction have their results saturated to the 32-bit signed integer range –231 ≤ x ≤
231– 1. If saturation occurs in either operation, it sets the Q flag in the APSR.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
If saturation occurs, these instructions set the Q flag to 1.
Examples
QDADD R7, R4, R2 ; Doubles and saturates R4 to 32 bits, adds R2,
; saturates to 32 bits, writes to R7
QDSUB R0, R3, R5 ; Subtracts R3 doubled and saturated to 32 bits
; from R5, saturates to 32 bits, writes to R0.
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12.6.7.6UQASX and UQSAX
Saturating Add and Subtract with Exchange and Saturating Subtract and Add with Exchange, unsigned.
Syntax op{cond} {Rd}, Rm, Rn
where:
type is one of:
UQASX Add and Subtract with Exchange and Saturate.
UQSAX Subtract and Add with Exchange and Saturate.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn, Rm are registers holding the first and second operands.
Operation
The UQASX instruction:
1. Adds the bottom halfword of the source operand with the top halfword of the second operand.
2. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
3. Saturates the results of the sum and writes a 16-bit unsigned integer in the range
0 ≤ x ≤ 216 – 1, where x equals 16, to the top halfword of the destination register.
4. Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where x
equals 16, to the bottom halfword of the destination register.
The UQSAX instruction:
1. Subtracts the bottom halfword of the second operand from the top highword of the first operand.
2. Adds the bottom halfword of the first operand with the top halfword of the second operand.
3. Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where
x
equals 16, to the top halfword of the destination register.
4. Saturates the results of the addition and writes a 16-bit unsigned integer in the range 0 ≤ x ≤ 216 – 1, where
x
equals
16, to the bottom halfword of the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UQASX R7, R4, R2 ; Adds top halfword of R4 with bottom halfword of R2,
; saturates to 16 bits, writes to top halfword of R7
; Subtracts top halfword of R2 from bottom halfword of
; R4, saturates to 16 bits, writes to bottom halfword of R7
UQSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of R3,
; saturates to 16 bits, writes to top halfword of R0
; Adds bottom halfword of R4 to top halfword of R5
; saturates to 16 bits, writes to bottom halfword of R0.
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12.6.7.7UQADD and UQSUB
Saturating Add and Saturating Subtract Unsigned.
Syntax op{cond} {Rd}, Rn, Rm
op{cond} {Rd}, Rn, Rm
where:
op is one of:
UQADD8 Saturating four unsigned 8-bit integer additions.
UQADD16 Saturating two unsigned 16-bit integer additions.
UDSUB8 Saturating four unsigned 8-bit integer subtractions.
UQSUB16 Saturating two unsigned 16-bit integer subtractions.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn, Rm are registers holding the first and second operands.
Operation
These instructions add or subtract two or four values and then writes an unsigned saturated value in the destination
register.
The UQADD16 instruction:
Adds the respective top and bottom halfwords of the first and second operands.
Saturates the result of the additions for each halfword in the destination register to the unsigned range 0 £ x £ 216-
1, where x is 16.
The UQADD8 instruction:
Adds each respective byte of the first and second operands.
Saturates the result of the addition for each byte in the destination register to the unsigned range 0 £ x £ 28-1,
where x is 8.
The UQSUB16 instruction:
Subtracts both halfwords of the second operand from the respective halfwords of the first operand.
Saturates the result of the differences in the destination register to the unsigned range 0 £ x £ 216-1, where x is 16.
The UQSUB8 instructions:
Subtracts the respective bytes of the second operand from the respective bytes of the first operand.
Saturates the results of the differences for each byte in the destination register to the unsigned range 0 £ x £ 28-1,
where x is 8.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the condition code flags.
Examples
UQADD16 R7, R4, R2 ; Adds halfwords in R4 to corresponding halfword in R2,
; saturates to 16 bits, writes to corresponding halfword of R7
UQADD8 R4, R2, R5 ; Adds bytes of R2 to corresponding byte of R5, saturates
; to 8 bits, writes to corresponding bytes of R4
UQSUB16 R6, R3, R0 ; Subtracts halfwords in R0 from corresponding halfword
; in R3, saturates to 16 bits, writes to corresponding
; halfword in R6
UQSUB8 R1, R5, R6 ; Subtracts bytes in R6 from corresponding byte of R5,
; saturates to 8 bits, writes to corresponding byte of R1.
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12.6.8 Packing and Unpacking Instructions
The table below shows the instructions that operate on packing and unpacking data:
Table 12-23. Packing and Unpacking Instructions
Mnemonic Description
PKH Pack Halfword
SXTAB Extend 8 bits to 32 and add
SXTAB16 Dual extend 8 bits to 16 and add
SXTAH Extend 16 bits to 32 and add
SXTB Sign extend a byte
SXTB16 Dual extend 8 bits to 16 and add
SXTH Sign extend a halfword
UXTAB Extend 8 bits to 32 and add
UXTAB16 Dual extend 8 bits to 16 and add
UXTAH Extend 16 bits to 32 and add
UXTB Zero extend a byte
UXTB16 Dual zero extend 8 bits to 16 and add
UXTH Zero extend a halfword
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12.6.8.1PKHBT and PKHTB
Pack Halfword
Syntax op{cond} {Rd}, Rn, Rm {, LSL #imm}
op{cond} {Rd}, Rn, Rm {, ASR #imm}
where:
op is one of:
PKHBT Pack Halfword, bottom and top with shift.
PKHTB Pack Halfword, top and bottom with shift.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the first operand register
Rm is the second operand register holding the value to be optionally shifted.
imm is the shift length. The type of shift length depends on the instruction:
For PKHBT
LSL a left shift with a shift length from 1 to 31, 0 means no shift.
For PKHTB
ASR an arithmetic shift right with a shift length from 1 to 32,
a shift of 32-bits is encoded as 0b00000.
Operation
The PKHBT instruction:
1. Writes the value of the bottom halfword of the first operand to the bottom halfword of the destination register.
2. If shifted, the shifted value of the second operand is written to the top halfword of the destination register.
The PKHTB instruction:
1. Writes the value of the top halfword of the first operand to the top halfword of the destination register.
2. If shifted, the shifted value of the second operand is written to the bottom halfword of the destination register.
Restrictions
Rd
must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
PKHBT R3, R4, R5 LSL #0 ; Writes bottom halfword of R4 to bottom halfword of
; R3, writes top halfword of R5, unshifted, to top
; halfword of R3
PKHTB R4, R0, R2 ASR #1 ; Writes R2 shifted right by 1 bit to bottom halfword
; of R4, and writes top halfword of R0 to top
; halfword of R4.
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12.6.8.2SXT and UXT
Sign extend and Zero extend.
Syntax op{cond} {Rd,} Rm {, ROR #n}
op{cond} {Rd}, Rm {, ROR #n}
where:
op is one of:
SXTB Sign extends an 8-bit value to a 32-bit value.
SXTH Sign extends a 16-bit value to a 32-bit value.
SXTB16 Sign extends two 8-bit values to two 16-bit values.
UXTB Zero extends an 8-bit value to a 32-bit value.
UXTH Zero extends a 16-bit value to a 32-bit value.
UXTB16 Zero extends two 8-bit values to two 16-bit values.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rm is the register holding the value to extend.
ROR #n is one of:
ROR #8 Value from Rm is rotated right 8 bits.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2. Extract bits from the resulting value:
SXTB extracts bits[7:0] and sign extends to 32 bits.
UXTB extracts bits[7:0] and zero extends to 32 bits.
SXTH extracts bits[15:0] and sign extends to 32 bits.
UXTH extracts bits[15:0] and zero extends to 32 bits.
SXTB16 extracts bits[7:0] and sign extends to 16 bits,
and extracts bits [23:16] and sign extends to 16 bits.
UXTB16 extracts bits[7:0] and zero extends to 16 bits,
and extracts bits [23:16] and zero extends to 16 bits.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
SXTH R4, R6, ROR #16 ; Rotates R6 right by 16 bits, obtains bottom halfword of
; of result, sign extends to 32 bits and writes to R4
UXTB R3, R10 ; Extracts lowest byte of value in R10, zero extends, and
; writes to R3.
12.6.8.3SXTA and UXTA
Signed and Unsigned Extend and Add
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Syntax op{cond} {Rd,} Rn, Rm {, ROR #n}
op{cond} {Rd,} Rn, Rm {, ROR #n}
where:
op is one of:
SXTAB Sign extends an 8-bit value to a 32-bit value and add.
SXTAH Sign extends a 16-bit value to a 32-bit value and add.
SXTAB16 Sign extends two 8-bit values to two 16-bit values and add.
UXTAB Zero extends an 8-bit value to a 32-bit value and add.
UXTAH Zero extends a 16-bit value to a 32-bit value and add.
UXTAB16 Zero extends two 8-bit values to two 16-bit values and add.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the first operand register.
Rm is the register holding the value to rotate and extend.
ROR #n is one of:
ROR #8 Value from Rm is rotated right 8 bits.
ROR #16 Value from Rm is rotated right 16 bits.
ROR #24 Value from Rm is rotated right 24 bits.
If ROR #n is omitted, no rotation is performed.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2. Extract bits from the resulting value:
SXTAB extracts bits[7:0] from Rm and sign extends to 32 bits.
UXTAB extracts bits[7:0] from Rm and zero extends to 32 bits.
SXTAH extracts bits[15:0] from Rm and sign extends to 32 bits.
UXTAH extracts bits[15:0] from Rm and zero extends to 32 bits.
SXTAB16 extracts bits[7:0] from Rm and sign extends to 16 bits,
and extracts bits [23:16] from Rm and sign extends to 16 bits.
UXTAB16 extracts bits[7:0] from Rm and zero extends to 16 bits,
and extracts bits [23:16] from Rm and zero extends to 16 bits.
3. Adds the signed or zero extended value to the word or corresponding halfword of Rn and writes the result in Rd.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
SXTAH R4, R8, R6, ROR #16 ; Rotates R6 right by 16 bits, obtains bottom
; halfword, sign extends to 32 bits, adds
; R8,and writes to R4
UXTAB R3, R4, R10 ; Extracts bottom byte of R10 and zero extends
; to 32 bits, adds R4, and writes to R3.
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12.6.9 Bitfield Instructions
The table below shows the instructions that operate on adjacent sets of bits in registers or bitfields:
Table 12-24. Packing and Unpacking Instructions
Mnemonic Description
BFC Bit Field Clear
BFI Bit Field Insert
SBFX Signed Bit Field Extract
SXTB Sign extend a byte
SXTH Sign extend a halfword
UBFX Unsigned Bit Field Extract
UXTB Zero extend a byte
UXTH Zero extend a halfword
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12.6.9.1BFC and BFI
Bit Field Clear and Bit Field Insert.
Syntax BFC{cond} Rd, #lsb, #width
BFI{cond} Rd, Rn, #lsb, #width
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the source register.
lsb is the position of the least significant bit of the bitfield. lsb must be in the range
0 to 31.
width is the width of the bitfield and must be in the range 1 to 32-lsb.
Operation
BFC clears a bitfield in a register. It clears width bits in Rd, s tarting at the low bi t position lsb. Other bits in Rd are
unchanged.
BFI copies a bitfield into one register from another register. It replaces width bits in Rd starting at the low bit position lsb,
with width bits from Rn starting at bit[0]. Other bits in Rd are unchanged.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
BFC R4, #8, #12 ; Clear bit 8 to bit 19 (12 bits) of R4 to 0
BFI R9, R2, #8, #12 ; Replace bit 8 to bit 19 (12 bits) of R9 with
; bit 0 to bit 11 from R2.
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12.6.9.2SBFX and UBFX
Signed Bit Field Extract and Unsigned Bit Field Extract.
Syntax SBFX{cond} Rd, Rn, #lsb, #width
UBFX{cond} Rd, Rn, #lsb, #width
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rn is the source register.
lsb is the position of the least significant bit of the bitfield. lsb must be in the range
0 to 31.
width is the width of the bitfield and must be in the range 1 to 32-lsb.
Operation
SBFX extracts a bitfield from one register, sign extends it to 32 bits, and writes the result to the destination register.
UBFX extracts a bitfield from one register, zero extends it to 32 bits, and writes the result to the destination register.
Restrictions
Do not use SP and do not use PC
.
Condition Flags
These instructions do not affect the flags.
Examples
SBFX R0, R1, #20, #4 ; Extract bit 20 to bit 23 (4 bits) from R1 and sign
; extend to 32 bits and then write the result to R0.
UBFX R8, R11, #9, #10 ; Extract bit 9 to bit 18 (10 bits) from R11 and zero
; extend to 32 bits and then write the result to R8.
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12.6.9.3SXT and UXT
Sign extend and Zero extend.
Syntax SXTextend{cond} {Rd,} Rm {, ROR #n}
UXTextend{cond} {Rd}, Rm {, ROR #n}
where:
extend is one of:
B Extends an 8-bit value to a 32-bit value.
H Extends a 16-bit value to a 32-bit value.
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
Rm is the register holding the value to extend.
ROR #n is one of:
ROR #8 Value from Rm is rotated right 8 bits.
ROR #16 Value from Rm is rotated right 16 bits.
ROR #24 Value from Rm is rotated right 24 bits.
If ROR #n is omitted, no rotation is performed.
Operation
These instructions do the following:
1. Rotate the value from Rm right by 0, 8, 16 or 24 bits.
2. Extract bits from the resulting value:
SXTB extracts bits[7:0] and sign extends to 32 bits.
UXTB extracts bits[7:0] and zero extends to 32 bits.
SXTH extracts bits[15:0] and sign extends to 32 bits.
UXTH extracts bits[15:0] and zero extends to 32 bits.
Restrictions
Do not use SP and do not use PC.
Condition Flags
These instructions do not affect the flags.
Examples
SXTH R4, R6, ROR #16 ; Rotate R6 right by 16 bits, then obtain the lower
; halfword of the result and then sign extend to
; 32 bits and write the result to R4.
UXTB R3, R10 ; Extract lowest byte of the value in R10 and zero
; extend it, and write the result to R3.
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12.6.10 Branch and Control Instructions
The table below shows the branch and control instructions:
Table 12-25. Branch and Control Instructions
Mnemonic Description
B Branch
BL Branch with Link
BLX Branch indirect with Link
BX Branch indirect
CBNZ Compare and Branch if Non Zero
CBZ Compare and Branch if Zero
IT If-Then
TBB Table Branch Byte
TBH Table Branch Halfword
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12.6.10.1B, BL, BX, and BLX
Branch instructions.
Syntax B{cond} label
BL{cond} label
BX{cond} Rm
BLX{cond} Rm
where:
B is branch (immediate).
BL is branch with link (immediate).
BX is branch indirect (register).
BLX is branch indirect with link (register).
cond is an optional condition code, see “Conditional Execution” .
label is a PC-relative expression. See “PC-relative Expressions” .
Rm is a register that indicates an address to branch to. Bit[0] of the value in Rm
must be 1, but the address to branch to is created by changing bit[0] to 0.
Operation
All these instructions cause a branch to label, or to the address indicated in Rm. In addition:
The BL and BLX instructions write the address of the next instruction to LR (the link register, R14).
The BX and BLX instructions result in a UsageFault exception if bit[0] of Rm is 0.
Bcond label is the only conditional instruction that can be either inside or outside an IT block. All other branch instructions
must be conditional inside an IT block, and must be unconditional outside the IT block, see “IT” .
The table below shows the ranges for the various branch instructions.
The .W suffix might be used to get the maximum branch range. See “Instruction Width Selection” .
Restrictions
The restrictions are:
Do not use PC in the BLX instruction
For BX and BLX, bit[0] of Rm must be 1 for correct execution but a branch occurs to the target address created by
changing bit[0] to 0
When any of these instructions is inside an IT block, it must be the last instruction of the IT block.
B
cond is the only conditional instruction that is not required to be inside an IT block. However, it has a longer branch
range when it is inside an IT block.
Condition Flags
Table 12-26. Branch Ranges
Instruction Branch Range
B label −16 MB to +16 MB
Bcond label
(outside IT block) −1 MB to +1 MB
Bcond label
(inside IT block) −16 MB to +16 MB
BL{cond} label −16 MB to +16 MB
BX{cond} Rm Any value in register
BLX{cond} Rm Any value in register
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These instructions do not change the flags.
Examples
B loopA ; Branch to loopA
BLE ng ; Conditionally branch to label ng
B.W target ; Branch to target within 16MB range
BEQ target ; Conditionally branch to target
BEQ.W target ; Conditionally branch to target within 1MB
BL funC ; Branch with link (Call) to function funC, return address
; stored in LR
BX LR ; Return from function call
BXNE R0 ; Conditionally branch to address stored in R0
BLX R0 ; Branch with link and exchange (Call) to a address stored in R0.
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12.6.10.2CBZ and CBNZ
Compare and Branch on Zero, Compare and Branch on Non-Zero.
Syntax CBZ Rn, label
CBNZ Rn, label
where:
Rn is the register holding the operand.
label is the branch destination.
Operation
Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of instructions.
CBZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP Rn, #0
BEQ label
CBNZ Rn, label does not change condition flags but is otherwise equivalent to:
CMP Rn, #0
BNE label
Restrictions
The restrictions are:
Rn must be in the range of R0 to R7
The branch destination must be within 4 to 130 bytes after the instruction
These instructions must not be used inside an IT block.
Condition Flags
These instructions do not change the flags.
Examples
CBZ R5, target ; Forward branch if R5 is zero
CBNZ R0, target ; Forward branch if R0 is not zero
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12.6.10.3IT
If-Then condition instruction.
Syntax IT{x{y{z}}} cond
where:
x specifies the condition switch for the second instruction in the IT block.
y specifies the condition switch for the third instruction in the IT block.
z specifies the condition switch for the fourth instruction in the IT block.
cond specifies the condition for the first instruction in the IT block.
The condition switch for the second, third and fourth instruction in the IT block can be either:
T Then. Applies the condition cond to the instruction.
E Else. Applies the inverse condition of cond to the instruction.
It is possible to use AL (the always condition) for cond in an IT instruction. If this is done, all of the instructions in the IT
block must be unconditional, and each of x, y, and z must be T or omitted but not E.
Operation
The IT instruction makes up to four following instructions conditional. The conditions can be all the same, or some of
them can be the logical inverse of the others. The conditional instructions following the IT instruction form the IT block.
The instructions in the IT block, including any branches, must specify the condition in the {cond} part of their syntax.
The assembler might be able to generate the required IT instructions for conditional instructions automatically, so that the
user does not have to write them. See the assembler documentation for details.
A BKPT instruction in an IT block is always executed, even if its condition fails.
Exceptions can be taken between an IT instruction and the corresponding IT block, or within an IT block. Such an
exception results in entry to the appropriate exception handler, with suitable return information in LR and stacked PSR.
Instructions designed for use for exception returns can be used as normal to return from the exception, and execution of
the IT block resumes correctly. This is the only way that a PC-modifying instruction is permitted to branch to an
instruction in an IT block.
Restrictions
The following instructions are not permitted in an IT block:
IT
CBZ and CBNZ
CPSID and CPSIE.
Other restrictions when using an IT block are:
A branch or any instruction that modifies the PC must either be outside an IT block or must be the last instruction
inside the IT block. These are:
ADD PC, PC, Rm
MOV PC, Rm
B, BL, BX, BLX
Any LDM, LDR, or POP instruction that writes to the PC
TBB and TBH
Do not branch to any instruction inside an IT block, except when returning from an exception handler
All conditional instructions except Bcond must be inside an IT block. Bcond can be either outside or inside an IT
block but has a larger branch range if it is inside one
Each instruction inside the IT block must specify a condition code suffix that is either the same or logical inverse as
for the other instructions in the block.
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Your assembler might place extra restrictions on the use of IT blocks, such as prohibiting the use of assembler directives
within them.
Condition Flags
This instruction does not change the flags.
Example ITTE NE ; Next 3 instructions are conditional
ANDNE R0, R0, R1 ; ANDNE does not update condition flags
ADDSNE R2, R2, #1 ; ADDSNE updates condition flags
MOVEQ R2, R3 ; Conditional move
CMP R0, #9 ; Convert R0 hex value (0 to 15) into ASCII
; ('0'-'9', 'A'-'F')
ITE GT ; Next 2 instructions are conditional
ADDGT R1, R0, #55 ; Convert 0xA -> 'A'
ADDLE R1, R0, #48 ; Convert 0x0 -> '0'
IT GT ; IT block with only one conditional instruction
ADDGT R1, R1, #1 ; Increment R1 conditionally
ITTEE EQ ; Next 4 instructions are conditional
MOVEQ R0, R1 ; Conditional move
ADDEQ R2, R2, #10 ; Conditional add
ANDNE R3, R3, #1 ; Conditional AND
BNE.W dloop ; Branch instruction can only be used in the last
; instruction of an IT block
IT NE ; Next instruction is conditional
ADD R0, R0, R1 ; Syntax error: no condition code used in IT block
12.6.10.4TBB and TBH
Table Branch Byte and Table Branch Halfword.
Syntax TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
where:
Rn is the register containing the address of the table of branch lengths.
If Rn is PC, then the address of the table is the address of the byte immediately
following the TBB or TBH instruction.
Rm is the index register. This contains an index into the table. For halfword tables,
LSL #1 doubles the value in Rm to form the right offset into the table.
Operation
These instructions cause a PC-relative forward branch using a table of single byte offsets for TBB, or halfword offsets for
TBH. Rn provides a pointer to the table, and Rm supplies an index into the table. For TBB the branch offset is twice the
unsigned value of the byte returned from the table. and for TBH the branch offset is twice the unsigned value of the
halfword returned from the table. The branch occurs to the address at that offset from the address of the byte
immediately after the TBB or TBH instruction.
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Restrictions
The restrictions are:
Rn must not be SP
Rm must not be SP and must not be PC
When any of these instructions is used inside an IT block, it must be the last instruction of the IT block.
Condition Flags
These instructions do not change the flags.
Examples
ADR.W R0, BranchTable_Byte
TBB [R0, R1] ; R1 is the index, R0 is the base address of the
; branch table
Case1
; an instruction sequence follows
Case2
; an instruction sequence follows
Case3
; an instruction sequence follows
BranchTable_Byte
DCB 0 ; Case1 offset calculation
DCB ((Case2-Case1)/2) ; Case2 offset calculation
DCB ((Case3-Case1)/2) ; Case3 offset calculation
TBH [PC, R1, LSL #1] ; R1 is the index, PC is used as base of the
; branch table
BranchTable_H
DCI ((CaseA - BranchTable_H)/2) ; CaseA offset calculation
DCI ((CaseB - BranchTable_H)/2) ; CaseB offset calculation
DCI ((CaseC - BranchTable_H)/2) ; CaseC offset calculation
CaseA
; an instruction sequence follows
CaseB
; an instruction sequence follows
CaseC
; an instruction sequence follows
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12.6.11 Miscellaneous Instructions
The table below shows the remaining Cortex-M4 instructions:
Table 12-27. Miscellaneous Instructions
Mnemonic Description
BKPT Breakpoint
CPSID Change Processor State, Disable Interrupts
CPSIE Change Processor State, Enable Interrupts
DMB Data Memory Barrier
DSB Data Synchronization Barrier
ISB Instruction Synchronization Barrier
MRS Move from special register to register
MSR Move from register to special register
NOP No Operation
SEV Send Event
SVC Supervisor Call
WFI Wait For Interrupt
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12.6.11.1BKPT
Breakpoint.
Syntax BKPT #imm
where:
imm is an expression evaluating to an integer in the range 0-255 (8-bit value).
Operation
The BKPT instruction causes the processor to enter Debug state. Debug tools can use this to investigate system state
when the instruction at a particular address is reached.
imm is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint.
The BKPT instruction can be placed inside an IT block, but it executes unconditionally, unaffected by the condition
specified by the IT instruction.
Condition Flags
This instruction does not change the flags.
Examples
BKPT 0xAB ; Breakpoint with immediate value set to 0xAB (debugger can
; extract the immediate value by locating it using the PC)
Note: ARM does not recommend the use of the BKPT instruction with an immediate value set to 0xAB for any purpose
other than Semi-hosting.
12.6.11.2CPS
Change Processor State.
Syntax CPSeffect iflags
where:
effect is one of:
IE Clears the special purpose register.
ID Sets the special purpose register.
iflags is a sequence of one or more flags:
i Set or clear PRIMASK.
f Set or clear FAULTMASK.
Operation
CPS changes the PRIMASK and FAULTMASK special register values. See “Exception Mask Registers” for more
information about these registers.
Restrictions
The restrictions are:
Use CPS only from privileged software, it has no effect if used in unprivileged software
CPS cannot be conditional and so must not be used inside an IT block.
Condition Flags
This instruction does not change the condition flags.
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Examples
CPSID i ; Disable interrupts and configurable fault handlers (set PRIMASK)
CPSID f ; Disable interrupts and all fault handlers (set FAULTMASK)
CPSIE i ; Enable interrupts and configurable fault handlers (clear PRIMASK)
CPSIE f ; Enable interrupts and fault handlers (clear FAULTMASK)
12.6.11.3DMB
Data Memory Barrier.
Syntax DMB{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before
the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB
instruction. DMB does not affect the ordering or execution of instructions that do not access memory.
Condition Flags
This instruction does not change the flags.
Examples
DMB ; Data Memory Barrier
12.6.11.4DSB
Data Synchronization Barrier.
Syntax DSB{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do
not exec ute until t he DSB inst ruction c omplete s. The D SB instru ction com pletes wh en all e xplicit m emory acc esse s
before it complete.
Condition Flags
This instruction does not change the flags.
Examples
DSB ; Data Synchronisation Barrier
12.6.11.5ISB
Instruction Synchronization Barrier.
Syntax ISB{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
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ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following
the ISB are fetched from memory again, after the ISB instruction has been completed.
Condition Flags
This instruction does not change the flags.
Examples
ISB ; Instruction Synchronisation Barrier
12.6.11.6MRS
Move the contents of a special register to a general-purpose register.
Syntax MRS{cond} Rd, spec_reg
where:
cond is an optional condition code, see “Conditional Execution” .
Rd is the destination register.
spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
Operation
Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to clear the
Q flag.
In process swap code, the programmers model state of the process being swapped out must be saved, including
relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These operations use
MRS in the state-saving instruction sequence and MSR in the state-restoring instruction sequence.
Note: BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.
See “MSR” .
Restrictions
Rd must not be SP and must not be PC.
Condition Flags
This instruction does not change the flags.
Examples
MRS R0, PRIMASK ; Read PRIMASK value and write it to R0
12.6.11.7MSR
Move the contents of a general-purpose register into the specified special register.
Syntax MSR{cond} spec_reg, Rn
where:
cond is an optional condition code, see “Conditional Execution” .
Rn is the source register.
spec_reg can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP,
PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.
Operation
The register access operation in MSR depends on the privilege level. Unprivileged software can only access the APSR.
See “Application Program Status Register” . Privileged software can access all special registers.
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In unprivileged software writes to unallocated or execution state bits in the PSR are ignored.
Note: When the user writes to BASEPRI_MAX, the instruction writes to BASEPRI only if either:
Rn is non-zero and the current BASEPRI value is 0
Rn is non-zero and less than the current BASEPRI value.
See “MRS” .
Restrictions
Rn must not be SP and must not be PC.
Condition Flags
This instruction updates the flags explicitly based on the value in Rn.
Examples
MSR CONTROL, R1 ; Read R1 value and write it to the CONTROL register
12.6.11.8NOP
No Operation.
Syntax NOP{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline
before it reaches the execution stage.
Use NOP for padding, for example to place the following instruction on a 64-bit boundary.
Condition Flags
This instruction does not change the flags.
Examples
NOP ; No operation
12.6.11.9SEV
Send Event.
Syntax SEV{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system. It also sets
the local event register to 1, see “Power Management” .
Condition Flags
This instruction does not change the flags.
Examples
SEV ; Send Event
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12.6.11.10SVC
Supervisor Call.
Syntax SVC{cond} #imm
where:
cond is an optional condition code, see “Conditional Execution” .
imm is an expression evaluating to an integer in the range 0-255 (8-bit value).
Operation
The SVC instruction causes the SVC exception.
imm is ignored by the processor. If required, it can be retrieved by the exception handler to determine what service is
being requested.
Condition Flags
This instruction does not change the flags.
Examples
SVC 0x32 ; Supervisor Call (SVC handler can extract the immediate value
; by locating it via the stacked PC)
12.6.11.11WFI
Wait for Interrupt.
Syntax WFI{cond}
where:
cond is an optional condition code, see “Conditional Execution” .
Operation
WFI is a hint instruction that suspends execution until one of the following events occurs:
An exception
A Debug Entry request, regardless of whether Debug is enabled.
Condition Flags
This instruction does not change the flags.
Examples
WFI ; Wait for interrupt
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12.7 Cortex-M4 Core Peripherals
12.7.1 Peripherals
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low latency
interrupt processing. See Section 12.8 ”Nested Vectored Interrupt Controller (NVIC)”
System Control Block (SCB)
The System Control Block (SCB) is the programmers model interface to the processor. It provides system
implementation information and system control, including configuration, control, and reporting of system
exceptions. See Section 12.9 ”System Control Block (SCB)”
System Timer (SysTick)
The System Timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System (RTOS) tick
timer or as a simple counter. See Section 12.10 ”System Timer (SysTick)”
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) improves system reliability by defining the memory attributes for different
memory regions. It provides up to eight different regions, and an optional predefined background region. See
Section 12.11 ”Memory Protection Unit (MPU)”
12.7.2 Address Map
The address map of the Private peripheral bus (PPB) is:
In register descriptions:
The required privilege gives the privilege level required to access the register, as follows:
Privileged: Only privileged software can access the register.
Unprivileged: Both unprivileged and privileged software can access the register.
Table 12-28. Core Peripheral Register Regions
Address Core Peripheral
0xE000E008-0xE000E00F System Control Block
0xE000E010-0xE000E01F System Timer
0xE000E100-0xE000E4EF Nested Vectored Interrupt Controller
0xE000ED00-0xE000ED3F System control block
0xE000ED90-0xE000EDB8 Memory Protection Unit
0xE000EF00-0xE000EF03 Nested Vectored Interrupt Controller
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12.8 Nested Vectored Interrupt Controller (NVIC)
This section describes the NVIC and the registers it uses. The NVIC supports:
1 to 35 interrupts.
A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so level 0 is
the highest interrupt priority.
Level detection of interrupt signals.
Dynamic reprioritization of interrupts.
Grouping of priority values into group priority and subpriority fields.
Interrupt tail-chaining.
An external Non-maskable interrupt (NMI)
The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no
instruction overhead. This provides low latency exception handling.
12.8.1 Level-sensitive Interrupts
The processor supports level-sensitive interrupts. A level-sensitive interrupt is held asserted until the peripheral
deasserts the interrupt signal. Typically, this happens because the ISR accesses the peripher al, causing it to clear the
interrupt request.
When the processor enters the ISR, it automatically removes the pending state from the interrupt (see “Hardware and
Software Control of Interrupts” ). For a level-sensitive interrupt, if the signal is not deasserted before the processor
returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. This means
that the peripheral can hold the interrupt signal asserted until it no longer requires servicing.
12.8.1.1Hardware and Software Control of Interrupts
The Cortex-M4 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:
The NVIC detects that the interrupt signal is HIGH and the interrupt is not active
The NVIC detects a rising edge on the interrupt signal
A software writes to the corresponding interrupt set-pending register bit, see “Interrupt Set-pending Registers” , or
to the NVIC_STIR register to make an interrupt pending, see “Software Trigger Interrupt Register” .
A pending interrupt remains pending until one of the following:
The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active. Then:
For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the interrupt
signal. If the signal is asserted, the state of the interrupt changes to pending, which might cause the
processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to inactive.
Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change.
Otherwise, the state of the interrupt changes to inactive.
12.8.2 NVIC Design Hints and Tips
Ensure that the software uses correctly aligned register accesses. The processor does not support unaligned accesses
to NVIC registers. See the individual register descriptions for the supported access sizes.
A interrupt can enter a pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking
that interrupt.
Before programming SCB_VTOR to relocate the vector table, ensure that the vector table entries of the new vector table
are set up for fault handlers, NMI and all enabled exception like interrupts. For more information, see the “Vector Table
Offset Register” .
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12.8.2.1NVIC Programming Hints
The software uses the CPSIE I and CPSID I instructions to enable and disable the interrupts. The CMSIS provides the
following intrinsic functions for these instructions:
void __disable_irq(void) // Disable Interrupts
void __enable_irq(void) // Enable Interrupts
In addition, the CMSIS provides a number of functions for NVIC control, including:
The input parameter IRQn is the IRQ number. For more information about these functions, see the CMSIS
documentation.
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS:
The Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of 32-bit
integers, so that:
The array ISER[0] to ISER[1] corresponds to the registers ISER0-ISER1
The array ICER[0] to ICER[1] corresponds to the registers ICER0-ICER1
The array ISPR[0] to ISPR[1] corresponds to the registers ISPR0-ISPR1
The array ICPR[0] to ICPR[1] corresponds to the registers ICPR0-ICPR1
The array IABR[0]to IABR[1] corresponds to the registers IABR0-IABR1
The 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the array IP[0] to IP[34]
corresponds to the registers IPR0-IPR8, and the array entry IP[n] holds the interrupt priority for interrupt n.
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. Table 12-30 shows
how the interrupts, or IRQ numbers, map onto the interrupt registers and corresponding CMSIS variables that have one
bit per interrupt.
Note: 1. Each array element corresponds to a single NVIC register, for example the
ICER[0]
element corresponds to
the ICER0 register.
Table 12-29. CMSIS Functions for NVIC Control
CMSIS Interrupt Control Function Description
void NVIC_SetPriorityGrouping(uint32_t priority_grouping) Set the priority grouping
void NVIC_EnableIRQ(IRQn_t IRQn) Enable IRQn
void NVIC_DisableIRQ(IRQn_t IRQn) Disable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_t IRQn) Return true (IRQ-Number) if IRQn is pending
void NVIC_SetPendingIRQ (IRQn_t IRQn) Set IRQn pending
void NVIC_ClearPendingIRQ (IRQn_t IRQn) Clear IRQn pending status
uint32_t NVIC_GetActive (IRQn_t IRQn) Return the IRQ number of the active interrupt
void NVIC_SetPriority (IRQn_t IRQn, uint32_t priority) Set priority for IRQn
uint32_t NVIC_GetPriority (IRQn_t IRQn) Read priority of IRQn
void NVIC_SystemReset (void) Reset the system
Table 12-30. Mapping of Interrupts to the Interrupt Variables
Interrupts CMSIS Array Elements (1)
Set-enable Clear-enable Set-pending Clear-pending Active Bit
0-34 ISER[0] ICER[0] ISPR[0] ICPR[0] IABR[0]
35-63 ISER[1] ICER[1] ISPR[1] ICPR[1] IABR[1]
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12.8.3 Nested Vectored Interrupt Controller (NVIC) User Interface
Table 12-31. Nested Vectored Interrupt Controller (NVIC) Register Mapping
Offset Register Name Access Reset
0xE000E100 Interrupt Set-enable Register 0 NVIC_ISER0 Read-write 0x00000000
... ... ... ... ...
0xE000E11C Interrupt Set-enable Register 7 NVIC_ISER7 Read-write 0x00000000
0XE000E180 Interrupt Clear-enable Register0 NVIC_ICER0 Read-write 0x00000000
... ... ... ... ...
0xE000E19C Interrupt Clear-enable Register 7 NVIC_ICER7 Read-write 0x00000000
0XE000E200 Interrupt Set-pending Register 0 NVIC_ISPR0 Read-write 0x00000000
... ... ... ... ...
0xE000E21C Interrupt Set-pending Register 7 NVIC_ISPR7 Read-write 0x00000000
0XE000E280 Interrupt Clear-pending Register 0 NVIC_ICPR0 Read-write 0x00000000
... ... ... ... ...
0xE000E29C Interrupt Clear-pending Register 7 NVIC_ICPR7 Read-write 0x00000000
0xE000E300 Interrupt Active Bit Register 0 NVIC_IABR0 Read-write 0x00000000
... ... ... ... ...
0xE000E31C Interrupt Active Bit Register 7 NVIC_IABR7 Read-write 0x00000000
0xE000E400 Interrupt Priority Register 0 NVIC_IPR0 Read-write 0x00000000
... ... ... ... ...
0xE000E420 Interrupt Priority Register 8 NVIC_IPR8 Read-write 0x00000000
0xE000EF00 Software Trigger Interrupt Register NVIC_STIR Write-only 0x00000000
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12.8.3.1Interrupt Set-enable Registers
Name: NVIC_ISERx [x=0..7]
Access: Read-write
Reset: 0x000000000
These registers enable interrupts and show which interrupts are enabled.
• SETENA: Interrupt Set-enable
Write:
0: No effect.
1: Enables the interrupt.
Read:
0: Interrupt disabled.
1: Interrupt enabled.
Notes: 1. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority.
2. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, the NVIC never acti-
vates the interrupt, regardless of its priority.
31 30 29 28 27 26 25 24
SETENA
23 22 21 20 19 18 17 16
SETENA
15 14 13 12 11 10 9 8
SETENA
76543210
SETENA
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12.8.3.2Interrupt Clear-enable Registers
Name: NVIC_ICERx [x=0..7]
Access: Read-write
Reset: 0x000000000
These registers disable interrupts, and show which interrupts are enabled.
• CLRENA: Interrupt Clear-enable
Write:
0: No effect.
1: Disables the interrupt.
Read:
0: Interrupt disabled.
1: Interrupt enabled.
31 30 29 28 27 26 25 24
CLRENA
23 22 21 20 19 18 17 16
CLRENA
15 14 13 12 11 10 9 8
CLRENA
76543210
CLRENA
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12.8.3.3Interrupt Set-pending Registers
Name: NVIC_ISPRx [x=0..7]
Access: Read-write
Reset: 0x000000000
These registers force interrupts into the pending state, and show which interrupts are pending.
• SETPEND: Interrupt Set-pending
Write:
0: No effect.
1: Changes the interrupt state to pending.
Read:
0: Interrupt is not pending.
1: Interrupt is pending.
Notes: 1. Writing 1 to an ISPR bit corresponding to an interrupt that is pending has no effect.
2. Writing 1 to an ISPR bit corresponding to a disabled interrupt sets the state of that interrupt to pending.
31 30 29 28 27 26 25 24
SETPEND
23 22 21 20 19 18 17 16
SETPEND
15 14 13 12 11 10 9 8
SETPEND
76543210
SETPEND
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12.8.3.4Interrupt Clear-pending Registers
Name: NVIC_ICPRx [x=0..7]
Access: Read-write
Reset: 0x000000000
These registers remove the pending state from interrupts, and show which interrupts are pending.
• CLRPEND: Interrupt Clear-pending
Write:
0: No effect.
1: Removes the pending state from an interrupt.
Read:
0: Interrupt is not pending.
1: Interrupt is pending.
Note: Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.
31 30 29 28 27 26 25 24
CLRPEND
23 22 21 20 19 18 17 16
CLRPEND
15 14 13 12 11 10 9 8
CLRPEND
76543210
CLRPEND
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12.8.3.5Interrupt Active Bit Registers
Name: NVIC_IABRx [x=0..7]
Access: Read-write
Reset: 0x000000000
These registers indicate which interrupts are active.
• ACTIVE: Interrupt Active Flags
0: Interrupt is not active.
1: Interrupt is active.
Note: A bit reads as one if the status of the corresponding interrupt is active, or active and pending.
31 30 29 28 27 26 25 24
ACTIVE
23 22 21 20 19 18 17 16
ACTIVE
15 14 13 12 11 10 9 8
ACTIVE
76543210
ACTIVE
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12.8.3.6Interrupt Priority Registers
Name: NVIC_IPRx [x=0..8]
Access: Read-write
Reset: 0x000000000
The NVIC_IPR0-NVIC_IPR8 registers provide a 4-bit priority field for each interrupt. These registers are byte-accessible. Each
register holds four priority fields, that map up to four elements in the CMSIS interrupt priority array
IP[0]
to
IP[34]
• PRI3: Priority (4m+3)
Priority, Byte Offset 3, refers to register bits [31:24].
• PRI2: Priority (4m+2)
Priority, Byte Offset 2, refers to register bits [23:16].
• PRI1: Priority (4m+1)
Priority, Byte Offset 1, refers to register bits [15:8].
• PRI0: Priority (4m)
Priority, Byte Offset 0, refers to register bits [7:0].
Notes: 1. Each priority field holds a priority value, 0-
15
. The lower the value, the greater the priority of the corresponding inter-
rupt. The processor implements only bits[7:4] of each field; bits[3:0] read as zero and ignore writes.
2. for more information about the IP[0] to IP[
34
] interrupt priority array, that provides the software view of the interrupt pri-
orities, see Table 12-29, “CMSIS Functions for NVIC Control” .
3. The corresponding IPR number n is given by n = m DIV 4.
4. The byte offset of the required Priority field in this register is m MOD 4.
31 30 29 28 27 26 25 24
PRI3
23 22 21 20 19 18 17 16
PRI2
15 14 13 12 11 10 9 8
PRI1
76543210
PRI0
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12.8.3.7Software Trigger Interrupt Register
Name: NVIC_STIR
Access: Write-only
Reset: 0x000000000
Write to this register to generate an interrupt from the software.
• INTID: Interrupt ID
Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of
0x03
specifies interrupt IRQ3.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––INTID
76543210
INTID
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12.9 System Control Block (SCB)
The System Control Block (SCB) provides system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions.
Ensure that the software uses aligned accesses of the correct size to access the system control block registers:
Except for the SCB_CFSR and SCB_SHPR1-SCB_SHPR3 registers, it must use aligned word accesses
For the SCB_CFSR and SCB_SHPR1-SCB_SHPR3 registers, it can use byte or aligned halfword or word
accesses.
The processor does not support unaligned accesses to system control block registers.
In a fault handler, to determine the true faulting address:
1. Read and save the MMFAR or SCB_BFAR value.
2. Read the MMARVALID bit in the MMFSR subregister, or the BFARVALID bit in the BFSR subregister. The
SCB_MMFAR or SCB_BFAR address is valid only if this bit is 1.
The software must follow this sequence because another higher priority exception might change the SCB_MMFAR or
SCB_BFAR value. For example, if a higher priority handler preempts the current fault handler, the other fault might
change the SCB_MMFAR or SCB_BFAR value.
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12.9.1 System Control Block (SCB) User Interface
Notes: 1. See the register description for more information.
2. This register contains the subregisters: “MMFSR: Memory Management Fault Status Subregister” (0xE000ED28 - 8
bits), “BFSR: Bus Fault Status Subregister” (0xE000ED29 - 8 bits), “UFSR: Usage Fault Status Subregister”
(0xE000ED2A - 16 bits).
Table 12-32. System Control Block (SCB) Register Mapping
Offset Register Name Access Reset
0xE000E008 Auxiliary Control Register SCB_ACTLR Read-write 0x00000000
0xE000ED00 CPUID Base Register SCB_CPUID Read-only 0x410FC240
0xE000ED04 Interrupt Control and State Register SCB_ICSR Read-write(1) 0x00000000
0xE000ED08 Vector Table Offset Register SCB_VTOR Read-write 0x00000000
0xE000ED0C Application Interrupt and Reset Control Register SCB_AIRCR Read-write 0xFA050000
0xE000ED10 System Control Register SCB_SCR Read-write 0x00000000
0xE000ED14 Configuration and Control Register SCB_CCR Read-write 0x00000200
0xE000ED18 System Handler Priority Register 1 SCB_SHPR1 Read-write 0x00000000
0xE000ED1C System Handler Priority Register 2 SCB_SHPR2 Read-write 0x00000000
0xE000ED20 System Handler Priority Register 3 SCB_SHPR3 Read-write 0x00000000
0xE000ED24 System Handler Control and State Register SCB_SHCSR Read-write 0x00000000
0xE000ED28 Configurable Fault Status Register SCB_CFSR(2) Read-write 0x00000000
0xE000ED2C HardFault Status Register SCB_HFSR Read-write 0x00000000
0xE000ED34 MemManage Fault Address Register SCB_MMFAR Read-write Unknown
0xE000ED38 BusFault Address Register SCB_BFAR Read-write Unknown
0xE000ED3C Auxiliary Fault Status Register SCB_AFSR Read-write 0x00000000
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12.9.1.1Auxiliary Control Register
Name: SCB_ACTLR
Access: Read-write
Reset: 0x000000000
The SCB_ACTLR register provides disable bits for the following processor functions:
• IT folding
• Write buffer use for accesses to the default memory map
• Interruption of multi-cycle instructions.
By default, this register is set to provide optimum performance from the Cortex-M4 processor, and does not normally require
modification.
• DISOOFP: Disable Out Of Order Floating Point
Disables floating point instructions that complete out of order with respect to integer instructions.
• DISFPCA: Disable FPCA
Disables an automatic update of CONTROL.FPCA.
• DISFOLD: Disable Folding
When set to 1, disables the IT folding.
Note: In some situations, the processor can start executing the first instruction in an IT block while it is still executing the IT
instruction. This behavior is called IT folding, and it improves the performance. However, IT folding can cause jitter in
looping. If a task must avoid jitter, set the DISFOLD bit to 1 before executing the task, to disable the IT folding.
• DISDEFWBUF: Disable Default Write Buffer
When set to 1, it disables the write buffer use during default memory map accesses. This causes BusFault to be precise but
decreases the performance, as any store to memory must complete before the processor can execute the next instruction.
This bit only affects write buffers implemented in the Cortex-M4 processor.
• DISMCYCINT: Disable Multiple Cycle Interruption
When set to 1, it disables the interruption of load multiple and store multiple instructions. This increases the interrupt latency of the
processor, as any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
– DISOOFP DISFPCA
76543210
–DISFOLD DISDEFWBUF DISMCYCINT
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12.9.1.2CPUID Base Register
Name: SCB_CPUID
Access: Read-write
Reset: 0x000000000
The SCB_CPUID register contains the processor part number, version, and implementation information.
• Implementer: Implementer Code
0x41: ARM.
• Variant: Variant Number
It is the r value in the rnpn product revision identifier:
0x0: Revision 0.
• Constant
Reads as 0xF.
• PartNo: Part Number of the Processor
0xC24 = Cortex-M4.
• Revision: Revision Number
It is the p value in the rnpn product revision identifier:
0x0: Patch 0.
31 30 29 28 27 26 25 24
Implementer
23 22 21 20 19 18 17 16
Variant Constant
15 14 13 12 11 10 9 8
PartNo
76543210
PartNo Revision
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12.9.1.3Interrupt Control and State Register
Name: SCB_ICSR
Access: Read-write
Reset: 0x000000000
The SCB_ICSR register provides a set-pending bit for the Non-Maskable Interrupt (NMI) exception, and set-pending and clear-
pending bits for the PendSV and SysTick exceptions.
It indicates:
• The exception number of the exception being processed, and whether there are preempted active exceptions,
• The exception number of the highest priority pending exception, and whether any interrupts are pending.
• NMIPENDSET: NMI Set-pending
Write:
PendSV set-pending bit.
Write:
0: No effect.
1: Changes NMI exception state to pending.
Read:
0: NMI exception is not pending.
1: NMI exception is pending.
As NMI is the highest-priority exception, the processor normally enters the NMI exception handler as soon as it registers a write of
1 to this bit. Entering the handler clears this bit to 0. A read of this bit by the NMI exception handler returns 1 only if the NMI signal
is reasserted while the processor is executing that handler.
• PENDSVSET: PendSV Set-pending
Write:
0: No effect.
1: Changes PendSV exception state to pending.
Read:
0: PendSV exception is not pending.
1: PendSV exception is pending.
Writing 1 to this bit is the only way to set the PendSV exception state to pending.
31 30 29 28 27 26 25 24
NMIPENDSET – PENDSVSET PENDSVCLR PENDSTSET PENDSTCLR –
23 22 21 20 19 18 17 16
– ISRPENDING VECTPENDING
15 14 13 12 11 10 9 8
VECTPENDING RETTOBASE – VECTACTIVE
76543210
VECTACTIVE
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• PENDSVCLR: PendSV Clear-pending
Write:
0: No effect.
1: Removes the pending state from the PendSV exception.
• PENDSTSET: SysTick Exception Set-pending
Write:
0: No effect.
1: Changes SysTick exception state to pending.
Read:
0: SysTick exception is not pending.
1: SysTick exception is pending.
• PENDSTCLR: SysTick Exception Clear-pending
Write:
0: No effect.
1: Removes the pending state from the SysTick exception.
This bit is Write-only. On a register read, its value is Unknown.
• ISRPENDING: Interrupt Pending Flag (Excluding NMI and Faults)
0: Interrupt not pending.
1: Interrupt pending.
• VECTPENDING: Exception Number of the Highest Priority Pending Enabled Exception
0: No pending exceptions.
Nonzero: The exception number of the highest priority pending enabled exception.
The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRI-
MASK register.
• RETTOBASE: Preempted Active Exceptions Present or Not
0: There are preempted active exceptions to execute.
1: There are no active exceptions, or the currently-executing exception is the only active exception.
• VECTACTIVE: Active Exception Number Contained
0: Thread mode.
Nonzero: The exception number of the currently active exception. The value is the same as IPSR bits [8:0]. See “Interrupt Program
Status Register” .
Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Clear-Enable, Set-Enable, Clear-Pend-
ing, Set-Pending, or Priority Registers, see “Interrupt Program Status Register” .
Note: When the user writes to the SCB_ICSR register, the effect is unpredictable if:
- Writing 1 to the PENDSVSET bit and writing 1 to the PENDSVCLR bit
- Writing 1 to the PENDSTSET bit and writing 1 to the PENDSTCLR bit.
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12.9.1.4Vector Table Offset Register
Name: SCB_VTOR
Access: Read-write
Reset: 0x000000000
The SCB_VTOR register indicates the offset of the vector table base address from memory address 0x00000000.
• TBLOFF: Vector Table Base Offset
It contains bits [29:7] of the offset of the table base from the bottom of the memory map.
Bit [29] determines whether the vector table is in the code or SRAM memory region:
0: Code.
1: SRAM.
It is sometimes called the TBLBASE bit.
Note: When setting TBLOFF, the offset must be aligned to the number of exception entries in the vector table. Configure the
next statement to give the information required for your implementation; the statement reminds the user of how to
determine the alignment requirement. The minimum alignment is 32 words, enough for up to 16 interrupts. For more
interrupts, adjust the alignment by rounding up to the next power of two. For example, if 21 interrupts are required, the
alignment must be on a 64-word boundary because the required table size is 37 words, and the next power of two is
64.
Table alignment requirements mean that bits[6:0] of the table offset are always zero.
31 30 29 28 27 26 25 24
TBLOFF
23 22 21 20 19 18 17 16
TBLOFF
15 14 13 12 11 10 9 8
TBLOFF
76543210
TBLOFF –
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12.9.1.5Application Interrupt and Reset Control Register
Name: SCB_AIRCR
Access: Read-write
Reset: 0x000000000
The SCB_AIRCR register provides priority grouping control for the exception model, endian status for data accesses, and reset
control of the system. To write to this register, write 0x5FA to the VECTKEY field, otherwise the processor ignores the write.
• VECTKEYSTAT: Register Key
Read:
Reads as 0xFA05.
• VECTKEY: Register Key
Write:
Writes 0x5FA to VECTKEY, otherwise the write is ignored.
• ENDIANNESS: Data Endianness
0: Little-endian.
1: Big-endian.
• PRIGROUP: Interrupt Priority Grouping
This field determines the split of group priority from subpriority. It shows the position of the binary point that splits the PRI_n fields
in the Interrupt Priority Registers into separate group priority and subpriority fields. The table below shows how the PRIGROUP
value controls this split:
31 30 29 28 27 26 25 24
VECTKEYSTAT/VECTKEY
23 22 21 20 19 18 17 16
VECTKEYSTAT/VECTKEY
15 14 13 12 11 10 9 8
ENDIANNESS – PRIGROUP
76543210
– SYSRESETREQ VECTCLRACTI
VE VECTRESET
Interrupt Priority Level Value, PRI_N[7:0] Number of
PRIGROUP Binary Point
(1) Group Priority Bits Subpriority Bits Group Priorities Subpriorities
0b000 bxxxxxxx.y [7:1] None 128 2
0b001 bxxxxxx.yy [7:2] [4:0] 64 4
0b010 bxxxxx.yyy [7:3] [4:0] 32 8
0b011 bxxxx.yyyy [7:4] [4:0] 16 16
0b100 bxxx.yyyyy [7:5] [4:0] 8 32
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Note: 1. PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit.
Determining preemption of an exception uses only the group priority field.
• SYSRESETREQ: System Reset Request
0: No system reset request.
1: Asserts a signal to the outer system that requests a reset.
This is intended to force a large system reset of all major components except for debug. This bit reads as 0.
• VECTCLRACTIVE
Reserved for Debug use. This bit reads as 0. When writing to the register, write 0 to this bit, otherwise the behavior is
unpredictable.
• VECTRESET
Reserved for Debug use. This bit reads as 0. When writing to the register, write 0 to this bit, otherwise the behavior is
unpredictable.
0b101 bxx.yyyyyy [7:6] [5:0] 4 64
0b110 bx.yyyyyyy [7] [6:0] 2 128
0b111 b.yyyyyyy None [7:0] 1 256
Interrupt Priority Level Value, PRI_N[7:0] Number of
PRIGROUP Binary Point (1) Group Priority Bits Subpriority Bits Group Priorities Subpriorities
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12.9.1.6System Control Register
Name: SCB_SCR
Access: Read-write
Reset: 0x000000000
• SEVONPEND: Send Event on Pending Bit
0: Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded.
1: Enabled events and all interrupts, including disabled interrupts, can wake up the processor.
The processor also wakes up on execution of an
SEV
instruction or an external event.
• SLEEPDEEP: Sleep or Deep Sleep
Controls whether the processor uses sleep or deep sleep as its low power mode:
0: Sleep.
1: Deep sleep.
• SLEEPONEXIT: Sleep-on-exit
Indicates sleep-on-exit when returning from the Handler mode to the Thread mode:
0: Do not sleep when returning to Thread mode.
1: Enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt-driven application to avoid returning to an empty main application.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– SEVONPEND – SLEEPDEEP SLEEPONEXIT –
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12.9.1.7Configuration and Control Register
Name: SCB_CCR
Access: Read-write
Reset: 0x000000000
The SCB_CCR register controls the entry to the Thread mode and enables the handlers for NMI, hard fault and faults escalated
by FAULTMASK to ignore BusFaults. It also enables the division by zero and unaligned access trapping, and the access to the
NVIC_STIR register by unprivileged software (see “Software Trigger Interrupt Register” ).
• STKALIGN: Stack Alignment
Indicates the stack alignment on exception entry:
0: 4-byte aligned.
1: 8-byte aligned.
On exception entry, the processor uses bit [9] of the stacked PSR to indicate the stack alignment. On return from the exception, it
uses this stacked bit to restore the correct stack alignment.
• BFHFNMIGN: Bus Faults Ignored
Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. This applies to the hard fault
and FAULTMASK escalated handlers:
0: Data bus faults caused by load and store instructions cause a lock-up.
1: Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.
Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system
devices and bridges to detect control path problems and fix them.
• DIV_0_TRP: Division by Zero Trap
Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0:
0: Do not trap divide by 0.
1: Trap divide by 0.
When this bit is set to 0, a divide by zero returns a quotient of 0.
• UNALIGN_TRP: Unaligned Access Trap
Enables unaligned access traps:
0: Do not trap unaligned halfword and word accesses.
1: Trap unaligned halfword and word accesses.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
– STKALIGN BFHFNMIGN
76543210
– DIV_0_TRP UNALIGN_TRP – USERSETMPE
ND NONBASETHR
DENA
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If this bit is set to 1, an unaligned access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1.
• USERSETMPEND
Enables unprivileged software access to the NVIC_STIR register, see “Software Trigger Interrupt Register” :
0: Disable.
1: Enable.
• NONEBASETHRDENA: Thread Mode Enable
Indicates how the processor enters Thread mode:
0: The processor can enter the Thread mode only when no exception is active.
1: The processor can enter the Thread mode from any level under the control of an EXC_RETURN value, see “Exception Return”
.
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12.9.1.8System Handler Priority Registers
The SCB_SHPR1-SCB_SHPR3 registers set the priority level, 0 to 15 of the exception handlers that have configurable priority.
They are byte-accessible.
The system fault handlers and the priority field and register for each handler are:
Each PRI_N field is 8 bits wide, but the processor implements only bits [7:4] of each field, and bits [3:0] read as zero and ignore
writes.
12.9.1.9System Handler Priority Register 1
Name: SCB_SHPR1
Access: Read-write
Reset: 0x000000000
• PRI_6: Priority
Priority of system handler 6, UsageFault.
• PRI_5: Priority
Priority of system handler 5, BusFault.
• PRI_4: Priority
Priority of system handler 4, MemManage.
Table 12-33. System Fault Handler Priority Fields
Handler Field Register Description
Memory management fault (MemManage) PRI_4
“System Handler Priority Register 1” Bus fault (BusFault) PRI_5
Usage fault (UsageFault) PRI_6
SVCall PRI_11 “System Handler Priority Register 2”
PendSV PRI_14 “System Handler Priority Register 3”
SysTick PRI_15
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
PRI_6
15 14 13 12 11 10 9 8
PRI_5
76543210
PRI_4
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12.9.1.10System Handler Priority Register 2
Name: SCB_SHPR2
Access: Read-write
Reset: 0x000000000
• PRI_11: Priority
Priority of system handler 11, SVCall.
12.9.1.11System Handler Priority Register 3
Name: SCB_SHPR3
Access: Read-write
Reset: 0x000000000
• PRI_15: Priority
Priority of system handler 15, SysTick exception.
• PRI_14: Priority
Priority of system handler 14, PendSV.
31 30 29 28 27 26 25 24
PRI_11
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
–
31 30 29 28 27 26 25 24
PRI_15
23 22 21 20 19 18 17 16
PRI_14
15 14 13 12 11 10 9 8
–
76543210
–
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12.9.1.12System Handler Control and State Register
Name: SCB_SHCSR
Access: Read-write
Reset: 0x000000000
The SHCSR register enables the system handlers, and indicates the pending status of the bus fault, memory management fault,
and SVC exceptions; it also indicates the active status of the system handlers.
• USGFAULTENA: Usage Fault Enable
0: Disables the exception.
1: Enables the exception.
• BUSFAULTENA: Bus Fault Enable
0: Disables the exception.
1: Enables the exception.
• MEMFAULTENA: Memory Management Fault Enable
0: Disables the exception.
1: Enables the exception.
• SVCALLPENDED: SVC Call Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• BUSFAULTPENDED: Bus Fault Exception Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• MEMFAULTPENDED: Memory Management Fault Exception Pending
Read:
0: The exception is not pending.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
– USGFAULTENABUSFAULTENAMEMFAULTENA
15 14 13 12 11 10 9 8
SVCALLPENDE
DBUSFAULTPEN
DED MEMFAULTPEN
DED USGFAULTPEN
DED SYSTICKACT PENDSVACT – MONITORACT
76543210
SVCALLAVCT – USGFAULTACT – BUSFAULTACTMEMFAULTACT
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1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• USGFAULTPENDED: Usage Fault Exception Pending
Read:
0: The exception is not pending.
1: The exception is pending.
Note: The user can write to these bits to change the pending status of the exceptions.
• SYSTICKACT: SysTick Exception Active
Read:
0: The exception is not active.
1: The exception is active.
Note: The user can write to these bits to change the active status of the exceptions.
- Caution: A software that changes the value of an active bit in this register without a correct adjustment to the
stacked content can cause the processor to generate a fault exception. Ensure that the software writing to this regis-
ter retains and subsequently restores the current active status.
- Caution: After enabling the system handlers, to change the value of a bit in this register, the user must use a read-
modify-write procedure to ensure that only the required bit is changed.
• PENDSVACT: PendSV Exception Active
0: The exception is not active.
1: The exception is active.
• MONITORACT: Debug Monitor Active
0: Debug monitor is not active.
1: Debug monitor is active.
• SVCALLACT: SVC Call Active
0: SVC call is not active.
1: SVC call is active.
• USGFAULTACT: Usage Fault Exception Active
0: Usage fault exception is not active.
1: Usage fault exception is active.
• BUSFAULTACT: Bus Fault Exception Active
0: Bus fault exception is not active.
1: Bus fault exception is active.
• MEMFAULTACT: Memory Management Fault Exception Active
0: Memory management fault exception is not active.
1: Memory management fault exception is active.
If the user disables a system handler and the corresponding fault occurs, the processor treats the fault as a hard fault.
The user can write to this register to change the pending or active status of system exceptions. An OS kernel can write to the
active bits to perform a context switch that changes the current exception type.
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12.9.1.13Configurable Fault Status Register
Name: SCB_CFSR
Access: Read-write
Reset: 0x000000000
• IACCVIOL: Instruction Access Violation Flag
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No instruction access violation fault.
1: The processor attempted an instruction fetch from a location that does not permit execution.
This fault occurs on any access to an XN region, even when the MPU is disabled or not present.
When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has not written a
fault address to the SCB_MMFAR register.
• DACCVIOL: Data Access Violation Flag
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No data access violation fault.
1: The processor attempted a load or store at a location that does not permit the operation.
When this bit is 1, the PC value stacked for the exception return points to the faulting instruction. The processor has loaded the
SCB_MMFAR register with the address of the attempted access.
• MUNSTKERR: Memory Manager Fault on Unstacking for a Return From Exception
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No unstacking fault.
1: Unstack for an exception return has caused one or more access violations.
This fault is chained to the handler. This means that when this bit is 1, the original return stack is still present. The processor has
not adjusted the SP from the failing return, and has not performed a new save. The processor has not written a fault address to
the SCB_MMFAR register.
• MSTKERR: Memory Manager Fault on Stacking for Exception Entry
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No stacking fault.
1: Stacking for an exception entry has caused one or more access violations.
When this bit is 1, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor has not
written a fault address to SCB_MMFAR register.
31 30 29 28 27 26 25 24
– DIVBYZERO UNALIGNED
23 22 21 20 19 18 17 16
– NOCP INVPC INVSTATE UNDEFINSTR
15 14 13 12 11 10 9 8
BFRVALID – STKERR UNSTKERR IMPRECISERR PRECISERR IBUSERR
76543210
MMARVALID – MLSPERR MSTKERR MUNSTKERR – DACCVIOL IACCVIOL
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• MLSPERR: MemManage during Lazy State Preservation
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: No MemManage fault occurred during the floating-point lazy state preservation.
1: A MemManage fault occurred during the floating-point lazy state preservation.
• MMARVALID: Memory Management Fault Address Register (SCB_MMFAR) Valid Flag
This is part of “MMFSR: Memory Management Fault Status Subregister” .
0: The value in SCB_MMFAR is not a valid fault address.
1: SCB_MMFAR register holds a valid fault address.
If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit
to 0. This prevents problems on return to a stacked active memory management fault handler whose SCB_MMFAR value has
been overwritten.
• IBUSERR: Instruction Bus Error
This is part of “BFSR: Bus Fault Status Subregister” .
0: No instruction bus error.
1: Instruction bus error.
The processor detects the instruction bus error on prefetching an instruction, but it sets the IBUSERR flag to 1 only if it attempts
to issue the faulting instruction.
When the processor sets this bit to 1, it does not write a fault address to the BFAR register.
• PRECISERR: Precise Data Bus Error
This is part of “BFSR: Bus Fault Status Subregister” .
0: No precise data bus error.
1: A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault.
When the processor sets this bit to 1, it writes the faulting address to the SCB_BFAR register.
• IMPRECISERR: Imprecise Data Bus Error
This is part of “BFSR: Bus Fault Status Subregister” .
0: No imprecise data bus error.
1: A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error.
When the processor sets this bit to 1, it does not write a fault address to the SCB_BFAR register.
This is an asynchronous fault. Therefore, if it is detected when the priority of the current process is higher than the bus fault prior-
ity, the bus fault becomes pending and becomes active only when the processor returns from all higher priority processes. If a
precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both this bit and
one of the precise fault status bits are set to 1.
• UNSTKERR: Bus Fault on Unstacking for a Return From Exception
This is part of “BFSR: Bus Fault Status Subregister” .
0: No unstacking fault.
1: Unstack for an exception return has caused one or more bus faults.
This fault is chained to the handler. This means that when the processor sets this bit to 1, the original return stack is still present.
The processor does not adjust the SP from the failing return, does not performed a new save, and does not write a fault address
to the BFAR.
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• STKERR: Bus Fault on Stacking for Exception Entry
This is part of “BFSR: Bus Fault Status Subregister” .
0: No stacking fault.
1: Stacking for an exception entry has caused one or more bus faults.
When the processor sets this bit to 1, the SP is still adjusted but the values in the context area on the stack might be incorrect.
The processor does not write a fault address to the SCB_BFAR register.
• BFARVALID: Bus Fault Address Register (BFAR) Valid flag
This is part of “BFSR: Bus Fault Status Subregister” .
0: The value in SCB_BFAR is not a valid fault address.
1: SCB_BFAR holds a valid fault address.
The processor sets this bit to 1 after a bus fault where the address is known. Other faults can set this bit to 0, such as a memory
management fault occurring later.
If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must set this bit to 0. This prevents
problems if returning to a stacked active bus fault handler whose SCB_BFAR value has been overwritten.
• UNDEFINSTR: Undefined Instruction Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” .
0: No undefined instruction usage fault.
1: The processor has attempted to execute an undefined instruction.
When this bit is set to 1, the PC value stacked for the exception return points to the undefined instruction.
An undefined instruction is an instruction that the processor cannot decode.
• INVSTATE: Invalid State Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” .
0: No invalid state usage fault.
1: The processor has attempted to execute an instruction that makes illegal use of the EPSR.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the
EPSR.
This bit is not set to 1 if an undefined instruction uses the EPSR.
• INVPC: Invalid PC Load Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” . It is caused by an invalid PC load by EXC_RETURN:
0: No invalid PC load usage fault.
1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid
EXC_RETURN value.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load
of the PC.
• NOCP: No Coprocessor Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” . The processor does not support coprocessor instructions:
0: No usage fault caused by attempting to access a coprocessor.
1: The processor has attempted to access a coprocessor.
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• UNALIGNED: Unaligned Access Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” .
0: No unaligned access fault, or unaligned access trapping not enabled.
1: The processor has made an unaligned memory access.
Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the SCB_CCR register to 1. See “Configuration and
Control Register” . Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of UNALIGN_TRP.
• DIVBYZERO: Divide by Zero Usage Fault
This is part of “UFSR: Usage Fault Status Subregister” .
0: No divide by zero fault, or divide by zero trapping not enabled.
1: The processor has executed an SDIV or UDIV instruction with a divisor of 0.
When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed the
divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the SCB_CCR register to 1. See “Configuration
and Control Register” .
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12.9.1.14Configurable Fault Status Register (Byte Access)
Name: SCB_CFSR (BYTE)
Access: Read-write
Reset: 0x000000000
• MMFSR: Memory Management Fault Status Subregister
The flags in the MMFSR subregister indicate the cause of memory access faults. See bitfield [7..0] description in Section
12.9.1.13.
• BFSR: Bus Fault Status Subregister
The flags in the BFSR subregister indicate the cause of a bus access fault. See bitfield [14..8] description in Section 12.9.1.13.
• UFSR: Usage Fault Status Subregister
The flags in the UFSR subregister indicate the cause of a usage fault. See bitfield [31..15] description in Section 12.9.1.13.
Note: The UFSR bits are sticky. This means that as one or more fault occurs, the associated bits are set to 1. A bit that is set
to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.
The SCB_CFSR register indicates the cause of a memory management fault, bus fault, or usage fault. It is byte accessible. The
user can access the SCB_CFSR register or its subregisters as follows:
• Access complete SCB_CFSR with a word access to 0xE000ED28
• Access MMFSR with a byte access to 0xE000ED28
• Access MMFSR and BFSR with a halfword access to 0xE000ED28
• Access BFSR with a byte access to 0xE000ED29
• Access UFSR with a halfword access to 0xE000ED2A.
31 30 29 28 27 26 25 24
UFSR
23 22 21 20 19 18 17 16
UFSR
15 14 13 12 11 10 9 8
BFSR
76543210
MMFSR
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12.9.1.15Hard Fault Status Register
Name: SCB_HFSR
Access: Read-write
Reset: 0x000000000
The HFSR register gives information about events that activate the hard fault handler. This register is read, write to clear. This
means that bits in the register read normally, but writing 1 to any bit clears that bit to 0.
• DEBUGEVT: Reserved for Debug Use
When writing to the register, write 0 to this bit, otherwise the behavior is unpredictable.
• FORCED: Forced Hard Fault
It indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because
of priority or because it is disabled:
0: No forced hard fault.
1: Forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault status registers to find the cause of the fault.
• VECTTBL: Bus Fault on a Vector Table
It indicates a bus fault on a vector table read during an exception processing:
0: No bus fault on vector table read.
1: Bus fault on vector table read.
This error is always handled by the hard fault handler.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction that was preempted by the
exception.
Note: The HFSR bits are sticky. This means that, as one or more fault occurs, the associated bits are set to 1. A bit that is
set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.
31 30 29 28 27 26 25 24
DEBUGEVT FORCED –
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– VECTTBL –
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12.9.1.16MemManage Fault Address Register
Name: SCB_MMFAR
Access: Read-write
Reset: 0x000000000
The MMFAR register contains the address of the location that generated a memory management fault.
• ADDRESS
When the MMARVALID bit of the MMFSR subregister is set to 1, this field holds the address of the location that generated the
memory management fault.
Notes: 1. When an unaligned access faults, the address is the actual address that faulted. Because a single read or write
instruction can be split into multiple aligned accesses, the fault address can be any address in the range of the
requested access size.
2. Flags in the MMFSR subregister indicate the cause of the fault, and whether the value in the SCB_MMFAR register is
valid. See “MMFSR: Memory Management Fault Status Subregister” .
31 30 29 28 27 26 25 24
ADDRESS
23 22 21 20 19 18 17 16
ADDRESS
15 14 13 12 11 10 9 8
ADDRESS
76543210
ADDRESS
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12.9.1.17Bus Fault Address Register
Name: SCB_BFAR
Access: Read-write
Reset: 0x000000000
The BFAR register contains the address of the location that generated a bus fault.
• ADDRESS
When the BFARVALID bit of the BFSR subregister is set to 1, this field holds the address of the location that generated the bus
fault.
Notes: 1. When an unaligned access faults, the address in the SCB_BFAR register is the one requested by the instruction,
even if it is not the address of the fault.
2. Flags in the BFSR indicate the cause of the fault, and whether the value in the SCB_BFAR register is valid. See
“BFSR: Bus Fault Status Subregister” .
31 30 29 28 27 26 25 24
ADDRESS
23 22 21 20 19 18 17 16
ADDRESS
15 14 13 12 11 10 9 8
ADDRESS
76543210
ADDRESS
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12.10 System Timer (SysTick)
The processor has a 24-bit system timer, SysTick, that counts down from the reload value to zero, reloads (wraps to) the
value in the SYST_RVR register on the next clock edge, then counts down on subsequent clocks.
When the processor is halted for debugging, the counter does not decrement.
The SysTick counter runs on the processor clock. If this clock signal is stopped for low power mode, the SysTick counter
stops.
Ensure that the software uses aligned word accesses to access the SysTick registers.
The SysTick counter reload and current value are undefined at reset; the correct initialization sequence for the SysTick
counter is:
1. Program the reload value.
2. Clear the current value.
3. Program the Control and Status register.
12.10.1 System Timer (SysTick) User Interface
Table 12-34. System Timer (SYST) Register Mapping
Offset Register Name Access Reset
0xE000E010 SysTick Control and Status Register SYST_CSR Read-write 0x00000004
0xE000E014 SysTick Reload Value Register SYST_RVR Read-write Unknown
0xE000E018 SysTick Current Value Register SYST_CVR Read-write Unknown
0xE000E01C SysTick Calibration Value Register SYST_CALIB Read-only 0xC0000000
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12.10.1.1SysTick Control and Status
Name: SYST_CSR
Access: Read-write
Reset: 0x000000000
The SysTick SYST_CSR register enables the SysTick features.
• COUNTFLAG: Count Flag
Returns 1 if the timer counted to 0 since the last time this was read.
• CLKSOURCE: Clock Source
Indicates the clock source:
0: External Clock.
1: Processor Clock.
• TICKINT
Enables a SysTick exception request:
0: Counting down to zero does not assert the SysTick exception request.
1: Counting down to zero asserts the SysTick exception request.
The software can use COUNTFLAG to determine if SysTick has ever counted to zero.
• ENABLE
Enables the counter:
0: Counter disabled.
1: Counter enabled.
When ENABLE is set to 1, the counter loads the RELOAD value from the SYST_RVR register and then counts down. On reach-
ing 0, it sets the COUNTFLAG to 1 and optionally asserts the SysTick depending on the value of TICKINT. It then loads the
RELOAD value again, and begins counting.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
– COUNTFLAG
15 14 13 12 11 10 9 8
–
76543210
CLKSOURCE TICKINT ENABLE
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12.10.1.2SysTick Reload Value Registers
Name: SYST_RVR
Access: Read-write
Reset: 0x000000000
The SYST_RVR register specifies the start value to load into the SYST_CVR register.
• RELOAD
Value to load into the SYST_CVR register when the counter is enabled and when it reaches 0.
The RELOAD value can be any value in the range 0x00000001-0x00FFFFFF. A start value of 0 is possible, but has no effect
because the SysTick exception request and COUNTFLAG are activated when counting from 1 to 0.
The RELOAD value is calculated according to its use: For example, to generate a multi-shot timer with a period of N processor
clock cycles, use a RELOAD value of N-1. If the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
RELOAD
15 14 13 12 11 10 9 8
RELOAD
76543210
RELOAD
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12.10.1.3SysTick Current Value Register
Name: SYST_CVR
Access: Read-write
Reset: 0x000000000
The SysTick SYST_CVR register contains the current value of the SysTick counter.
• CURRENT
Reads return the current value of the SysTick counter.
A write of any value clears the field to 0, and also clears the SYST_CSR.COUNTFLAG bit to 0.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
CURRENT
15 14 13 12 11 10 9 8
CURRENT
76543210
CURRENT
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12.10.1.4SysTick Calibration Value Register
Name: SYST_CALIB
Access: Read-write
Reset: 0x000000000
The SysTick SYST_CSR register indicates the SysTick calibration properties.
• NOREF: No Reference Clock
It indicates whether the device provides a reference clock to the processor:
0: Reference clock provided.
1: No reference clock provided.
If your device does not provide a reference clock, the SYST_CSR.CLKSOURCE bit reads-as-one and ignores writes.
• SKEW
It indicates whether the TENMS value is exact:
0: TENMS value is exact.
1: TENMS value is inexact, or not given.
An inexact TENMS value can affect the suitability of SysTick as a software real time clock.
• TENMS: Ten Milliseconds
The reload value for 10 ms (100 Hz) timing is subject to system clock skew errors. If the value reads as zero, the calibration value
is not known.
Read as 0x000030D4. The SysTick calibration value is fixed at 0x000030D4 (8000), which allows the generation of a time base of
1 ms with SysTick clock at 12.5 MHz (100/8 = 12.5 MHz).
31 30 29 28 27 26 25 24
NOREF SKEW –
23 22 21 20 19 18 17 16
TENMS
15 14 13 12 11 10 9 8
TENMS
76543210
TENMS
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12.11 Memory Protection Unit (MPU)
The MPU divides the memory map into a number of regions, and defines the location, size, access permissions, and
memory attributes of each region. It supports:
Independent attribute settings for each region
Overlapping regions
Export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M4 MPU defines:
Eight separate memory regions, 0-7
A background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the highest number. For
example, the attributes for region 7 take precedence over the attributes of any region that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is accessible from
privileged software only.
The Cortex-M4 MPU memory map is unified. This means that instruction accesses and data accesses have the same
region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates a memory management
fault. This causes a fault exception, and might cause the termination of the process in an OS environment.
In an OS environment, the kernel can update the MPU region setting dynamically based on the process to be executed.
Typically, an embedded OS uses the MPU for memory protection.
The configuration of MPU regions is based on memory types (see “Memory Regions, Types and Attributes” ).
Table shows the possible MPU region attributes. These include Share ability and cache behavior attributes that are not
relevant to most microcontroller implementations. See “MPU Configuration for a Microcontroller” for guidelines for
programming such an implementation.
12.11.1 MPU Access Permission Attributes
This section describes the MPU access permission attributes. The access permission bits (TEX, C, B, S, AP, and XN) of
the MPU_RASR control the access to the corresponding memory region. If an access is made to an area of memory
without the required permissions, then the MPU generates a permission fault.
Memory Attributes Summary
Memory Type Shareability Other Attributes Description
Strongly- ordered - - All accesses to Strongly-ordered memory occur in program order. All
Strongly-ordered regions are assumed to be shared.
Device Shared - Memory-mapped peripherals that several processors share.
Non-shared - Memory-mapped peripherals that only a single processor uses.
Normal Shared Normal memory that is shared between several processors.
Non-shared Normal memory that only a single processor uses.
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The table below shows the encodings for the TEX, C, B, and S access permission bits.
Note: 1. The MPU ignores the value of this bit.
Table 12-36 shows the cache policy for memory attribute encodings with a TEX value is in the range 4-7.
Table 12-35. TEX, C, B, and S Encoding
TEX C B S Memory Type Shareability Other Attributes
b000
0
0 x
(1) Strongly-
ordered Shareable -
1 x
(1) Device Shareable -
1
0 0Normal Not
shareable Outer and inner write-through. No
write allocate.
1 Shareable
1 0Normal Not
shareable Outer and inner write-back. No write
allocate.
1 Shareable
b001
0
0 0Normal Not
shareable
1 Shareable
1 x
(1) Reserved encoding -
1
0 x
(1) Implementation defined
attributes. -
1 0Normal Not
shareable Outer and inner write-back. Write and
read allocate.
1 Shareable
b010 00 x
(1) Device Not
shareable Nonshared Device.
1 x
(1) Reserved encoding -
1x
(1) x (1) Reserved encoding -
b1B
BAA0Normal Not
shareable
1Shareable
Table 12-36. Cache Policy for Memory Attribute Encoding
Encoding, AA or BB Corresponding Cache Policy
00 Non-cacheable
01 Write back, write and read allocate
10 Write through, no write allocate
11 Write back, no write allocate
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Table 12-37 shows the AP encodings that define the access permissions for privileged and unprivileged software.
12.11.1.1MPU Mismatch
When an access violates the MPU permissions, the processor generates a memory management fault, see “Exceptions
and Interrupts” . The MMFSR indicates the cause of the fault. See “MMFSR: Memory Management Fault Status
Subregister” for more information.
12.11.1.2Updating an MPU Region
To update the attributes for an MPU region, update the MPU_RNR, MPU_RBAR and MPU_RASR registers. Each
register can be programed separately, or a multiple-word write can be used to program all of these registers.
MPU_RBAR and MPU_RASR aliases can be used to program up to four regions simultaneously using an STM
instruction.
12.11.1.3Updating an MPU Region Using Separate Words
Simple code to configure one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R4, [R0, #0x4] ; Region Base Address
STRH R2, [R0, #0x8] ; Region Size and Enable
STRH R3, [R0, #0xA] ; Region Attribute
Disable a region before writing new region settings to the MPU, if the region being changed was previously enabled. For
example:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
BIC R2, R2, #1 ; Disable
STRH R2, [R0, #0x8] ; Region Size and Enable
STR R4, [R0, #0x4] ; Region Base Address
Table 12-37. AP Encoding
AP[2:0] Privileged
Permissions Unprivileged
Permissions Description
000 No access No access All accesses generate a permission fault
001 RW No access Access from privileged software only
010 RW RO Writes by unprivileged software generate a
permission fault
011 RW RW Full access
100 Unpredictable Unpredictable Reserved
101 RO No access Reads by privileged software only
110 RO RO Read only, by privileged or unprivileged software
111 RO RO Read only, by privileged or unprivileged software
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STRH R3, [R0, #0xA] ; Region Attribute
ORR R2, #1 ; Enable
STRH R2, [R0, #0x8] ; Region Size and Enable
The software must use memory barrier instructions:
Before the MPU setup, if there might be outstanding memory transfers, such as buffered writes, that might be
affected by the change in MPU settings
After the MPU setup, if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by entering an exception handler,
or is followed by an exception return, because the exception entry and exception return mechanisms cause memory
barrier behavior.
The software does not need any memory barrier instructions during an MPU setup, because it accesses the MPU
through the PPB, which is a Strongly-Ordered memory region.
For example, if the user wants all of the memory access behavior to take effect immediately after the programming
sequence, a DSB instruction and an ISB instruction must be used. A DSB is required after changing MPU settings, such
as at the end of a context switch. An ISB is required if the code that programs the MPU region or regions is entered using
a branch or call. If the programming sequence is entered using a return from exception, or by taking an exception, then
an ISB is not required.
12.11.1.4Updating an MPU Region Using Multi-word Writes
The user can program directly using multi-word writes, depending on how the information is divided. Consider the
following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
STR R2, [R0, #0x4] ; Region Base Address
STR R3, [R0, #0x8] ; Region Attribute, Size and Enable
Use an STM instruction to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR ; 0xE000ED98, MPU region number register
STM R0, {R1-R3} ; Region Number, address, attribute, size and enable
This can be done in two words for pre-packed information. This means that the MPU_RBAR contains the required region
number and had the VALID bit set to 1. See “MPU Region Base Address Register” . Use this when the data is statically
packed, for example in a boot loader:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0, =MPU_RBAR ; 0xE000ED9C, MPU Region Base register
STR R1, [R0, #0x0] ; Region base address and
; region number combined with VALID (bit 4) set to 1
STR R2, [R0, #0x4] ; Region Attribute, Size and Enable
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Use an STM instruction to optimize this:
; R1 = address and region number in one
; R2 = size and attributes in one
LDR R0,=MPU_RBAR ; 0xE000ED9C, MPU Region Base register
STM R0, {R1-R2} ; Region base address, region number and VALID bit,
; and Region Attribute, Size and Enable
12.11.1.5Subregions
Regions of 256 bytes or more are divided into eight equal-sized subregions. Set the corresponding bit in the SRD field of
the MPU_RASR field to disable a subregion. See “MPU Region Attribute and Size Register” . The least significant bit of
SRD contro ls the first subre gion, and the most si gnificant bit contro ls the last subregi on. Disabling a su bregion means
another region overlapping the disabled range matches instead. If no other enabled region overlaps the disabled
subregion, the MPU issues a fault.
Regions of 32, 64, and 128 bytes do not support subregions. With regions of these sizes, the SRD field must be set to
0x00, otherwise the MPU behavior is unpredictable.
12.11.1.6Example of SRD Use
Two regions with the same base address overlap. Region 1 is 128 KB, and region 2 is 512 KB. To ensure the attributes
from region 1 apply to the first 128 KB region, set the SRD field for region 2 to b00000011 to disable the first two
subregions, as in Figure 12-13 below:
Figure 12-13.SRD Use
12.11.1.7MPU Design Hints And Tips
To avoid unexpected behavior, disable the interrupts before updating the attributes of a region that the interrupt handlers
might access.
Ensure the software uses aligned accesses of the correct size to access MPU registers:
Except for the MPU_RASR register, it must use aligned word accesses
For the MPU_RASR register, it can use byte or aligned halfword or word accesses.
The processor does not support unaligned accesses to MPU registers.
When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any
previous region settings from affecting the new MPU setup.
Region 1
Disabled subregion
Disabled subregion
Region 2, with
subregions
Base address of both regions
Offset from
base address
0
64KB
128KB
192KB
256KB
320KB
384KB
448KB
512KB
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MPU Configuration for a Microcontroller
Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU as
follows:
In most microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior.
However, using these settings for the MPU regions can make the application code more portable. The values given are
for typical situations. In special systems, such as multiprocessor designs or designs with a separate DMA engine, the
shareability attribute might be important. In these cases, refer to the recommendations of the memory device
manufacturer.
Table 12-38. Memory Region Attributes for a Microcontroller
Memory Region TEX C B S Memory Type and Attributes
Flash memory b000 1 0 0 Normal memory, non-shareable, write-through
Internal SRAM b000 1 0 1 Normal memory, shareable, write-through
External SRAM b000 1 1 1 Normal memory, shareable, write-back, write-allocate
Peripherals b000 0 1 1 Device memory, shareable
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12.11.2 Memory Protection Unit (MPU) User Interface
Table 12-39. Memory Protection Unit (MPU) Register Mapping
Offset Register Name Access Reset
0xE000ED90 MPU Type Register MPU_TYPE Read-only 0x00000800
0xE000ED94 MPU Control Register MPU_CTRL Read-write 0x00000000
0xE000ED98 MPU Region Number Register MPU_RNR Read-write 0x00000000
0xE000ED9C MPU Region Base Address Register MPU_RBAR Read-write 0x00000000
0xE000EDA0 MPU Region Attribute and Size Register MPU_RASR Read-write 0x00000000
0xE000EDA4 Alias of RBAR, see MPU Region Base Address
Register MPU_RBAR_A1 Read-write 0x00000000
0xE000EDA8 Alias of RASR, see MPU Region Attribute and Size
Register MPU_RASR_A1 Read-write 0x00000000
0xE000EDAC Alias of RBAR, see MPU Region Base Address
Register MPU_RBAR_A2 Read-write 0x00000000
0xE000EDB0 Alias of RASR, see MPU Region Attribute and Size
Register MPU_RASR_A2 Read-write 0x00000000
0xE000EDB4 Alias of RBAR, see MPU Region Base Address
Register MPU_RBAR_A3 Read-write 0x00000000
0xE000EDB8 Alias of RASR, see MPU Region Attribute and Size
Register MPU_RASR_A3 Read-write 0x00000000
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12.11.2.1MPU Type Register
Name: MPU_TYPE
Access: Read-write
Reset: 0x00000800
The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports.
• IREGION: Instruction Region
Indicates the number of supported MPU instruction regions.
Always contains 0x00. The MPU memory map is unified and is described by the DREGION field.
• DREGION: Data Region
Indicates the number of supported MPU data regions:
0x08 = Eight MPU regions.
• SEPARATE: Separate Instruction
Indicates support for unified or separate instruction and date memory maps:
0: Unified.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
IREGION
15 14 13 12 11 10 9 8
DREGION
76543210
– SEPARATE
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12.11.2.2MPU Control Register
Name: MPU_CTRL
Access: Read-write
Reset: 0x00000800
The MPU CTRL register enables the MPU, enables the default memory map background region, and enables the use of the MPU
when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers.
• PRIVDEFENA: Privileged Default Memory Map Enabled
Enables privileged software access to the default memory map:
0: If the MPU is enabled, disables the use of the default memory map. Any memory access to a location not covered by any
enabled region causes a fault.
1: If the MPU is enabled, enables the use of the default memory map as a background region for privileged software accesses.
When enabled, the background region acts as a region number -1. Any region that is defined and enabled has priority over this
default map.
If the MPU is disabled, the processor ignores this bit.
• HFNMIENA: Hard Fault and NMI Enabled
Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
When the MPU is enabled:
0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit.
1: The MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
When the MPU is disabled, if this bit is set to 1, the behavior is unpredictable.
• ENABLE
Enables the MPU:
0: MPU disabled.
1: MPU enabled.
When ENABLE and PRIVDEFENA are both set to 1:
• For privileged accesses, the default memory map is as described in “Memory Model” . Any access by privileged
software that does not address an enabled memory region behaves as defined by the default memory map.
• Any access by unprivileged software that does not address an enabled memory region causes a memory management
fault.
XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
– PRIVDEFENA HFNMIENA ENABLE
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When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for the system to function unless the
PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set to 1 and no regions are enabled, then only privileged software can
operate.
When the ENABLE bit is set to 0, the system uses the default memory map. This has the same memory attributes as if the MPU
is not implemented. The default memory map applies to accesses from both privileged and unprivileged software.
When the MPU is enabled, accesses to the System Control Space and vector table are always permitted. Other areas are acces-
sible based on regions and whether PRIVDEFENA is set to 1.
Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the handler for an exception with priority
–1 or –2. These priorities are only possible when handling a hard fault or NMI exception, or when FAULTMASK is enabled. Set-
ting the HFNMIENA bit to 1 enables the MPU when operating with these two priorities.
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12.11.2.3MPU Region Number Register
Name: MPU_RNR
Access: Read-write
Reset: 0x00000800
The MPU_RNR selects which memory region is referenced by the MPU_RBAR and MPU_RASR registers.
• REGION
Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.
The MPU supports 8 memory regions, so the permitted values of this field are 0-7.
Normally, the required region number is written to this register before accessing the MPU_RBAR or MPU_RASR. However, the
region number can be changed by writing to the MPU_RBAR with the VALID bit set to 1; see “MPU Region Base Address Regis-
ter” . This write updates the value of the REGION field.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
REGION
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12.11.2.4MPU Region Base Address Register
Name: MPU_RBAR
Access: Read-write
Reset: 0x00000000
Note: If the region size is 32B, the ADDR field is bits [31:5] and there is no Reserved field.
The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and can update the value of the
MPU_RNR.
Write MPU_RBAR with the VALID bit set to 1 to change the current region number and update the MPU_RNR.
• ADDR: Region Base Address
The value of N depends on the region size. The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified by the
SIZE field in the MPU_RASR, defines the value of N:
N = Log2(Region size in bytes),
If the region size is configured to 4 GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies the
complete memory map, and the base address is 0x00000000.
The base address is aligned to the size of the region. For example, a 64 KB region must be aligned on a multiple of 64 KB, for
example, at 0x00010000 or 0x00020000.
• VALID: MPU Region Number Valid
Write:
0: MPU_RNR not changed, and the processor updates the base address for the region specified in the MPU_RNR, and ignores
the value of the REGION field.
1: The processor updates the value of the MPU_RNR to the value of the REGION field, and updates the base address for the
region specified in the REGION field.
Always reads as zero.
• REGION: MPU Region
For the behavior on writes, see the description of the VALID field.
On reads, returns the current region number, as specified by the MPU_RNR.
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 N
ADDR
N-16543210
– VALID REGION
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12.11.2.5MPU Region Attribute and Size Register
Name: MPU_RASR
Access: Read-write
Reset: 0x00000000
The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that
region and any subregions.
MPU_RASR is accessible using word or halfword accesses:
• The most significant halfword holds the region attributes.
• The least significant halfword holds the region size, and the region and subregion enable bits.
• XN: Instruction Access Disable
0: Instruction fetches enabled.
1: Instruction fetches disabled.
• AP: Access Permission
See Table 12-37.
• TEX, C, B: Memory Access Attributes
See Table 12-35.
• S: Shareable
See Table 12-35.
• SRD: Subregion Disable
For each bit in this field:
0: Corresponding sub-region is enabled.
1: Corresponding sub-region is disabled.
See “Subregions” for more information.
Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD field
as 0x00.
31 30 29 28 27 26 25 24
–XN–AP
23 22 21 20 19 18 17 16
– TEX S C B
15 14 13 12 11 10 9 8
SRD
76543210
– SIZE ENABLE
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• SIZE: Size of the MPU Protection Region
The minimum permitted value is 3 (b00010).
The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The table below gives an example of SIZE values,
with the corresponding region size and value of N in the MPU_RBAR.
Note: 1. In the MPU_RBAR, see “MPU Region Base Address Register”
• ENABLE: Region Enable
Note: For information about access permission, see “MPU Access Permission Attributes” .
SIZE Value Region Size Value of N (1) Note
b00100 (4) 32 B 5 Minimum permitted size
b01001 (9) 1 KB 10 -
b10011 (19) 1 MB 20 -
b11101 (29) 1 GB 30 -
b11111 (31) 4 GB b01100 Maximum possible size
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12.12 Glossary
This glossary describes some of the terms used in technical documents from ARM.
Abort A mechanism that indicates to a processor that the value associated with a memory access is invalid.
An abort can be caused by the external or internal memory system as a result of attempting to access
invalid instruction or data memory.
Aligned A data item stored at an address that is divisible by the number of bytes that defines the data size is
said to be aligned. Aligned words and halfwords have addresses that are divisible by four and two
respectively. The terms word-aligned and halfword-aligned therefore stipulate addresses that are
divisible by four and two respectively.
Banked register A register that has multiple physical copies, where the state of the processor determines which copy is
used. The Stack Pointer, SP (R13) is a banked register.
Base register In instruction descriptions, a register specified by a load or store instruction that is used to hold the
base value for the instruction’s address calculation. Depending on the instruction and its addressing
mode, an offset can be added to or subtracted from the base register value to form the address that is
sent to memory.
See also “Index register”
Big-endian (BE) Byte ordering scheme in which bytes of decreasing significance in a data word are stored at
increasing addresses in memory.
See also “Byte-invariant” , “Endianness” , “Little-endian (LE)” .
Big-endian memory Memory in which:
a byte or halfword at a word-aligned address is the most significant byte or halfword within the word at
that address,
a byte at a halfword-aligned address is the most significant byte within the halfword at that address.
See also “Little-endian memory” .
Breakpoint A breakpoint is a mechanism provided by debuggers to identify an instruction at which program
execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of register
contents, memory locations, variable values at fixed points in the program execution to test that the
program is operating correctly. Breakpoints are removed after the program is successfully tested.
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Byte-invariant In a byte-invariant system, the address of each byte of memory remains unchanged when switching
between little-endian and big-endian operation. When a data item larger than a byte is loaded from or
stored to memory, the bytes making up that data item are arranged into the correct order depending
on the endianness of the memory access.
An ARM byte-invariant implementation also supports unaligned halfword and word memory accesses.
It expects multi-word accesses to be word-aligned.
Condition field A four-bit field in an instruction that specifies a condition under which the instruction can execute.
Conditional execution If the condition code flags indicate that the corresponding condition is true when the instruction starts
executing, it executes normally. Otherwise, the instruction does nothing.
Context The environment that each process operates in for a multitasking operating system. In ARM
processors, this is limited to mean the physical address range that it can access in memory and the
associated memory access permissions.
Coprocessor A processor that supplements the main processor. Cortex-M4 does not support any coprocessors.
Debugger A debugging system that includes a program, used to detect, locate, and correct software faults,
together with custom hardware that supports software debugging.
Direct Memory Access
(DMA) An operation that accesses main memory directly, without the processor performing any accesses to
the data concerned.
Doubleword A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated.
Doubleword-aligned A data item having a memory address that is divisible by eight.
Endianness Byte ordering. The scheme that determines the order that successive bytes of a data word are stored
in memory. An aspect of the system’s memory mapping.
See also “Little-endian (LE)” and “Big-endian (BE)”
Exception
An event that interrupts program execution. When an exception occurs, the processor suspends the
normal program flow and starts execution at the address indicated by the corresponding exception
vector. The indicated address contains the first instruction of the handler for the exception.
An exception can be an interrupt request, a fault, or a software-generated system exception. Faults
include attempting an invalid memory access, attempting to execute an instruction in an invalid
processor state, and attempting to execute an undefined instruction.
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Exception service routine See “Interrupt handler” .
Exception vector See “Interrupt vector” .
Flat address mapping A system of organizing memory in which each physical address in the memory space is the same as
the corresponding virtual address.
Halfword A 16-bit data item.
Illegal instruction An instruction that is architecturally Undefined.
Implementation-defined The behavior is not architecturally defined, but is defined and documented by individual
implementations.
Implementation-specific The behavior is not architecturally defined, and does not have to be documented by individual
implementations. Used when there are a number of implementation options available and the option
chosen does not affect software compatibility.
Index register In some load and store instruction descriptions, the value of this register is used as an offset to be
added to or subtracted from the base register value to form the address that is sent to memory. Some
addressing modes optionally enable the index register value to be shifted prior to the addition or
subtraction.
See also “Base register” .
Instruction cycle count The number of cycles that an instruction occupies the Execute stage of the pipeline.
Interrupt handler A program that control of the processor is passed to when an interrupt occurs.
Interrupt vector One of a number of fixed addresses in low memory, or in high memory if high vectors are configured,
that contains the first instruction of the corresponding interrupt handler.
Little-endian (LE) Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing
addresses in memory.
See also “Big-endian (BE)” , “Byte-invariant” , “Endianness” .
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Little-endian memory Memory in which:
a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at
that address,
a byte at a halfword-aligned address is the least significant byte within the halfword at that address.
See also “Big-endian memory” .
Load/store architecture A processor architecture where data-processing operations only operate on register contents, not
directly on memory contents.
Memory Protection Unit
(MPU) Hardware that controls access permissions to blocks of memory. An MPU does not perform any
address translation.
Prefetching In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before
the preceding instructions have finished executing. Prefetching an instruction does not mean that the
instruction has to be executed.
Preserved Preserved by writing the same value back that has been previously read from the same field on the
same processor.
Read Reads are defined as memory operations that have the semantics of a load. Reads include the Thumb
instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.
Region A partition of memory space.
Reserved A field in a control register or instruction format is reserved if the field is to be defined by the
implementation, or produces Unpredictable results if the contents of the field are not zero. These fields
are reserved for use in future extensions of the architecture or are implementation-specific. All
reserved bits not used by the implementation must be written as 0 and read as 0.
Thread-safe In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing
shared resources, to ensure correct operation without the risk of shared access conflicts.
Thumb instruction One or two halfwords that specify an operation for a processor to perform. Thumb instructions must be
halfword-aligned.
Unaligned A data item stored at an address that is not divisible by the number of bytes that defines the data size
is said to be unaligned. For example, a word stored at an address that is not divisible by four.
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Undefined Indicates an instruction that generates an Undefined instruction exception.
Unpredictable One cannot rely on the behavior. Unpredictable behavior must not represent security holes.
Unpredictable behavior must not halt or hang the processor, or any parts of the system.
Warm reset Also known as a core reset. Initializes the majority of the processor excluding the debug controller and
debug logic. This type of reset is useful if debugging features of a processor.
Word A 32-bit data item.
Write Writes are defined as operations that have the semantics of a store. Writes include the Thumb
instructions STM, STR, STRH, STRB, and PUSH.
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13. Debug and Test Features
13.1 Description
The SAM4 Series Microcontrollers feature a number of complementary debug and test capabilities. The Serial
Wire/JTAG Debug Port (SWJ-DP) combining a Serial Wire Debug Port (SW-DP) and JTAG Debug (JTAG-DP) port
is used for standard debugging functions, such as downloading code and single-stepping through programs. It also
embeds a serial wire trace.
13.2 Embedded Characteristics
Debug access to all memory and registers in the system, including Cortex-M4 register bank when the core is
running, halted, or held in reset.
Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access
Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches
Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling
Instrumentation Trace Macrocell (ITM) for support of printf style debugging
IEEE1149.1 JTAG Boundary-can on All Digital Pins
Figure 13-1. Debug and Test Block Diagram
TST
TMS
TCK/SWCLK
TDI
JTAGSEL
TDO/TRACESWO
Boundary
TAP SWJ-DP
Reset
and
Test
POR
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13.3 Application Examples
13.3.1 Debug Environment
Figure 13-2 shows a complete debug environment example. The SWJ-DP interface is used for standard debugging
functions, such as downloading code and single-stepping through the program and viewing core and peripheral registers.
Figure 13-2. Application Debug Environment Example
13.3.2 Test Environment
Figure 13-3 shows a test environment example (JTAG Boundary scan). Test vectors are sent and interpreted by the
tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be
connected to form a single scan chain.
SAM4
Host Debugger
PC
SAM4-based Application Board
SWJ-DP
Connector
SWJ-DP
Emulator/Probe
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Figure 13-3. Application Test Environment Example
13.4 Debug and Test Pin Description
Chip 2
Chip n
Chip 1
SAM4
SAM4-based Application Board In Test
JTAG
Connector
Tester
Test Adaptor
JTAG
Probe
Table 13-1. Debug and Test Signal List
Signal Name Function Type Active Level
Reset/Test
NRST Microcontroller Reset Input/Output Low
TST Test Select Input
SWD/JTAG
TCK/SWCLK Test Clock/Serial Wire Clock Input
TDI Test Data In Input
TDO/TRACESWO Test Data Out/Trace
Asynchronous Data Out Output
TMS/SWDIO Test Mode Select/Serial Wire
Input/Output Input
JTAGSEL JTAG Selection Input High
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13.5 Functional Description
13.5.1 Test Pin
One dedicated pin, TST, is used to define the device operating mode. When this pin is at low level during power-up, the
device is in normal operating mode. When at high level, the device is in test mode or FFPI mode. The TST pin integrates
a permanent pull-down resistor of about 15 kΩ,so that it can be left unconnected for normal operation. Note that when
setting the TST pin to low or high level at power up, it must remain in the same state during the duration of the whole
operation.
13.5.2 Debug Architecture
Figure 13-4 shows the Debug Architecture used in the SAM4. The Cortex-M4 embeds four functional units for debug:
SWJ-DP (Serial Wire/JTAG Debug Port)
FPB (Flash Patch Breakpoint)
DWT (Data Watchpoint and Trace)
ITM (Instrumentation Trace Macrocell)
TPIU (Trace Port Interface Unit)
The debug architecture information that follows is mainly dedicated to developers of SWJ-DP Emulators/Probes and
debugging tool vendors for Cortex-M4 based microcontrollers. For further details on SWJ-DP see the Cortex-M4
technical reference manual.
Figure 13-4. Debug Architecture
13.5.3 Serial Wire/JTAG Debug Port (SWJ-DP)
The Cortex-M4 embeds a SWJ-DP Debug port which is the standard CoreSight™ debug port. It combines Serial Wire
Debug Port (SW-DP), from 2 to 3 pins and JTAG debug Port (JTAG-DP), 5 pins.
By default, the JTAG Debug Port is active. If the host debugger wants to switch to the Serial Wire Debug Port, it must
provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables JTAG-DP and enables SW-DP.
4 watchpoints
PC sampler
data address sampler
data sampler
interrupt trace
CPU statistics
DWT
6 breakpoints
FPB
software trace
32 channels
time stamping
ITM
SWD/JTAG
SWJ-DP
SWO trace
TPIU
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When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output
(TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP.
SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly between SWJ-DP and
JTAG boundary scan operations. A chip reset must be performed after JTAGSEL is changed.
13.5.3.1SW-DP and JTAG-DP Selection Mechanism
Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-DP is selected by
default after reset.
Switch from JTAG-DP to SW-DP. The sequence is:
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first)
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Switch from SWD to JTAG. The sequence is:
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB first)
Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
13.5.4 FPB (Flash Patch Breakpoint)
The FPB:
Implements hardware breakpoints
Patches code and data from code space to system space.
The FPB unit contains:
Two literal comparators for matching against literal loads from Code space, and remapping to a corresponding
area in System space.
Six instruction comparators for matching against instruction fetches from Code space and remapping to a
corresponding area in System space.
Alternatively, comparators can also be configured to generate a Breakpoint instruction to the processor core on a
match.
13.5.5 DWT (Data Watchpoint and Trace)
The DWT contains four comparators which can be configured to generate the following:
PC sampling packets at set intervals
PC or Data watchpoint packets
Watchpoint event to halt core
The DWT contains counters for the items that follow:
Clock cycle (CYCCNT)
Folded instructions
Load Store Unit (LSU) operations
Sleep Cycles
Table 13-2. SWJ-DP Pin List
Pin Name JTAG Port Serial Wire Debug Port
TMS/SWDIO TMS SWDIO
TCK/SWCLK TCK SWCLK
TDI TDI -
TDO/TRACESWO TDO TRACESWO (optional: trace)
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CPI (all instruction cycles except for the first cycle)
Interrupt overhead
13.5.6 ITM (Instrumentation Trace Macrocell)
The ITM is an application driven trace source that supports printf style debugging to trace Operating System (OS) and
application events, and emits diagnostic system information. The ITM emits trace information as packets which can be
generated by three different sources with several priority levels:
Software trace: Software can write directly to ITM stimulus registers. This can be done thanks to the “printf”
function. For more information, refer to Section 13.5.6.1 “How to Configure the ITM”.
Hardware trace: The ITM emits packets generated by the DWT.
Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit counter to generate the
timestamp.
13.5.6.1How to Configure the ITM
The following example describes how to output trace data in asynchronous trace mode.
Configure the TPIU for asynchronous trace mode (refer to Section 13.5.6.3 “5.4.3. How to Configure the TPIU”)
Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the Lock Access Register
(Address: 0xE0000FB0)
Write 0x00010015 into the Trace Control Register:
Enable ITM
Enable Synchronization packets
Enable SWO behavior
Fix the ATB ID to 1
Write 0x1 into the Trace Enable Register:
Enable the Stimulus port 0
Write 0x1 into the Trace Privilege Register:
Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will result in the
corresponding stimulus port being accessible in user mode.)
Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit)
The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macrocell (ITM).
The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.
13.5.6.2Asynchronous Mode
The TPIU is configured in asynchronous mode, trace data are output using the single TRACESWO pin. The
TRACESWO signal is multiplexed with the TDO signal of the JTAG Debug Port. As a consequence, asynchronous trace
mode is only available when the Serial Wire Debug mode is selected since TDO signal is used in JTAG debug mode.
Two encoding formats are available for the single pin output:
Manchester encoded stream. This is the reset value.
NRZ_based UART byte structure
13.5.6.35.4.3. How to Configure the TPIU
This example only concerns the asynchronous trace mode.
Set the TRCENA bit to 1 into the Debug Exception and Monitor Register (0xE000EDFC) to enable the use of trace
and debug blocks.
Write 0x2 into the Selected Pin Protocol Register
Select the Serial Wire Output – NRZ
Write 0x100 into the Formatter and Flush Control Register
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Set the suitable clock prescaler value into the Async Clock Prescaler Register to scale the baud rate of the
asynchronous output (this can be done automatically by the debugging tool).
13.5.7 IEEE® 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when TST is tied to low, while JTAGSEL is high during power-up, and
must be kept in this state during the whole boundary scan operation. The SAMPLE, EXTEST and BYPASS functions are
implemented. In SWD/JTAG debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the
processor. This is not IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG Boundary Scan and SWJ Debug Port operations. A chip reset must be
performed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided on Atmel’s web site to set up the test.
13.5.7.1JTAG Boundary-scan Register
The Boundary-scan Register (BSR) contains a number of bits which correspond to active pins and associated control
signals.
Each SAM4 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be
forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the
direction of the pad.
For more information, please refer to BDSL files available for the SAM4 Series.
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13.5.8 ID Code Register
Access: Read-only
• VERSION[31:28]: Product Version Number
Set to 0x0.
• PART NUMBER[27:12]: Product Part Number
• MANUFACTURER IDENTITY[11:1]
Set to 0x01F.
• Bit[0] Required by IEEE Std. 1149.1.
Set to 0x1.
31 30 29 28 27 26 25 24
VERSION PART NUMBER
23 22 21 20 19 18 17 16
PART NUMBER
15 14 13 12 11 10 9 8
PART NUMBER MANUFACTURER IDENTITY
76543210
MANUFACTURER IDENTITY 1
Chip Name Chip ID
SAM4S 0x05B32
Chip Name JTAG ID Code
SAM4S 0x05B3203F
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14. Reset Controller (RSTC)
14.1 Description
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external
components. It reports which reset occurred last.
The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor
resets.
14.2 Embedded Characteristics
Manages all Resets of the System, Including
External Devices through the NRST Pin
Processor Reset
Peripheral Set Reset
Based on Embedded Power-on Cell
Reset Source Status
Status of the Last Reset
Either Software Reset, User Reset, Watchdog Reset
External Reset Signal Shaping
14.3 Block Diagram
Figure 14-1. Reset Controller Block Diagram
NRST
proc_nreset
wd_fault
periph_nreset
SLCK
Reset
State
Manager
Reset Controller
rstc_irq
NRST
Manager exter_nreset
nrst_out
core_backup_reset
WDRPROC
user_reset
vddcore_nreset
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14.4 Functional Description
14.4.1 Reset Controller Overview
The Reset Controller is made up of an NRST Manager and a Reset State Manager. It runs at Slow Clock and generates
the following reset signals:
proc_nreset: Processor reset line. It also resets the Watchdog Timer
periph_nreset: Affects the whole set of embedded peripherals
nrst_out: Drives the NRST pin
These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset
State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of
the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets.
The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with
VDDIO, so that its configuration is saved as long as VDDIO is on.
14.4.2 NRST Manager
After power-up, NRST is an output during the ERSTL time period defined in the RSTC_MR. When ERSTL has elapsed,
the pin behaves as an input and all the system is held in reset if NRST is tied to GND by an external signal.
The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager.
Figure 14-2 shows the block diagram of the NRST Manager.
Figure 14-2. NRST Manager
14.4.2.1NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported
to the Reset State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the
bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST
is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.
The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit
URSTIEN in RSTC_MR must be written at 1.
External Reset Timer
URSTS
URSTEN
ERSTL
exter_nreset
URSTIEN
RSTC_MR
RSTC_MR
RSTC_MR
RSTC_SR
NRSTL
nrst_out
NRST
rstc_irq
Other
interrupt
sources
user_reset
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14.4.2.2NRST External Reset Control
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is
driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration,
named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an
assertion between 60 μs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven
low for a time compliant with potential external devices connected on the system reset.
As the ERSTL field is within RSTC_MR register, which is backed-up, it can be used to shape the system power-up reset
for devices requiring a longer startup time than the Slow Clock Oscillator.
14.4.3 Brownout Manager
The Brownout manager is embedded within the Supply Controller, please refer to the product Supply Controller section
for a detailed description.
14.4.4 Reset States
The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset
status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the
processor reset is released.
14.4.4.1General Reset
A general reset occurs when a Power-on-reset is detected, a Brownout or a Voltage regulation loss is detected by the
Supply controller. The vddcore_nreset signal is asserted by the Supply Controller when a general reset occurs.
All the re set si gnal s are re leas ed and t he field RS TTYP i n RSTC _SR re port s a General R eset . As the R STC_ MR is
reset, the NRST line rises 2 cycles after the vddcore_nreset, as ERSTL defaults at value 0x0.
Figure 14-3 shows how the General Reset affects the reset signals.
Figure 14-3. General Reset State
SLCK
periph_nreset
proc_nreset
NRST
(nrst_out)
EXTERNAL RESET LENGTH
= 2 cycles
MCK
Processor Startup
= 2 cycles
backup_nreset
Any
Freq.
RSTTYP XXX 0x0 = General Reset XXX
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14.4.4.2Backup Reset
A Backup reset occurs when the chip returns from Backup Mode. The core_backup_reset signal is asserted by the
Supply Controller when a Backup reset occurs.
The field RSTTYP in RSTC_SR is updated to report a Backup Reset.
14.4.4.3User Reset
The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The
NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset
are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The
processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the
value 0x4, indicating a User Reset.
The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as
programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is
driven low externally, the internal reset lines remain asserted until NRST actually rises.
Figure 14-4. User Reset State
SLCK
periph_nreset
proc_nreset
NRST
NRST
(nrst_out)
>= EXTERNAL RESET LENGTH
MCK
Processor Startup
= 2 cycles
Any
Freq.
Resynch.
2 cycles
RSTTYP Any XXX
Resynch.
2 cycles
0x4 = User Reset
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14.4.4.4Software Reset
The Reset Controller offers several commands used to assert the different reset signals. These commands are
performed by writing the Control Register (RSTC_CR) with the following bits at 1:
PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer
PERRST: Writing PERRST at 1 resets all the embedded peripherals including the memory system, and, in
particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.
Except for debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and
PROCRST set both at 1 simultaneously).
EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode
Register (RSTC_MR).
The software reset is entered if at least one of these bits is set by the software. All these commands can be performed
independently or simultaneously. The software reset lasts 3 Slow Clock cycles.
The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock
(MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.
If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the
resulting falling edge on NRST does not lead to a User Reset.
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status
Register (RSTC_SR). Other Software Resets are not reported in RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status
Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while
the SRCMP bit is set, and writing any value in RSTC_CR has no effect.
Figure 14-5. Software Reset
SLCK
periph_nreset
if PERRST=1
proc_nreset
if PROCRST=1
Write RSTC_CR
NRST
(nrst_out)
if EXTRST=1 EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 2 cycles
Any
Freq.
RSTTYP Any XXX 0x3 = Software Reset
Resynch.
1 cycle
SRCMP in RSTC_SR
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14.4.4.5Watchdog Reset
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:
If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted,
depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a
User Reset state.
If WDRPROC = 1, only the processor reset is asserted.
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if
WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default
and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.
Figure 14-6. Watchdog Reset
Only if
WDRPROC = 0
SLCK
periph_nreset
proc_nreset
wd_fault
NRST
(nrst_out)
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
MCK
Processor Startup
= 2 cycles
Any
Freq.
RSTTYP Any XXX 0x2 = Watchdog Reset
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14.4.5 Reset State Priorities
The Reset State Manager manages the following priorities between the different reset sources, given in descending
order:
General Reset
Backup Reset
Watchdog Reset
Software Reset
User Reset
Particular cases are listed below:
When in User Reset:
A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.
A software reset is impossible, since the processor reset is being activated.
When in Software Reset:
A watchdog event has priority over the current state.
The NRST has no effect.
When in Watchdog Reset:
The processor reset is active and so a Software Reset cannot be programmed.
A User Reset cannot be entered.
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14.4.6 Reset Controller Status Register
The Reset Controller status register (RSTC_SR) provides several status fields:
RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset
should be performed until the end of the current one. This bit is automatically cleared at the end of the current
software reset.
NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising
edge.
URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is
also detected on the Master Clock (MCK) rising edge (see Figure 14-7). If the User Reset is disabled (URSTEN =
0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an
interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt.
Figure 14-7. Reset Controller Status and Interrupt
MCK
NRST
NRSTL
2 cycle
resynchronization 2 cycle
resynchronization
URSTS
read
RSTC_SR
Peripheral Access
rstc_irq
if (URSTEN = 0) and
(URSTIEN = 1)
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14.5 Reset Controller (RSTC) User Interface
Table 14-1. Register Mapping
Offset Register Name Access Reset
0x00 Control Register RSTC_CR Write-only -
0x04 Status Register RSTC_SR Read-only 0x0000_0000
0x08 Mode Register RSTC_MR Read-write 0x0000 0001
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14.5.1 Reset Controller Control Register
Name: RSTC_CR
Address: 0x400E1400
Access: Write-only
• PROCRST: Processor Reset
0 = No effect.
1 = If KEY is correct, resets the processor.
• PERRST: Peripheral Reset
0 = No effect.
1 = If KEY is correct, resets the peripherals.
• EXTRST: External Reset
0 = No effect.
1 = If KEY is correct, asserts the NRST pin and resets the processor and the peripherals.
• KEY: System Reset Key
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – EXTRST PERRST – PROCRST
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14.5.2 Reset Controller Status Register
Name: RSTC_SR
Address: 0x400E1404
Access: Read-only
• URSTS: User Reset Status
0 = No high-to-low edge on NRST happened since the last read of RSTC_SR.
1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
• RSTTYP: Reset Type
Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
• NRSTL: NRST Pin Level
Registers the NRST Pin Level at Master Clock (MCK).
• SRCMP: Software Reset Command in Progress
0 = No software command is being performed by the reset controller. The reset controller is ready for a software command.
1 = A software reset command is being performed by the reset controller. The reset controller is busy.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – – – SRCMP NRSTL
15 14 13 12 11 10 9 8
– – – – – RSTTYP
76543210
–––––––URSTS
RSTTYP Reset Type Comments
0 0 0 General Reset First power-up Reset
0 0 1 Backup Reset Return from Backup Mode
0 1 0 Watchdog Reset Watchdog fault occurred
0 1 1 Software Reset Processor reset required by the software
1 0 0 User Reset NRST pin detected low
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14.5.3 Reset Controller Mode Register
Name: RSTC_MR
Address: 0x400E1408
Access: Read-write
• URSTEN: User Reset Enable
0 = The detection of a low level on the pin NRST does not generate a User Reset.
1 = The detection of a low level on the pin NRST triggers a User Reset.
• URSTIEN: User Reset Interrupt Enable
0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• ERSTL: External Reset Length
This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This
allows assertion duration to be programmed between 60 μs and 2 seconds.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – ERSTL
76543210
– – URSTIEN – – – URSTEN
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15. Real-time Timer (RTT)
15.1 Description
The Real-time Timer is built around a 32-bit counter used to count roll-over events of the programmable 16-bit prescaler
which enables counting elapsed seconds from a 32 kHz slow clock source. It generates a periodic interrupt and/or
triggers an alarm on a programmed value.
It can be configured to be driven by the 1 Hz signal generated by the RTC, thus taking advantage of a calibrated 1 Hz
clock.
The slow clock source can be fully disabled to reduce power consumption when RTT is not required.
15.2 Embedded Characteristics
32-bit Free-running Counter on prescaled slow clock or RTC calibrated 1 Hz clock
16-bit Configurable Prescaler
Interrupt on Alarm
15.3 Block Diagram
Figure 15-1. Real-time Timer
15.4 Functional Description
The Real-time Timer can be used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided
by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register
(RTT_MR).
Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock
is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to
0.
SLCK
RTPRES
RTTINC
ALMS
16-bit
Divider
32-bit
Counter
ALMV =
CRTV
RTT_MR
RTT_VR
RTT_AR
RTT_SR
RTTINCIEN
RTT_MR
0
10
ALMIEN
rtt_int
RTT_MR
set
set
RTT_SR
read
RTT_SR
reset
reset
RTT_MR
reload
rtt_alarm
RTTRST
RTT_MR
RTTRST
RTT_MR
RTTDIS
10
RTT_MR
CLKSRC
RTC 1Hz
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The real-time 32-bit counter can also be supplied by the RTC 1 Hz clock. This mode is interesting when the RTC 1Hz is
calibrated (CORRECTION field of RTC_MR register differs from 0) in order to guaranty the synchronism between RTC
and RTT counters.
Setting the RTC 1HZ clock to 1 in RTT_MR register allows to drive the 32-bit RTT counter with the RTC 1Hz clock. In this
mode, RTTPRESC field has no effect.
The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by
writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the
status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the
interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt
handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear.
The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this
value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value
to improve accuracy of the returned value.
The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm
Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its
maximum value, corresponding to 0xFFFF_FFFF, after a reset.
The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a
periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to
32.768 Hz.
Reading the RTT_SR status register resets the RTTINC and ALMS fields.
Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value.
This also resets the 32-bit counter.
When not used, the Real-time Timer can be disabled in order to suppress dynamic power consumption in this module.
This can be achieved by setting the RTTDIS field to 1 in RTT_MR register.
Figure 15-2. RTT Counting
Prescaler
ALMVALMV-10 ALMV+1
0
RTPRES - 1
RTT
APB cycle
read RTT_SR
ALMS (RTT_SR)
APB Interface
SCLK
RTTINC (RTT_SR)
ALMV+2 ALMV+3
...
APB cycle
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15.5 Real-time Timer (RTT) User Interface
Table 15-1. Register Mapping
Offset Register Name Access Reset
0x00 Mode Register RTT_MR Read-write 0x0000_8000
0x04 Alarm Register RTT_AR Read-write 0xFFFF_FFFF
0x08 Value Register RTT_VR Read-only 0x0000_0000
0x0C Status Register RTT_SR Read-only 0x0000_0000
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15.5.1 Real-time Timer Mode Register
Name: RTT_MR
Address: 0x400E1430
Access: Read-write
• RTPRES: Real-time Timer Prescaler Value
Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows:
RTPRES = 0: The prescaler period is equal to 216 * SCLK period.
RTPRES ≠ 0: The prescaler period is equal to RTPRES * SCLK period.
• ALMIEN: Alarm Interrupt Enable
0 = The bit ALMS in RTT_SR has no effect on interrupt.
1 = The bit ALMS in RTT_SR asserts interrupt.
• RTTINCIEN: Real-time Timer Increment Interrupt Enable
0 = The bit RTTINC in RTT_SR has no effect on interrupt.
1 = The bit RTTINC in RTT_SR asserts interrupt.
• RTTRST: Real-time Timer Restart
0 = No effect.
1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.
• RTTDIS: Real-time Timer Disable
0 = The real-time timer is enabled.
1 = The real-time timer is disabled (no dynamic power consumption).
• RTC1HZ: Real-Time Clock 1Hz Clock Selection
0 = The RTT 32-bit counter is driven by the 16-bit prescaler roll-over events.
1 = The RTT 32-bit counter is driven by the RTC 1 Hz clock.
31 30 29 28 27 26 25 24
–––––––RTC1HZ
23 22 21 20 19 18 17 16
– – – RTTDIS – RTTRST RTTINCIEN ALMIEN
15 14 13 12 11 10 9 8
RTPRES
76543210
RTPRES
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15.5.2 Real-time Timer Alarm Register
Name: RTT_AR
Address: 0x400E1434
Access: Read-write
• ALMV: Alarm Value
Defines the alarm value (ALMV+1) compared with the Real-time Timer.
15.5.3 Real-time Timer Value Register
Name: RTT_VR
Address: 0x400E1438
Access: Read-only
• CRTV: Current Real-time Value
Returns the current value of the Real-time Timer.
31 30 29 28 27 26 25 24
ALMV
23 22 21 20 19 18 17 16
ALMV
15 14 13 12 11 10 9 8
ALMV
76543210
ALMV
31 30 29 28 27 26 25 24
CRTV
23 22 21 20 19 18 17 16
CRTV
15 14 13 12 11 10 9 8
CRTV
76543210
CRTV
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15.5.4 Real-time Timer Status Register
Name: RTT_SR
Address: 0x400E143C
Access: Read-only
• ALMS: Real-time Alarm Status
0 = The Real-time Alarm has not occurred since the last read of RTT_SR.
1 = The Real-time Alarm occurred since the last read of RTT_SR.
• RTTINC: Real-time Timer Increment
0 = The Real-time Timer has not been incremented since the last read of the RTT_SR.
1 = The Real-time Timer has been incremented since the last read of the RTT_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – – – RTTINC ALMS
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16. Real-time Clock (RTC)
16.1 Description
The Real-time Clock (RTC) peripheral is designed for very low power consumption.
It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian or Persian calendar,
complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data
bus.
The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or
12-hour mode with an AM/PM indicator.
Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data
bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible
date according to the current month/year/century.
A clock divider calibration circuitry enables to compensate crystal oscillator frequency inaccuracy.
An RTC output can be programmed to generate several waveforms, including a prescaled clock derived from 32.768 kHz
16.2 Embedded Characteristics
Ultra Low Power Consumption
Full Asynchronous Design
Gregorian Calendar up to 2099 or Persian Calendar
Programmable Periodic Interrupt
Safety/security features:
Valid Time and Date Programmation Check
On-The-Fly Time and Date Validity Check
Crystal Oscillator Clock Calibration
Waveform Generation
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16.3 Block Diagram
Figure 16-1. RTC Block Diagram
16.4 Product Dependencies
16.4.1 Power Management
The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC
behavior.
16.4.2 Interrupt
RTC interrupt line is connected on one of the internal sources of the interrupt controller. RTC interrupt requires the
interrupt controller to be programmed first.
User Interface
32768 Divider Time
Slow Clock: SLCK
APB
Date
RTC Interrupt
Entry
Control Interrupt
Control
Clock Calibration
RTCOUT0
RTCOUT1
Wave
Generator
Alarm
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16.5 Functional Description
The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month,
date, day, hours, minutes and seconds.
The valid year range is 1900 to 2099 in Gregorian mode, a two-hundred-year calendar (or 1300 to 1499 in Persian
mode).
The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator.
Corrections for leap years are included (all years divisible by 4 being leap years). This is correct up to the year 2099.
The RTC can generate configurable waveforms on RTCOUT0/1 outputs.
16.5.1 Reference Clock
The reference clock is Slow Clock (SLCK). It can be driven internally or by an external 32.768 kHz crystal.
During low power modes of the processor, the oscillator runs and power consumption is critical. The crystal selection has
to take into account the current consumption for power saving and the frequency drift due to temperature effect on the
circuit for time accuracy.
16.5.2 Timing
The RTC is updated in real time at one-second intervals in normal mode for the counters of seconds, at one-minute
intervals for the counter of minutes and so on.
Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the
RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read
these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of
three accesses are required.
16.5.3 Alarm
The RTC has five programmable fields: month, date, hours, minutes and seconds.
Each of these fields can be enabled or disabled to match the alarm condition:
If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt
generated if enabled) at a given month, date, hour/minute/second.
If only the “seconds” field is enabled, then an alarm is generated every minute.
Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from
minutes to 365/366 days.
Hour, minute and second matching alarm (SECEN, MINEN, HOUREN) can be enabled independently of SEC, MIN,
HOUR fields.
Note: To change one of the SEC, MIN, HOUR, DATE, MONTH fields, it is recommended to disable the field before
changing the value and then re-enable it after the change has been made. This requires up to 3 accesses to the
RTC_TIMALR or RTC_CALALR registers. The first access clears the enable corresponding to the field to
change (SECEN,MINEN,HOUREn,DATEEN,MTHEN). If the field is already cleared, this access is not required.
The second access performs the change of the value (SEC, MIN, HOUR, DATE, MONTH). The third access is
required to re-enable the field by writing 1 in SECEN,MINEN,HOUREn,DATEEN,MTHEN fields.
16.5.4 Error Checking when Programming
Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes,
seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year
and century configured.
If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity
register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any
further side effects in the hardware. The same procedure is done for the alarm.
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The following checks are performed:
1. Century (check if it is in range 19 - 20 or 13-14 in Persian mode)
2. Year (BCD entry check)
3. Date (check range 01 - 31)
4. Month (check if it is in BCD range 01 - 12, check validity regarding “date”)
5. Day (check range 1 - 7)
6. Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is not set if RTC is set in 24-
hour mode; in 12-hour mode check range 01 - 12)
7. Minute (check BCD and range 00 - 59)
8. Second (check BCD and range 00 - 59)
Note: If the 12-hour mode is selected by means of the RTC_MR register, a 12-hour value can be programmed and the
returned value on RTC_TIMR will be the corresponding 24-hour value. The entry control checks the value of the
AM/PM indicator (bit 22 of RTC_TIMR register) to determine the range to be checked.
16.5.5 RTC Internal Free Running Counter Error Checking
To improve the reliability and security of the RTC, a permanent check is performed on the internal free running counters
to report non-BCD or invalid date/time values.
An error is reported by TDERR bit in the status register (RTC_SR) if an incorrect value has been detected. The flag can
be cleared by programming the TDERRCLR in the RTC status clear control register (RTC_SCCR).
Anyway the TDERR error flag will be set again if the source of the error has not been cleared before clearing the TDERR
flag. The clearing of the source of such error can be done either by reprogramming a correct value on RTC_CALR and/or
RTC_TIMR registers.
The RTC internal free running counters may automatically clear the source of TDERR due to their roll-over (i.e. every 10
seconds for SECONDS[3:0] bitfield in RTC_TIMR register). In this case the TDERR is held high until a clear command is
asserted by TDERRCLR bit in RTC_SCCR register.
16.5.6 Updating Time/Calendar
To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the
Control Register. Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to
update calendar fields (century, year, month, date, day).
Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status Register. Once the bit reads 1, it
is mandatory to clear this flag by writing the corresponding bit in RTC_SCCR. The user can now write to the appropriate
Time and Calendar register.
Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control
When entering programming mode of the calendar fields, the time fields remain enabled. When entering the
programming mode of the time fields, both time and calendar fields are stopped. This is due to the location of the
calendar logic circuity (downstream for low-power considerations). It is highly recommended to prepare all the fields to be
updated before entering programming mode. In successive update operations, the user must wait at least one second
after resetting the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these bits again. This is done
by waiting for the SEC flag in the Status Register before setting UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL,
the SEC flag must also be cleared.
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Figure 16-2. Update Sequence
Prepare TIme or Calendar Fields
Set UPDTIM and/or UPDCAL
bit(s) in RTC_CR
Read RTC_SR
ACKUPD
= 1 ?
Clear ACKUPD bit in RTC_SCCR
Update Time and/or Calendar values in
RTC_TIMR/RTC_CALR
Clear UPDTIM and/or UPDCAL bit in
RTC_CR
No
Yes
Begin
End
Polling or
IRQ (if enabled)
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16.5.7 RTC Accurate Clock Calibration
The crystal oscillator that drives the RTC may not be as accurate as expected mainly due to temperature variation. The
RTC is equipped with circuitry able to correct slow clock crystal drift.
To compensate for possible temperature variations over time, this accurate clock calibration circuitry can be programmed
on-the-fly and also programmed during application manufacturing, in order to correct the crystal frequency accuracy at
room temperature (20-25°C). The typical clock drift range at room temperature is ±20 ppm.
In the device operating temperature range, the 32.768 kHz crystal oscillator clock inaccuracy can be up to -200 ppm.
The RTC clock calibration circuitry allows positive or negative correction in a range of 1.5 ppm to 1950 ppm. After
correction, the remaining crystal drift is as follows:
Below 1 ppm, for an initial crystal drift between 1.5 ppm up to 90 ppm
Below 2 ppm, for an initial crystal drift between 90 ppm up to 130 ppm
Below 5 ppm, for an initial crystal drift between 130 ppm up to 200 ppm
The calibration circuitry acts by slightly modifying the 1 Hz clock period from time to time. When the period is modified,
depending on the sign of the correction, the 1 Hz clock period increases or reduces by around 4 ms. The period interval
between 2 correction events is programmable in order to cover the possible crystal oscillator clock variations.
The inaccuracy of a crystal oscillator at typical room temperature (±20 ppm at 20-25 degrees Celsius) can be
compensated if a reference clock/signal is used to measure such inaccuracy. This kind of calibration operation can be set
up during the final product manufacturing by means of measurement equipment embedding such a reference clock. The
correction of value must be programmed into the RTC Mode Register (RTC_MR), and this value is kept as long as the
circuitry is powered (backup area). Removing the backup power supply cancels this calibration. This room temperature
calibration can be further processed by means of the networking capability of the target application.
To ease the comparison of the inherent crystal accuracy with the reference clock/signal during manufacturing, an internal
prescaled 32.768 kHz clock derivative signal can be assigned to drive RTC output. To accommodate the measure,
several clock frequencies can be selected among 1 Hz, 32 Hz, 64 Hz, 512 Hz.
In any event, this adjustment does not take into account the temperature variation.
The frequency drift (up to -200 ppm) due to temperature variation can be compensated using a reference time if the
application can access such a reference. If a reference time cannot be used, a temperature sensor can be placed close
to the crystal oscillator in order to get the operating temperature of the crystal oscillator. Once obtained, the temperature
may be converted using a lookup table (describing the accuracy/temperature curve of the crystal oscillator used) and
RTC_MR configured accordingly. The calibration can be performed on-the-fly. This adjustment method is not based on a
measurement of the crystal frequency/drift and therefore can be improved by means of the networking capability of the
target application.
If no crystal frequency adjustment has been done during manufacturing, it is still possible to do it. In the case where a
reference time of the day can be obtained through LAN/WAN network, it is possible to calculate the drift of the application
crystal oscillator by comparing the values read on RTC Time Register (RTC_TIMR) and programming the HIGHPPM and
CORRECTION bitfields on RTC_MR according to the difference measured between the reference time and those of
RTC_TIMR.
16.5.8 Waveform Generation
Waveforms can be generated by the RTC in order to take advantage of the RTC inherent prescalers while the RTC is the
only powered circuitry (low power mode of operation, backup mode) or in any active modes. Going into backup or low
power operating modes does not affect the waveform generation outputs.
The RTC outputs (RTCOUT0 and RTCOUT1) have a source driver selected among 7 possibilities.
The first selection choice sticks the associated output at 0 (This is the reset value and it can be used at any time to
disable the waveform generation).
Selection choices 1 to 4 respectively select 1 Hz, 32 Hz, 64 Hz and 512 Hz.
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32 Hz or 64 Hz can drive, for example, a TN LCD backplane signal while 1 Hz can be used to drive a blinking character
like “:” for basic time display (hour, minute) on TN LCDs.
Selection choice 5 provides a toggling signal when the RTC alarm is reached.
Selection choice 6 provides a copy of the alarm flag, so the associated output is set high (logical 1) when an alarm occurs
and immediately cleared when software clears the alarm interrupt source.
Selection choice 7 provides a 1 Hz periodic high pulse of 15 μs duration that can be used to drive external devices for
power consumption reduction or any other purpose.
PIO lines associated to RTC outputs are automatically selecting these waveforms as soon as RTC_MR register
corresponding fields OUT0 and OUT1 differ from 0.
Figure 16-3. Waveform Generation
RTCOUT1
‘0’
1 Hz
32 Hz
64 Hz
512 Hz
toggle_alarm
ag_alarm
pulse
0
1
2
3
4
5
6
7
RTC_MR(OUT1)
RTCOUT0
‘0’
1 Hz
32 Hz
64 Hz
512 Hz
toggle_alarm
ag_alarm
pulse
0
1
2
3
4
5
6
7
RTC_MR(OUT0)
ag_alarm
alarm match
event 1
RTC_SCCR(ALRCLR)
alarm match
event 2
RTC_SCCR(ALRCLR)
toggle_alarm
pulse
Tperiod Tperiod
Thigh
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16.6 Real-time Clock (RTC) User Interface
Note: If an offset is not listed in the table it must be considered as reserved.
Table 16-1. Register Mapping
Offset Register Name Access Reset
0x00 Control Register RTC_CR Read-write 0x0
0x04 Mode Register RTC_MR Read-write 0x0
0x08 Time Register RTC_TIMR Read-write 0x0
0x0C Calendar Register RTC_CALR Read-write 0x01A11020
0x10 Time Alarm Register RTC_TIMALR Read-write 0x0
0x14 Calendar Alarm Register RTC_CALALR Read-write 0x01010000
0x18 Status Register RTC_SR Read-only 0x0
0x1C Status Clear Command Register RTC_SCCR Write-only –
0x20 Interrupt Enable Register RTC_IER Write-only –
0x24 Interrupt Disable Register RTC_IDR Write-only –
0x28 Interrupt Mask Register RTC_IMR Read-only 0x0
0x2C Valid Entry Register RTC_VER Read-only 0x0
0x30–0xC4 Reserved Register – – –
0xC8–0xF8 Reserved Register – – –
0xFC Reserved Register – – –
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16.6.1 RTC Control Register
Name: RTC_CR
Address: 0x400E1460
Access: Read-write
• UPDTIM: Update Request Time Register
0 = No effect.
1 = Stops the RTC time counting.
Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowl-
edged by the bit ACKUPD of the Status Register.
• UPDCAL: Update Request Calendar Register
0 = No effect.
1 = Stops the RTC calendar counting.
Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit
is set.
• TIMEVSEL: Time Event Selection
The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL.
• CALEVSEL: Calendar Event Selection
The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––– CALEVSEL
15 14 13 12 11 10 9 8
–––––– TIMEVSEL
76543210
––––––UPDCAL UPDTIM
Value Name Description
0 MINUTE Minute change
1 HOUR Hour change
2 MIDNIGHT Every day at midnight
3 NOON Every day at noon
Value Name Description
0 WEEK Week change (every Monday at time 00:00:00)
1 MONTH Month change (every 01 of each month at time 00:00:00)
2 YEAR Year change (every January 1 at time 00:00:00)
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16.6.2 RTC Mode Register
Name: RTC_MR
Address: 0x400E1464
Access: Read-write
• HRMOD: 12-/24-hour Mode
0 = 24-hour mode is selected.
1 = 12-hour mode is selected.
• PERSIAN: PERSIAN Calendar
0 = Gregorian Calendar.
1 = Persian Calendar.
• NEGPPM: NEGative PPM Correction
0 = positive correction (the divider will be slightly lower than 32768).
1 = negative correction (the divider will be slightly higher than 32768).
Refer to CORRECTION and HIGHPPM field descriptions.
• CORRECTION: Slow Clock Correction
0 = No correction
1..127 = The slow clock will be corrected according to the formula given below in HIGHPPM description.
• HIGHPPM: HIGH PPM Correction
0 = lower range ppm correction with accurate correction.
1 = higher range ppm correction with accurate correction.
If the absolute value of the correction to be applied is lower than 30ppm, it is recommended to clear HIGHPPM. HIGHPPM set to
1 is recommended for 30 ppm correction and above.
Formula:
If HIGHPPM = 0, then the clock frequency correction range is from 1.5 ppm up to 98 ppm. The RTC accuracy is less
than 1 ppm for a range correction from 1.5 ppm up to 30 ppm..
The correction field must be programmed according to the required correction in ppm, the formula is as follows:
31 30 29 28 27 26 25 24
– – TPERIOD – THIGH
23 22 21 20 19 18 17 16
– OUT1 – OUT0
15 14 13 12 11 10 9 8
HIGHPPM CORRECTION
76543210
– – – NEGPPM – – PERSIAN HRMOD
CORRECTION 3906
20 ppm×
------------------------ 1–=
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The value obtained must be rounded to the nearest integer prior to being programmed into CORRECTION field.
If HIGHPPM = 1, then the clock frequency correction range is from 30.5 ppm up to 1950 ppm. The RTC accuracy is less
than 1 ppm for a range correction from 30.5 ppm up to 90 ppm.
The correction field must be programmed according to the required correction in ppm, the formula is as follows:
The value obtained must be rounded to the nearest integer prior to be programmed into CORRECTION field.
If NEGPPM is set to 1, the ppm correction is negative.
• OUT0: RTCOUT0 Output Source Selection
• OUT1: RTCOUT1 Output Source Selection
• THIGH: High Duration of the Output Pulse
Value Name Description
0 NO_WAVE no waveform, stuck at ‘0’
1 FREQ1HZ 1 Hz square wave
2 FREQ32HZ 32 Hz square wave
3 FREQ64HZ 64 Hz square wave
4 FREQ512HZ 512 Hz square wave
5 ALARM_TOGGLE output toggles when alarm flag rises
6 ALARM_FLAG output is a copy of the alarm flag
7 PROG_PULSE duty cycle programmable pulse
Value Name Description
0 NO_WAVE no waveform, stuck at ‘0’
1 FREQ1HZ 1 Hz square wave
2 FREQ32HZ 32 Hz square wave
3 FREQ64HZ 64 Hz square wave
4 FREQ512HZ 512 Hz square wave
5 ALARM_TOGGLE output toggles when alarm flag rises
6 ALARM_FLAG output is a copy of the alarm flag
7 PROG_PULSE duty cycle programmable pulse
Value Name Description
0 H_31MS 31.2 ms
1 H_16MS 15.6 ms
2 H_4MS 3.91 Oms
3 H_976US 976 μs
4 H_488US 488 μs
CORRECTION 3906
ppm
-------------1–=
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• TPERIOD: Period of the Output Pulse
5 H_122US 122 μs
6 H_30US 30.5 μs
7 H_15US 15.2 μs
Value Name Description
0 P_1S 1 second
1 P_500MS 500 ms
2 P_250MS 250 ms
3 P_125MS 125 ms
Value Name Description
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16.6.3 RTC Time Register
Name: RTC_TIMR
Address: 0x400E1468
Access: Read-write
• SEC: Current Second
The range that can be set is 0 - 59 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• MIN: Current Minute
The range that can be set is 0 - 59 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• HOUR: Current Hour
The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode.
• AMPM: Ante Meridiem Post Meridiem Indicator
This bit is the AM/PM indicator in 12-hour mode.
0 = AM.
1 = PM.
All non-significant bits read zero.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– AMPM HOUR
15 14 13 12 11 10 9 8
–MIN
76543210
– SEC
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16.6.4 RTC Calendar Register
Name: RTC_CALR
Address: 0x400E146C
Access: Read-write
• CENT: Current Century
The range that can be set is 19 - 20 (gregorian) or 13-14 (persian) (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• YEAR: Current Year
The range that can be set is 00 - 99 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• MONTH: Current Month
The range that can be set is 01 - 12 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
• DAY: Current Day in Current Week
The range that can be set is 1 - 7 (BCD).
The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter.
• DATE: Current Day in Current Month
The range that can be set is 01 - 31 (BCD).
The lowest four bits encode the units. The higher bits encode the tens.
All non-significant bits read zero.
31 30 29 28 27 26 25 24
–– DATE
23 22 21 20 19 18 17 16
DAY MONTH
15 14 13 12 11 10 9 8
YEAR
76543210
– CENT
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16.6.5 RTC Time Alarm Register
Name: RTC_TIMALR
Address: 0x400E1470
Access: Read-write
Note: To change one of the SEC, MIN, HOUR fields, it is recommended to disable the field before changing the value and
then re-enable it after the change has been made. This requires up to 3 accesses to the RTC_TIMALR register. The
first access clears the enable corresponding to the field to change (SECEN,MINEN,HOUREN). If the field is already
cleared, this access is not required. The second access performs the change of the value (SEC, MIN, HOUR). The
third access is required to re-enable the field by writing 1 in SECEN, MINEN, HOUREN fields.
• SEC: Second Alarm
This field is the alarm field corresponding to the BCD-coded second counter.
• SECEN: Second Alarm Enable
0 = The second-matching alarm is disabled.
1 = The second-matching alarm is enabled.
• MIN: Minute Alarm
This field is the alarm field corresponding to the BCD-coded minute counter.
• MINEN: Minute Alarm Enable
0 = The minute-matching alarm is disabled.
1 = The minute-matching alarm is enabled.
• HOUR: Hour Alarm
This field is the alarm field corresponding to the BCD-coded hour counter.
• AMPM: AM/PM Indicator
This field is the alarm field corresponding to the BCD-coded hour counter.
• HOUREN: Hour Alarm Enable
0 = The hour-matching alarm is disabled.
1 = The hour-matching alarm is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
HOUREN AMPM HOUR
15 14 13 12 11 10 9 8
MINEN MIN
76543210
SECEN SEC
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16.6.6 RTC Calendar Alarm Register
Name: RTC_CALALR
Address: 0x400E1474
Access: Read-write
Note: To change one of the DATE, MONTH fields, it is recommended to disable the field before changing the value and
then re-enable it after the change has been made. This requires up to 3 accesses to the RTC_CALALR register. The
first access clears the enable corresponding to the field to change (DATEEN,MTHEN). If the field is already cleared,
this access is not required. The second access performs the change of the value (DATE,MONTH). The third access is
required to re-enable the field by writing 1 in DATEEN, MTHEN fields.
• MONTH: Month Alarm
This field is the alarm field corresponding to the BCD-coded month counter.
• MTHEN: Month Alarm Enable
0 = The month-matching alarm is disabled.
1 = The month-matching alarm is enabled.
• DATE: Date Alarm
This field is the alarm field corresponding to the BCD-coded date counter.
• DATEEN: Date Alarm Enable
0 = The date-matching alarm is disabled.
1 = The date-matching alarm is enabled.
31 30 29 28 27 26 25 24
DATEEN – DATE
23 22 21 20 19 18 17 16
MTHEN – – MONTH
15 14 13 12 11 10 9 8
––––––––
76543210
––––––––
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16.6.7 RTC Status Register
Name: RTC_SR
Address: 0x400E1478
Access: Read-only
• ACKUPD: Acknowledge for Update
0 (FREERUN) = Time and calendar registers cannot be updated.
1 (UPDATE) = Time and calendar registers can be updated.
• ALARM: Alarm Flag
0 (NO_ALARMEVENT) = No alarm matching condition occurred.
1 (ALARMEVENT) = An alarm matching condition has occurred.
• SEC: Second Event
0 (NO_SECEVENT) = No second event has occurred since the last clear.
1 (SECEVENT) = At least one second event has occurred since the last clear.
• TIMEV: Time Event
0 (NO_TIMEVENT) = No time event has occurred since the last clear.
1 (TIMEVENT) = At least one time event has occurred since the last clear.
The time event is selected in the TIMEVSEL field in RTC_CR (Control Register) and can be any one of the following events: min-
ute change, hour change, noon, midnight (day change).
• CALEV: Calendar Event
0 (NO_CALEVENT) = No calendar event has occurred since the last clear.
1 (CALEVENT) = At least one calendar event has occurred since the last clear.
The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change,
month change and year change.
• TDERR: Time and/or Date Free Running Error
0 (CORRECT) = The internal free running counters are carrying valid values since the last read of RTC_SR.
1 (ERR_TIMEDATE) = The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the
last read and/or they are still invalid.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – TDERR CALEV TIMEV SEC ALARM ACKUPD
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16.6.8 RTC Status Clear Command Register
Name: RTC_SCCR
Address: 0x400E147C
Access: Write-only
• ACKCLR: Acknowledge Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• ALRCLR: Alarm Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• SECCLR: Second Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• TIMCLR: Time Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• CALCLR: Calendar Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
• TDERRCLR: Time and/or Date Free Running Error Clear
0 = No effect.
1 = Clears corresponding status flag in the Status Register (RTC_SR).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – TDERRCLR CALCLR TIMCLR SECCLR ALRCLR ACKCLR
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16.6.9 RTC Interrupt Enable Register
Name: RTC_IER
Address: 0x400E1480
Access: Write-only
• ACKEN: Acknowledge Update Interrupt Enable
0 = No effect.
1 = The acknowledge for update interrupt is enabled.
• ALREN: Alarm Interrupt Enable
0 = No effect.
1 = The alarm interrupt is enabled.
• SECEN: Second Event Interrupt Enable
0 = No effect.
1 = The second periodic interrupt is enabled.
• TIMEN: Time Event Interrupt Enable
0 = No effect.
1 = The selected time event interrupt is enabled.
• CALEN: Calendar Event Interrupt Enable
0 = No effect.
1 = The selected calendar event interrupt is enabled.
• TDERREN: Time and/or Date Error Interrupt Enable
0 = No effect.
1 = The time and date error interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – TDERREN CALEN TIMEN SECEN ALREN ACKEN
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16.6.10 RTC Interrupt Disable Register
Name: RTC_IDR
Address: 0x400E1484
Access: Write-only
• ACKDIS: Acknowledge Update Interrupt Disable
0 = No effect.
1 = The acknowledge for update interrupt is disabled.
• ALRDIS: Alarm Interrupt Disable
0 = No effect.
1 = The alarm interrupt is disabled.
• SECDIS: Second Event Interrupt Disable
0 = No effect.
1 = The second periodic interrupt is disabled.
• TIMDIS: Time Event Interrupt Disable
0 = No effect.
1 = The selected time event interrupt is disabled.
• CALDIS: Calendar Event Interrupt Disable
0 = No effect.
1 = The selected calendar event interrupt is disabled.
• TDERRDIS: Time and/or Date Error Interrupt Disable
0 = No effect.
• 1 = The time and date error interrupt is disabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – TDERRDIS CALDIS TIMDIS SECDIS ALRDIS ACKDIS
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16.6.11 RTC Interrupt Mask Register
Name: RTC_IMR
Address: 0x400E1488
Access: Read-only
• ACK: Acknowledge Update Interrupt Mask
0 = The acknowledge for update interrupt is disabled.
1 = The acknowledge for update interrupt is enabled.
• ALR: Alarm Interrupt Mask
0 = The alarm interrupt is disabled.
1 = The alarm interrupt is enabled.
• SEC: Second Event Interrupt Mask
0 = The second periodic interrupt is disabled.
1 = The second periodic interrupt is enabled.
• TIM: Time Event Interrupt Mask
0 = The selected time event interrupt is disabled.
1 = The selected time event interrupt is enabled.
• CAL: Calendar Event Interrupt Mask
0 = The selected calendar event interrupt is disabled.
1 = The selected calendar event interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – CAL TIM SEC ALR ACK
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16.6.12 RTC Valid Entry Register
Name: RTC_VER
Address: 0x400E148C
Access: Read-only
• NVTIM: Non-valid Time
0 = No invalid data has been detected in RTC_TIMR (Time Register).
1 = RTC_TIMR has contained invalid data since it was last programmed.
• NVCAL: Non-valid Calendar
0 = No invalid data has been detected in RTC_CALR (Calendar Register).
1 = RTC_CALR has contained invalid data since it was last programmed.
• NVTIMALR: Non-valid Time Alarm
0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register).
1 = RTC_TIMALR has contained invalid data since it was last programmed.
• NVCALALR: Non-valid Calendar Alarm
0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register).
1 = RTC_CALALR has contained invalid data since it was last programmed.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––NVCALALR NVTIMALR NVCAL NVTIM
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17. Watchdog Timer (WDT)
17.1 Description
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a
12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a
general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode.
17.2 Embedded Characteristics
12-bit Key-protected Programmable Counter
Provides Reset or Interrupt Signals to the System
Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
17.3 Block Diagram
Figure 17-1. Watchdog Timer Block Diagram
17.4 Functional Description
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied
with VDDCORE. It restarts with initial values on processor reset.
The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode
Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog
period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
After a Pro cessor Reset, the value of W DV is 0xFFF, corres ponding to the maxi mum value of the counter wit h the
external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default Watchdog is
=0
10
set
reset
read WDT_SR
or
reset
wdt_fault
(to Reset Controller)
set
reset
WDFIEN
wdt_int
WDT_MR
SLCK
1/128
12-bit Down
Counter
Current
Value
WDD
WDT_MR
<= WDD
WDV
WDRSTT
WDT_MR
WDT_CR
reload
WDUNF
WDERR
reload
write WDT_MR
WDT_MR
WDRSTEN
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running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he does not
expect to use it or must reprogram it to meet the maximum Watchdog period the application requires.
If the watchdog is restarted by writing into the WDT_CR register, the WDT_MR register must not be programmed during
a period of time of 3 slow clock periods following the WDT_CR write access. In any case, programming a new value in
the WDT_MR register automatically initiates a restart instruction.
The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the
WDT_MR register reloads the timer with the newly programmed mode parameters.
In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writing the
Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately reloaded from
WDT_MR and restarted, and the Slow Clock 128 divider is reset and restarted. The WDT_CR register is write-protected.
As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault”
signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode Register (WDT_MR). Moreover, the bit
WDUNF is set in the Watchdog Status Register (WDT_SR).
To prevent a software deadlock that continuously triggers the Watchdog, the reload of the Watchdog must occur while
the Watchdog counter is within a window between 0 and WDD, WDD is defined in the WatchDog Mode Register
WDT_MR.
Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD results in a Watchdog error,
even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the “wdt_fault” signal to the Reset
Controller is asserted.
Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a
configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error.
This is the default configuration on reset (the WDD and WDV values are equal).
The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit
WDFIEN is set in the mode register. The signal “wdt_fault” to the reset controller causes a Watchdog reset if the
WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the processor and
the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset.
If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to
the reset controller is deasserted.
Writing the WDT_MR reloads and restarts the down counter.
While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed
for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.
Figure 17-2. Watchdog Behavior
0
WDV
WDD
WDT_CR = WDRSTT
Watchdog
Fault
Normal behavior
Watchdog Error Watchdog Underflow
FFF if WDRSTEN is 1
if WDRSTEN is 0
Forbidden
Window
Permitted
Window
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17.5 Watchdog Timer (WDT) User Interface
Table 17-1. Register Mapping
Offset Register Name Access Reset
0x00 Control Register WDT_CR Write-only -
0x04 Mode Register WDT_MR Read-write Once 0x3FFF_2FFF
0x08 Status Register WDT_SR Read-only 0x0000_0000
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17.5.1 Watchdog Timer Control Register
Register Name: WDT_CR
Address: 0x400E1450
Access Type: Write-only
• WDRSTT: Watchdog Restart
0: No effect.
1: Restarts the Watchdog.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––WDRSTT
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17.5.2 Watchdog Timer Mode Register
Register Name: WDT_MR
Address: x400E1454
Access Type: Read-write Once
• WDV: Watchdog Counter Value
Defines the value loaded in the 12-bit Watchdog Counter.
• WDFIEN: Watchdog Fault Interrupt Enable
0: A Watchdog fault (underflow or error) has no effect on interrupt.
1: A Watchdog fault (underflow or error) asserts interrupt.
• WDRSTEN: Watchdog Reset Enable
0: A Watchdog fault (underflow or error) has no effect on the resets.
1: A Watchdog fault (underflow or error) triggers a Watchdog reset.
• WDRPROC: Watchdog Reset Processor
0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets.
1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.
• WDD: Watchdog Delta Value
Defines the permitted range for reloading the Watchdog Timer.
If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer.
If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.
• WDDBGHLT: Watchdog Debug Halt
0: The Watchdog runs when the processor is in debug state.
1: The Watchdog stops when the processor is in debug state.
• WDIDLEHLT: Watchdog Idle Halt
0: The Watchdog runs when the system is in idle mode.
1: The Watchdog stops when the system is in idle state.
• WDDIS: Watchdog Disable
0: Enables the Watchdog Timer.
1: Disables the Watchdog Timer.
31 30 29 28 27 26 25 24
WDIDLEHLT WDDBGHLT WDD
23 22 21 20 19 18 17 16
WDD
15 14 13 12 11 10 9 8
WDDIS WDRPROC WDRSTEN WDFIEN WDV
76543210
WDV
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17.5.3 Watchdog Timer Status Register
Register Name: WDT_SR
Address: 0x400E1458
Access Type: Read-only
• WDUNF: Watchdog Underflow
0: No Watchdog underflow occurred since the last read of WDT_SR.
1: At least one Watchdog underflow occurred since the last read of WDT_SR.
• WDERR: Watchdog Error
0: No Watchdog error occurred since the last read of WDT_SR.
1: At least one Watchdog error occurred since the last read of WDT_SR.
Note: The WDD and WDV values must not be modified within a period of time of 3 slow clock periods following a restart of
the watchdog performed by means of a write access in the WDT_CR register, else the watchdog may trigger an end
of period earlier than expected.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––WDERR WDUNF
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18. Supply Controller (SUPC)
18.1 Description
The Supply Controller (SUPC) controls the supply voltage of the Core of the system and manages the Backup Low
Power Mode. In this mode, the current consumption is reduced to a few microamps for Backup power retention. Exit from
this mode is possible on multiple wake-up sources including events on WKUP pins, or a Clock alarm. The SUPC also
generates the Slow Clock by selecting either the Low Power RC oscillator or the Low Power Crystal oscillator.
18.2 Embedded Characteristics
Manages the Core Power Supply VDDCORE and the Backup Low Power Mode by Controlling the Embedded
Voltage Regulator
Generates the Slow Clock SLCK, by Selecting Either the 22-42 kHz Low Power RC Oscillator or the 32 kHz Low
Power Crystal Oscillator
Supports Multiple Wake Up Sources, for Exit from Backup Low Power Mode
16 Wake Up Inputs, with Programmable Debouncing
Real Time Clock Alarm
Real Time Timer Alarm
Supply Monitor Detection on VDDIO, with Programmable Scan Period and Voltage Threshold
A Supply Monitor Detection on VDDIO or a Brownout Detection on VDDCORE can Trigger a Core Reset
Embeds:
One 22 to 42 kHz Low Power RC Oscillator
One 32 kHz Low Power Crystal Oscillator
One Zero-Power Power-On Reset Cell
One Software Programmable Supply Monitor, on VDDIO Located in Backup Section
One Brownout Detector on VDDCORE Located in the Core
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18.3 Block Diagram
Figure 18-1. Supply Controller Block Diagram
Software Controlled
Voltage Regulator
Matrix
SRAM
Watchdog
Timer
Flash
Peripherals
Peripheral
Bridge
Zero-Power
Power-on Reset
Supply
Monitor
(Backup)
RTC
Power
Management
Controller
Embedded
32 kHz RC
Oscillator
Xtal 32 kHz
Oscillator
Supply
Controller
Brownout
Detector
(Core)
Reset
Controller
Backup Power Supply
Core Power Supply
PLLA
vr_on = VROFF / ONREG
controlled
ON
out
rtc_alarm
SLCK
rtc_nreset
proc_nreset
periph_nreset
ice_nreset
Master Clock
MCK
SLCK
NRST
MAINCK PLL ACK
XIN32
XOUT32
osc32k_xtal_en
Slow Clock
SLCK
osc32k_rc_en
VDDIO
VDDCORE
VDDOUT
ADVREF
ADx
WKUP0 - WKUP15
bod_core_on
lcore_brown_out
RTT
rtt_alarm
SLCK
rtt_nreset
XIN
XOUT
VDDIO
VDDIN
PIOx
USB
Transceivers
VDDIO
DDP
DDM
MAINCK
DAC Analog
Circuitry
DACx
PLLB
PLLBCK
Embedded
12 / 8 / 4 MHz
RC
Oscillator
Main Clock
MAINCK
SLCK
3 - 20 MHz
X TAL Oscillator
VDDIO
XTALSEL
Gene ral Pu rpose
Ba ckup Registers
vddcore_nreset
vddcore_nreset
PIOA/B/C
Input/Output Buers
ADC Analog
Circuitry
Analog
Comparator
Cortex-M
Processor
Note1: FSTT0 - FSTT15 are possible Fast Startup Sources, generated by WKUP0-WKUP15 Pins but are not physical
FSTT0 - FSTT15 (Note 1)
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18.4 Supply Controller Functional Description
18.4.1 Supply Controller Overview
The device can be divided into two power supply areas:
The Backup VDDIO Power Supply: including the Supply Controller, a part of the Reset Controller, the Slow Clock
switch, the General Purpose Backup Registers, the Supply Monitor and the Clock which includes the Real Time
Timer and the Real Time Clock
The Core Power Supply: including the other part of the Reset Controller, the Brownout Detector, the Processor, the
SRAM memory, the FLASH memory and the Peripherals
The Supply Controller (SUPC) controls the supply voltage of the core power supply. The SUPC intervenes when the
VDDIO power supply rises (when the system is starting) or when the Backup Low Power Mode is entered.
The SUPC also integrates the Slow Clock generator which is based on a 32 kHz crystal oscillator and an embedded 32
kHz RC oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal oscillator and
select it as the Slow Clock source.
The Supply Cont roller and the VDD IO power supply hav e a reset circuitr y based on a zero-power po wer-on reset cell.
The zero-power power-on reset allows the SUPC to start properly as soon as the VDDIO voltage becomes valid.
At start-up of the system, once the backup voltage VDDIO is valid and the embedded 32 kHz RC oscillator is stabilized,
the SUPC starts up the core by sequentially enabling the internal Voltage Regulator, waiting that the core voltage
VDDCORE is valid, then releasing the reset signal of the core “vddcore_nreset” signal.
Once the system has started, the user can program a supply monitor and/or a brownout detector. If the supply monitor
detects a voltage on VDDIO that is too low, the SUPC can assert the reset signal of the core “vddcore_nreset” signal until
VDDIO is valid. Likewise, if the brownout detector detects a core voltage VDDCORE that is too low, the SUPC can assert
the reset signal “vddcore_nreset” until VDDCORE is valid.
When the Backup Low Power Mode is entered, the SUPC sequentially asserts the reset signal of the core power supply
“vddcore_nreset” and disables the voltage regulator, in order to supply only the VDDIO power supply. In this mode the
current consumption is reduced to a few microamps for Backup part retention. Exit from this mode is possible on multiple
wake-up sources including an event on WKUP pins, or a Clock alarm. To exit this mode, the SUPC operates in the same
way as system start-up.
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18.4.2 Slow Clock Generator
The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply. As soon as the
VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the embedded
RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 μs).
The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate frequency.
The command is made by writing the Supply Controller Control Register (SUPC_CR) with the XTALSEL bit at 1.This
results in a sequence which first configures the PIO lines multiplexed with XIN32 and XOUT32 to be driven by the
oscillator, then enables the crystal oscillator, then counts a number of slow RC oscillator clock periods to cover the start-
up time of the crystal oscillator (refer to electrical characteristics for details of 32KHz crystal oscillator start-up time), then
switches the slow clock on the output of the crystal oscillator and then disables the RC oscillator to save power. The
switching time may vary according to the slow RC oscillator clock frequency range. The switch of the slow clock source is
glitch free. The OSCSEL bit of the Supply Controller Status Register (SUPC_SR) allows knowing when the switch
sequence is done.
Coming back on the RC oscillator is only possible by shutting down the VDDIO power supply.
If the user does not need the crystal oscillator, the XIN32 and XOUT32 pins should be left unconnected.
The user can also set the crystal oscillator in bypass mode instead of connecting a crystal. In this case, the user has to
provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the product electrical
characteristics section. In order to set the bypass mode, the OSCBYPASS bit of the Supply Controller Mode Register
(SUPC_MR) needs to be set at 1.
18.4.3 Voltage Regulator Control/Backup Low Power Mode
The Supply Controller can be used to control the embedded voltage regulator.
The voltage regulator automatically adapts its quiescent current depending on the required load current. Please refer to
the electrical characteristics section.
The programmer can switch off the voltage regulator, and thus put the device in Backup mode, by writing the Supply
Controller Control Register (SUPC_CR) with the VROFF bit at 1.
This asserts the vddcore_nreset signal after the write resynchronization time which lasts, in the worse case, two slow
clock cycles. Once the vddcore_nreset signal is asserted, the processor and the peripherals are stopped one slow clock
cycle before the core power supply shuts off.
When the user does not use the internal voltage regulator and wants to supply VDDCORE by an external supply, it is
possible to disable the voltage regulator. Note that it is different from the Backup mode. Depending on the application,
disabling the voltage regulator can reduce power consumption as the voltage regulator input (VDDIN) is shared with the
ADC and DAC. This is done through ONREG bit in SUPC_MR.
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18.4.4 Supply Monitor
The Supply Controller embeds a supply monitor which is located in the VDDIO Power Supply and which monitors VDDIO
power supply.
The supply monitor can be used to prevent the processor from falling into an unpredictable state if the Main power supply
drops below a certain level.
The threshold of the supply monitor is programmable. It can be selected from 1.9V to 3.4V by steps of 100 mV. This
threshold is programmed in the SMTH field of the Supply Controller Supply Monitor Mode Register (SUPC_SMMR).
The supply monitor can also be enabled during one slow clock period on every one of either 32, 256 or 2048 slow clock
periods, according to the choice of the user. This can be configured by programming the SMSMPL field in SUPC_SMMR.
Enabling the supply monitor for such reduced times allows to divide the typical supply monitor power consumption
respectively by factors of 32, 256 or 2048, if the user does not need a continuous monitoring of the VDDIO power supply.
A supply monitor detection can either generate a reset of the core power supply or a wake up of the core power supply.
Generating a core reset when a supply monitor detection occurs is enabled by writing the SMRSTEN bit to 1 in
SUPC_SMMR.
Waking up the core power supply when a supply monitor detection occurs can be enabled by programming the SMEN bit
to 1 in the Supply Controller Wake Up Mode Register (SUPC_WUMR).
The Supply Controller provides two status bits in the Supply Controller Status Register for the supply monitor which
allows to determine whether the last wake up was due to the supply monitor:
The SMOS bit provides real time information, which is updated at each measurement cycle or updated at each
Slow Clock cycle, if the measurement is continuous.
The SMS bit provides saved information and shows a supply monitor detection has occurred since the last read of
SUPC_SR.
The SMS bit can generate an interrupt if the SMIEN bit is set to 1 in the Supply Controller Supply Monitor Mode Register
(SUPC_SMMR).
Figure 18-2. Supply Monitor Status Bit and Associated Interrupt
Supply Monitor ON
3.3 V
0 V
Threshold
SMS and SUPC interrupt
Read SUPC_SR
Periodic Sampling
Continuous Sampling (SMSMPL = 1)
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18.4.5 Backup Power Supply Reset
18.4.5.1Raising the Backup Power Supply
As soon as the backup voltage VDDIO rises, the RC oscillator is powered up and the zero-power power-on reset cell
maintains its output low as long as VDDIO has not reached its target voltage. During this time, the Supply Controller is
entirely reset. When the VDDIO voltage becomes valid and zero-power power-on reset signal is released, a counter is
started for 5 slow clock cycles. This is the time it takes for the 32 kHz RC oscillator to stabilize.
After this time, the voltage regulator is enabled. The core power supply rises and the brownout detector provides the
bodcore_in signal as soon as the core voltage VDDCORE is valid. This results in releasing the vddcore_nreset signal to
the Reset Controller after the bodcore_in signal has been confirmed as being valid for at least one slow clock cycle.
Figure 18-3. Raising the VDDIO Power Supply
Zero-Power Power-On
Reset Cell output
22 - 42 kHz RC
Oscillator output
Fast RC
Oscillator output
Backup Power Supply
vr_on
bodcore_in
vddcore_nreset
NRST
(no ext. drive assumed)
proc_nreset
Note: After “proc_nreset” rising, the core starts fetching instructions from Flash at 4 MHz.
periph_nreset
7 x Slow Clock Cycles 3 x Slow Clock
Cycles
2 x Slow Clock
Cycles
6.5 x Slow Clock
Cycles
TON Voltage
Regulator
Zero-Power POR
Core Power Supply
RSTC.ERSTL
(5 for startup slow RC + 2 for synchro.)
default = 2
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18.4.6 Core Reset
The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described previously in Section
18.4.5 ”Backup Power Supply Reset”. The vddcore_nreset signal is normally asserted before shutting down the core
power supply and released as soon as the core power supply is correctly regulated.
There are two additional sources which can be programmed to activate vddcore_nreset:
a supply monitor detection
a brownout detection
18.4.6.1Supply Monitor Reset
The supply monitor is capable of generating a reset of the system. This can be enabled by setting the SMRSTEN bit in
the Supply Controller Supply Monitor Mode Register (SUPC_SMMR).
If SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is immediately activated for a
minimum of 1 slow clock cycle.
18.4.6.2Brownout Detector Reset
The brownout detector provides the bodcore_in signal to the SUPC which indicates that the voltage regulation is
operating as programmed. If this signal is lost for longer than 1 slow clock period while the voltage regulator is enabled,
the Supply Controller can assert vddcore_nreset. This feature is enabled by writing the bit, BODRSTEN (Brownout
Detector Reset Enable) to 1 in the Supply Controller Mode Register (SUPC_MR).
If BODRSTEN is set and the voltage regulation is lost (output voltage of the regulator too low), the vddcore_nreset signal
is asserted for a minimum of 1 slow clock cycle and then released if bodcore_in has been reactivated. The BODRSTS bit
is set in the Supply Controller Status Register (SUPC_SR) so that the user can know the source of the last reset.
Until bodcore_in is deactivated, the vddcore_nreset signal remains active.
18.4.7 Wake Up Sources
The wake up events allow the device to exit backup mode. When a wake up event is detected, the Supply Controller
performs a sequence which automatically reenables the core power supply.
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Figure 18-4. Wake Up Sources
18.4.7.1Wake Up Inputs
The w ake up in puts, W KUP0 to W KUP15 , can be pr ogram med to pe rform a w ake up of t he core p ower su pply. E ach
input can be enabled by writing to 1 the corresponding bit, WKUPEN0 to WKUPEN 15, in the Wake Up Inputs Register
(SUPC_WUIR). The wake up level can be selected with the corresponding polarity bit, WKUPPL0 to WKUPPL15, also
located in SUPC_WUIR.
All the resulting signals are wired-ORed to trigger a debounce counter, which can be programmed with the WKUPDBC
field in the Supply Controller Wake Up Mode Register (SUPC_WUMR). The WKUPDBC field can select a debouncing
period of 3, 32, 512, 4,096 or 32,768 slow clock cycles. This corresponds respectively to about 100 μs, about 1 ms, about
16 ms, about 128 ms and about 1 second (for a typical slow clock frequency of 32 kHz). Programming WKUPDBC to 0x0
selects an immediate wake up, i.e., an enabled WKUP pin must be active according to its polarity during a minimum of
one slow clock period to wake up the core power supply.
If an enabled WKUP pin is asserted for a time longer than the debouncing period, a wake up of the core power supply is
started and the signals, WKUP0 to WKUP15 as shown in Figure 18-4, are latched in the Supply Controller Status
Register (SUPC_SR). This allows the user to identify the source of the wake up, however, if a new wake up condition
occurs, the primary information is lost. No new wake up can be detected since the primary wake up condition has
disappeared.
WKUP15
WKUPEN15
WKUPT15
WKUPEN1
WKUPEN0
Debouncer
SLCK
WKUPDBC
WKUPS
RTCEN
rtc_alarm
SMEN
sm_out
Core
Supply
Restart
WKUPIS0
WKUPIS1
WKUPIS15
WKUPT0
WKUPT1
WKUP0
WKUP1
RTTEN
rtt_alarm
Debouncer
RTCOUT0
LPDBC
Debouncer
LPDBC
RTCOUT0
LPDBCS0
LPDBCS1
LPDBCEN1
Low/High
Level Detect
WKUPT1
LPDBCEN0
Low/High
Level Detect
WKUPT0
Low/High
Level Detect
Low/High
Level Detect
Low/High
Level Detect
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18.4.7.2Low Power Debouncer Inputs
It is possible to generate a waveform (RTCOUT0 and RTCOUT1) in all modes (including backup mode). It can be useful
to control an external sensor and/or tampering function without waking up the processor. Please refer to the RTC section
for waveform generation.
Two separate debouncers are embedded for WKUP0 and WKUP1 inputs.
The WKUP0 and/or WKUP1 inputs can be programmed to perform a wake up of the core power supply with a
debouncing done by RTCOUT0.
These inputs can be also used when VDDCORE is powered to get tamper detection function with a low power debounce
function.
This can be enabled by setting LPDBC0 bit and/or LPDBC1 bit in SUPC_WUMR.
In this mode of operation, WKUP0 and/or WKUP1 must not be configured to also act as debouncing source for the
WKUPDBC counter (WKUPEN0 and/or WKUPEN1 must be cleared in SUPC_WUIR). Refer to Figure 18-4.
This mode of operation requires the RTC Output (RTCOUT0) to be configured to generate a duty cycle programmable
pulse (i.e. OUT0 = 0x7 in RTC_MR) in order to create the sampling points of both debouncers. The sampling point is the
falling edge of the RTCOUT0 waveform.
Figure 18-5 shows an example of an application where two tamper switches are used. RTCOUT0 powers the external
pull-up used by the tampers.
Figure 18-5. Low Power Debouncer (Push-to-Make switch, pull-up resistors)
AT91SAM
WKUP0
WKUP1
RTCOUT0
Pull-Up
Resistor
Pull-Up
Resistor
GND
GND
GND
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Figure 18-6. Low Power Debouncer (Push-to-Break switch, pull-down resistors)
The debouncing parameters can be adjusted and are shared (except the wake up input polarity) by both debouncers.
The number of successive identical samples to wake up the core can be configured from 2 up to 8 in the LPDBC field of
SUPC_WUMR. The period of time between 2 samples can be configured by programming the TPERIOD field in the
RTC_MR register.
Power parameters can be adjusted by modifying the period of time in the THIGH field in RTC_MR.
The wake up polarity of the inputs can be independently configured by writing WKUPT0 and WKUPT1 fields in
SUPC_WUMR.
In order to determine which wake up pin triggers the core wake up or simply which debouncer triggers an event (even if
there is no wake up, so when VDDCORE is powered on), a status flag is associated for each low power debouncer.
These 2 flags can be read in the SUPC_SR.
A debounce event can perform an immediate clear (0 delay) on first half the general purpose backup registers (GPBR).
The LPDBCCLR bit must be set to 1 in SUPC_MR.
18.4.7.3Clock Alarms
The RTC and the RTT alarms can generate a wake up of the core power supply. This can be enabled by writing
respectively, the bits RTCEN and RTTEN to 1 in the Supply Controller Wake Up Mode Register (SUPC_WUMR).
The Supply Controller does not provide any status as the information is available in the User Interface of either the Real
Time Timer or the Real Time Clock.
18.4.7.4Supply Monitor Detection
The supply monitor can generate a wake-up of the core power supply. See Section 18.4.4 ”Supply Monitor”.
18.4.8 Low Power Tamper Detection Inputs
WKUP0 and WKUP1 can be used as tamper detect inputs.
In Backup Mode they can be used also to wake up the core. In other modes an interrupt can be generated.
If a tamper is detected, it performs an immediate clear (0 delay) on first half the general purpose backup registers
(GPBR).
Refer to “Wake Up Sources” on page 293 for more details.
AT91SAM
WKUP0
WKUP1
RTCOUT0
Pull-Down
Resistors
GND GND
GND
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18.5 Supply Controller (SUPC) User Interface
The User Interface of the Supply Controller is part of the System Controller User Interface.
18.5.1 System Controller (SYSC) User Interface
18.5.2 Supply Controller (SUPC) User Interface
Table 18-1. System Controller Registers
Offset System Controller Peripheral Name
0x00-0x0c Reset Controller RSTC
0x10-0x2C Supply Controller SUPC
0x30-0x3C Real Time Timer RTT
0x50-0x5C Watchdog Timer WDT
0x60-0x8C Real Time Clock RTC
0x90-0xDC General Purpose Backup Register GPBR
0xE0 Reserved
0xE4 Write Protect Mode Register SYSC_WPMR
0xE8-0xF8 Reserved
Table 18-2. Register Mapping
Offset Register Name Access Reset
0x00 Supply Controller Control Register SUPC_CR Write-only N/A
0x04 Supply Controller Supply Monitor Mode Register SUPC_SMMR Read-write 0x0000_0000
0x08 Supply Controller Mode Register SUPC_MR Read-write 0x0000_5A00
0x0C Supply Controller Wake Up Mode Register SUPC_WUMR Read-write 0x0000_0000
0x10 Supply Controller Wake Up Inputs Register SUPC_WUIR Read-write 0x0000_0000
0x14 Supply Controller Status Register SUPC_SR Read-only 0x0000_0000
0x18 Reserved
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18.5.3 Supply Controller Control Register
Name: SUPC_CR
Address: 0x400E1410
Access: Write-only
• VROFF: Voltage Regulator Off
0 (NO_EFFECT) = no effect.
1 (STOP_VREG) = if KEY is correct, asserts vddcore_nreset and stops the voltage regulator.
• XTALSEL: Crystal Oscillator Select
0 (NO_EFFECT) = no effect.
1 (CRYSTAL_SEL) = if KEY is correct, switches the slow clock on the crystal oscillator output.
• KEY: Password
Should be written to value 0xA5. Writing any other value in this field aborts the write operation.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––– –
76543210
– – – – XTALSEL VROFF – –
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18.5.4 Supply Controller Supply Monitor Mode Register
Name: SUPC_SMMR
Address: 0x400E1414
Access: Read-write
• SMTH: Supply Monitor Threshold
Allows to select the threshold voltage of the supply monitor. Refer to electrical characteristics for voltage values.
• SMSMPL: Supply Monitor Sampling Period
• SMRSTEN: Supply Monitor Reset Enable
0 (NOT_ENABLE) = the core reset signal “vddcore_nreset” is not affected when a supply monitor detection occurs.
1 (ENABLE) = the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs.
• SMIEN: Supply Monitor Interrupt Enable
0 (NOT_ENABLE) = the SUPC interrupt signal is not affected when a supply monitor detection occurs.
1 (ENABLE) = the SUPC interrupt signal is asserted when a supply monitor detection occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – SMIEN SMRSTEN – SMSMPL
76543210
– – – – SMTH
Value Name Description
0x0 SMD Supply Monitor disabled
0x1 CSM Continuous Supply Monitor
0x2 32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods
0x3 256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods
0x4 2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods
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18.5.5 Supply Controller Mode Register
Name: SUPC_MR
Address: 0x400E1418
Access: Read-write
• BODRSTEN: Brownout Detector Reset Enable
0 (NOT_ENABLE) = the core reset signal “vddcore_nreset” is not affected when a brownout detection occurs.
1 (ENABLE) = the core reset signal, vddcore_nreset is asserted when a brownout detection occurs.
• BODDIS: Brownout Detector Disable
0 (ENABLE) = the core brownout detector is enabled.
1 (DISABLE) = the core brownout detector is disabled.
• ONREG: Voltage Regulator enable
0 (ONREG_UNUSED) = Internal voltage regulator is not used (external power supply is used)
1 (ONREG_USED) = internal voltage regulator is used
Note:
• OSCBYPASS: Oscillator Bypass
0 (NO_EFFECT) = no effect. Clock selection depends on XTALSEL value.
1 (BYPASS) = the 32-kHz XTAL oscillator is selected and is put in bypass mode.
• KEY: Password Key
Should be written to value 0xA5. Writing any other value in this field aborts the write operation.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
–––OSCBYPASS––––
15 14 13 12 11 10 9 8
ONREG BODDIS BODRSTEN ––––
76543210
––––––––
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18.5.6 Supply Controller Wake Up Mode Register
Name: SUPC_WUMR
Address: 0x400E141C
Access: Read-write
• SMEN: Supply Monitor Wake Up Enable
0 (NOT_ENABLE) = the supply monitor detection has no wake up effect.
1 (ENABLE) = the supply monitor detection forces the wake up of the core power supply.
• RTTEN: Real Time Timer Wake Up Enable
0 (NOT_ENABLE) = the RTT alarm signal has no wake up effect.
1 (ENABLE) = the RTT alarm signal forces the wake up of the core power supply.
• RTCEN: Real Time Clock Wake Up Enable
0 (NOT_ENABLE) = the RTC alarm signal has no wake up effect.
1 (ENABLE) = the RTC alarm signal forces the wake up of the core power supply.
• LPDBCEN0: Low power Debouncer ENable WKUP0
0 (NOT_ENABLE) = the WKUP0 input pin is not connected with low power debouncer.
1 (ENABLE) = the WKUP0 input pin is connected with low power debouncer and can force a core wake up.
• LPDBCEN1: Low power Debouncer ENable WKUP1
0 (NOT_ENABLE) = the WKUP1input pin is not connected with low power debouncer.
1 (ENABLE) = the WKUP1 input pin is connected with low power debouncer and can force a core wake up.
• LPDBCCLR: Low power Debouncer Clear
0 (NOT_ENABLE) = a low power debounce event does not create an immediate clear on first half GPBR registers.
1 (ENABLE) = a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – – LPDBC
15 14 13 12 11 10 9 8
– WKUPDBC ––––
76543210
LPDBCCLR LPDBCEN1 LPDBCEN0 – RTCEN RTTEN SMEN –
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• WKUPDBC: Wake Up Inputs Debouncer Period
• LPDBC: Low Power DeBounCer Period
Value Name Description
0 IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge.
1 3_SCLK WKUPx shall be in its active state for at least 3 SLCK periods
2 32_SCLK WKUPx shall be in its active state for at least 32 SLCK periods
3 512_SCLK WKUPx shall be in its active state for at least 512 SLCK periods
4 4096_SCLK WKUPx shall be in its active state for at least 4,096 SLCK periods
5 32768_SCLK WKUPx shall be in its active state for at least 32,768 SLCK periods
6 Reserved Reserved
7 Reserved Reserved
Value Name Description
0 DISABLE Disable the low power debouncer.
1 2_RTCOUT0 WKUP0/1 in its active state for at least 2 RTCOUT0 periods
2 3_RTCOUT0 WKUP0/1 in its active state for at least 3 RTCOUT0 periods
3 4_RTCOUT0 WKUP0/1 in its active state for at least 4 RTCOUT0 periods
4 5_RTCOUT0 WKUP0/1 in its active state for at least 5 RTCOUT0 periods
5 6_RTCOUT0 WKUP0/1 in its active state for at least 6 RTCOUT0 periods
6 7_RTCOUT0 WKUP0/1 in its active state for at least 7 RTCOUT0 periods
7 8_RTCOUT0 WKUP0/1 in its active state for at least 8 RTCOUT0 periods
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18.5.7 System Controller Wake Up Inputs Register
Name: SUPC_WUIR
Address: 0x400E1420
Access: Read-write
• WKUPEN0 - WKUPEN15: Wake Up Input Enable 0 to 15
0 (DISABLE) = the corresponding wake-up input has no wake up effect.
1 (ENABLE) = the corresponding wake-up input forces the wake up of the core power supply.
• WKUPT0 - WKUPT15: Wake Up Input Type 0 to 15
0 (LOW) = a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core
power supply.
1 (HIGH) = a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core
power supply.
31 30 29 28 27 26 25 24
WKUPT15 WKUPT14 WKUPT13 WKUPT12 WKUPT11 WKUPT10 WKUPT9 WKUPT8
23 22 21 20 19 18 17 16
WKUPT7 WKUPT6 WKUPT5 WKUPT4 WKUPT3 WKUPT2 WKUPT1 WKUPT0
15 14 13 12 11 10 9 8
WKUPEN15 WKUPEN14 WKUPEN13 WKUPEN12 WKUPEN11 WKUPEN10 WKUPEN9 WKUPEN8
76543210
WKUPEN7 WKUPEN6 WKUPEN5 WKUPEN4 WKUPEN3 WKUPEN2 WKUPEN1 WKUPEN0
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18.5.8 Supply Controller Status Register
Name: SUPC_SR
Address: 0x400E1424
Access: Read-only
Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK), the status register flag
reset is taken into account only 2 slow clock cycles after the read of the SUPC_SR.
• WKUPS: WKUP Wake Up Status
0 (NO) = no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
1 (PRESENT) = at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
• SMWS: Supply Monitor Detection Wake Up Status
0 (NO) = no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR.
1 (PRESENT) = at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR.
• BODRSTS: Brownout Detector Reset Status
0 (NO) = no core brownout rising edge event has been detected since the last read of the SUPC_SR.
1 (PRESENT) = at least one brownout output rising edge event has been detected since the last read of the SUPC_SR.
When the voltage remains below the defined threshold, there is no rising edge event at the output of the brownout detection cell.
The rising edge event occurs only when there is a voltage transition below the threshold.
• SMRSTS: Supply Monitor Reset Status
0 (NO) = no supply monitor detection has generated a core reset since the last read of the SUPC_SR.
1 (PRESENT) = at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR.
• SMS: Supply Monitor Status
0 (NO) = no supply monitor detection since the last read of SUPC_SR.
1 (PRESENT) = at least one supply monitor detection since the last read of SUPC_SR.
• SMOS: Supply Monitor Output Status
0 (HIGH) = the supply monitor detected VDDIO higher than its threshold at its last measurement.
1 (LOW) = the supply monitor detected VDDIO lower than its threshold at its last measurement.
31 30 29 28 27 26 25 24
WKUPIS15 WKUPIS14 WKUPIS13 WKUPIS12 WKUPIS11 WKUPIS10 WKUPIS9 WKUPIS8
23 22 21 20 19 18 17 16
WKUPIS7 WKUPIS6 WKUPIS5 WKUPIS4 WKUPIS3 WKUPIS2 WKUPIS1 WKUPIS0
15 14 13 12 11 10 9 8
LPDBCS1 LPDBCS0 –––––
76543210
OSCSEL SMOS SMS SMRSTS BODRSTS SMWS WKUPS –
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• OSCSEL: 32-kHz Oscillator Selection Status
0 (RC) = the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator.
1 (CRYST) = the slow clock, SLCK is generated by the 32-kHz crystal oscillator.
• LPDBCS0: Low Power Debouncer Wake Up Status on WKUP0
0 (NO) = no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
1 (PRESENT) = at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR.
• LPDBCS1: Low Power Debouncer Wake Up Status on WKUP1
0 (NO) = no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
1 (PRESENT) = at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR.
• WKUPIS0-WKUPIS15: WKUP Input Status 0 to 15
0 (DIS) = the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event.
1 (EN) = the corresponding wake-up input was active at the time the debouncer triggered a wake up event.
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18.5.9 System Controller Write Protect Mode Register
Name: SYSC_WPMR
Access: Read-write
• WPEN:
0: The Write Protection is disabled.
1: The Write Protection is enabled.
• WPKEY:
If a value is written in WPEN, the value is taken into account only if WPKEY is written with “RTC” (RTC written in ASCII Code, i.e.
0x525443 in hexadecimal).
List of the write-protected registers:
RSTC Mode Register
RTT Mode Register
RTT Alarm Register
RTC Control Register
RTC Mode Register
RTC Time Alarm Register
RTC Calendar Alarm Register
General Purpose Backup Registers
SUPC Control Register
SUPC Supply Monitor Mode Register
SUPC Mode Register
SUPC WakeUp Mode Register
SUPC WakeUp Input Mode Register
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
WPEN
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19. General Purpose Backup Registers (GPBR)
19.1 Description
The System Controller embeds Eight general-purpose backup registers.
If a tamper event has been detected, it is not possible to write into general-purpose backup registers while the LPDBCS0
or LPDBCS1 flags are not cleared in supply controller status register SUPC_SR.
19.2 Embedded Characteristics
Eight 32-bit General Purpose Backup Registers
19.3 General Purpose Backup Registers (GPBR) User Interface
Table 19-1. Register Mapping
Offset Register Name Access Reset
0x0 General Purpose Backup Register 0 SYS_GPBR0 Read-write –
... ... ... ... ...
0x1C General Purpose Backup Register 7 SYS_GPBR7 Read-write –
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19.3.1 General Purpose Backup Register x
Name: SYS_GPBRx
Address: 0x400E1490
Access: Read-write
• GPBR_VALUE: Value of GPBR x
If a tamper event has been detected, it is not possible to write GPBR_VALUE while the LPDBCS0 or LPDBCS1 flags are
not cleared in supply controller status register SUPC_SR.
31 30 29 28 27 26 25 24
GPBR_VALUE
23 22 21 20 19 18 17 16
GPBR_VALUE
15 14 13 12 11 10 9 8
GPBR_VALUE
76543210
GPBR_VALUE
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20. Enhanced Embedded Flash Controller (EEFC)
20.1 Description
The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal bus.
Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing, locking
and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash
descriptor definition that informs the system about the Flash organization, thus making the software generic.
20.2 Embedded Characteristics
Interface of the Flash Block with the 32-bit Internal Bus
Increases Performance in Thumb2 Mode with 128-bit or -64 bit Wide Memory Interface up to 100 or 120 MHz
Code loops optimization
256 Lock Bits, Each Protecting a Lock Region
GPNVMx General-purpose GPNVM Bits
One-by-one Lock Bit Programming-Commands Protected by a Keyword
Erases the Entire Flash
Erases by Plane
Erase by Sector
Erase by Pages
Possibility of Erasing before Programming
Locking and Unlocking Operations
Consecutive Programming and Locking Operations
Possibility to read the Calibration Bits
20.3 Product Dependencies
20.3.1 Power Management
The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Management Controller has no
effect on its behavior.
20.3.2 Interrupt Sources
The Enhanced Embedded Flash Controller (EEFC) interrupt line is connected to the Nested Vectored Interrupt Controller
(NVIC). Using the Enhanced Embedded Flash Controller (EEFC) interrupt requires the NVIC to be programmed first. The
EEFC interrupt is generated only on FRDY bit rising.
20.4 Functional Description
20.4.1 Embedded Flash Organization
The embedded Flash interfaces directly with the 32-bit internal bus. The embedded Flash is composed of:
One memory plane organized in several pages of the same size.
Two 128-bit or 64-bit read buffers used for code read optimization.
Table 20-1. Peripheral IDs
Instance ID
EFC0 6
EFC1 7
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One 128-bit or 64-bit read buffer used for data read optimization.
One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer is
write-only and accessible all along the 1 MByte address space, so that each word can be written to its final
address.
Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is associated with
a lock region composed of several pages in the memory plane.
Several bits that may be set and cleared through the Enhanced Embedded Flash Controller (EEFC) interface,
called General Purpose Non Volatile Memory bits (GPNVM bits).
The embedded Flash size, the page size, the lock regions organization and GPNVM bits definition are specific to the
product. The Enhanced Embedded Flash Controller (EEFC) returns a descriptor of the Flash controlled after a get
descriptor command issued by the application (see “Getting Embedded Flash Descriptor” on page 314).
Figure 20-1. Embedded Flash Organization
20.4.2 Read Operations
An optimized controller manages embedded Flash reads, thus increasing performance when the processor is running in
Thumb2 mode by means of the 128- or 64- bit wide memory interface.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded Flash
wraps around the address space and appears to be repeated within it.
The read operations can be performed with or without wait states. Wait states must be programmed in the field FWS
(Flash Read Wait State) in the Flash Mode Register (EEFC_FMR). Defining FWS to be 0 enables the single-cycle
access of the embedded Flash. Refer to the Electrical Characteristics for more details.
20.4.2.1128-bit or 64-bit Access Mode
By default the read accesses of the Flash are performed through a 128-bit wide memory interface. It enables better
system performance especially when 2 or 3 wait state needed.
For systems requiring only 1 wait state, or to privilege current consumption rather than performance, the user can select
a 64-bit wide memory access via the FAM bit in the Flash Mode Register (EEFC_FMR)
Please refer to the electrical characteristics section of the product datasheet for more details.
Start Address
Page 0
Lock Region 0
Lock Region 1
Memory Plane
Page (m-1)
Lock Region (n-1)
Page (n*m-1)
Start Address + Flash size -1
Lock Bit 0
Lock Bit 1
Lock Bit (n-1)
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20.4.2.2Code Read Optimization
This feature is enabled if the EEFC_FMR register bit SCOD is cleared.
A system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize sequential Code Fetch.
Note: Immediate consecutive code read accesses are not mandatory to benefit from this optimization.
The sequential code read optimization is enabled by default. If the bit SCOD in Flash Mode Register (EEFC_FMR) is set
to 1, these buffers are disabled and the sequential code read is not optimized anymore.
Another system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize loop code fetch (see “Code Loops
Optimization” on page 311).
Figure 20-2. Code Read Optimization for FWS = 0
Note: When FWS is equal to 0, all the accesses are performed in a single-cycle access.
Figure 20-3. Code Read Optimization for FWS = 3
Note: When FWS is included between 1 and 3, in case of sequential reads, the first access takes (FWS+1) cycles, the other
ones only 1 cycle.
20.4.2.3Code Loops Optimization
The Code Loops optimization is enabled when the CLOE bit of the EEFC_FMR register is set at 1.
Flash Access
Buffer 0 (128bits)
Master Clock
ARM Request
(32-bit)
XXX
Data To ARM
Bytes 0-15 Bytes 16-31 Bytes 32-47
Bytes 0-15
Buffer 1 (128bits)
Bytes 32-47
Bytes 0-3 Bytes 4-7 Bytes 8-11 Bytes 12-15 Bytes 16-19 Bytes 20-23 Bytes 24-27
XXX
XXX Bytes 16-31
Byte 0 Byte 4 Byte 8 Byte 12 Byte 16 Byte 20 Byte 24 Byte 28 Byte 32
Bytes 28-31
Flash Access
Buffer 0 (128bits)
Master Clock
ARM Request
(32-bit)
Data To ARM
Buffer 1 (128bits)
0-3
XXX
XXX
Bytes 16-31
Byte 0 4 8
Bytes 0-15 Bytes 16-31 Bytes 32-47 Bytes 48-63
XXX Bytes 0-15
4-7 8-11 12-15
12 16 20
24-27 28-31 32-35 36-3916-19 20-23 40-43 44-47
24 28 32 36 40 44 48 52
Bytes 32-47
48-51
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When a backward jump is inserted in the code, the pipeline of the sequential optimization is broken, and it becomes
inefficient. In this case the loop code read optimization takes over from the sequential code read optimization to avoid
insertion of wait states. The loop code read optimization is enabled by default. If in Flash Mode Register (EEFC_FMR),
the bit CLOE is reset to 0 or the bit SCOD is set to 1, these buffers are disabled and the loop code read is not optimized
anymore.
When this feature is enabled, if inner loop body instructions L0 to Ln lay from the 128-bit flash memory cell Mb0 to the
memory cell Mp1, after recognition of a first backward branch, the two first fl ash memory cells Mb0 and Mb1 targeted by
this branch are cached for fast access from the processor at the next loop iterations.
Afterwards, combining the sequential prefetch (described in Section 20.4.2.2 ”Code Read Optimization”) through the loop
body with the fast read access to the loop entry cache, the whole loop can be iterated with no wait-state.
Figure 20-4 below illustrates the Code Loops optimization.
Figure 20-4. Code Loops Optimization
20.4.2.4Data Read Optimization
The organization of the Flash in 128 bits (or 64 bits) is associated with two 128-bit (or 64-bi t) prefetch buffers and one
128-bit (or 64-bit) data read buffer, thus providing maximum system performance. This buffer is added in order to store
the requested data plus all the data contained in the 128-bit (64-bit) aligned data. This speeds up sequential data reads
if, for example, FWS is equal to 1 (see Figure 20-5). The data read optimization is enabled by default. If the bit SCOD in
Flash Mode Register (EEFC_FMR) is set to 1, this buffer is disabled and the data read is not optimized anymore.
Note: No consecutive data read accesses are mandatory to benefit from this optimization.
Figure 20-5. Data Read Optimization for FWS = 1
L
n
L
n-1
L
n-2
L
n-3
L
n-4
L
n-5
L
5
L
4
L
3
L
2
L
1
L
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
0
M
b
0
M
b0
M
b1
M
p0
M
p1
Backward address jump
2x128-bit loop entry
cache 2x128-bit prefetch
buffer
L
0
Loop Entry instruction
L
n
Loop End instruction
Flash Memory
128-bit words
M
b0
Branch Cache 0
M
b1
Branch Cache 1
M
p0
Prefetch Buffer 0
M
p1
Prefetch Buffer 1
Flash Access
Buffer (128bits)
Master Clock
ARM Request
(32-bit)
XXX
Data To ARM
Bytes 0-15 Bytes 16-31
Bytes 0-15
Bytes 0-3 4-7 8-11 12-15 16-19 20-23
XXX
Bytes 16-31
Byte 0 4 8 12 16 20 24 28 32 36
XXX Bytes 32-47
24-27 28-31 32-35
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20.4.3 Flash Commands
The Enhanced Embedded Flash Controller (EEFC) offers a set of commands such as programming the memory Flash,
locking and unlocking lock regions, consecutive programming and locking and full Flash erasing, etc.
.
In order to perform one of these commands, the Flash Command Register (EEFC_FCR) has to be written with the
correct command using the FCMD field. As soon as the EEFC_FCR register is written, the FRDY flag and the FVALUE
field in the EEFC_FRR register are automatically cleared. Once the current command is achieved, then the FRDY flag is
automatically set. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the corresponding interrupt
line of the NVIC is activated. (Note that this is true for all commands except for the STUI Command. The FRDY flag is not
set when the STUI command is achieved.)
All the commands are protected by the same keyword, which has to be written in the 8 highest bits of the EEFC_FCR
register.
Writing EEFC_FCR with data that does not contain the correct key and/or with an invalid command has no effect on the
whole memory plane, but the FCMDE flag is set in the EEFC_FSR register. This flag is automatically cleared by a read
access to the EEFC_FSR register.
When the current command writes or erases a page in a locked region, the command has no effect on the whole memory
plane, but the FLOCKE flag is set in the EEFC_FSR register. This flag is automatically cleared by a read access to the
EEFC_FSR register.
Table 20-2. Set of Commands
Command Value Mnemonic
Get Flash Descriptor 0x00 GETD
Write page 0x01 WP
Write page and lock 0x02 WPL
Erase page and write page 0x03 EWP
Erase page and write page then lock 0x04 EWPL
Erase all 0x05 EA
Erase Pages 0x07 EPA
Set Lock Bit 0x08 SLB
Clear Lock Bit 0x09 CLB
Get Lock Bit 0x0A GLB
Set GPNVM Bit 0x0B SGPB
Clear GPNVM Bit 0x0C CGPB
Get GPNVM Bit 0x0D GGPB
Start Read Unique Identifier 0x0E STUI
Stop Read Unique Identifier 0x0F SPUI
Get CALIB Bit 0x10 GCALB
Erase Sector 0x11 ES
Write User Signature 0x12 WUS
Erase User Signature 0x13 EUS
Start Read User Signature 0x14 STUS
Stop Read User Signature 0x15 SPUS
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Figure 20-6. Command State Chart
20.4.3.1Getting Embedded Flash Descriptor
This command allows the system to learn about the Flash organization. The system can take full advantage of this
information. For instance, a device could be replaced by one with more Flash capacity, and so the software is able to
adapt itself to the new configuration.
To get the embedded Flash descriptor, the application writes the GETD command in the EEFC_FCR register. The first
word of the descriptor can be read by the software application in the EEFC_FRR register as soon as the FRDY flag in the
EEFC_FSR register rises. The next reads of the EEFC_FRR register provide the following word of the descriptor. If extra
Check if FRDY flag Set No
Yes
Read Status: MC_FSR
Write FCMD and PAGENB in Flash Command Register
Check if FLOCKE flag Set
Check if FRDY flag Set No
Read Status: MC_FSR
Yes
Yes Locking region violation
No
Check if FCMDE flag Set Yes
No
Bad keyword violation
Command Successfull
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read operations to the EEFC_FRR register are done after the last word of the descriptor has been returned, then the
EEFC_FRR register value is 0 until the next valid command.
20.4.3.2Write Commands
Several commands can be used to program the Flash.
Flash technology requires that an erase be done before programming. The full memory plane can be erased at the same
time, or several pages can be erased at the same time (refer to Figure 20-7, "Example of Partial Page Programming",
and the paragraph below the figure.). Also, a page erase can be automatically done before a page write using EWP or
EWPL commands.
After programming, the page (the whole lock region) can be locked to prevent miscellaneous write or erase sequences.
The lock bit can be automatically set after page programming using WPL or EWPL commands.
Data to be written are stored in an internal latch buffer. The size of the latch buffer corresponds to the page size. The
latch buffer wraps around within the internal memory area address space and is repeated as many times as the number
of pages within this address space.
Note: Writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Write operations are performed in a number of wait states equal to the number of wait states for read operations.
Data are written to the latch buffer before the programming command is written to the Flash Command Register
EEFC_FCR. The sequence is as follows:
Write the full page, at any page address, within the internal memory area address space.
Programming starts as soon as the page number and the programming command are written to the Flash
Command Register. The FRDY bit in the Flash Programming Status Register (EEFC_FSR) is automatically
cleared.
When programming is completed, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If
an interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the corresponding interrupt line of the NVIC
is activated.
Two errors can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Lock Error: the page to be programmed belongs to a locked region. A command must be previously run to unlock
the corresponding region.
Table 20-3. Flash Descriptor Definition
Symbol Word Index Description
FL_ID 0 Flash Interface Description
FL_SIZE 1 Flash size in bytes
FL_PAGE_SIZE 2 Page size in bytes
FL_NB_PLANE 3 Number of planes.
FL_PLANE[0] 4 Number of bytes in the first plane.
...
FL_PLANE[FL_NB_PLANE-1] 4 + FL_NB_PLANE - 1 Number of bytes in the last plane.
FL_NB_LOCK 4 + FL_NB_PLANE
Number of lock bits. A bit is associated
with a lock region. A lock bit is used to
prevent write or erase operations in the
lock region.
FL_LOCK[0] 4 + FL_NB_PLANE + 1 Number of bytes in the first lock region.
...
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Flash Error: at the end of the programming, the WriteVerify test of the Flash memory has failed.
By using the WP command, a page can be programmed in several steps if it has been erased before (see Figure 20-7
below). This mode is called Partial Programming.
After any power-on sequence, the flash memory internal latch buffer is not initialized. Thus the latch buffer must be
initialized by writing the part-select to be programmed with user data and the remaining of the buffer must be written with
logical 1.
This action is not required for the next partial programming sequence because the latch buffer is automatically cleared
after programming the page.
Figure 20-7. Example of Partial Page Programming
20.4.3.3Erase Commands
Erase commands are allowed only on unlocked regions. Depending on the Flash memory, several commands can be
used to erase the Flash:
Erase all memory (EA): all memory is erased. The processor must not fetch code from the Flash memory.
Erase pages (EPA): 4, 8, 16 or 32 pages are erased in the memory plane. The first page to be erased is specified
in the FARG[15:2] field of the MC_FCR register. The first page number must be modulo 4, 8,16 or 32 according to
the number of pages to erase at the same time. The processor must not fetch code from the Flash memory.
Erase Sector (ES): A full memory sector is erased. Sector size depends on the Flash memory. FARG must be set
with a page number that is in the sector to be erased. The processor must not fetch code from the Flash memory.
The erase sequence is:
Erase starts as soon as one of the erase commands and the FARG field are written in the Flash Command
Register.
Erase All Flash Programming of the second part of PageY Programming of the third part of PageY
32-bit wide 32-bit wide 32-bit wide
X words
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
...
CA FE CA FE
CA FE CA FE
CA FE CA FE
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF CA FE CA FE
CA FE CA FE
CA FE CA FE
DE CA DE CA
DE CA DE CA
DE CA DE CA
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
FF FF FF FF
Step 1. Step 2. Step 3.
...
...
...
...
...
...
...
...
...
...
...
X words
X words
X words
So PageY erased
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For the EPA command, the 2 lowest bits of the FARG field define the number of pages to be erased
(FARG[1:0]):
When the programming completes, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If
an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated.
Two errors can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Lock Error: at least one page to be erased belongs to a locked region. The erase command has been refused, no
page has been erased. A command must be run previously to unlock the corresponding region.
Flash Error: at the end of the programming, the EraseVerify test of the Flash memory has failed.
20.4.3.4Lock Bit Protection
Lock bits are associated with several pages in the embedded Flash memory plane. This defines lock regions in the
embedded Flash memory plane. They prevent writing/erasing protected pages.
The lock sequence is:
The Set Lock command (SLB) and a page number to be protected are written in the Flash Command Register.
When the locking completes, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If an
interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated.
If the lock bit number is greater than the total number of lock bits, then the command has no effect. The result of
the SLB command can be checked running a GLB (Get Lock Bit) command.
One error can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Flash Error: at the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed.
It is possible to clear lock bits previously set. Then the locked region can be erased or programmed. The unlock
sequence is:
The Clear Lock command (CLB) and a page number to be unprotected are written in the Flash Command
Register.
When the unlock completes, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If an
interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated.
If the lock bit number is greater than the total number of lock bits, then the command has no effect.
One error can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Flash Error: at the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed.
The status of lock bits can be returned by the Enhanced Embedded Flash Controller (EEFC). The Get Lock Bit status
sequence is:
The Get Lock Bit command (GLB) is written in the Flash Command Register, FARG field is meaningless.
Lock bits can be read by the software application in the EEFC_FRR register. The first word read corresponds to
the 32 first lock bits, next reads providing the next 32 lock bits as long as it is meaningful. Extra reads to the
EEFC_FRR register return 0.
Table 20-4. FARG Field for EPA command:
FARG[1:0] Number of pages to be erased with EPA command
0 4 pages
1 8 pages
2 16 pages
3 32 pages
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For example, if the third bit of the first word read in the EEFC_FRR is set, then the third lock region is locked.
One error can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Flash Error: at the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed.
Note: Access to the Flash in read is permitted when a set, clear or get lock bit command is performed.
20.4.3.5GPNVM Bit
GPNVM bits do not interfere with the embedded Flash memory plane. Refer to specific product details for information on
GPNVM bit action.
The set GPNVM bit sequence is:
Start the Set GPNVM Bit command (SGPB) by writing the Flash Command Register with the SGPB command and
the number of the GPNVM bit to be set.
When the GPVNM bit is set, the bit FRDY in the Flash Programming Status Register (EEFC_FSR) rises. If an
interrupt was enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated.
If the GPNVM bit number is greater than the total number of GPNVM bits, then the command has no effect. The
result of the SGPB command can be checked by running a GGPB (Get GPNVM Bit) command.
One error can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Flash Error: at the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed.
It is possible to clear GPNVM bits previously set. The clear GPNVM bit sequence is:
Start the Clear GPNVM Bit command (CGPB) by writing the Flash Command Register with CGPB and the number
of the GPNVM bit to be cleared.
When the clear completes, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If an
interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the interrupt line of the NVIC is activated.
If the GPNVM bit number is greater than the total number of GPNVM bits, then the command has no effect.
One error can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Flash Error: at the end of the programming, the EraseVerify or WriteVerify test of the Flash memory has failed.
The status of GPNVM bits can be returned by the Enhanced Embedded Flash Controller (EEFC). The sequence is:
Start the Get GPNVM bit command by writing the Flash Command Register with GGPB. The FARG field is
meaningless.
GPNVM bits can be read by the software application in the EEFC_FRR register. The first word read corresponds
to the 32 first GPNVM bits, following reads provide the next 32 GPNVM bits as long as it is meaningful. Extra reads
to the EEFC_FRR register return 0.
For example, if the third bit of the first word read in the EEFC_FRR is set, then the third GPNVM bit is active.
One error can be detected in the EEFC_FSR register after a programming sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Note: Access to the Flash in read is permitted when a set, clear or get GPNVM bit command is performed.
Note: If GPNVM bit number is greater than the maximum number of GPNVM available in the product, the command
has no effect on Flash and a Flash error can occur.
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20.4.3.6Calibration Bit
Calibration bits do not interfere with the embedded Flash memory plane.
It is impossible to modify the calibration bits.
The status of calibration bits can be returned by the Enhanced Embedded Flash Controller (EEFC). The sequence is:
Issue the Get CALIB Bit command by writing the Flash Command Register with GCALB (see Table 20-2). The
FARG field is meaningless.
Calibration bits can be read by the software application in the EEFC_FRR register. The first word read
corresponds to the 32 first calibration bits, following reads provide the next 32 calibration bits as long as it is
meaningful. Extra reads to the EEFC_FRR register return 0.
The 4/8/12 MHz Fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB Bit
command. The table below shows the bit implementation for each frequency:
The RC calibration for 4 MHz is set to 1,000,000.
20.4.3.7Security Bit Protection
When the security is enabled, access to the Flash, either through the JTAG/SWD interface or through the Fast Flash
Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.
The security bit is GPNVM0.
Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed.
When the security bit is deactivated, all accesses to the Flash are permitted.
20.4.3.8Unique Identifier
Each part is programmed with a 128 bits Unique Identifier. It can be used to generate keys for example. For the
SAM3SD8, the unique ID is accessible on both memory planes.
To read the Unique Identifier the sequence is:
Send the Start Read unique Identifier command (STUI) by writing the Flash Command Register with the STUI
command.
When the Unique Identifier is ready to be read, the FRDY bit in the Flash Programming Status Register
(EEFC_FSR) falls.
The Unique Identifier is located in the first 128 bits of the Flash memory mapping, thus, at the address
0x00400000-0x004003FF.
To stop the Unique Identifier mode, the user needs to send the Stop Read unique Identifier command (SPUI) by
writing the Flash Command Register with the SPUI command.
When the Stop read Unique Identifier command (SPUI) has been performed, the FRDY bit in the Flash
Programming Status Register (EEFC_FSR) rises. If an interrupt was enabled by setting the FRDY bit in
EEFC_FMR, the interrupt line of the NVIC is activated.
Note that during the sequence, the software can not run out of Flash (or the second plane in case of dual plane).
RC Calibration Frequency EEFC_FRR Bits
8 MHz output [28 - 22]
12 MHz output [38 - 32]
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20.4.3.9User Signature
Each part contains a User Signature of 512-bytes. It can be used by the user for storage. Read, write and erase of this
area is allowed.
To read the User Signature, the sequence is as follows:
Send the Start Read User Signature command (STUS) by writing the Flash Command Register with the STUS
command.
When the User Signature is ready to be read, the FRDY bit in the Flash Programming Status Register
(EEFC_FSR) falls.
The User Signature is located in the first 512 bytes of the Flash memory mapping, thus, at the address
0x00400000-0x004001FF.
To stop the User Signature mode, the user needs to send the Stop Read User Signature command (SPUS) by
writing the Flash Command Register with the SPUS command.
When the Stop Read User Signature command (SPUI) has been performed, the FRDY bit in the Flash
Programming Status Register (EEFC_FSR) rises. If an interrupt was enabled by setting the FRDY bit in
EEFC_FMR, the interrupt line of the NVIC is activated.
Note that during the sequence, the software can not run out of Flash (or the second plane, in case of dual plane).
One error can be detected in the EEFC_FSR register after this sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
To write the User Signature, the sequence is:
Write the full page, at any page address, within the internal memory area address space.
Send the Write User Signature command (WUS) by writing the Flash Command Register with the WUS command.
When programming is completed, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If
an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the corresponding interrupt line of the NVIC
is activated.
Two errors can be detected in the EEFC_FSR register after this sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Flash Error: at the end of the programming, the WriteVerify test of the Flash memory has failed.
To erase the User Signature, the sequence is:
Send the Erase User Signature command (EUS) by writing the Flash Command Register with the EUS command.
When programming is completed, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If
an interrupt has been enabled by setting the FRDY bit in EEFC_FMR, the corresponding interrupt line of the NVIC
is activated.
Two errors can be detected in the EEFC_FSR register after this sequence:
Command Error: a bad keyword has been written in the EEFC_FCR register.
Flash Error: at the end of the programming, the EraseVerify test of the Flash memory has failed.
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20.5 Enhanced Embedded Flash Controller (EEFC) User Interface
The User Interface of the Enhanced Embedded Flash Controller (EEFC) is integrated within the System Controller with base
address 0x400E0A00.
Table 20-5. Register Mapping
Offset Register Name Access Reset State
0x00 EEFC Flash Mode Register EEFC_FMR Read-write 0x0400_0000
0x04 EEFC Flash Command Register EEFC_FCR Write-only –
0x08 EEFC Flash Status Register EEFC_FSR Read-only 0x00000001
0x0C EEFC Flash Result Register EEFC_FRR Read-only 0x0
0x10 Reserved – – –
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20.5.1 EEFC Flash Mode Register
Name: EEFC_FMR
Address: 0x400E0A00 (0), 0x400E0C00 (1)
Access: Read-write
Offset: 0x00
• FRDY: Ready Interrupt Enable
0: Flash Ready does not generate an interrupt.
1: Flash Ready (to accept a new command) generates an interrupt.
• FWS: Flash Wait State
This field defines the number of wait states for read and write operations:
Number of cycles for Read/Write operations = FWS+1
• SCOD: Sequential Code Optimization Disable
0: The sequential code optimization is enabled.
1: The sequential code optimization is disabled.
No Flash read should be done during change of this register.
• FAM: Flash Access Mode
0: 128-bit access in read Mode only, to enhance access speed.
1: 64-bit access in read Mode only, to enhance power consumption.
No Flash read should be done during change of this register.
• CLOE: Code Loops Optimization Enable
0: The opcode loops optimization is disabled.
1: The opcode loops optimization is enabled.
No Flash read should be done during change of this register.
31 30 29 28 27 26 25 24
–––––CLOE–FAM
23 22 21 20 19 18 17 16
–––––––SCOD
15 14 13 12 11 10 9 8
–––– FWS
76543210
– –––––FRDY
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20.5.2 EEFC Flash Command Register
Name: EEFC_FCR
Address: 0x400E0A04 (0), 0x400E0C04 (1)
Access: Write-only
Offset: 0x04
• FCMD: Flash Command
31 30 29 28 27 26 25 24
FKEY
23 22 21 20 19 18 17 16
FARG
15 14 13 12 11 10 9 8
FARG
76543210
FCMD
Value Name Description
0x00 GETD Get Flash Descriptor
0x01 WP Write page
0x02 WPL Write page and lock
0x03 EWP Erase page and write page
0x04 EWPL Erase page and write page then lock
0x05 EA Erase all
0x07 EPA Erase Pages
0x08 SLB Set Lock Bit
0x09 CLB Clear Lock Bit
0x0A GLB Get Lock Bit
0x0B SGPB Set GPNVM Bit
0x0C CGPB Clear GPNVM Bit
0x0D GGPB Get GPNVM Bit
0x0E STUI Start Read Unique Identifier
0x0F SPUI Stop Read Unique Identifier
0x10 GCALB Get CALIB Bit
0x11 ES Erase Sector
0x12 WUS Write User Signature
0x13 EUS Erase User Signature
0x14 STUS Start Read User Signature
0x15 SPUS Stop Read User Signature
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• FARG: Flash Command Argument
• FKEY: Flash Writing Protection Key
Erase all command Field is meaningless.
Erase sector command FARG must be set with a page number that is in the sector to be erased.
Erase pages command
FARG[1:0] defines the number of pages to be erased.
The page number from which the erase will start is defined as follows:
FARG[1:0]=0, start page = 4*FARG[15:2]
FARG[1:0]=1, start page = 8*FARG[15:3], FARG[2] undefined
FARG[1:0]=2, start page = 16*FARG[15:4], FARG[3:2] undefined
FARG[1:0]=3, start page = 32*FARG[15:5], FARG[4:2] undefined
Note: undefined bit must be written to 0.
Refer to Table 20-4 on page 317
Programming command FARG defines the page number to be programmed.
Lock command FARG defines the page number to be locked.
GPNVM command FARG defines the GPNVM number.
Value Name Description
0x5A PASSWD The 0x5A value enables the command defined by the bits of
the register. If the field is written with a different value, the write
is not performed and no action is started.
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20.5.3 EEFC Flash Status Register
Name: EEFC_FSR
Address: 0x400E0A08 (0), 0x400E0C08 (1)
Access: Read-only
Offset: 0x08
• FRDY: Flash Ready Status
0: The Enhanced Embedded Flash Controller (EEFC) is busy.
1: The Enhanced Embedded Flash Controller (EEFC) is ready to start a new command.
When it is set, this flags triggers an interrupt if the FRDY flag is set in the EEFC_FMR register.
This flag is automatically cleared when the Enhanced Embedded Flash Controller (EEFC) is busy.
• FCMDE: Flash Command Error Status
0: No invalid commands and no bad keywords were written in the Flash Mode Register EEFC_FMR.
1: An invalid command and/or a bad keyword was/were written in the Flash Mode Register EEFC_FMR.
This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written.
• FLOCKE: Flash Lock Error Status
0: No programming/erase of at least one locked region has happened since the last read of EEFC_FSR.
1: Programming/erase of at least one locked region has happened since the last read of EEFC_FSR.
This flag is automatically cleared when EEFC_FSR is read or EEFC_FCR is written.
• FLERR: Flash Error Status
0: No Flash Memory error occurred at the end of programming (EraseVerify or WriteVerify test has passed).
1: A Flash Memory error occurred at the end of programming (EraseVerify or WriteVerify test has failed).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––FLERR FLOCKE FCMDE FRDY
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20.5.4 EEFC Flash Result Register
Name: EEFC_FRR
Address: 0x400E0A0C (0), 0x400E0C0C (1)
Access: Read-only
Offset: 0x0C
• FVALUE: Flash Result Value
The result of a Flash command is returned in this register. If the size of the result is greater than 32 bits, then the next resulting
value is accessible at the next register read.
31 30 29 28 27 26 25 24
FVALUE
23 22 21 20 19 18 17 16
FVALUE
15 14 13 12 11 10 9 8
FVALUE
76543210
FVALUE
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21. Fast Flash Programming Interface (FFPI)
21.1 Description
The Fast Flash Programming Interface (FFPI) provides parallel high-volume programming using a standard gang
programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM.
Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities.
Although the Fast Flash Programming Mode is a dedicated mode for high volume programming, this mode is not
designed for in-situ programming.
21.2 Parallel Fast Flash Programming
21.2.1 Device Configuration
In Fast Flash Programming Mode, the device is in a specific test mode. Only a certain set of pins is significant. The rest
of the PIOs are used as inputs with a pull-up. The crystal oscillator is in bypass mode. Other pins must be left
unconnected.
Figure 21-1. SAM4SxB/C (64/100 pins) Parallel Programming Interface
NCMD PGMNCMD
RDY PGMRDY
NOE PGMNOE
NVALID PGMNVALID
MODE[3:0] PGMM[3:0]
DATA[7:0] PGMD[7:0]
XIN
TST
VDDIO PGMEN0
PGMEN1
0 - 50MHz
VDDIO
VDDCORE
VDDIO
VDDPLL
GND
GND
VDDIO
PGMEN2
Table 21-1. Signal Description List
Signal Name Function Type Active
Level Comments
Power
VDDIO I/O Lines Power Supply Power
VDDCORE Core Power Supply Power
VDDPLL PLL Power Supply Power
GND Ground Ground
Clocks
XIN Main Clock Input. Input 32KHz to 50MHz
Test
TST Test Mode Select Input High Must be connected to VDDIO
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21.2.2 Signal Names
Depending on the MODE settings, DATA is latched in different internal registers.
When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command
register.
PGMEN0 Test Mode Select Input High Must be connected to VDDIO
PGMEN1 Test Mode Select Input High Must be connected to VDDIO
PGMEN2 Test Mode Select Input Low Must be connected to GND
PIO
PGMNCMD Valid command available Input Low Pulled-up input at reset
PGMRDY 0: Device is busy
1: Device is ready for a new command Output High Pulled-up input at reset
PGMNOE Output Enable (active high) Input Low Pulled-up input at reset
PGMNVALID 0: DATA[15:0] is in input mode
1: DATA[15:0] is in output mode Output Low Pulled-up input at reset
PGMM[3:0] Specifies DATA type (See Table 21-2) Input Pulled-up input at reset
PGMD[15:0] Bi-directional data bus Input/Output Pulled-up input at reset
Table 21-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Comments
Table 21-2. Mode Coding
MODE[3:0] Symbol Data
0000 CMDE Command Register
0001 ADDR0 Address Register LSBs
0010 ADDR1
0011 ADDR2
0100 ADDR3 Address Register MSBs
0101 DATA Data Register
Default IDLE No register
Table 21-3. Command Bit Coding
DATA[15:0] Symbol Command Executed
0x0011 READ Read Flash
0x0012 WP Write Page Flash
0x0022 WPL Write Page and Lock Flash
0x0032 EWP Erase Page and Write Page
0x0042 EWPL Erase Page and Write Page then Lock
0x0013 EA Erase All
0x0014 SLB Set Lock Bit
0x0024 CLB Clear Lock Bit
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21.2.3 Entering Programming Mode
The following algorithm puts the device in Parallel Programming Mode:
Apply GND, VDDIO, VDDCORE and VDDPLL.
Apply XIN clock within TPOR_RESET if an external clock is available.
Wait for TPOR_RESET
Start a read or write handshaking.
Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an external clock (>
32 kHz) is connected to XIN, then the device switches on the external clock. Else, XIN input is not considered. A
higher frequency on XIN speeds up the programmer handshake.
21.2.4 Programmer Handshaking
An handshake is defined for read and write operations. When the device is ready to start a new operation (RDY signal
set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is achieved once NCMD
signal is high and RDY is high.
21.2.4.1Write Handshaking
For details on the write handshaking sequence, refer to Figure 21-2 and Table 21-4.
Figure 21-2. SAM4SxB/C (64/100 pins) Parallel Programming Timing, Write Sequence
0x0015 GLB Get Lock Bit
0x0034 SGPB Set General Purpose NVM bit
0x0044 CGPB Clear General Purpose NVM bit
0x0025 GGPB Get General Purpose NVM bit
0x0054 SSE Set Security Bit
0x0035 GSE Get Security Bit
0x001F WRAM Write Memory
0x001E GVE Get Version
Table 21-3. Command Bit Coding (Continued)
DATA[15:0] Symbol Command Executed
NCMD
RDY
NOE
NVALID
DATA[7:0]
MODE[3:0]
1
2
3
4
5
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21.2.4.2Read Handshaking
For details on the read handshaking sequence, refer to Figure 21-3 and Table 21-5.
Figure 21-3. SAM4SxB/C (64/100 pins) Parallel Programming Timing, Read Sequence
Table 21-4. Write Handshake
Step Programmer Action Device Action Data I/O
1 Sets MODE and DATA signals Waits for NCMD low Input
2 Clears NCMD signal Latches MODE and DATA Input
3 Waits for RDY low Clears RDY signal Input
4 Releases MODE and DATA signals Executes command and polls NCMD high Input
5 Sets NCMD signal Executes command and polls NCMD high Input
6 Waits for RDY high Sets RDY Input
NCMD
RDY
NOE
NVALID
DATA[7:0]
MODE[3:0]
1
2
3
4
5
6
7
9
8
ADDR
Adress IN Z Data OUT
10
11
XIN
12
13
Table 21-5. Read Handshake
Step Programmer Action Device Action DATA I/O
1 Sets MODE and DATA signals Waits for NCMD low Input
2 Clears NCMD signal Latch MODE and DATA Input
3 Waits for RDY low Clears RDY signal Input
4 Sets DATA signal in tristate Waits for NOE Low Input
5 Clears NOE signal Tristate
6 Waits for NVALID low Sets DATA bus in output mode and outputs
the flash contents. Output
7 Clears NVALID signal Output
8 Reads value on DATA Bus Waits for NOE high Output
9 Sets NOE signal Output
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21.2.5 Device Operations
Several commands on the Flash memory are available. These commands are summarized in Table 21-3 on page 328.
Each command is driven by the programmer through the parallel interface running several read/write handshaking
sequences.
When a new command is executed, the previous one is automatically achieved. Thus, chaining a read command after a
write automatically flushes the load buffer in the Flash.
In the following table:
DATA[15:0] pertains to SAM4SxB/C (64/100 pins)
21.2.5.1Flash Read Command
This command is used to read the contents of the Flash memory. The read command can start at any valid address in
the memory plane and is optimized for consecutive reads. Read handshaking can be chained; an internal address buffer
is automatically increased.
21.2.5.2Flash Write Command
This command is used to write the Flash contents.
The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corresponds
to a Flash memory page. The load buffer is automatically flushed to the Flash:
Before access to any page other than the current one
When a new command is validated (MODE = CMDE)
10 Waits for NVALID high Sets DATA bus in input mode X
11 Sets DATA in output mode Sets NVALID signal Input
12 Sets NCMD signal Waits for NCMD high Input
13 Waits for RDY high Sets RDY signal Input
Table 21-5. Read Handshake (Continued)
Step Programmer Action Device Action DATA I/O
Table 21-6. Read Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE READ
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Read handshaking DATA *Memory Address++
5 Read handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Read handshaking DATA *Memory Address++
n+3 Read handshaking DATA *Memory Address++
... ... ... ...
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The Write Page command (WP) is optimized for consecutive writes. Write handshaking can be chained; an internal
address buffer is automatically increased.
The Flash command Write Page and Lock (WPL) is equivalent to the Flash Write Command. However, the lock bit is
automatically set at the end of the Flash write operation. As a lock region is composed of several pages, the programmer
writes to the first pages of the lock region using Flash write commands and writes to the last page of the lock region using
a Flash write and lock command.
The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before
programming the load buffer, the page is erased.
The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands.
21.2.5.3Flash Full Erase Command
This command is used to erase the Flash memory planes.
All lock regions must be unlocked before the Full Erase command by using the CLB command. Otherwise, the erase
command is aborted and no page is erased.
21.2.5.4Flash Lock Commands
Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With
this command, several lock bits can be activated. A Bit Mask is provided as argument to the command. When bit 0 of the
bit mask is set, then the first lock bit is activated.
In the same way, the Clear Lock command (CLB) is used to clear lock bits.
Table 21-7. Write Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE WP or WPL or EWP or EWPL
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Write handshaking DATA *Memory Address++
5 Write handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Write handshaking DATA *Memory Address++
n+3 Write handshaking DATA *Memory Address++
... ... ... ...
Table 21-8. Full Erase Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE EA
2 Write handshaking DATA 0
Table 21-9. Set and Clear Lock Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SLB or CLB
2 Write handshaking DATA Bit Mask
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Lock bits can be read using the Get Lock Bit command (GLB). The nth lock bit is active when the bit n of the bit mask is
set..
21.2.5.5Flash General-purpose NVM Commands
General-purpose NVM bits (GP NVM bits) can be set using the Set GPNVM command (SGPB). This command also
activates GP NVM bits. A bit mask is provided as argument to the command. When bit 0 of the bit mask is set, then the
first GP NVM bit is activated.
In the same way, the Clear GPNVM command (CGPB) is used to clear general-purpose NVM bits. The general-purpose
NVM bit is deactivated when the corresponding bit in the pattern value is set to 1.
General-purpose NVM bits can be read using the Get GPNVM Bit command (GGPB). The nth GP NVM bit is active when
bit n of the bit mask is set..
21.2.5.6Flash Security Bit Command
A security bit can be set using the Set Security Bit command (SSE). Once the security bit is active, the Fast Flash
programming is disabled. No other command can be run. An event on the Erase pin can erase the security bit once the
contents of the Flash have been erased.
Once the security bit is set, it is not possible to access FFPI. The only way to erase the security bit is to erase the Flash.
In order to erase the Flash, the user must perform the following:
Power-off the chip
Power-on the chip with TST = 0
Table 21-10. Get Lock Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GLB
2 Read handshaking DATA Lock Bit Mask Status
0 = Lock bit is cleared
1 = Lock bit is set
Table 21-11. Set/Clear GP NVM Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SGPB or CGPB
2 Write handshaking DATA GP NVM bit pattern value
Table 21-12. Get GP NVM Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GGPB
2 Read handshaking DATA GP NVM Bit Mask Status
0 = GP NVM bit is cleared
1 = GP NVM bit is set
Table 21-13. Set Security Bit Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE SSE
2 Write handshaking DATA 0
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Assert Erase during a period of more than 220 ms
Power-off the chip
Then it is possible to return to FFPI mode and check that Flash is erased.
21.2.5.7Memory Write Command
This command is used to perform a write access to any memory location.
The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an
internal address buffer is automatically increased.
21.2.5.8Get Version Command
The Get Version (GVE) command retrieves the version of the FFPI interface.
Table 21-14. Write Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE WRAM
2 Write handshaking ADDR0 Memory Address LSB
3 Write handshaking ADDR1 Memory Address
4 Write handshaking DATA *Memory Address++
5 Write handshaking DATA *Memory Address++
... ... ... ...
n Write handshaking ADDR0 Memory Address LSB
n+1 Write handshaking ADDR1 Memory Address
n+2 Write handshaking DATA *Memory Address++
n+3 Write handshaking DATA *Memory Address++
... ... ... ...
Table 21-15. Get Version Command
Step Handshake Sequence MODE[3:0] DATA[15:0]
1 Write handshaking CMDE GVE
2 Write handshaking DATA Version
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22. Cortex M Cache Controller (CMCC) (ONLY FOR SAM4SD32/SD16/SA16)
22.1 Description
The Cortex M Cache Controller (CMCC) is a 4-Way set associative unified cache controller. It integrates a controller, a
tag directory, data memory, metadata memory and a configuration interface.
22.2 Embedded Characteristics
Physically addressed and physically tagged
L1 data cache set to 2 Kbytes
L1 cache line size set to 16 Bytes
L1 cache integrates 32-bit bus master interface
Unified Direct mapped cache architecture
Unified 4-Way set associative cache architecture
Write through cache operations, read allocate
Round Robin victim selection policy
Event Monitoring, with one programmable 32-bit counter
Configuration registers accessible through Cortex M Private Peripheral Bus
Cache Interface includes cache maintenance operations registers
22.3 Block Diagram
Figure 22-1. Block Diagram
Cache
Controller METADATA RAM
DATA RAM
TAG RAM
RAM
Interface
Cortex M Interface
Memory Interface
Registers
Interface
APB
Interface
Cortex M Memory Interface Bus
System Memory Bus
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22.4 Functional Description
22.4.1 Cache Operation
On reset, the cache controller data entries are all invalidated and the cache is disabled. The cache is transparent to
processor operations. The cache controller is activated through the use of its configuration registers. The configuration
interface is memory mapped in the private peripheral bus.
Use the following sequence to enable the cache controller.
1. Verify that the cache controller is disabled, reading the value of the CSTS (cache status) field of the CMCC_SR
register.
2. Enable the cache controller, writing one to CEN (cache enable) field of the CMCC_CTRL register.
22.4.2 Cache Maintenance
If the contents seen by the cache has changed, the user needs to invalidate the cache entries. It can be done line by line
or for all cache entries.
22.4.2.1Cache Invalidate by Line Operation
When an invalidate by line command is issued the cache controller resets the valid bit information of the decoded cache
line. As the line is no longer valid the replacement counter points to that line.
Use the following sequence to invalidate one line of cache.
1. Disable the cache controller, writing 0 to the CEN field of the CMCC_CTRL register.
2. Check CSTS field of the CMCC_SR to verify that the cache is successfully disabled.
3. Perform an invalidate by line writing the bit set {index, way} in the CMCC_MAINT1 register.
4. Enable the cache controller, writing 1 to the CEN field of the CMCC_CTRL register.
22.4.2.2Cache Invalidate All Operation
To invalidate all cache entries:
Write 1 to the INVALL field of the CMCC_MAINT0 register.
22.4.3 Cache Performance Monitoring
The Cortex M cache controller includes a programmable 32-bit monitor counter. The monitor can be configured to count
the number of clock cycles, the number of data hits or the number of instruction hits.
Use the following sequence to activate the counter
1. Configure the monitor counter, writing the MODE field of the CMCC_CFG register.
2. Enable the counter, writing one to the MENABLE field of the CMCC_MEN register.
3. If required, reset the counter, writing one to the SWRST field of the CMCC_MCTRL register.
4. Check the value of the monitor counter, reading EVENT_CNT field of the CMCC_SR.
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22.5 Cortex M Cache Controller (CMCC) User Interface
Table 22-1. Register Mapping
Offset Register Name Access Reset
0x00 Cache Type Register CMCC_TYPE Read-only –
0x04 Cache Configuration Register CMCC_CFG Read-write 0x00000000
0x08 Cache Control Register CMCC_CTRL Write-only 0x00000000
0x0C Cache Status Register CMCC_SR Read-only 0x00000000
0x10 - 0x1C Reserved – – –
0x20 Cache Maintenance Register 0 CMCC_MAINT0 Write-only –
0x24 Cache Maintenance Register 1 CMCC_MAINT1 Write-only –
0x28 Cache Monitor Configuration Register CMCC_MCFG Read-write 0x00000000
0x2C Cache Monitor Enable Register CMCC_MEN Read-write 0x00000000
0x30 Cache Monitor Control Register CMCC_MCTRL Write-only –
0x34 Cache Monitor Status Register CMCC_MSR Read-only 0x00000000
0x38 - 0xFC Reserved – – –
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22.5.1 Cache Controller Type Register
Name: CMCC_TYPE
Address: 0x4007C000
Access: Read-only
• AP: Access Port Access Allowed
0: Access Port Access is disabled.
1: Access Port Access is enabled.
• GCLK: Dynamic Clock Gating Supported
0: Cache controller does not support clock gating.
1: Cache controller uses dynamic clock gating.
• RANDP: Random Selection Policy Supported
0: Random victim selection is not supported.
1: Random victim selection is supported.
• LRUP: Least Recently Used Policy Supported
0: Least Recently Used Policy is not supported.
1: Least Recently Used Policy is supported.
• RRP: Random Selection Policy Supported
0: Random Selection Policy is not supported.
1: Random Selection Policy is supported.
• WAYNUM: Number of Way
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– CLSIZE CSIZE
76543210
LCKDOWN WAYNUM RRP LRUP RANDP GCLK AP
Value Name Description
0 DMAPPED Direct Mapped Cache
1 ARCH2WAY 2-WAY set associative
2 ARCH4WAY 4-WAY set associative
3 ARCH8WAY 8-WAY set associative
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• LCKDOWN: Lock Down Supported
0: Lock Down is not supported.
1: Lock Down is supported.
• CSIZE: Cache Size
• CLSIZE: Cache Size
Value Name Description
0 CSIZE_1KB Cache Size 1 Kbytes
1 CSIZE_2KB Cache Size 2 Kbytes
2 CSIZE_4KB Cache Size 4 Kbytes
3 CSIZE_8KB Cache Size 8 Kbytes
Value Name Description
0 CLSIZE_1KB 4 bytes
1 CLSIZE_2KB 8 bytes
2 CLSIZE_4KB 16 bytes
3 CLSIZE_8KB 32 bytes
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22.5.2 Cache Controller Configuration Register
Name: CMCC_CFG
Address: 0x4007C004
Access: Read-write
• GCLKDIS: Disable Clock Gating
0: Clock gating is activated.
1: Clock gating is disabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––GCLKDIS
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22.5.3 Cache Controller Control Register
Name: CMCC_CTRL
Address: 0x4007C008
Access: Write-only
• CEN: Cache Controller Enable
0: When set to 0, this field disables the cache controller.
1: When set to 1, this field enables the cache controller.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––CEN
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22.5.4 Cache Controller Status Register
Name: CMCC_SR
Address: 0x4007C00C
Access: Read-only
• CSTS: Cache Controller Status
0: When read as 0, this field indicates that the cache controller is disabled.
1: When read as 1, this field indicates that the cache controller is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––CSTS
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22.5.5 Cache Controller Maintenance Register 0
Name: CMCC_MAINT0
Address: 0x4007C020
Access: Write-only
• INVALL: Cache Controller Invalidate All
0: No effect.
1: When set to one, this field invalidates all cache entries.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––INVALL
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22.5.6 Cache Controller Maintenance Register 1
Name: CMCC_MAINT1
Address: 0x4007C024
Access: Write-only
• INDEX: Invalidate Index
This field indicates the cache line that is being invalidated.
The size of the INDEX field depends on the cache size:
– for 2 Kbytes: 5 bits
– for 4 Kbytes: 6 bits
– for 8 Kbytes: 7 bits, and so on
• WAY: Invalidate Way
31 30 29 28 27 26 25 24
WAY ––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––INDEX
76543210
INDEX ––––
Value Name Description
0WAY0
Way 0 is selection for
index invalidation
1WAY1
Way 1 is selection for
index invalidation
2WAY2
Way 2 is selection for
index invalidation
3WAY3
Way 3 is selection for
index invalidation
345
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22.5.7 Cache Controller Monitor Configuration Register
Name: CMCC_MCFG
Address: 0x4007C028
Access: Write-only
• MODE: Cache Controller Monitor Counter Mode
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – – – MODE
Value Name Description
0 CYCLE_COUNT Cycle counter
1 IHIT_COUNT Instruction hit counter
2 DHIT_COUNT Data hit counter
346
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22.5.8 Cache Controller Monitor Enable Register
Name: CMCC_MEN
Address: 0x4007C02C
Access: Write-only
Reset: 0x00002000
• MENABLE: Cache Controller Monitor Enable
0: When set to 0, the monitor counter is disabled.
1: When set to 1, the monitor counter is activated.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––MENABLE
347
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22.5.9 Cache Controller Monitor Control Register
Name: CMCC_MCTRL
Address: 0x4007C030
Access: Write-only
Reset: 0x00002000
• SWRST: Monitor
0: No effect.
1: When set to 1, this field resets the event counter register.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SWRST
348
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22.5.10 Cache Controller Monitor Status Register
Name: CMCC_MSR
Address: 0x4007C034
Access: Read-only
Reset: 0x00002000
• EVENT_CNT: Monitor Event Counter
31 30 29 28 27 26 25 24
EVENT_CNT
23 22 21 20 19 18 17 16
EVENT_CNT
15 14 13 12 11 10 9 8
EVENT_CNT
76543210
EVENT_CNT
349
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23. Cyclic Redundancy Check Calculation Unit (CRCCU)
23.1 Description
The Cyclic Redundancy Check Calculation Unit (CRCCU) has its own DMA which functions as a Master with the Bus
Matrix. Three different polynomials are available: CCITT802.3, CASTAGNOLI and CCITT16.
23.2 Embedded Characteristics
32-bit cyclic redundancy check automatic calculation
CRC calculation between two addresses of the memory
23.3 CRCCU Block Diagram
Figure 23-1. Block Diagram
AHB-Layer
Context FSM
AHB Interface
Host
Interface
Atmel
APB Bus
AHB SRAM
Data Register
Addr Register
HRDATA
HTRANS
HSIZE
CRC Register
Flash
External
Bus Interface
350
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23.4 Product Dependencies
23.4.1 Power Management
The CRCCU is clocked through the Power Management Controller (PMC), the programmer must first configure the
CRCCU in the PMC to enable the CRCCU clock.
23.4.2 Interrupt Source
The CRCCU has an interrupt line connected to the Interrupt Controller. Handling the CRCCU interrupt requires
programming the Interrupt Controller before configuring the CRCCU.
23.5 CRCCU Functional Description
23.5.1 CRC Calculation Unit description
The CRCCU integrates a dedicated Cyclic Redundancy Check (CRC) engine. When configured and activated, this CRC
engine performs a checksum computation on a Memory Area. CRC computation is performed from the LSB to MSB bit.
Three different polynomials are available CCITT802.3, CASTAGNOLI and CCITT16, see the bitfield description,
“PTYPE: Primitive Polynomial” on page 365, for details.
23.5.2 CRC Calculation Unit Operation
The CRCCU has a DMA controller that supports programmable CRC memory checks. When enabled, the DMA channel
reads a programmable amount of data and computes CRC on the fly.
The CRCCU is controlled by two registers, TR_ADDR and TR_CTRL which need to be mapped in the internal SRAM.
The addresses of these two registers are pointed at by the CRCCU_DSCR register.
TR_ADDR defines the start address of memory area targeted for CRC calculation.
TR_CTRL defines the buffer transfer size, the transfer width (byte, halfword, word) and the transfer-completed interrupt
enable.
To start the CRCCU, the user needs to set the CRC enable bit (ENABLE) in the CRCCU Mode Register (CRCCU_MR),
then configure it and finally set the DMA enable bit (DMAEN) in the CRCCU DMA Enable Register (CRCCU_DMA_EN).
When the CRCCU is enabled, the CRCCU reads the predefined amount of data (defined in TR_CTRL) located from
TR_ADDR start address and computes the checksum.
The CRCCU_SR register contains the temporary CRC value.
Table 23-1. CRCCU Descriptor Memory Mapping
SRAM
Memory
CRCCU_DSCR+0x0 ----> TR_ADDR
CRCCU_DSCR+0x4 ----> TR_CTRL
CRCCU_DSCR+0x8 ----> Reserved
CRCCU_DSCR+0xC ----> Reserved
CRCCU_DSCR+0x10 ----> TR_CRC
351
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The BTSIZE field located in the TR_CTRL register (located in memory), is automatically decremented if its value is
different from zero. Once the value of the BTSIZE field is equal to zero, the CRCCU is disabled by hardware. In this case,
the relevant CRCCU DMA Status Register bit, DMASR, is automatically cleared.
If the COMPARE field of the CRCCU_MR register is set to true, the TR_CRC (Transfer Reference Register) is compared
with the last CRC computed. If a mismatch occurs, an error flag is set and an interrupt is raised (if unmasked).
The CRCCU accesses the memory by single access (TRWIDTH size) in order not to limit the bandwidth usage of the
system, but the DIVIDER field of the CRCCU Mode Register can be used to lower it by dividing the frequency of the
single accesses.
The CRCCU scrolls the defined memory area using ascending addresses.
In order to compute the CRC for a memory size larger than 256 Kbytes or for non-contiguous memory area, it is possible
to re-enable the CRCCU on the new memory area and the CRC will be updated accordingly. Use the RESET field of the
CRCCU_CR register to reset the CRCCU Status Register to its default value (0xFFFF_FFFF).
23.6 Transfer Control Registers Memory Mapping
Note: These Registers are memory mapped
Table 23-2. Transfer Control Register Memory Mapping
Offset Register Name Access
CRCCU_DSCR + 0x0 CRCCU Transfer Address Register TR_ADDR Read-write
CRCCU_DSCR + 0x4 CRCCU Transfer Control Register TR_CTRL Read-write
CRCCU_DSCR + 0xC - 0x10 Reserved
CRCCU_DSCR+0x10 CRCCU Transfer Reference Register TR_CRC Read-write
352
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23.6.1 Transfer Address Register
Name: TR_ADDR
Access: Read-write
Reset: 0x00000000
• ADDR: Transfer Address
31 30 29 28 27 26 25 24
ADDR
23 22 21 20 19 18 17 16
ADDR
15 14 13 12 11 10 9 8
ADDR
76543210
ADDR
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23.6.2 Transfer Control Register
Name: TR_CTRL
Access: Read-write
Reset: 0x00000000
• BTSIZE: Buffer Transfer Size
• TRWIDTH: Transfer Width Register
• IEN: Context Done Interrupt Enable
When set to zero, the transfer done status bit is set at the end of the transfer.
31 30 29 28 27 26 25 24
– – – – IEN – TRWIDTH
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
BTSIZE
76543210
BTSIZE
Value Name Description
00 BYTE The data size is 8-bit
01 HALFWORD The data size is 16-bit
10 WORD The data size is 32-bit
354
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23.6.3 Transfer Reference Register
Name: TR_CRC
Access: Read-write
Reset: 0x00000000
• REFCRC: Reference CRC
When Compare mode is enabled, the checksum is compared with that register.
31 30 29 28 27 26 25 24
REFCRC
23 22 21 20 19 18 17 16
REFCRC
15 14 13 12 11 10 9 8
REFCRC
76543210
REFCRC
355
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23.7 Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface
Table 23-3. Register Mapping
Offset Register Name Access Reset
0x00000000 CRCCU Descriptor Base Register CRCCU_DSCR Read-write 0x00000000
0x00000004 Reserved
0x00000008 CRCCU DMA Enable Register CRCCU_DMA_EN Write-only 0x00000000
0x0000000C CRCCU DMA Disable Register CRCCU_DMA_DIS Write-only 0x00000000
0x00000010 CRCCU DMA Status Register CRCCU_DMA_SR Read-only 0x00000000
0x00000014 CRCCU DMA Interrupt Enable Register CRCCU_DMA_IER Write-only 0x00000000
0x00000018 CRCCU DMA Interrupt Disable Register CRCCU_DMA_IDR Write-only 0x00000000
0x0000001C CRCCU DMA Interrupt Mask Register CRCCU_DMA_IMR Read-only 0x00000000
0x00000020 CRCCU DMA Interrupt Status Register CRCCU_DMA_ISR Read-only 0x00000000
0x0024-0x0030 Reserved
0x00000034 CRCCU Control Register CRCCU_CR Write-only 0x00000000
0x00000038 CRCCU Mode Register CRCCU_MR Read-write 0x00000000
0x0000003C CRCCU Status Register CRCCU_SR Read-only 0xFFFFFFFF
0x00000040 CRCCU Interrupt Enable Register CRCCU_IER Write-only 0x00000000
0x00000044 CRCCU Interrupt Disable Register CRCCU_IDR Write-only 0x00000000
0x00000048 CRCCU Interrupt Mask Register CRCCU_IMR Read-only 0x00000000
0x0000004C CRCCU Interrupt Status Register CRCCU_ISR Read-only 0x00000000
356
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23.7.1 CRCCU Descriptor Base Address Register
Name: CRCCU_DSCR
Address:0x40044000
Access: Read-write
Reset: 0x00000000
• DSCR: Descriptor Base Address
DSCR needs to be aligned with 512-byte boundaries.
31 30 29 28 27 26 25 24
DSCR
23 22 21 20 19 18 17 16
DSCR
15 14 13 12 11 10 9 8
DSCR –
76543210
––––––––
357
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23.7.2 CRCCU DMA Enable Register
Name: CRCCU_DMA_EN
Address:0x40044008
Access: Write-only
Reset: 0x00000000
• DMAEN: DMA Enable Register
Write one to enable the CRCCU DMA channel.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMAEN
358
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23.7.3 CRCCU DMA Disable Register
Name: CRCCU_DMA_DIS
Address:0x4004400C
Access: Write-only
Reset: 0x00000000
• DMADIS: DMA Disable Register
Write one to disable the DMA channel
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMADIS
359
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23.7.4 CRCCU DMA Status Register
Name: CRCCU_DMA_SR
Address:0x40044010
Access: Read-only
Reset: 0x00000000
• DMASR: DMA Status Register
When set to one, this bit indicates that DMA Channel is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMASR
360
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23.7.5 CRCCU DMA Interrupt Enable Register
Name: CRCCU_DMA_IER
Address:0x40044014
Access: Write-only
Reset: 0x00000000
• DMAIER: Interrupt Enable register
Set bit to one to enable the interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMAIER
361
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23.7.6 CRCCU DMA Interrupt Disable Register
Name: CRCCU_DMA_IDR
Address:0x40044018
Access: Write-only
Reset: 0x00000000
• DMAIDR: Interrupt Disable register
Set to one to disable the interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMAIDR
362
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23.7.7 CRCCU DMA Interrupt Mask Register
Name: CRCCU_DMA_IMR
Address:0x4004401C
Access: Write-only
Reset: 0x00000000
• DMAIMR: Interrupt Mask Register
0: Buffer Transfer Completed interrupt is disabled.
1: Buffer Transfer Completed interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMAIMR
363
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23.7.8 CRCCU DMA Interrupt Status Register
Name: CRCCU_DMA_ISR
Address:0x40044020
Access: Read-only
Reset: 0x00000000
• DMAISR: Interrupt Status register
When DMAISR is set, DMA buffer transfer has terminated. This flag is reset after read.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––DMAISR
364
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23.7.9 CRCCU Control Register
Name: CRCCU_CR
Address:0x40044034
Access: Write-only
Reset: 0x00000000
• RESET: CRC Computation Reset
When set to one, this bit resets the CRCCU_SR register to 0xFFFF FFFF.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––RESET
365
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23.7.10 CRCCU Mode Register
Name: CRCCU_MR
Address:0x40044038
Access: Read Write
Reset: 0x00000000
• ENABLE: CRC Enable
• COMPARE: CRC Compare
If set to one, this bit indicates that the CRCCU DMA will compare the CRC computed on the data stream with the value stored.
in the TR_CRC reference register. If a mismatch occurs, the ERRISR bit in the CRCCU_ISR register is set.
• PTYPE: Primitive Polynomial
• DIVIDER: Request Divider
CRCCU DMA performs successive transfers. It is possible to reduce the bandwidth drained by the CRCCU DMA by programming
the DIVIDER field. The transfer request frequency is divided by 2^(DIVIDER+1).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
DIVIDER PTYPE COMPARE ENABLE
Value Name Description
0 CCITT8023 Polynom 0x04C11DB7
1 CASTAGNOLI Polynom 0x1EDC6F41
2 CCITT16 Polynom 0x1021
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23.7.11 CRCCU Status Register
Name: CRCCU_SR
Address:0x4004403C
Access: Read-only
Reset: 0x00000000
• CRC: Cyclic Redundancy Check Value
This register can not be read if the COMPARE field of the CRC_MR register is set to true.
31 30 29 28 27 26 25 24
CRC
23 22 21 20 19 18 17 16
CRC
15 14 13 12 11 10 9 8
CRC
76543210
CRC
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23.7.12 CRCCU Interrupt Enable Register
Name: CRCCU_IER
Address:0x40044040
Access: Write-only
Reset: 0x00000000
• ERRIER: CRC Error Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––ERRIER
368
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23.7.13 CRCCU Interrupt Disable Register
Name: CRCCU_IDR
Address:0x40044044
Access: Write-only
Reset: 0x00000000
• ERRIDR: CRC Error Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––ERRIDR
369
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23.7.14 CRCCU Interrupt Mask Register
Name: CRCCU_IMR
Address:0x40044048
Access: Write-only
Reset: 0x00000000
• ERRIMR: CRC Error Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––ERRIMR
370
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23.7.15 CRCCU Interrupt Status Register
Name: CRCCU_ISR
Address:0x4004404C
Access: Read-only
Reset: 0x00000000
• ERRISR: CRC Error Interrupt Status
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––ERRISR
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24. SAM4S Boot Program
24.1 Description
The SAM-BA Boot Program integrates an array of programs permitting download and/or upload into the different
memories of the product.
24.2 Hardware and Software Constraints
SAM-BA Boot uses the first 2048 bytes of the SRAM for variables and stacks. The remaining available size can be
used for user's code.
USB Requirements:
External Crystal or External Clock(1) with frequency of:
11,289 MHz
12,000 MHz
16,000 MHz
18,432 MHz
UART0 requirements: None
Note: 1. Must be 2500 ppm and 1.2V Square Wave Signal.
24.3 Flow Diagram
The Boot Program implements the algorithm in Figure 24-1.
Figure 24-1. Boot Program Algorithm Flow Diagram
The SAM-BA Boot program seeks to detect a source clock either from the embedded main oscillator with external crystal
(main oscillator enabled) or from a supported frequency signal applied to the XIN pin (Main oscillator in bypass mode).
If a clock is found from the two possible sources above, the boot program checks to verify that the frequency is one of the
supported external frequencies. If the frequency is one of the supported external frequencies, USB activation is allowed,
else (no clock or frequency other than one of the supported external frequencies), the internal 12 MHz RC oscillator is
used as main clock and USB clock is not allowed due to frequency drift of the 12 MHz RC oscillator.
Table 24-1. Pins Driven during Boot Program Execution
Peripheral Pin PIO Line
UART0 URXD0 PA9
UART0 UTXD0 PA10
Device
Setup Character received
from UART0
Run SAM-BA Monitor
USB Enumeration
Successful
Yes
Run SAM-BA Monitor
Yes
No
No
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24.4 Device Initialization
Initialization follows the steps described below:
1. Stack setup
2. Setup the Embedded Flash Controller
3. External Clock detection (crystal or external clock on XIN)
4. If external crystal or clock with supported frequency, allow USB activation
5. Else, does not allow USB activation and use internal 12 MHz RC oscillator
6. Main oscillator frequency detection if no external clock detected
7. Switch Master Clock on Main Oscillator
8. C variable initialization
9. PLLA setup: PLLA is initialized to generate a 48 MHz clock
10. Disable the Watchdog
11. Initialization of UART0 (115200 bauds, 8, N, 1)
12. Initialization of the USB Device Port (in case USB activation allowed)
13. Wait for one of the following events
1. Check if USB device enumeration has occurred
2. Check if characters have been received in UART0
14. Jump to SAM-BA Monitor (see Section 24.5 ”SAM-BA Monitor”)
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24.5 SAM-BA Monitor
The SAM-BA boot principle:
Once the communication interface is identified, to run in an infinite loop waiting for different commands as shown in Table
24-2.
Mode commands:
Normal mode configures SAM-BA Monitor to send/receive data in binary format,
Terminal mode configures SAM-BA Monitor to send/receive data in ascii format.
Write commands: Write a byte (O), a halfword (H) or a word (W) to the target.
Address: Address in hexadecimal.
Value: Byte, halfword or word to write in hexadecimal.
Output: ‘>’.
Read commands: Read a byte (o), a halfword (h) or a word (w) from the target.
Address: Address in hexadecimal
Output: The byte, halfword or word read in hexadecimal following by ‘>’
Send a file (S): Send a file to a specified address
Address: Address in hexadecimal
Output: ‘>’.
Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the com-
mand execution.
Receive a file (R): Receive data into a file from a specified address
Address: Address in hexadecimal
NbOfBytes: Number of bytes in hexadecimal to receive
Output: ‘>’
Go (G): Jump to a specified address and execute the code
Address: Address to jump in hexadecimal
Output: ‘>’
Table 24-2. Commands Available through the SAM-BA Boot
Command Action Argument(s) Example
NSet Normal Mode No argument N#
TSet Terminal Mode No argument T#
OWrite a Byte Address, Value# O200001,CA#
oRead a Byte Address,# o200001,#
HWrite a Half Word Address, Value# H200002,CAFE#
hRead a Half Word Address,# h200002,#
WWrite a Word Address, Value# W200000,CAFEDECA#
wRead a Word Address,# w200000,#
SSend a File Address,# S200000,#
RReceive a File Address, NbOfBytes# R200000,1234#
GGo Address# G200200#
VDisplay Version No argument V#
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Get Version (V): Return the SAM-BA boot version
Output: ‘>’
24.5.1 UART0 Serial Port
Communication is performed through the UART0 initialized to 115200 Baud, 8, n, 1.
The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol
can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size
embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem
protocol requires some SRAM memory to work. See, Section 24.2 ”Hardware and Software Constraints”
24.5.2 Xmodem Protocol
The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee
detection of a maximum bit error.
Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of
the transfer looks like:
<SOH><blk #><255-blk #><--128 data bytes--><checksum> in which:
<SOH> = 01 hex
<blk #> = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01)
<255-blk #> = 1’s complement of the blk#.
<checksum> = 2 bytes CRC16
Figure 24-2 shows a transmission using this protocol.
Figure 24-2. Xmodem Transfer Example
24.5.3 USB Device Port
The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232
software to talk over the USB. The CDC class is implemented in all releases of Windows®, from Windows 98SE to
Windows XP. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN
modems and virtual COM ports.
Host Device
SOH 01 FE Data[128] CRC CRC
C
ACK
SOH 02 FD Data[128] CRC CRC
ACK
SOH 03 FC Data[100] CRC CRC
ACK
EOT
ACK
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The Vendor ID (VID) is Atmel’s vendor ID 0x03EB. The product ID (PID) is 0x6124. These references are used by the
host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence
between vendor ID and product ID.
For More details about VID/PID for End Product/Systems, please refer to the Vendor ID form available from the USB
Implementers Forum:
http://www.usb.org/developers/vendor/VID_Only_Form_withCCAuth_102407b.pdf
"Unauthorized use of assigned or unassigned USB Vendor ID Numbers and associated Product ID Numbers is strictly
prohibited."
Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by
the SAM-BA application: atm6124.sys. Refer to the document “USB Basic Application”, literature number 6123, for more
details.
24.5.3.1Enumeration Process
The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device
through the control endpoint. The device handles standard requests as defined in the USB Specification.
The device also handles some class requests defined in the CDC class.
Unhandled requests are STALLed.
24.5.3.2Communication Endpoints
There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte
Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the host through
endpoint 1. If required, the message is split by the host into several data payloads by the host driver.
If the command requires a response, the host can send IN transactions to pick up the response.
Table 24-3. Handled Standard Requests
Request Definition
GET_DESCRIPTOR Returns the current device configuration value.
SET_ADDRESS Sets the device address for all future device access.
SET_CONFIGURATION Sets the device configuration.
GET_CONFIGURATION Returns the current device configuration value.
GET_STATUS Returns status for the specified recipient.
SET_FEATURE Set or Enable a specific feature.
CLEAR_FEATURE Clear or Disable a specific feature.
Table 24-4. Handled Class Requests
Request Definition
SET_LINE_CODING Configures DTE rate, stop bits, parity and number of
character bits.
GET_LINE_CODING Requests current DTE rate, stop bits, parity and number
of character bits.
SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE
device is now present.
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24.5.4 In Application Programming (IAP) Feature
The IAP feature is a function located in ROM that can be called by any software application.
When called, this function sends the desired FLASH command to the EEFC and waits for the Flash to be ready (looping
while the FRDY bit is not set in the MC_FSR register).
Since this function is executed from ROM, this allows Flash programming (such as sector write) to be done by code
running in Flash.
The IAP function entry point is retrieved by reading the NMI vector in ROM (0x00800008).
This function takes one argument in parameter: the command to be sent to the EEFC.
This function returns the value of the MC_FSR register.
IAP software code example:
(unsigned int) (*IAP_Function)(unsigned long);
void main (void){
unsigned long FlashSectorNum = 200; //
unsigned long flash_cmd = 0;
unsigned long flash_status = 0;
unsigned long EFCIndex = 0; // 0:EEFC0, 1: EEFC1
/* Initialize the function pointer (retrieve function address from NMI vector)
*/
IAP_Function = ((unsigned long) (*)(unsigned long))
0x00800008;
/* Send your data to the sector here */
/* build the command to send to EEFC */
flash_cmd = (0x5A << 24) | (FlashSectorNum << 8) |
AT91C_MC_FCMD_EWP;
/* Call the IAP function with appropriate command */
flash_status = IAP_Function (EFCIndex, flash_cmd);
}
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25. Bus Matrix (MATRIX)
25.1 Description
The Bus Matrix (MATRIX) implements a multi-layer AHB that enables parallel access paths between multiple AHB
masters and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 4 AHB Masters to 5
AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the
accessed slave which is connected directly (zero cycle latency).
The Bus Matrix user interface also provides a Chip Configuration User Interface with Registers that allow to support
application specific features.
25.2 Embedded Characteristics
25.2.1 Matrix Masters
The Bus Matrix manages 4 masters, which means that each master can perform an access concurrently with others, to
an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the
masters have the same decodings.
25.2.2 Matrix Slaves
The Bus Matrix manages 5 slaves. Each slave has its own arbiter, allowing a different arbitration per slave.
Table 25-1. List of Bus Matrix Masters
Master 0 Cortex-M4 Instruction/Data
Master 1 Cortex-M4 System
Master 2 Peripheral DMA Controller (PDC)
Master 3 CRC Calculation Unit
Table 25-2. List of Bus Matrix Slaves
Slave 0 Internal SRAM
Slave 1 Internal ROM
Slave 2 Internal Flash
Slave 3 External Bus Interface
Slave 4 Peripheral Bridge
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25.2.3 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing
access from the Cortex-M4 S Bus to the Internal ROM. Thus, these paths are forbidden or simply not wired, and shown
as “-” in the following table
25.3 Memory Mapping
Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each AHB Master several memory
mappings. In fact, depending on the product, each memory area may be assigned to several slaves. Booting at the same
address while using different AHB slaves (i.e. internal ROM or internal Flash) becomes possible.
25.4 Special Bus Granting Techniques
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some
masters. This mechanism allows to reduce latency at first accesses of a burst or single transfer. The bus granting
mechanism allows to set a default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated default
master. A slave can be associated with three kinds of default masters: no default master, last access master and fixed
default master.
25.4.1 No Default Master
At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default
Master suits low power mode.
25.4.2 Last Access Master
At the end of the current access, if no other request is pending, the slave remains connected to the last master that
performed an access request.
25.4.3 Fixed Default Master
At the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike last
access master, the fixed master doesn’t change unless the user modifies it by a software action (field FIXED_DEFMSTR
of the related MATRIX_SCFG).
To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration
Registers, one for each slave, that allow to set a default master for each slave. The Slave Configuration Register
contains two fields:
DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field allows to choose the default master type (no
default, last access master, fixed default master) whereas the 4-bit FIXED_DEFMSTR field allows to choose a fixed
Table 25-3. Master to Slave Access
Slaves
Masters 0 1 2 3
Cortex-M4
I/D Bus Cortex-M4
S Bus PDC CRCCU
0 Internal SRAM - X X X
1 Internal ROM X - X X
2 Internal Flash X - - X
3 External Bus Interface - X X X
4 Peripheral Bridge - X X -
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default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user interface
description.
25.5 Arbitration
The Bus Matrix provides an arbitration mechanism that allows to reduce latency when conflict cases occur, basically
when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided,
allowing to arbitrate each slave differently.
The Bus Matrix provides to the user the possibility to choose between 2 arbitration types, and this for each slave:
1. Round-Robin Arbitration (the default)
2. Fixed Priority Arbitration
This choice is given through the field ARBT of the Slave Configuration Registers (MATRIX_SCFG).
Each algorithm may be complemented by selecting a default master configuration for each slave.
When a re-arbitration has to be done, it is realized only under some specific conditions detailed in the following
paragraph.
25.5.1 Arbitration Rules
Each arbiter has the ability to arbitrate between two or more different master’s requests. In order to avoid burst breaking
and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following
cycles:
1. Idle Cycles: when a slave is not connected to any master or is connected to a master which is not currently
accessing it.
2. Single Cycles: when a slave is currently doing a single access.
3. End of Burst Cycles: when the current cycle is the last cycle of a burst transfer. For defined length burst, predicted
end of burst matches the size of the transfer but is managed differently for undefined length burst (See Section
25.5.1.1 “Undefined Length Burst Arbitration” on page 379“).
4. Slot Cycle Limit: when the slot cycle counter has reached the limit value indicating that the current master access
is too long and must be broken (See Section 25.5.1.2 “Slot Cycle Limit Arbitration” on page 379).
25.5.1.1Undefined Length Burst Arbitration
In order to avoid too long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in
order to re-arbitrate before the end of the INCR transfer.
A predicted end of burst is used for defined length burst transfer, which is selected between the following:
1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer will never be broken.
2. Four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside INCR transfer.
3. Eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside INCR transfer.
4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside INCR
transfer.
This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG).
25.5.1.2Slot Cycle Limit Arbitration
The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a very slow slave (e.g. an
external low speed memory). At the beginning of the burst access, a counter is loaded with the value previously written in
the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock cycle.
When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word
transfer.
25.5.2 Round-Robin Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave in a
round-robin manner. If two or more master’s requests arise at the same time, the master with the lowest number is first
serviced then the others are serviced in a round-robin manner.
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There are three round-robin algorithm implemented:
Round-Robin arbitration without default master
Round-Robin arbitration with last access master
Round-Robin arbitration with fixed default master
25.5.2.1Round-Robin arbitration without default master
This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different
masters to the same slave in a pure round-robin manner. At the end of the current access, if no other request is pending,
the slave is disconnected from all masters. This configuration incurs one latency cycle for the first access of a burst.
Arbitration without default master can be used for masters that perform significant bursts.
25.5.2.2Round-Robin arbitration with last access master
This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency
cycle for the last master that accessed the slave. In fact, at the end of the current transfer, if no other master request is
pending, the slave remains connected to the last master that performs the access. Other non privileged masters will still
get one latency cycle if they want to access the same slave. This technique can be used for masters that mainly perform
single accesses.
25.5.2.3Round-Robin arbitration with fixed default master
This is another biased round-robin algorithm, it allows the Bus Matrix arbiters to remove the one latency cycle for the
fixed default master per slave. At the end of the current access, the slave remains connected to its fixed default master.
Every request attempted by this fixed default master will not cause any latency whereas other non privileged masters will
still get one latency cycle. This technique can be used for masters that mainly perform single accesses.
25.5.3 Fixed Priority Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using
the fixed priority defined by the user. If two or more master’s requests are active at the same time, the master with the
highest priority number is serviced first. If two or more master’s requests with the same priority are active at the same
time, the master with the highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority Registers for Slaves (MATRIX_PRAS and
MATRIX_PRBS).
25.6 System I/O Configuration
The System I/O Configuration register (CCFG_SYSIO) allows to configure some I/O lines in System I/O mode (such as
JTAG, ERASE, USB, etc...) or as general purpose I/O lines. Enabling or disabling the corresponding I/O lines in
peripheral mode or in PIO mode (PIO_PER or PIO_PDR registers) in the PIO controller as no effect. However, the
direction (input or output), pull-up, pull-down and other mode control is still managed by the PIO controller.
25.7 Write Protect Registers
To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX address space from
address offset 0x000 to 0x1FC can be write-protected by setting the WPEN bit in the MATRIX Write Protect Mode
Register (MATRIX_WPMR).
If a write access to anywhere in the MATRIX address space from address offset 0x000 to 0x1FC is detected, then the
WPVS flag in the MATRIX Write Protect Status Register (MATRIX_WPSR) is set and the field WPVSRC indicates in
which register the write access has been attempted.
The WPVS flag is reset by writing the MATRIX Write Protect Mode Register (MATRIX_WPMR) with the appropriate
access key WPKEY.
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25.8 Bus Matrix (MATRIX) User Interface
Table 25-4. Register Mapping
Offset Register Name Access Reset
0x0000 Master Configuration Register 0 MATRIX_MCFG0 Read-write 0x00000000
0x0004 Master Configuration Register 1 MATRIX_MCFG1 Read-write 0x00000000
0x0008 Master Configuration Register 2 MATRIX_MCFG2 Read-write 0x00000000
0x000C Master Configuration Register 3 MATRIX_MCFG3 Read-write 0x00000000
0x0010 - 0x003C Reserved – – –
0x0040 Slave Configuration Register 0 MATRIX_SCFG0 Read-write 0x00010010
0x0044 Slave Configuration Register 1 MATRIX_SCFG1 Read-write 0x00050010
0x0048 Slave Configuration Register 2 MATRIX_SCFG2 Read-write 0x00000010
0x004C Slave Configuration Register 3 MATRIX_SCFG3 Read-write 0x00000010
0x0050 Slave Configuration Register 4 MATRIX_SCFG4 Read-write 0x00000010
0x0054 - 0x007C Reserved – – –
0x0080 Priority Register A for Slave 0 MATRIX_PRAS0 Read-write 0x00000000
0x0084 Reserved – – –
0x0088 Priority Register A for Slave 1 MATRIX_PRAS1 Read-write 0x00000000
0x008C Reserved – – –
0x0090 Priority Register A for Slave 2 MATRIX_PRAS2 Read-write 0x00000000
0x0094 Reserved – – –
0x0098 Priority Register A for Slave 3 MATRIX_PRAS3 Read-write 0x00000000
0x009C Reserved – – –
0x00A0 Priority Register A for Slave 4 MATRIX_PRAS4 Read-write 0x00000000
0x00A4 - 0x0110 Reserved – – –
0x0114 System I/O Configuration register CCFG_SYSIO Read/Write 0x00000000
0x0118 Reserved – – –
0x011C SMC Chip Select NAND Flash Assignment
Register CCFG_SMCNFCS Read/Write 0x00000000
0x0120 - 0x010C Reserved – – –
0x1E4 Write Protect Mode Register MATRIX_WPMR Read-write 0x0
0x1E8 Write Protect Status Register MATRIX_WPSR Read-only 0x0
0x0110 - 0x01FC Reserved – – –
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25.8.1 Bus Matrix Master Configuration Registers
Name: MATRIX_MCFG0..MATRIX_MCFG3
Address: 0x400E0200
Access: Read-write
• ULBT: Undefined Length Burst Type
0: Infinite Length Burst
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
1: Single Access
The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR burst.
2: Four Beat Burst
The undefined length burst is split into a 4-beat bursts allowing rearbitration at each 4-beat burst end.
3: Eight Beat Burst
The undefined length burst is split into 8-beat bursts allowing rearbitration at each 8-beat burst end.
4: Sixteen Beat Burst
The undefined length burst is split into 16-beat bursts allowing rearbitration at each 16-beat burst end.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––– ULBT
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25.8.2 Bus Matrix Slave Configuration Registers
Name: MATRIX_SCFG0..MATRIX_SCFG4
Address: 0x400E0240
Access: Read-write
• SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reach for a burst it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slaves when very long bursts are used.
This limit should not be very small though. An unreasonable small value will break every burst and the Bus Matrix will spend its
time to arbitrate without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
• DEFMSTR_TYPE: Default Master Type
0: No Default Master
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in having a one cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of current slave access, if no other master request is pending, the slave stays connected to the last master having
accessed it.
This results in not having the one cycle latency when the last master re-tries access on the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number
that has been written in the FIXED_DEFMSTR field.
This results in not having the one cycle latency when the fixed master re-tries access on the slave again.
• FIXED_DEFMSTR: Fixed Default Master
This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master
which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
• ARBT: Arbitration Type
0: Round-Robin Arbitration
1: Fixed Priority Arbitration
2: Reserved
3: Reserved
31 30 29 28 27 26 25 24
–––––– ARBT
23 22 21 20 19 18 17 16
– – – FIXED_DEFMSTR DEFMSTR_TYPE
15 14 13 12 11 10 9 8
––––––––
76543210
SLOT_CYCLE
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25.8.3 Bus Matrix Priority Registers For Slaves
Name: MATRIX_PRAS0..MATRIX_PRAS4
Address: 0x400E0280 [0], 0x400E0288 [1], 0x400E0290 [2], 0x400E0298 [3], 0x400E02A0 [4]
Access: Read-write
• MxPR: Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––– M4PR
15 14 13 12 11 10 9 8
– – M3PR – – M2PR
76543210
– – M1PR – – M0PR
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25.8.4 System I/O Configuration Register
Name: CCFG_SYSIO
Address: 0x400E0314
Access Read-write
Reset: 0x0000_0000
• SYSIO4: PB4 or TDI Assignment
0 = TDI function selected.
1 = PB4 function selected.
• SYSIO5: PB5 or TDO/TRACESWO Assignment
0 = TDO/TRACESWO function selected.
1 = PB5 function selected.
• SYSIO6: PB6 or TMS/SWDIO Assignment
0 = TMS/SWDIO function selected.
1 = PB6 function selected.
• SYSIO7: PB7 or TCK/SWCLK Assignment
0 = TCK/SWCLK function selected.
1 = PB7 function selected.
• SYSIO10: PB10 or DDM Assignment
0 = DDM function selected.
1 = PB10 function selected.
• SYSIO11: PB11 or DDP Assignment
0 = DDP function selected.
1 = PB11 function selected.
• SYSIO12: PB12 or ERASE Assignment
0 = ERASE function selected.
1 = PB12 function selected.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – SYSIO12 SYSIO11 SYSIO10 – –
76543210
SYSIO7 SYSIO6 SYSIO5 SYSIO4 – – – –
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25.8.5 SMC NAND Flash Chip select Configuration Register
Name: CCFG_SMCNFCS
Address: 0x400E031C
Type: Read-write
Reset: 0x0000_0000
• SMC_NFCS0: SMC NAND Flash Chip Select 0 Assignment
0 = NCS0 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS0)
1 = NCS0 is assigned to a NAND Flash (NANDOE and NANWE used for NCS0)
• SMC_NFCS1: SMC NAND Flash Chip Select 1 Assignment
0 = NCS1 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS1)
1 = NCS1 is assigned to a NAND Flash (NANDOE and NANWE used for NCS1)
• SMC_NFCS2: SMC NAND Flash Chip Select 2 Assignment
0 = NCS2 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS2)
1 = NCS2 is assigned to a NAND Flash (NANDOE and NANWE used for NCS2)
• SMC_NFCS3: SMC NAND Flash Chip Select 3 Assignment
0 = NCS3 is not assigned to a NAND Flash (NANDOE and NANWE not used for NCS3)
1 = NCS3 is assigned to a NAND Flash (NANDOE and NANWE used for NCS3)
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––SMC_NFCS3 SMC_NFCS2 SMC_NFCS1 SMC_NFCS0
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25.8.6 Write Protect Mode Register
Name: MATRIX_WPMR
Address: 0x400E03E4
Access: Read-write
For more details on MATRIX_WPMR, refer to Section 25.7 “Write Protect Registers” on page 380.
• WPEN: Write Protect ENable
0 = Disables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x4D4154 (“MAT” in ASCII).
Protects the entire MATRIX address space from address offset 0x000 to 0x1FC.
• WPKEY: Write Protect KEY (Write-only)
Should be written at value 0x4D4154 (“MAT” in ASCII). Writing any other value in this field aborts the write operation of the WPEN
bit. Always reads as 0.
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
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25.8.7 Write Protect Status Register
Name: MATRIX_WPSR
Address: 0x400E03E8
Access: Read-only
For more details on MATRIX_WPSR, refer to Section 25.7 “Write Protect Registers” on page 380.
• WPVS: Write Protect Violation Status
0: No Write Protect Violation has occurred since the last write of MATRIX_WPMR.
1: At least one Write Protect Violation has occurred since the last write of MATRIX_WPMR.
• WPVSRC: Write Protect Violation Source
Should be written at value 0x4D4154 (“MAT” in ASCII). Writing any other value in this field aborts the write operation of the WPEN
bit. Always reads as 0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
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26. Static Memory Controller (SMC)
26.1 Description
The External Bus Interface is designed to ensure the successful data transfer between several external devices and the
Cortex-M4 based device. The External Bus Interface of the SAM4S consists of a Static Memory Controller (SMC).
This SMC is capable of handling several types of external memory and peripheral devices, such as SRAM, PSRAM,
PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.
The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or
peripheral devices. It has 4 Chip Selects, a 24-bit address bus, and an 8-bit data bus. Separate read and write control
signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully adjustable.
The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an
automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate specific
waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for page size up
to 32 bytes.
The External Data Bus can be scrambled/unscrambled by means of user keys.
26.2 Embedded Characteristics
16-Mbyte Address Space per Chip Select
8- bit Data Bus
Word, Halfword, Byte Transfers
Byte Write or Byte Select Lines
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
Programmable Data Float Time per Chip Select
Compliant with LCD Module
External Wait Request
Automatic Switch to Slow Clock Mode
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
NAND Flash additional logic supporting NAND Flash with Multiplexed Data/Address buses
Hardware Configurable number of chip select from 1 to 4
Programmable timing on a per chip select basis
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26.3 I/O Lines Description
26.4 Product Dependencies
26.4.1 I/O Lines
The pins used for interfacing the Static Memory Controller are multiplexed with the PIO lines. The programmer must first
program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O Lines of the SMC
are not used by the application, they can be used for other purposes by the PIO Controller.
26.4.2 Power Management
The SMC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the SMC clock.
26.5 External Memory Mapping
The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address up to 16 Mbytes of
memory.
If the physical memory device connected on one chip select is smaller than 16 Mbytes, it wraps around and appears to
be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see
Figure 26-1).
Table 26-1. I/O Line Description
Name Description Type Active Level
NCS[3:0] Static Memory Controller Chip Select Lines Output Low
NRD Read Signal Output Low
NWE Write Enable Signal Output Low
A[23:0] Address Bus Output
D[7:0] Data Bus I/O
NWAIT External Wait Signal Input Low
NANDCS NAND Flash Chip Select Line Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
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Figure 26-1. Memory Connections for Four External Devices
26.6 Connection to External Devices
26.6.1 Data Bus Width
The data bus width is 8 bits.
Figure 26-2 shows how to connect a 512K x 8-bit memory on NCS0.
Figure 26-2. Memory Connection for an 8-bit Data Bus
26.6.1.1NAND Flash Support
The SMC integrates circuitry that interfaces to NAND Flash devices.
The NAND Flash logic is driven by the Static Memory Controller. It depends on the programming of the SMC_NFCSx
field in the CCFG_SMCNFCS Register on the Bus Matrix User Interface. For details on this register, refer to the Bus
Matrix User Interface section. Access to an external NAND Flash device via the address space reserved to the chip
select programmed.
The user can connect up to 4 NAND Flash devices with separated chip select.
The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals
when the NCSx programmed is active. NANDOE and NANDWE are disabled as soon as the transfer address fails to lie
in the NCSx programmed address space.
NRD
NWE
A[23:0]
D[7:0]
8
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Output Enable
Write Enable
A[23:0]
D[7:0]
NCS3
NCS0
NCS1
NCS2
NCS[0] - NCS[3]
SMC
24
SMC
NWE
NRD
NCS[0]
Write Enable
Output Enable
Memory Enable
D[7:0] D[7:0]
A[18:0]
A[18:0]
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Figure 26-3. NAND Flash Signal Multiplexing on SMC Pins
Note: When NAND Flash logic is activated, (SMCNFCSx=1), NWE pin cannot be used i PIO Mode but only in peripheral
mode (NWE function). If NWE function is not used for other external memories (SRAM, LCD), it must be configured in
one of the following modes.
PIO Input with pull-up enabled (default state after reset)
PIO Output set at level 1
The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22
and A21of the address bus. Any bit of the address bus can also be used for this purpose. The command, address or data
words on the data bus of the NAND Flash device use their own addresses within the NCSx address space (configured by
CCFG_SMCNFCS Register on the Bus Matrix User Interface). The chip enable (CE) signal of the device and the
ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCS3 is not
selected, preventing the device from returning to standby mode. The NANDCS output signal should be used in
accordance with the external NAND Flash device type.
Two types of CE behavior exist depending on the NAND flash device:
Standard NAND Flash devices require that the CE pin remains asserted Low continuously during the read busy
period to prevent the device from returning to standby mode. Since the Static Memory Controller (SMC) asserts
the NCSx signal High, it is necessary to connect the CE pin of the NAND Flash device to a GPIO line, in order to
hold it low during the busy period preceding data read out.
This restriction has been removed for “CE don’t care” NAND Flash devices. The NCSx signal can be directly
connected to the CE pin of the NAND Flash device.
Figure 26-4 illustrates both topologies: Standard and “CE don’t care” NAND Flash.
SMC
NRD
NWE
NANDOE
NANDWE
NAND Flash Logic
NCSx (activated if SMC_NFCSx=1) *
NANDWE
NANDOE
* in CCFG_SMCNFCS Matrix register
393
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-4. Standard and “CE don’t care” NAND Flash Application Examples
26.7 Application Example
26.7.1 Implementation Examples
Hardware configurations are given for illustration only. The user should refer to the manufacturer web site to check for
memory device availability.
For hardware implementation examples, refer to SAM4S-EK schematics, which show examples of a connection to an
LCD module and NAND Flash.
D[7:0]
ALE
NANDWE NOE
NWE
A[22:21]
CLE
AD[7:0]
PIO R/B
SMC
CE
NAND Flash
PIO
NCSx Not Connected
NANDOE
D[7:0]
ALE
NANDWE NOE
NWE
A[22:21]
CLE
AD[7:0]
PIO R/B
SMC
CE
“CE don t care”
NAND Flash
NCSx
NANDOE
394
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.7.1.18-bit NAND Flash
Hardware Configuration
Software Configuration
Perform the following configuration:
Assign the SMC_NFCSx (for example SMC_NFCS3) field in the CCFG_SMCNFCS Register on the Bus Matrix
User Interface.
Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled respectively by setting
to 1 the address bits A21 and A22 during accesses.
NANDOE and NANDWE signals are multiplexed with PIO lines. Thus, the dedicated PIOs must be programmed in
peripheral mode in the PIO controller.
Configure a PIO line as an input to manage the Ready/Busy signal.
Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode according to NAND Flash timings, the
data bus width and the system bus frequency.
In this example, the NAND Flash is not addressed as a “CE don’t care”. To address it as a “CE don’t care”, connect
NCS3 (if SMC_NFCS3 is set) to the NAND Flash CE.
395
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.7.1.2NOR Flash
Hardware Configuration
Software Configuration
Configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus
frequency.
26.8 Standard Read and Write Protocols
In the following sections, NCS represents one of the NCS[0..3] chip select lines.
26.8.1 Read Waveforms
The read cycle is shown on Figure 26-5.
The read cycle starts with the address setting on the memory address bus.
A21
A1
A0
A2
A3
A4
A5
A6
A7
A8
A15
A9
A12
A13
A11
A10
A14
A16
D6
D0
D3
D4
D2
D1
D5
D7
A17
A20
A18
A19
D[0..7]
A
[0..21]
NRST
NWE
NCS0
NRD
3V3
3V3 C2
100NF
C2
100NF
C1
100NF
C1
100NF
U1U1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A21
A20
A19
WE
RESET
WP
OE
CE
VPP
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCCQ
VSS
VSS
VCC
396
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-5. Standard Read Cycle
26.8.1.1NRD Waveform
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge;
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge;
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge.
26.8.1.2NCS Waveform
Similarly, the NCS signal can be divided into a setup time, pulse length and hold time:
1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge.
2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge;
3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.
26.8.1.3Read Cycle
The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the
address bus to the point where address may change. The total read cycle time is equal to:
NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD
= NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD
All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. To
ensure that the NRD and NCS timings are coherent, user must define the total read cycle instead of the hold timing.
NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as:
NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE
NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE
A[23:0]
NCS
NRD_SETUP NRD_PULSE NRD_HOLD
MCK
NRD
D[7:0]
NCS_RD_SETUP NCS_RD_PULSE NCS_RD_HOLD
NRD_CYCLE
397
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.8.1.4Null Delay Setup and Hold
If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in
case of consecutive read cycles in the same memory (see Figure 26-6).
Figure 26-6. No Setup, No Hold on NRD and NCS Read Signals
26.8.1.5Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.
26.8.2 Read Mode
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is
avail able on th e data bus . The SMC do es not compar e NCS and NR D timing s to know wh ich signal ri ses firs t. The
READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal of NRD and
NCS controls the read operation.
26.8.2.1Read is Controlled by NRD (READ_MODE = 1):
Figure 26-7 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available tPACC
after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE must be set to
1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read
data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the programmed
waveform of NCS may be.
MCK
NRD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE NRD_PULSE
NCS_RD_PULSE NCS_RD_PULSE
NRD_CYCLE NRD_CYCLE
A[23:0]
NCS
NRD
D[7:0]
398
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-7. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD
26.8.2.2Read is Controlled by NCS (READ_MODE = 0)
Figure 26-8 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS
signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the
READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally sa mples the data on the rising edge of
Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD may be.
Figure 26-8. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS
Data Sampling
tPACC
MCK
A[23:0]
NCS
NRD
D[7:0]
Data Sampling
tPACC
MCK
D[7:0]
A[23:0]
NCS
NRD
399
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.8.3 Write Waveforms
The write protocol is similar to the read protocol. It is depicted in Figure 26-9. The write cycle starts with the address
setting on the memory address bus.
26.8.3.1NWE Waveforms
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge;
2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge;
3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after the NWE rising edge.
26.8.3.2NCS Waveforms
The NCS signal waveforms in write operation are not the same that those applied in read operations, but are separately
defined:
1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge.
2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge;
3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.
Figure 26-9. Write Cycle
26.8.3.3Write Cycle
The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the
address bus to the point where address may change. The total write cycle time is equal to:
NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD
= NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
A
[23:0]
NCS
NWE_SETUP NWE_PULSE NWE_HOLD
MCK
NWE
NCS_WR_SETUP NCS_WR_PULSE NCS_WR_HOLD
NWE_CYCLE
400
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock
cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the
hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as:
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
26.8.3.4Null Delay Setup and Hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of
consecutive write cycles in the same memory (see Figure 26-10). However, for devices that perform write operations on
the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.
Figure 26-10.Null Setup and Hold Values of NCS and NWE in Write Cycle
26.8.3.5Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.
26.8.4 Write Mode
The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal
controls the write operation.
26.8.4.1Write is Controlled by NWE (WRITE_MODE = 1):
Figure 26-11 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during
the pulse and hold steps of the NWE signal. The internal data buffers are switched to output mode after the
NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.
NCS
MCK
NWE
D[7:0]
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
A
[23:0]
401
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-11.WRITE_MODE = 1. The write operation is controlled by NWE
26.8.4.2Write is Controlled by NCS (WRITE_MODE = 0)
Figure 26-12 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during
the pulse and hold steps of the NCS signal. The internal data buffers are switched to output mode after the
NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.
Figure 26-12.WRITE_MODE = 0. The write operation is controlled by NCS
26.8.5 Write Protected Registers
To prevent any single software error that may corrupt SMC behavior, the registers listed below can be write-protected by
setting the WPEN bit in the SMC Write Protect Mode Register (SMC_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the SMC Write Protect Status Register
(SMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset after reading the SMC Write Protect Status Register (SMC_WPSR).
List of the write-protected registers:
Section 26.15.1 ”SMC Setup Register”
Section 26.15.2 ”SMC Pulse Register”
Section 26.15.3 ”SMC Cycle Register”
MCK
D[7:0]
NCS
A
[23:0]
NWE
MCK
D[7:0]
NCS
NWE
A
[23:0]
402
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Section 26.15.4 ”SMC MODE Register”
26.8.6 Coding Timing Parameters
All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to
their type.
The SMC_SETUP register groups the definition of all setup parameters:
• NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
• NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
• NRD_CYCLE, NWE_CYCLE
Table 26-2 shows how the timing parameters are coded and their permitted range.
26.8.7 Reset Values of Timing Parameters
Table 26-3 gives the default value of timing parameters at reset.
26.8.8 Usage Restriction
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters
is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC.
For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface
because of the propagation delay of theses signals through external logic and pads. If positive setup and hold values
must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between
address, NCS and NRD signals.
For write operations:
Table 26-2. Coding and Range of Timing Parameters
Coded Value Number of Bits Effective Value
Permitted Range
Coded Value Effective Value
setup [5:0] 6 128 x setup[5] + setup[4:0] 0 ≤ ≤ 31 0 ≤ ≤ 128+31
pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 ≤ ≤ 63 0 ≤ ≤ 256+63
cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 ≤ ≤ 127 0 ≤ ≤ 256+127
0 ≤ ≤ 512+127
0 ≤ ≤ 768+127
Table 26-3. Reset Values of Timing Parameters
Register Reset Value
SMC_SETUP 0x01010101 All setup timings are set to 1
SMC_PULSE 0x01010101 All pulse timings are set to 1
SMC_CYCLE 0x00030003 The read and write operation last 3 Master Clock
cycles and provide one hold cycle
WRITE_MODE 1 Write is controlled with NWE
READ_MODE 1 Read is controlled with NRD
403
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address and NCS signal after the
rising edge of NWE. This is true for WRITE_MODE = 1 only. See “Early Read Wait State” on page 404.
For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external
devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals
(write), these setup and hold times must be converted into setup and hold times in reference to the address bus.
26.9 Scrambling/Unscrambling Function
The external data bus D[7:0] can be scrambled in order to prevent intellectual property data located in off-chip memories
from being easily recovered by analyzing data at the package pin level of either microcontroller or memory device.
The scrambling and unscrambling are performed on-the-fly without additional wait states.
The scrambling method depends on two user-configurable key registers, SMC_KEY1 and SMC_KEY2. These key
registers are only accessible in write mode.
The key must be securely stored in a reliable non-volatile memory in order to recover data from the off-chip memory. Any
data scrambled with a given key cannot be recovered if the key is lost.
The scrambling/unscrambling function can be enabled or disabled by programming the SMC_OCMS register.
When multiple chip selects are handled, it is possible to configure the scrambling function per chip select using the
OCMS field in the SMC_OCMS registers.
26.10 Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or
operation conflict.
26.10.1 Chip Select Wait States
The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is
no bus contention between the de-activation of one device and the activation of the next one.
During chip select wait state, all control lines are turned inactive: NWR, NCS[0..3], NRD lines are all set to 1.
Figure 26-13 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.
404
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-13.Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
26.10.2 Early Read Wait State
In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write
cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait
state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip
select).
An early read wait state is automatically inserted if at least one of the following conditions is valid:
if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 26-14).
in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the
NCS_RD_SETUP parameter is set to 0, regardless of the read mode (Figure 26-15). The write operation must end
with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly.
in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the
write control signal is used to control address, data, and chip select lines. If the external write control signal is not
inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and
control signals are maintained one more cycle. See Figure 26-16.
A[23:0]
NCS0
NRD_CYCLE
Chip Select
Wait State
NWE_CYCLE
MCK
NCS2
NRD
NWE
D[7:0]
Read to Write
Wait State
405
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-14.Early Read Wait State: Write with No Hold Followed by Read with No Setup
Figure 26-15.Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup
write cycle Early Read
wait state
MCK
NRD
NWE
read cycle
no setup
no hold
D[7:0]
A[23:0]
write cycle
(WRITE_MODE = 0) Early Read
wait state
MCK
NRD
NCS
read cycle
no setup
no hold
D[7:0]
A[23:0]
(READ_MODE = 0 or READ_MODE = 1)
406
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-16.Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with one Set-up Cycle
26.10.3 Reload User Configuration Wait State
The user may change any of the configuration parameters by writing the SMC user interface.
When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before
starting the next access. The so called “Reload User Configuration Wait State” is used by the SMC to load the new set of
parameters to apply to next accesses.
The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before and after
re-programming the user interface are made to different devices (Chip Selects), then one single Chip Select Wait State is
applied.
On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload
Configuration Wait State is inserted, even if the change does not concern the current Chip Select.
26.10.3.1User Procedure
To insert a Reload Configuration Wait State, the SMC detects a write access to any SMC_MODE register of the user
interface. If the user only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in the user
interface, he must validate the modification by writing the SMC_MODE, even if no change was made on the mode
parameters.
The user must not change the configuration parameters of an SMC Chip Select (Setup, Pulse, Cycle, Mode) if accesses
are performed on this CS during the modification. Any change of the Chip Select parameters, while fetching the code
from a memory connected on this CS, may lead to unpredictable behavior. The instructions used to modify the
parameters of an SMC Chip Select can be executed from the internal RAM or from a memory connected to another CS.
A
[25:2]
write cycle
(WRITE_MODE = 1) Early Read
wait state
MCK
NRD
internal write controlling signal
external write controlling signal
(NWE)
D[7:0]
read cycle
no hold read setup = 1
(READ_MODE = 0 or READ_MODE = 1)
407
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.10.3.2Slow Clock Mode Transition
A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the
current transfer (see “Slow Clock Mode” on page 418).
26.10.4 Read to Write Wait State
Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted.
See Figure 26-13 on page 404.
408
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.11 Data Float Wait States
Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data
float wait states) after a read access:
before starting a read access to a different external memory
before starting a write access to the same device or to a different external one.
The Data Float Output Time (tDF) for each external memory device is programmed in the TDF_CYCLES field of the
SMC_MODE register for the corresponding chip select. The value of TDF_CYCLES indicates the number of data float
wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data
output to go to high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long
tDF will not slow down the execution of a program from internal memory.
The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the SMC_MODE
register for the corresponding chip select.
26.11.1 READ_MODE
Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers
of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts
TDF_CYCLES MCK cycles.
When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK
cycles during which the data bus remains busy after the rising edge of NCS.
Figure 26-17 illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), assuming a data float period
of 2 cycles (TDF_CYCLES = 2). Figure 26-18 shows the read operation when controlled by NCS (READ_MODE = 0) and
the TDF_CYCLES parameter equals 3.
Figure 26-17.TDF Period in NRD Controlled Read Access (TDF = 2)
NCS
NRD controlled read operation
tpacc
MCK
NRD
D[7:0]
TDF = 2 clock cycles
A[23:0]
409
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-18.TDF Period in NCS Controlled Read Operation (TDF = 3)
26.11.2 TDF Optimization Enabled (TDF_MODE = 1)
When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of
the setup period of the next access to optimize the number of wait states cycle to insert.
Figure 26-19 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0.
Chip Select 0 has been programmed with:
NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
NCS
TDF = 3 clock cycles
tpacc
MCK
D[7:0]
NCS controlled read operation
A[23:0]
NRD
410
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-19.TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins
26.11.3 TDF Optimization Disabled (TDF_MODE = 0)
When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is
ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no
additional tdf wait states will be inserted.
Figure 26-20, Figure 26-21 and Figure 26-22 illustrate the cases:
read access followed by a read access on another chip select,
read access followed by a write access on another chip select,
read access followed by a write access on the same chip select,
with no TDF optimization.
NCS0
MCK
NRD
NWE
D[7:0]
Read to Write
Wait State
TDF_CYCLES = 6
read access on NCS0 (NRD controlled)
NRD_HOLD= 4
NWE_SETUP= 3
write access on NCS0 (NWE controlled)
411
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-20.TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip selects
Figure 26-21. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects
TDF_CYCLES = 6
TDF_CYCLES = 6 TDF_MODE = 0
A[
23:0]
read1 cycle
Chip Select
Wait State
MCK
read1 controlling signal
(NRD)
read2 controlling signal
(NRD)
D[7:0]
read1 hold = 1
read 2 cycle
read2 setup = 1
5 TDF WAIT STATES
(optimization disabled)
TDF_CYCLES = 4
TDF_CYCLES = 4 TDF_MODE = 0
(optimization disabled)
A
[23:0]
read1 cycle
Chip Select
Wait State
Read to Write
Wait State
MCK
read1 controlling signal
(NRD)
write2 controlling signal
(NWE)
D[7:0]
read1 hold = 1
write2 cycle
write2 setup = 1
2 TDF WAIT STATES
412
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-22.TDF Mode = 0: TDF wait states between read and write accesses on the same chip select
26.12 External Wait
Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE field of
the SMC_MODE register on the corresponding chip select must be set to either to “10” (frozen mode) or “11” (ready
mode). When the EXNW_MODE is set to “00” (disabled), the NWAIT signal is simply ignored on the corresponding chip
select. The NWAIT signal delays the read or write operation in regards to the read or write controlling signal, depending
on the read and write modes of the corresponding chip select.
26.12.1 Restriction
When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write
controlling signal. For that reason, the NWAIT signal cannot be used in Page Mode (“Asynchronous Page Mode”
on page 419), or in Slow Clock Mode (“Slow Clock Mode” on page 418).
The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then NWAIT
is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal
outside the expected period has no impact on SMC behavior.
TDF_CYCLES = 5
TDF_CYCLES = 5 TDF_MODE = 0
(optimization disabled)
A
[23:0]
read1 cycle
Read to Write
Wait State
MCK
read1 controlling signal
(NRD)
write2 controlling signal
(NWE)
D[7:0]
read1 hold = 1
write2 cycle
write2 setup = 1
4 TDF WAIT STATES
413
SAM4S [DATASHEET]
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26.12.2 Frozen Mode
When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the
SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the
resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where
it was stopped. See Figure 26-23. This mode must be selected when the external device uses the NWAIT signal to delay
the access and to freeze the SMC.
The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 26-24.
Figure 26-23.Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
EXNW_MODE = 10 (Frozen)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
A
[23:0]
MCK
NWE
NCS
432 1 1101
4563222210
Write cycle
D[7:0]
NWAIT
FROZEN STATE
internally synchronized
NWAIT signal
414
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-24.Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
EXNW_MODE = 10 (Frozen)
READ_MODE = 0 (NCS_controlled)
NRD_PULSE = 2, NRD_HOLD = 6
NCS_RD_PULSE =5, NCS_RD_HOLD =3
A
[23:0]
MCK
NCS
NRD 10
43
43
2
555
22 0 210
210
1
Read cycle
Assertion is ignored
NWAIT
internally synchronized
NWAIT signal
FROZEN STATE
415
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.12.3 Ready Mode
In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down
counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the
resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in Figure 26-25 and Figure 26-26. After deassertion, the access is
completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to
complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling
read/write signal, it has no impact on the access length as shown in Figure 26-26.
Figure 26-25.NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11)
EXNW_MODE = 11 (Ready mode)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
A
[23:0]
MCK
NWE
NCS
432 1 000
456321110
Write cycle
D[7:0]
NWAIT
internally synchronized
NWAIT signal
Wait STATE
416
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-26.NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11)
EXNW_MODE = 11(Ready mode)
READ_MODE = 0 (NCS_controlled)
NRD_PULSE = 7
NCS_RD_PULSE =7
A[23:0]
MCK
NCS
NRD
4563200
0
1
4563211
Read cycle
Assertion is ignored
NWAIT
internally synchronized
NWAIT signal
Wait STATE
Assertion is ignored
417
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.12.4 NWAIT Latency and Read/Write Timings
There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal
by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus
the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting
the NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on Figure 26-27.
When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read and write controlling
signal of at least:
minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle
Figure 26-27.NWAIT Latency
EXNW_MODE = 10 or 11
READ_MODE = 1 (NRD_controlled)
NRD_PULSE = 5
A
[23:0]
MCK
NRD
43 210 00
Read cycle
minimal pulse length
NWAIT latency
NWAIT
intenally synchronized
NWAIT signal
WAIT STATE
2 cycle resynchronization
418
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.13 Slow Clock Mode
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven
by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically
32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are
applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow
clock rate. When activated, the slow mode is active on all chip selects.
26.13.1 Slow Clock Mode Waveforms
Figure 26-28 illustrates the read and write operations in slow clock mode. They are valid on all chip selects. Table 26-4
indicates the value of read and write parameters in slow clock mode.
Figure 26-28. Read/Write Cycles in Slow Clock Mode
26.13.2 Switching from (to) Slow Clock Mode to (from) Normal Mode
When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high
clock rate, with the set of slow clock mode parameters.See Figure 26-29 on page 419. The external device may not be
fast enough to support such timings.
Figure 26-30 illustrates the recommended procedure to properly switch from one mode to the other.
A[
23:0]
NCS
1
MCK
NWE 1
1
NWE_CYCLE = 3
A
[23:0]
MCK
NRD
NRD_CYCLE = 2
11
NCS
SLOW CLOCK MODE WRITE SLOW CLOCK MODE READ
Table 26-4. Read and Write Timing Parameters in Slow Clock Mode
Read Parameters Duration (cycles) Write Parameters Duration (cycles)
NRD_SETUP 1 NWE_SETUP 1
NRD_PULSE 1 NWE_PULSE 1
NCS_RD_SETUP 0 NCS_WR_SETUP 0
NCS_RD_PULSE 2 NCS_WR_PULSE 3
NRD_CYCLE 2 NWE_CYCLE 3
419
SAM4S [DATASHEET]
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Figure 26-29.Clock Rate Transition Occurs while the SMC is Performing a Write Operation
Figure 26-30.Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock
Mode
26.14 Asynchronous Page Mode
The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE
register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes.
A
[23:0]
NCS
1
MCK
NWE
1
1
NWE_CYCLE = 3
SLOW CLOCK MODE WRITE
Slow Clock Mode
internal signal from PMC
111 2 32
NWE_CYCLE = 7
NORMAL MODE WRITE
Slow clock mode
transition is detected:
Reload Configuration Wait State
This write cycle finishes with the slow clock mode set
of parameters after the clock rate transition
SLOW CLOCK MODE WRITE
A
[23:0]
NCS
1
MCK
NWE
1
1
SLOW CLOCK MODE WRITE
Slow Clock Mode
internal signal from PMC
232
NORMAL MODE WRITEIDLE STATE
Reload Conguration
Wait State
420
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned
to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the
page in memory, the LSB of address define the address of the data in the page as detailed in Table 26-5.
With page mode memory devices, the first access to one page (tpa) takes longer than the subsequent accesses to the
page (tsa) as shown in Figure 26-31. When in page mode, the SMC enables the user to define different read timings for
the first access within one page, and next accesses within the page.
Note: 1. “A” denotes the address bus of the memory device.
26.14.1 Protocol and Timings in Page Mode
Figure 26-31 shows the NRD and NCS timings in page mode access.
Figure 26-31.Page Mode Read Protocol (Address MSB and LSB are defined in Table 26-5)
The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and hold
timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the first
access to the page is defined with the NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of
subsequent accesses within the page are defined using the NRD_PULSE parameter.
In page mode, the programming of the read timings is described in Table 26-6:
Table 26-5. Page Address and Data Address within a Page
Page Size Page Address(1) Data Address in the Page
4 bytes A[23:2] A[1:0]
8 bytes A[23:3] A[2:0]
16 bytes A[23:4] A[3:0]
32 bytes A[23:5] A[4:0]
A[MSB]
NCS
MCK
NRD
D[7:0]
NCS_RD_PULSE NRD_PULSE
NRD_PULSE
tsatpa tsa
A[LSB]
Table 26-6. Programming of Read Timings in Page Mode
Parameter Value Definition
READ_MODE ‘x’ No impact
NCS_RD_SETUP ‘x’ No impact
NCS_RD_PULSE tpa Access time of first access to the page
421
SAM4S [DATASHEET]
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The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page access
timing (tpa) and the NRD_PULSE for accesses to the page (tsa), even if the programmed value for tpa is shorter than the
programmed value for tsa.
26.14.2 Page Mode Restriction
The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal may
lead to unpredictable behavior.
26.14.3 Sequential and Non-sequential Accesses
If the chip select and the MSB of addresses as defined in Table 26-5 are identical, then the current access lies in the
same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access
time (tsa). Figure 26-32 illustrates access to an 8-bit memory device in page mode, with 8-byte pages. Access to D1
causes a page access with a long access time (tpa). Accesses to D3 and D7, though they are not sequential accesses,
only require a short access time (tsa).
If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip select is
different from the previous access, a page break occurs. If two sequential accesses are made to the page mode memory,
but separated by an other internal or external peripheral access, a page break occurs on the second access because the
chip select of the device was deasserted between both accesses.
Figure 26-32. Access to Non-Sequential Data within the Same Page
NRD_SETUP ‘x’ No impact
NRD_PULSE tsa Access time of subsequent accesses in the page
NRD_CYCLE ‘x’ No impact
Table 26-6. Programming of Read Timings in Page Mode
Parameter Value Definition
A
[23:3]
A[2], A1, A0
NCS
MCK
NRD
Page address
A1 A3 A7
D[7:0]
NCS_RD_PULSE NRD_PULSE
NRD_PULSE
D1 D3 D7
422
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.15 Static Memory Controller (SMC) User Interface
The SMC is programmed using the registers listed in Table 26-7. For each chip select, a set of 4 registers is used to program the
parameters of the external device connected on it. In Table 26-7, “CS_number” denotes the chip select number. 16 bytes (0x10)
are required per chip select.
The user must complete writing the configuration by writing any one of the SMC_MODE registers.
Table 26-7. Register Mapping
Offset Register Name Access Reset
0x10 x CS_number + 0x00 SMC Setup Register SMC_SETUP Read-write 0x01010101
0x10 x CS_number + 0x04 SMC Pulse Register SMC_PULSE Read-write 0x01010101
0x10 x CS_number + 0x08 SMC Cycle Register SMC_CYCLE Read-write 0x00030003
0x10 x CS_number + 0x0C SMC Mode Register SMC_MODE Read-write 0x10000003
0x80 SMC OCMS MODE Register SMC_OCMS Read-write 0x00000000
0x84 SMC OCMS KEY1 Register SMC_KEY1 Write once 0x00000000
0x88 SMC OCMS KEY2 Register SMC_KEY2 Write once 0x00000000
0xE4 SMC Write Protect Mode Register SMC_WPMR Read-write 0x00000000
0xE8 SMC Write Protect Status Register SMC_WPSR Read-only 0x00000000
0xEC-0xFC Reserved - - -
423
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.15.1 SMC Setup Register
Name: SMC_SETUP[0..3]
Address: 0x400E0000 [0], 0x400E0010 [1], 0x400E0020 [2], 0x400E0030 [3]
Access: Read-write
• NWE_SETUP: NWE Setup Length
The NWE signal setup length is defined as:
NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles
• NCS_WR_SETUP: NCS Setup Length in WRITE Access
In write access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles
• NRD_SETUP: NRD Setup Length
The NRD signal setup length is defined in clock cycles as:
NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles
• NCS_RD_SETUP: NCS Setup Length in READ Access
In read access, the NCS signal setup length is defined as:
NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles
31 30 29 28 27 26 25 24
– – NCS_RD_SETUP
23 22 21 20 19 18 17 16
– – NRD_SETUP
15 14 13 12 11 10 9 8
– – NCS_WR_SETUP
76543210
– – NWE_SETUP
424
SAM4S [DATASHEET]
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26.15.2 SMC Pulse Register
Name: SMC_PULSE[0..3]
Address: 0x400E0004 [0], 0x400E0014 [1], 0x400E0024 [2], 0x400E0034 [3]
Access: Read-write
• NWE_PULSE: NWE Pulse Length
The NWE signal pulse length is defined as:
NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles
The NWE pulse length must be at least 1 clock cycle.
• NCS_WR_PULSE: NCS Pulse Length in WRITE Access
In write access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
• NRD_PULSE: NRD Pulse Length
In standard read access, the NRD signal pulse length is defined in clock cycles as:
NRD pulse length = (256* NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles
The NRD pulse length must be at least 1 clock cycle.
In page mode read access, the NRD_PULSE parameter defines the duration of the subsequent accesses in the page.
• NCS_RD_PULSE: NCS Pulse Length in READ Access
In standard read access, the NCS signal pulse length is defined as:
NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles
The NCS pulse length must be at least 1 clock cycle.
In page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page.
31 30 29 28 27 26 25 24
– NCS_RD_PULSE
23 22 21 20 19 18 17 16
– NRD_PULSE
15 14 13 12 11 10 9 8
– NCS_WR_PULSE
76543210
– NWE_PULSE
425
SAM4S [DATASHEET]
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26.15.3 SMC Cycle Register
Name: SMC_CYCLE[0..3]
Address: 0x400E0008 [0], 0x400E0018 [1], 0x400E0028 [2], 0x400E0038 [3]
Access: Read-write
• NWE_CYCLE: Total Write Cycle Length
The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and hold
steps of the NWE and NCS signals. It is defined as:
Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles
• NRD_CYCLE: Total Read Cycle Length
The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and hold
steps of the NRD and NCS signals. It is defined as:
Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles
31 30 29 28 27 26 25 24
–––––––NRD_CYCLE
23 22 21 20 19 18 17 16
NRD_CYCLE
15 14 13 12 11 10 9 8
–––––––NWE_CYCLE
76543210
NWE_CYCLE
426
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.15.4 SMC MODE Register
Name: SMC_MODE[0..3]
Address: 0x400E000C [0], 0x400E001C [1], 0x400E002C [2], 0x400E003C [3]
Access: Read-write
• READ_MODE:
1: The read operation is controlled by the NRD signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD.
0: The read operation is controlled by the NCS signal.
– If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS.
• WRITE_MODE
1: The write operation is controlled by the NWE signal.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE.
0: The write operation is controlled by the NCS signal.
– If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS.
• EXNW_MODE: NWAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the
read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for the
read and write controlling signal.
• Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select.
• Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write
cycle is resumed from the point where it was stopped.
• Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling
read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until
NWAIT returns high.
31 30 29 28 27 26 25 24
– – PS – – – PMEN
23 22 21 20 19 18 17 16
– – – TDF_MODE TDF_CYCLES
15 14 13 12 11 10 9 8
––––––––
76543210
– – EXNW_MODE – – WRITE_MODE READ_MODE
Value Name Description
0 DISABLED Disabled
1 Reserved
2 FROZEN Frozen Mode
3 READY Ready Mode
427
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• TDF_CYCLES: Data Float Time
This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the
read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus
cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set.
• TDF_MODE: TDF Optimization
1: TDF optimization is enabled.
– The number of TDF wait states is optimized using the setup period of the next read/write access.
0: TDF optimization is disabled.
– The number of TDF wait states is inserted before the next access begins.
• PMEN: Page Mode Enabled
1: Asynchronous burst read in page mode is applied on the corresponding chip select.
0: Standard read is applied.
• PS: Page Size
If page mode is enabled, this field indicates the size of the page in bytes.
Value Name Description
0 4_BYTE 4-byte page
1 8_BYTE 8-byte page
2 16_BYTE 16-byte page
3 32_BYTE 32-byte page
428
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.15.5 SMC OCMS Mode Register
Name: SMC_OCMS
Address: 0x400E0080
Access: Read-write
Reset: 0x00000000
• CSxSE: Chip Select (x = 0 to 3) Scrambling Enable
0: Disable Scrambling for CSx.
1: Enable Scrambling for CSx.
• SMSE: Static Memory Controller Scrambling Enable
0: Disable Scrambling for SMC access.
1: Enable Scrambling for SMC access.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – CS3SE CS2SE CS1SE CS0SE
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – – – - SMSE
429
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.15.6 SMC OCMS Key1 Register
Name: SMC_KEY1
Address: 0x400E0084
Access: Write Once
Reset: 0x00000000
• KEY1: Off Chip Memory Scrambling (OCMS) Key Part 1
When Off Chip Memory Scrambling is enabled setting the SMC_OCMS and SMC_TIMINGS registers in accordance, the data
scrambling depends on KEY1 and KEY2 values.
31 30 29 28 27 26 25 24
KEY1
23 22 21 20 19 18 17 16
KEY1
15 14 13 12 11 10 9 8
KEY1
76543210
KEY1
430
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.15.7 SMC OCMS Key2 Register
Name: SMC_KEY2
Address: 0x400E0088
Access: Write Once
Reset: 0x00000000
• KEY2: Off Chip Memory Scrambling (OCMS) Key Part 2
When Off Chip Memory Scrambling is enabled setting the SMC_OCMS and SMC_TIMINGS registers in accordance, the data
scrambling depends on KEY2 and KEY1 values.
31 30 29 28 27 26 25 24
KEY2
23 22 21 20 19 18 17 16
KEY2
15 14 13 12 11 10 9 8
KEY2
76543210
KEY2
431
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.15.8 SMC Write Protect Mode Register
Name: SMC_WPMR
Address: 0x400E00E4
Access: Read-write
Reset: See Table 26-7
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x534D43 (“SMC” in ASCII).
Protects the registers listed below:
•Section 26.15.1 ”SMC Setup Register”
•Section 26.15.2 ”SMC Pulse Register”
•Section 26.15.3 ”SMC Cycle Register”
•Section 26.15.4 ”SMC MODE Register”
• WPKEY: Write Protect KEY
Should be written at value 0x534D43 (“SMC” in ASCII). Writing any other value in this field aborts the write operation of the
WPEN bit. Always reads as 0.
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
———————WPEN
432
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
26.15.9 SMC Write Protect Status Register
Name: SMC_WPSR
Address: 0x400E00E8
Type: Read-only
Value: See Table 26-7
• WPVS: Write Protect Enable
0 = No Write Protect Violation has occurred since the last read of the SMC_WPSR register.
1 = A Write Protect Violation occurred since the last read of the SMC_WPSR register. If this violation is an unauthorized attempt
to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has
been attempted.
Note: Reading SMC_WPSR automatically clears all fields.
31 30 29 28 27 26 25 24
————————
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
———————WPVS
433
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
27. Peripheral DMA Controller (PDC)
27.1 Description
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip
memories. The link between the PDC and a serial peripheral is operated by the AHB to APB bridge.
The user interface of each PDC channel is integrated into the user interface of the peripheral it serves. The user interface
of mono directional channels (receive only or transmit only), contains two 32-bit memory pointers and two 16-bit
counters, one set (pointer, counter) for current transfer and one set (pointer, counter) for next transfer. The bi-directional
channel user interface contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer, counter) is used
by current transmit, next transmit, current receive and next receive.
Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly reduces
the number of clock cycles required for a data transfer, which improves microcontroller performance.
To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals. When
the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself.
27.2 Embedded Characteristics
Handles data transfer between peripherals and memories
Low bus arbitration overhead
One Master Clock cycle needed for a transfer from memory to peripheral
Two Master Clock cycles needed for a transfer from peripheral to memory
Next Pointer management for reducing interrupt latency requirement
The Peripheral DMA Controller handles transfer requests from the channel accord ing to the following priorities (Low to
High priorities):
Table 27-1. Peripheral DMA Controller
Instance Name Channel T/R
PWM Transmit
TWI1 Transmit
TWI0 Transmit
UART1 Transmit
UART0 Transmit
USART1 Transmit
USART0 Transmit
DACC Transmit
SPI Transmit
SSC Transmit
HSMCI Transmit
PIOA Receive
TWI1 Receive
TWI0 Receive
UART1 Receive
UART0 Receive
USART1 Receive
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27.3 Block Diagram
Figure 27-1. Block Diagram
USART0 Receive
ADC Receive
SPI Receive
SSC Receive
HSMCI Receive
Table 27-1. Peripheral DMA Controller
Instance Name Channel T/R
PDC
FULL DUPLEX
PERIPHERAL
THR
RHR
PDC Channel A
PDC Channel B
Control
Status Control
Control
PDC Channel C
HALF DUPLEX
PERIPHERAL
THR
Status Control
RECEIVE or TRANSMIT
PERIPHERAL
RHR or THR
Control
Control
RHR
PDC Channel D
Status Control
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27.4 Functional Description
27.4.1 Configuration
The PDC channel user interface enables the user to configure and control data transfers for each channel. The user
interface of each PDC channel is integrated into the associated peripheral user interface.
The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR,
TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR). However, the transmit and receive parts of each
type are programmed differently: the transmit and receive parts of a full duplex peripheral can be programmed at the
same time, whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at a time.
32-bit pointers define the access location in memory for current and next transfer, whether it is for read (transmit) or write
(receive). 16-bit counters define the size of current and next transfers. It is possible, at any moment, to read the number
of transfers left for each channel.
The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The status
for each channel is located in the associated peripheral status register. Transfers can be enabled and/or disabled by
setting TXTEN/TXTDIS and RXTEN/RXTDIS in the peripheral’s Transfer Control Register.
At the end of a transfer, the PDC channel sends status flags to its associated peripheral. These flags are visible in the
peripheral status register (ENDRX, ENDTX, RXBUFF, and TXBUFE). Refer to Section 27.4.3 and to the associated
peripheral user interface.
27.4.2 Memory Pointers
Each full duplex peripheral is connected to the PDC by a receive channel and a transmit channel. Both channels have
32-bit memory pointers that point respectively to a receive area and to a transmit area in on- and/or off-chip memory.
Each half duplex peripheral is connected to the PDC by a bidirectional channel. This channel has two 32-bit memory
pointers, one for current transfer and the other for next transfer. These pointers point to transmit or receive data
depending on the operating mode of the peripheral.
Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented respectively by 1, 2 or 4
bytes.
If a memory pointer address changes in the middle of a transfer, the PDC channel continues operating using the new
address.
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27.4.3 Transfer Counters
Each channel has two 16-bit counters, one for current transfer and the other one for next transfer. These counters define
the size of data to be transferred by the channel. The current transfer counter is decremented first as the data addressed
by current memory pointer starts to be transferred. When the current transfer counter reaches zero, the channel checks
its next transfer counter. If the value of next counter is zero, the channel stops transferring data and sets the appropriate
flag. But if the next counter value is greater then zero, the values of the next pointer/next counter are copied into the
current pointer/current counter and the channel resumes the transfer whereas next pointer/next counter get zero/zero as
values. At the end of this transfer the PDC channel sets the appropriate flags in the Peripheral Status Register.
The following list gives an overview of how status register flags behave depending on the counters’ values:
ENDRX flag is set when the PERIPH_RCR register reaches zero.
RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.
ENDTX flag is set when the PERIPH_TCR register reaches zero.
TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero.
These status flags are described in the Peripheral Status Register.
27.4.4 Data Transfers
The serial peripheral triggers its associated PDC channels’ transfers using transmit enable (TXEN) and receive enable
(RXEN) flags in the transfer control register integrated in the peripheral’s user interface.
When the peripheral receives an external data, it sends a Receive Ready signal to its PDC receive channel which then
requests access to the Matrix. When access is granted, the PDC receive channel starts reading the peripheral Receive
Holding Register (RHR). The read data are stored in an internal buffer and then written to memory.
When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit channel which then requests
access to the Matrix. When access is granted, the PDC transmit channel reads data from memory and puts them to
Transmit Holding Register (THR) of its associated peripheral. The same peripheral sends data according to its
mechanism.
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27.4.5 PDC Flags and Peripheral Status Register
Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the PDC sends back flags
to the peripheral. All these flags are only visible in the Peripheral Status Register.
Depending on the type of peripheral, half or full duplex, the flags belong to either one single channel or two different
channels.
27.4.5.1Receive Transfer End
This flag is set when PERIPH_RCR register reaches zero and the last data has been transferred to memory.
It is reset by writing a non zero value in PERIPH_RCR or PERIPH_RNCR.
27.4.5.2Transmit Transfer End
This flag is set when PERIPH_TCR register reaches zero and the last data has been written into peripheral THR.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
27.4.5.3Receive Buffer Full
This flag is set when PERIPH_RCR register reaches zero with PERIPH_RNCR also set to zero and the last data has
been transferred to memory.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
27.4.5.4Transmit Buffer Empty
This flag is set when PERIPH_TCR register reaches zero with PERIPH_TNCR also set to zero and the last data has
been written into peripheral THR.
It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
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27.5 Peripheral DMA Controller (PDC) User Interface
Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the
user according to the function and the desired peripheral.)
Table 27-2. Register Mapping
Offset Register Name Access Reset
0x00 Receive Pointer Register PERIPH(1)_RPR Read-write 0
0x04 Receive Counter Register PERIPH_RCR Read-write 0
0x08 Transmit Pointer Register PERIPH_TPR Read-write 0
0x0C Transmit Counter Register PERIPH_TCR Read-write 0
0x10 Receive Next Pointer Register PERIPH_RNPR Read-write 0
0x14 Receive Next Counter Register PERIPH_RNCR Read-write 0
0x18 Transmit Next Pointer Register PERIPH_TNPR Read-write 0
0x1C Transmit Next Counter Register PERIPH_TNCR Read-write 0
0x20 Transfer Control Register PERIPH_PTCR Write-only 0
0x24 Transfer Status Register PERIPH_PTSR Read-only 0
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27.5.1 Receive Pointer Register
Name: PERIPH_RPR
Access: Read-write
• RXPTR: Receive Pointer Register
RXPTR must be set to receive buffer address.
When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
31 30 29 28 27 26 25 24
RXPTR
23 22 21 20 19 18 17 16
RXPTR
15 14 13 12 11 10 9 8
RXPTR
76543210
RXPTR
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27.5.2 Receive Counter Register
Name: PERIPH_RCR
Access: Read-write
• RXCTR: Receive Counter Register
RXCTR must be set to receive buffer size.
When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
0 = Stops peripheral data transfer to the receiver
1 - 65535 = Starts peripheral data transfer if corresponding channel is active
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RXCTR
76543210
RXCTR
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27.5.3 Transmit Pointer Register
Name: PERIPH_TPR
Access: Read-write
• TXPTR: Transmit Counter Register
TXPTR must be set to transmit buffer address.
When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
31 30 29 28 27 26 25 24
TXPTR
23 22 21 20 19 18 17 16
TXPTR
15 14 13 12 11 10 9 8
TXPTR
76543210
TXPTR
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27.5.4 Transmit Counter Register
Name: PERIPH_TCR
Access: Read-write
• TXCTR: Transmit Counter Register
TXCTR must be set to transmit buffer size.
When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
0 = Stops peripheral data transfer to the transmitter
1- 65535 = Starts peripheral data transfer if corresponding channel is active
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXCTR
76543210
TXCTR
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27.5.5 Receive Next Pointer Register
Name: PERIPH_RNPR
Access: Read-write
• RXNPTR: Receive Next Pointer
RXNPTR contains next receive buffer address.
When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
31 30 29 28 27 26 25 24
RXNPTR
23 22 21 20 19 18 17 16
RXNPTR
15 14 13 12 11 10 9 8
RXNPTR
76543210
RXNPTR
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27.5.6 Receive Next Counter Register
Name: PERIPH_RNCR
Access: Read-write
• RXNCTR: Receive Next Counter
RXNCTR contains next receive buffer size.
When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RXNCTR
76543210
RXNCTR
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27.5.7 Transmit Next Pointer Register
Name: PERIPH_TNPR
Access: Read-write
• TXNPTR: Transmit Next Pointer
TXNPTR contains next transmit buffer address.
When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
31 30 29 28 27 26 25 24
TXNPTR
23 22 21 20 19 18 17 16
TXNPTR
15 14 13 12 11 10 9 8
TXNPTR
76543210
TXNPTR
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27.5.8 Transmit Next Counter Register
Name: PERIPH_TNCR
Access: Read-write
• TXNCTR: Transmit Counter Next
TXNCTR contains next transmit buffer size.
When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXNCTR
76543210
TXNCTR
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27.5.9 Transfer Control Register
Name: PERIPH_PTCR
Access: Write-only
• RXTEN: Receiver Transfer Enable
0 = No effect.
1 = Enables PDC receiver channel requests if RXTDIS is not set.
When a half duplex peripheral is connected to the PDC, enabling the receiver channel requests automatically disables the trans-
mitter channel requests. It is forbidden to set both TXTEN and RXTEN for a half duplex peripheral.
• RXTDIS: Receiver Transfer Disable
0 = No effect.
1 = Disables the PDC receiver channel requests.
When a half duplex peripheral is connected to the PDC, disabling the receiver channel requests also disables the transmitter
channel requests.
• TXTEN: Transmitter Transfer Enable
0 = No effect.
1 = Enables the PDC transmitter channel requests.
When a half duplex peripheral is connected to the PDC, it enables the transmitter channel requests only if RXTEN is not set. It is
forbidden to set both TXTEN and RXTEN for a half duplex peripheral.
• TXTDIS: Transmitter Transfer Disable
0 = No effect.
1 = Disables the PDC transmitter channel requests.
When a half duplex peripheral is connected to the PDC, disabling the transmitter channel requests disables the receiver channel
requests.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––TXTDIS TXTEN
76543210
––––––RXTDIS RXTEN
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27.5.10 Transfer Status Register
Name: PERIPH_PTSR
Access: Read-only
• RXTEN: Receiver Transfer Enable
0 = PDC Receiver channel requests are disabled.
1 = PDC Receiver channel requests are enabled.
• TXTEN: Transmitter Transfer Enable
0 = PDC Transmitter channel requests are disabled.
1 = PDC Transmitter channel requests are enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––TXTEN
76543210
–––––––RXTEN
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28. Power Management Controller (PMC)
28.1 Clock Generator
28.1.1 Description
The Clock Generator User Interface is embedded within the Power Management Controller and is
described in Section 28.2.16 “Power Management Controller (PMC) User Interface”. However, the
Clock Generator registers are named CKGR_.
28.1.2 Embedded Characteristics
The Clock Generator is made up of:
A Low Power 32768 Hz Slow Clock Oscillator with bypass mode.
A Low Power RC Oscillator
A 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator, which can be bypassed.
A factory programmed Fast RC Oscillator. Three output frequencies can be selected:
12/8/4 MHz. By default 4 MHz is selected.
Two 80 to 240 MHz programmable PLL (input from 3 to 32 MHz), capable of providing the
clock MCK to the processor and to the peripherals.
Write Protected Registers
It provides the following clocks:
SLCK, the Slow Clock, which is the only permanent clock within the system.
MAINCK is the output of the Main Clock Oscillator selection: either the Crystal or Ceramic
Resonator-based Oscillator or 12/8/4 MHz Fast RC Oscillator.
PLLACK is the output of the Divider and 80 to 240 MHz programmable PLL (PLLA).
PLLBCK is the output of the Divider and 80 to 240 MHz programmable PLL (PLLB).
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28.1.3 Block Diagram
Figure 28-1. Clock Generator Block Diagram
28.1.4 Slow Clock
The Supply Controller embeds a slow clock generator that is supplied with the VDDIO power supply.
As soon as the VDDIO is supplied, both the crystal oscillator and the embedded RC oscillator are
powered up, but only the embedded RC oscillator is enabled. This allows the slow clock to be valid in
a short time (about 100 μs).
The Slow Clock is generated either by the Slow Clock Crystal Oscillator or by the Slow Clock RC
Oscillator.
The selection between the RC or the crystal oscillator is made by writing the XTALSEL bit in the
Supply Controller Control Register (SUPC_CR).
PLLA and
Divider /2
PLLB and
Divider /2
PLLADIV2
PLLBDIV2
Management
Controller
MAINCK
ControlStatus
MOSCSEL
XIN
XOUT
XIN32
XOUT32
SLCK
(Supply Controller)
PLLBCK
0
1
0
1
3-20 MHz
Crystal
or
Ceramic
Resonator
Oscillator
Embedded
4/8/12 MHz
Fast
RC Oscillator
32768 Hz
Crystal
Oscillator
Embedded
32 kHz
RC Oscillator
Clock Generator
XTALSEL
Slow Clock
Main Clock
PLLB Clock
PLLA Cloc
k
PLLACK
Power
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28.1.4.1Slow Clock RC Oscillator
By default, the Slow Clock RC Oscillator is enabled and selected. The user has to take into account
the possible drifts of the RC Oscillator. More details are given in the section “DC Characteristics” of
the product datasheet.
It can be disabled via the XTALSEL bit in the Supply Controller Control Register (SUPC_CR).
28.1.4.2Slow Clock Crystal Oscillator
The Clock Generator integrates a 32768 Hz low-power oscillator. In order to use this oscillator, the
XIN32 and XOUT32 pins must be connected to a 32768 Hz crystal. Two external capacitors must be
wired as shown in Figure 28-2. More details are given in the section “DC Characteristics” of the
product datasheet.
Note that the user is not obliged to use the Slow Clock Crystal and can use the RC oscillator instead.
Figure 28-2. Typical Slow Clock Crystal Oscillator Connection
The user can select the crystal oscillator to be the source of the slow clock, as it provides a more
accurate frequency. The command is made by writing the Supply Controller Control Register
(SUPC_CR) with the XTALSEL bit at 1. This results in a sequence which first configures the PIO lines
multiplexed with XIN32 and XOUT32 to be driven by the oscillator, then enables the crystal oscillator
and then disables the RC oscillator to save power. The switch of the slow clock source is glitch free.
The OSCSEL bit of the Supply Controller Status Register (SUPC_SR) or the OSCSEL bit of the PMC
Status Register (PMC_SR) tracks the oscillator frequency downstream. It must be read in order to be
informed when the switch sequence, initiated when a new value is written in the XTALSEL bit of
SUPC_CR, is done.
Coming back on the RC oscillator is only possible by shutting down the VDDIO power supply. If the
user does not need the crystal oscillator, the XIN32 and XOUT32 pins can be left unconnected since
by default the XIN32 and XOUT32 system I/O pins are in PIO input mode with pull-up after reset.
The user can also set the crystal oscillator in bypass mode instead of connecting a crystal. In this
case, the user has to provide the external clock signal on XIN32. The input characteristics of the
XIN32 pin are given in the product electrical characteristics section. In order to set the bypass mode,
the OSCBYPASS bit of the Supply Controller Mode Register (SUPC_MR) needs to be set at 1.
The user can set the Slow Clock Crystal Oscillator in bypass mode instead of connecting a crystal. In
this case, the user has to provide the external clock signal on XIN32. The input characteristics of the
XIN32 pin under these conditions are given in the product electrical characteristics section.
The programmer has to be sure to set the OSCBYPASS bit in the Supply Controller Mode Register
(SUPC_MR) and XTALSEL bit in the Supply Controller Control Register (SUPC_CR).
XIN32 XOUT32 GND
32768 Hz
Crystal
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28.1.5 Main Clock
Figure 28-3 shows the Main Clock block diagram.
Figure 28-3. Main Clock Block Diagram
The Main Clock has two sources:
12/8/4 MHz Fast RC Oscillator which starts very quickly and is used at start-up.
3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator which can be bypassed.
28.1.5.1Fast RC Oscillator
After reset, the 12/8/4 MHz Fast RC Oscillator is enabled with the 4 MHz frequency selected and it is
selected as the source of MAINCK. MAINCK is the default clock selected to start up the system.
The Fast RC Oscillator frequencies are calibrated in production except the lowest frequency which is
not calibrated.
Please refer to the “DC Characteristics” section of the product datasheet.
The software can disable or enable the 12/8/4 MHz Fast RC Oscillator with the MOSCRCEN bit in the
Clock Generator Main Oscillator Register (CKGR_MOR).
The user can also select the output frequency of the Fast RC Oscillator, either 12/8/4 MHz are
available. It can be done through MOSCRCF bits in CKGR_MOR. When changing this frequency
selection, the MOSCRCS bit in the Power Management Controller Status Register (PMC_SR) is
automatically cleared and MAINCK is stopped until the oscillator is stabilized. Once the oscillator is
stabilized, MAINCK restarts and MOSCRCS is set.
XIN
XOUT
MOSCXTEN
MOSCXTST
MOSCXTS
Main Clock
Frequency
Counter
MAINF
MAINRDY
SLCK
Slow Clock
3-20 MHz
Crystal
or
Ceramic Resonator
Oscillator
3-20 MHz
Oscillator
Counter
MOSCRCEN
Fast RC
Oscillator
MOSCRCS
MOSCRCF
MOSCRCEN
MOSCXTEN
MOSCSEL
MOSCSEL MOSCSELS
1
0
MAINCK
Main Clock
MAINCK
Main Clock
Ref.
RCMEAS
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When disabling the Main Clock by clearing the MOSCRCEN bit in CKGR_MOR, the MOSCRCS bit in
the Power Management Controller Status Register (PMC_SR) is automatically cleared, indicating the
Main Clock is off.
Setting the MOSCRCS bit in the Power Management Controller Interrupt Enable Register (PMC_IER)
can trigger an interrupt to the processor.
It is recommended to disable the Main Clock as soon as the processor no longer uses it and runs out
of SLCK.
The CAL12, CAL8 and CAL4 values in the PMC Oscillator Calibration Register (PMC_OCR) are the
default values set by Atmel during production. These values are stored in a specific Flash memory
area different from the main memory plane. These values cannot be modified by the user and cannot
be erased by a Flash erase command or by the ERASE pin. Values written by the user's application
in PMC_OCR are reset after each power up or peripheral reset.
28.1.5.2Fast RC Oscillator Clock Frequency Adjustment
It is possible for the user to adjust the main RC oscillator frequency through PMC_OCR. By default,
SEL12/8/4 are low, so the RC oscillator will be driven with Flash calibration bits which are
programmed during chip production.
The user can adjust the trimming of the 12/8/4 MHz Fast RC Oscillator through this register in order to
obtain more accurate frequency (to compensate derating factors such as temperature and voltage).
In order to calibrate the oscillator lower frequency, SEL12 must be set to 1 and a good frequency
value must be configured in CAL12. Likewise, SEL8/4 must be set to 1 and a trim value must be
configured in CAL8/4 in order to adjust the other frequencies of the oscillator.
It is possible to adjust the oscillator frequency while operating from this clock. For example, when
running on lowest frequency it is possible to change the CAL12 value if SEL12 is set in PMC_OCR.
It is possible to restart, at anytime, a measurement of the main frequency by means of the RCMEAS
bit in Main Clock Frequency Register (CKGR_MCFR). Thus, when MAINFRDY flag reads 1, another
read access on Main Clock Frequency Register (CKGR_MCFR) provides an image of the frequency
of the main clock on MAINF field. The software can calculate the error with an expected frequency
and correct the CAL12 (or CAL8/CAL4) field accordingly. This may be used to compensate frequency
drift due to derating factors such as temperature and/or voltage.
28.1.5.33 to 20 MHz Crystal or Ceramic Resonator-based Oscillator
After reset, the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is disabled and it is not
selected as the source of MAINCK.
The user can select the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator to be the source
of MAINCK, as it provides a more accurate frequency. The software enables or disables the main
oscillator so as to reduce power consumption by clearing the MOSCXTEN bit in the Main Oscillator
Register (CKGR_MOR).
When disabling the main oscillator by clearing the MOSCXTEN bit in CKGR_MOR, the MOSCXTS bit
in PMC_SR is automatically cleared, indicating the Main Clock is off.
When enabling the main oscillator, the user must initiate the main oscillator counter with a value
corresponding to the start-up time of the oscillator. This start-up time depends on the crystal
frequency connected to the oscillator.
When the MOSCXTEN bit and the MOSCXTST are written in CKGR_MOR to enable the main
oscillator, the XIN and XOUT pins are automatically switched into oscillator mode and MOSCXTS bit
in the Power Management Controller Status Register (PMC_SR) is cleared and the counter starts
counting down on the slow clock divided by 8 from the MOSCXTST value. Since the MOSCXTST
value is coded with 8 bits, the maximum start-up time is about 62 ms.
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When the counter reaches 0, the MOSCXTS bit is set, indicating that the main clock is valid. Setting
the MOSCXTS bit in PMC_IMR can trigger an interrupt to the processor.
28.1.5.4Main Clock Oscillator Selection
The user can select either the 12/8/4 MHz Fast RC Oscillator or the 3 to 20 MHz Crystal or Ceramic
Resonator-based oscillator to be the source of Main Clock.
The advantage of the 12/8/4 MHz Fast RC Oscillator is that it provides fast start-up time, this is why it
is selected by default (to start up the system) and when entering Wait Mode.
The advantage of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator is that it is very
accurate.
The selection is made by writing the MOSCSEL bit in the Main Oscillator Register (CKGR_MOR).
The switch of the Main Clock source is glitch free, so there is no need to run out of SLCK, PLLACK in
order to change the selection. The MOSCSELS bit of the Power Management Controller Status
Register (PMC_SR) allows knowing when the switch sequence is done.
Setting the MOSCSELS bit in PMC_IMR can trigger an interrupt to the processor.
Enabling the Fast RC Oscillator (MOSCRCEN = 1) and changing the Fast RC Frequency
(MOSCCRF) at the same time is not allowed.
The Fast RC must be enabled first and its frequency changed in a second step.
28.1.5.5Software Sequence to Detect the Presence of Fast Crystal
The frequency meter carried on the CKGR_MCFR register is operating on the selected main clock
and not on the fast crystal clock nor on the fast RC Oscillator clock.
Therefore, to check for the presence of the fast crystal clock, it is necessary to have the main clock
(MAINCK) driven by the fast crystal clock (MOSCSEL=1).
The following software sequence order must be followed:
MCK must select the slow clock (CSS=0 in the PMC_MCKR register).
Wait for the MCKRDY flag in the PMC_SR register to be 1.
The fast crystal must be enabled by programming 1 in the MOSCXTEN field in the
CKGR_MOR register with the MOSCXTST field being programmed to the appropriate
value (see the Electrical Characteristics chapter).
Wait for the MOSCXTS flag to be 1 in the PMC_SR register to get the end of a start-up
period of the fast crystal oscillator.
Then, MOSCSEL must be programmed to 1 in the CKGR_MOR register to select fast
main crystal oscillator for the main clock.
MOSCSEL must be read until its value equals 1.
Then the MOSCSELS status flag must be checked in the PMC_SR register.
At this point, 2 cases may occur (either MOSCSELS = 0 or MOSCSELS = 1).
If MOSCSELS = 1, there is a valid crystal connected and its frequency can be
determined by initiating a frequency measure by programming RCMEAS in the
CKGR_MCFR register.
If MOSCSELS = 0, there is no fast crystal clock (either no crystal connected or a crystal
clock out of specification).
A frequency measure can reinforce this status by initiating a frequency measure by
programming RCMEAS in the CKGR_MCFR register.
If MOSCSELS=0, the selection of the main clock must be programmed back to the main
RC oscillator by writing MOSCSEL to 0 prior to disabling the fast crystal oscillator.
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If MOSCSELS=0, the crystal oscillator can be disabled (MOSCXTEN=0 in the
CKGR_MOR register).
28.1.5.6Main Clock Frequency Counter
The device features a Main Clock frequency counter that provides the frequency of the Main Clock.
The Main Clock frequency counter is reset and starts incrementing at the Main Clock speed after the
next rising edge of the Slow Clock in the following cases:
When the 12/8/4 MHz Fast RC Oscillator clock is selected as the source of Main Clock and
when this oscillator becomes stable (i.e., when the MOSCRCS bit is set)
When the 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator is selected as the
source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit is
set)
When the Main Clock Oscillator selection is modified
When the RCMEAS bit of CKGR_MFCR is written to 1.
Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main Clock
Frequency Register (CKGR_MCFR) is set and the counter stops counting. Its value can be read in
the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of
Slow Clock, so that the frequency of the 12/8/4 MHz Fast RC Oscillator or 3 to 20 MHz Crystal or
Ceramic Resonator-based Oscillator can be determined.
28.1.6 Divider and PLL Block
The device features two Divider/two PLL Blocks that permit a wide range of frequencies to be
selected on either the master clock, the processor clock or the programmable clock outputs.
Additionally, they provide a 48 MHz signal to the embedded USB device port regardless of the
frequency of the main clock.
Figure 28-4 shows the block diagram of the dividers and PLL blocks.
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Figure 28-4. Dividers and PLL Blocks Diagram
28.1.6.1Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the
output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset,
each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
The PLLs (PLLA, PLLB) allow multiplication of the divider’s outputs. The PLL clock signal has a
frequency that depends on the respective source signal frequency and on the parameters DIV (DIVA,
DIVB) and MUL (MULA, MULB). The factor applied to the source signal frequency is (MUL + 1)/DIV.
When MUL is written to 0 or DIV=0, the PLL is disabled and its power consumption is saved. Re-
enabling the PLL can be performed by writing a value higher than 0 in the MUL field and DIV higher
than 0.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA, LOCKB) bit
in PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT,
PLLBCOUNT) in CKGR_PLLR (CKGR_PLLAR, CKGR_PLLBR) are loaded in the PLL counter. The
PLL counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK
bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of
Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field.
The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2, PLLBDIV2) bit in PMC Master
Clock Register (PMC_MCKR).
It is forbidden to change 12/8/4 MHz Fast RC Oscillator, or main selection in CKGR_MOR register
while Master Clock source is PLL and PLL reference clock is the Fast RC Oscillator.
The user must:
Divider B
DIVB
PLL B
MULB
DIVA
PLL A
Counter
PLLBCOUNT
LOCKB
PLL A
Counter
PLLACOUNT
LOCKA
MULA
OUTB
OUTA
SLCK
PLLACK
PLLBCK
Divider A
PLL B
MAINCK
PLLADIV2
PLLBDIV2
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Switch on the Main RC oscillator by writing 1 in CSS field of PMC_MCKR.
Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR.
Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in
PMC_SR.
Disable and then enable the PLL (LOCK in PMC_IDR and PMC_IER).
Wait for LOCK flag in PMC_SR.
Switch back to PLL by writing the appropriate value to CSS field of PMC_MCKR.
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28.2 Power Management Controller (PMC)
28.2.1 Description
The Power Management Controller (PMC) optimizes power consumption by controlling all system
and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals
and the Cortex-M4 Processor.
The Supply Controller selects between the 32 kHz RC oscillator or the slow crystal oscillator. The
unused oscillator is disabled automatically so that power consumption is optimized.
By default, at start-up the chip runs out of the Master Clock using the Fast RC Oscillator running at 4
MHz.
The user can trim the 8 and 4 MHz RC Oscillator frequencies by software.
28.2.2 Embedded Characteristics
The Power Management Controller provides the following clocks:
MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating
frequency of the device. It is available to the modules running permanently, such as the
Enhanced Embedded Flash Controller.
Processor Clock (HCLK) , automatically switched off when entering the processor in Sleep
Mode.
Free running processor Clock (FCLK)
The Cortex-M4 SysTick external clock
UDP Clock (UDPCK), required by USB Device Port operations.
Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SPI, TWI,
TC, etc.) and independently controllable. In order to reduce the number of clock names in a
product, the Peripheral Clocks are named MCK in the product datasheet.
Programmable Clock Outputs can be selected from the clocks provided by the clock generator
and driven on the PCKx pins.
Write Protected Registers
The Power Management Controller also provides the following operations on clocks:
A main crystal oscillator clock failure detector.
A frequency counter on main clock and an on-the-fly adjustable main RC oscillator frequency.
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28.2.3 Block Diagram
Figure 28-5. General Clock Block Diagram
28.2.4 Master Clock Controller
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the
clock provided to all the peripherals. The Master Clock is selected from one of the clocks provided by
the Clock Generator.
Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock
saves power consumption of the PLLs. The Master Clock Controller is made up of a clock selector
and a prescaler.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR
(Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock
between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared
in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
trigger an interrupt to the processor. This feature is useful when switching from a highspeed clock to a
lower one to inform the software when the change is actually done.
USB Clock
UDPCK
Management
Controller
Main Clock
MAINCK
PLLA Clock
PLLACK
ControlStatus
3-20 MHz
Crystal
or
Ceramic
Resonator
Oscillator
MOSCSEL
PLLA and
Divider /2
XIN
XOUT
XIN32
XOUT32
SLCK
(Supply Controller)
Embedded
32 kHz RC
Oscillator
32768 Hz
Crystal
Oscillator
PLLB Clock
PLLBCK
0
1
0
1
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1, /2, /3, /4, /8,
/16, /32, /64
HCLK
Processor
Clock
Controller
Sleep Mode
Master Clock Controller
(PMC_MCKR)
ON/OFF
Prescaler
/1, /2, /4, /8,
/16, /32, /64 pck[..]
PLLBCK
ON/OFF
FCLK
SysTick
Divider
/8
SLCK
MAINCK
PLLACK
PLLBCK
Processor clock
Free Running Cloc
k
Master Clock
PLLB and
Divider /2 Divider
/1, /2, /3,... /16
USB Clock Controller (PMC_USB)
PLLBCK
Embedded
4/8/12 MHz
Fast
RC Oscillator
Programmable Clock Controller
(PMC_PCKx)
PRES
USBDIV
PLLADIV2
PLLBDIV2
PRES
USBS
PLLACK
CSS
ON/OFF
CSS
MCK
Clock Generator
XTALSEL
Power
Slow Clock
Peripherals
Clock Controller
(PMC_PCERx)
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Figure 28-6. Master Clock Controller
28.2.5 Processor Clock Controller
The PMC features a Processor Clock Controller (HCLK) that implements the Processor Sleep Mode.
The Processor Clock can be disabled by executing the WFI (WaitForInterrupt) or the WFE
(WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Start-up Mode
Register (PMC_FSMR).
The Processor Clock HCLK is enabled after a reset and is automatically re-enabled by any enabled
interrupt. The Processor Sleep Mode is achieved by disabling the Processor Clock, which is
automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product.
When Processor Sleep Mode is entered, the current instruction is finished before the clock
is stopped, but this does not prevent data transfers from other masters of the system bus.
28.2.6 SysTick Clock
The SysTick calibration value is fixed to 12500 which allows the generation of a time base of 1 ms
with SysTick clock to the maximum frequency on MCK divided by 8.
28.2.7 USB Clock Controller
The user can select the PLLA or the PLLB output as the USB Source Clock by writing the USBS bit in
PMC_USB. If using the USB, the user must program the PLL to generate an appropriate frequency
depending on the USBDIV bit in PMC_USB.
When the PLL output is stable, i.e., the LOCK bit is set:
The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power
on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP bit
in PMC_SCSR gives the activity of this clock. The USB device port requires both the 48 MHz
signal and the Master Clock. The Master Clock may be controlled by means of the Master
Clock Controller.
Figure 28-7. USB Clock Controller
SLCK
Master Clock
Prescaler To the MCK Divider
PRESCSS
MAINCK
PLLACK
PLLBCK To the Processor
Clock Controller (PCK)
PMC_MCKR PMC_MCKR
USB
Source
Clock
UDP Clock (UDPCK)
UDP
USBDIV
Divider
/1,/2,/3,.../16
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28.2.8 Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by means of the
Peripheral Clock Controller. The user can individually enable and disable the Clock on the
peripherals.
The user can also enable and disable these clocks by writing Peripheral Clock Enable 0
(PMC_PCER0), Peripheral Clock Disable 0 (PMC_PCDR0), Peripheral Clock Enable 1
(PMC_PCER1) and Peripheral Clock Disable 1 (PMC_PCDR1) registers. The status of the peripheral
clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR0) and Peripheral
Clock Status Register (PMC_PCSR1).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are
automatically disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral has
executed its last programmed operation before disabling the clock. This is to avoid data corruption or
erroneous behavior of the system.
The bit number within the Peripheral Clock Control registers (PMC_PCER0-1, PMC_PCDR0-1, and
PMC_PCSR0-1) is the Peripheral Identifier defined at the product level. The bit number corresponds
to the interrupt source number assigned to the peripheral.
28.2.9 Free Running Processor Clock
The Free Running Processor Clock (FCLK) used for sampling interrupts and clocking debug blocks
ensures that interrupts can be sampled, and sleep events can be traced, while the processor is
sleeping. It is connected to Master Clock (MCK).
28.2.10 Programmable Clock Output Controller
The PMC controls 3 signals to be output on external pins, PCKx. Each signal can be independently
programmed via the Programmable Clock Registers (PMC_PCKx).
PCKx can be independently selected between the Slow Clock (SLCK), the Main Clock (MAINCK), the
PLLA Clock (PLLACK), the PLLB Clock (PLLBCK),and the Master Clock (MCK) by writing the CSS
field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by
writing the PRES (Prescaler) field in PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of
PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are
given in the PCKx bits of PMC_SCSR (System Clock Status Register).
Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually
what has been programmed in the Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching
clocks, it is strongly recommended to disable the Programmable Clock before any configuration
change and to re-enable it after the change is actually performed.
28.2.11 Fast Start-up
The device allows the processor to restart in less than 10 microseconds while the device is in Wait
Mode.
The system enters Wait Mode either by writing the WAITMODE bit at 1 in the PMC Clock Generator
Main Oscillator Register (CKGR_MOR), or by executing the WaitForEvent (WFE) instruction of the
processor while the LPM bit is at 1 in the PMC Fast Start-up Mode Register (PMC_FSMR). Waiting
for the MOSCRCEN bit to be cleared is strongly recommended to ensure that the core will not
execute undesired instructions.
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Important: Prior to instructing the system to enter the Wait Mode, the internal sources of wake-up
must be cleared. It must be verified that none of the enabled external wake-up inputs (WKUP) hold an
active polarity.
A Fast Start-up is enabled upon the detection of a programmed level on one of the 16 wake-up inputs
(WKUP) or upon an active alarm from the RTC, RTT and USB Controller. The polarity of the 16
wake-up inputs is programmable by writing the PMC Fast Start-up Polarity Register (PMC_FSPR).
The Fast Restart circuitry, as shown in Figure 28-8, is fully asynchronous and provides a fast start-up
signal to the Power Management Controller. As soon as the fast start-up signal is asserted, the
embedded 12/8/4 MHz Fast RC Oscillator restarts automatically.
When entering the Wait Mode, the embedded flash can be placed in low power mode depending on
the configuration of the FLPM in PMC_FSMR register. This bitfield can be programmed anytime and
will be taken into account at the next time the system enters Wait Mode.
The power consumption reduction is optimal when configuring 1 (deep power down mode) in FLPM. If
0 is programmed (standby mode), the power consumption is slightly higher as compared to the deep
power down mode.
When programming 2 in FLPM, the Wait Mode flash power consumption is equivalent to the active
mode when there is no read access on the flash.
Figure 28-8. Fast Start-up Circuitry
Each wake-up input pin and alarm can be enabled to generate a Fast Start-up event by writing 1 to
the corresponding bit in the Fast Start-up Mode Register (PMC_FSMR).
fast_restart
WKUP15
FSTT15
FSTP15
WKUP1
FSTT1
FSTP1
WKUP0
FSTT0
FSTP0
RTTAL
RTCAL
USBAL
RTT Alarm
RTC Alarm
USB Alarm
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The user interface does not provide any status for Fast Start-up, but the user can easily recover this
information by reading the PIO Controller and the status registers of the RTC, RTT and USB
Controller.
28.2.12 Main Crystal Clock Failure Detector
The clock failure detector monitors the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator to
identify an eventual defect of this oscillator (for example, if the crystal is unconnected).
The clock failure detector can be enabled or disabled by means of the CFDEN bit in the PMC Clock
Generator Main Oscillator Register (CKGR_MOR). After reset, the detector is disabled. However, if
the 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator is disabled, the clock failure detector
is disabled too.
The slow RC oscillator must be enabled.The clock failure detection must be enabled only when
system clock MCK selects the fast RC Oscillator. Then the status register must be read 2 slow clock
cycles after enabling.
A failure is detected by means of a counter incrementing on the 3 to 20 MHz Crystal oscillator or
Ceramic Resonator-based oscillator clock edge and timing logic clocked on the slow clock RC
oscillator controlling the counter. The counter is cleared when the slow clock RC oscillator signal is
low and enabled when the slow clock RC oscillator is high. Thus the failure detection time is 1 slow
clock RC oscillator clock period. If, during the high level period of the slow clock RC oscillator, less
than 8 fast crystal oscillator clock periods have been counted, then a failure is declared.
If a failure of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is detected, the
CFDEV flag is set in the PMC Status Register (PMC_SR), and generates an interrupt if it is not
masked. The interrupt remains active until a read operation in the PMC_SR register. The user can
know the status of the clock failure detector at any time by reading the CFDS bit in the PMC_SR
register.
If the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is selected as the source clock
of MAINCK (MOSCSEL = 1), and if the Master Clock Source is PLLACKor PLLBCK (CSS = 2 or 3), a
clock failure detection automatically forces MAINCK to be the source clock for the master clock
(MCK).Then, regardless of the PMC configuration, a clock failure detection automatically forces the
12/8/4 MHz Fast RC Oscillator to be the source clock for MAINCK. If the Fast RC Oscillator is
disabled when a clock failure detection occurs, it is automatically re-enabled by the clock failure
detection mechanism.
It takes 2 slow clock RC oscillator cycles to detect and switch from the 3 to 20 MHz Crystal, or
Ceramic Resonator-based Oscillator, to the 12/8/4 MHz Fast RC Oscillator if the Master Clock source
is Main Clock, or 3 slow clock RC oscillator cycles if the Master Clock source is PLLACKor PLLBCK.
A clock failure detection activates a fault output that is connected to the Pulse Width Modulator
(PWM) Controller. With this connection, the PWM controller is able to force its outputs and to protect
the driven device, if a clock failure is detected.
The user can know the status of the clock failure detector at any time by reading the FOS bit in the
PMC_SR register.
This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in
the PMC Fault Output Clear Register (PMC_FOCR).
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28.2.13 Programming Sequence
1. Enabling the Main Oscillator:
The main oscillator is enabled by setting the MOSCXTEN field in the Main Oscillator Register
(CKGR_MOR). The user can define a start-up time. This can be achieved by writing a value in
the MOSCXTST field in CKGR_MOR. Once this register has been correctly configured, the
user must wait for MOSCXTS field in the PMC_SR register to be set. This can be done either
by polling the status register, or by waiting the interrupt line to be raised if the associated inter-
rupt to MOSCXTS has been enabled in the PMC_IER register.
2. Checking the Main Oscillator Frequency (Optional):
In some situations the user may need an accurate measure of the main clock frequency. This
measure can be accomplished via the Main Clock Frequency Register (CKGR_MCFR).
Once the MAINFRDY field is set in CKGR_MCFR, the user may read the MAINF field in
CKGR_MCFR by performing another CKGR_MCFR read access. This provides the number of
main clock cycles within sixteen slow clock cycles.
3. Setting PLL and Divider:
All parameters needed to configure PLLA and the divider are located in CKGR_PLLAxR.
The DIV field is used to control the divider itself. It must be set to 1 when PLL is used. By
default, DIV parameter is set to 0 which means that the divider is turned off.
The MUL field is the PLL multiplier factor. This parameter can be programmed between 0 and
80. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is PLL input
frequency multiplied by (MUL + 1).
The PLLCOUNT field specifies the number of slow clock cycles before the LOCK bit is set in
PMC_SR, after CKGR_PLLA(B)R has been written.
Once the CKGR_PLL register has been written, the user must wait for the LOCK bit to be set in
the PMC_SR. This can be done either by polling the status register or by waiting the interrupt
line to be raised if the associated interrupt to LOCK has been enabled in PMC_IER. All param-
eters in CKGR_PLLA(B)R can be programmed in a single write operation. If at some stage one
of the following parameters, MUL or DIV is modified, the LOCK bit will go low to indicate that
PLL is not ready yet. When PLL is locked, LOCK will be set again. The user is constrained to
wait for LOCK bit to be set before using the PLL output clock.
4. Selection of Master Clock and Processor Clock
The Master Clock and the Processor Clock are configurable via the Master Clock Register
(PMC_MCKR).
The CSS field is used to select the Master Clock divider source. By default, the selected clock
source is main clock.
The PRES field is used to control the Master Clock prescaler. The user can choose between
different values (1, 2, 3, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by
PRES parameter. By default, PRES parameter is set to 1 which means that master clock is
equal to main clock.
Once PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in
PMC_SR. This can be done either by polling the status register or by waiting for the interrupt
line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER
register.
The PMC_MCKR must not be programmed in a single write operation. The preferred program-
ming sequence for PMC_MCKR is as follows:
If a new value for CSS field corresponds to PLL Clock,
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Program the PRES field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
Program the CSS field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
If a new value for CSS field corresponds to Main Clock or Slow Clock,
Program the CSS field in PMC_MCKR.
Wait for the MCKRDY bit to be set in the PMC_SR.
Program the PRES field in PMC_MCKR.
Wait for the MCKRDY bit to be set in PMC_SR.
If at some stage one of the following parameters, CSS or PRES is modified, the MCKRDY bit
will go low to indicate that the Master Clock and the Processor Clock are not ready yet. The
user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks.
Note: IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing
in CKGR_PLLR, the MCKRDY flag will go low while PLL is unlocked. Once PLL is locked
again, LOCK goes high and MCKRDY is set.
While PLL is unlocked, the Master Clock selection is automatically changed to Slow Clock.
For further information, see Section 28.2.14.2 “Clock Switching Waveforms” on page 467.
Code Example:
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
wait (MCKRDY=1)
The Master Clock is main clock divided by 2.
The Processor Clock is the Master Clock.
5. Selection of Programmable Clocks
Programmable clocks are controlled via registers, PMC_SCER, PMC_SCDR and PMC_SCSR.
Programmable clocks can be enabled and/or disabled via PMC_SCER and PMC_SCDR. 3
Programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication
as to which Programmable clock is enabled. By default all Programmable clocks are disabled.
Programmable Clock Registers (PMC_PCKx) are used to configure Programmable clocks.
The CSS field is used to select the Programmable clock divider source. Four clock options are
available: main clock, slow clock, PLLACK, PLLBCK. By default, the clock source selected is
slow clock.
The PRES field is used to control the Programmable clock prescaler. It is possible to choose
between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input
divided by PRES parameter. By default, the PRES parameter is set to 0 which means that
master clock is equal to slow clock.
Once PMC_PCKx has been programmed, The corresponding Programmable clock must be
enabled and the user is constrained to wait for the PCKRDYx bit to be set in PMC_SR. This
can be done either by polling the status register or by waiting the interrupt line to be raised, if
the associated interrupt to PCKRDYx has been enabled in the PMC_IER register. All parame-
ters in PMC_PCKx can be programmed in a single write operation.
If the CSS and PRES parameters are to be modified, the corresponding Programmable clock
must be disabled first. The parameters can then be modified. Once this has been done, the
user must re-enable the Programmable clock and wait for the PCKRDYx bit to be set.
6. Enabling Peripheral Clocks
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Once all of the previous steps have been completed, the peripheral clocks can be enabled
and/or disabled via registers PMC_PCER0, PMC_PCER, PMC_PCDR0 and PMC_PCDR.
28.2.14 Clock Switching Details
28.2.14.1Master Clock Switching Timings
Table 28-1 and Table 28-2 give the worst case timings required for the Master Clock to switch from
one selected clock to another one. This is in the event that the prescaler is de-activated. When the
prescaler is activated, an additional time of 64 clock cycles of the newly selected clock has to be
added.
Notes: 1. PLL designates either the PLLA or the PLLB Clock.
2. PLLCOUNT designates either PLLACOUNT or PLLBCOUNT.
Table 28-1. Clock Switching Timings (Worst Case)
Fro
mMain Clock SLCK PLL Clock
To
Main
Clock –4 x SLCK +
2.5 x Main Clock
3 x PLL Clock +
4 x SLCK +
1 x Main Clock
SLCK 0.5 x Main Clock +
4.5 x SLCK –3 x PLL Clock +
5 x SLCK
PLL Clock
0.5 x Main Clock +
4 x SLCK +
PLLCOUNT x SLCK +
2.5 x PLLx Clock
2.5 x PLL Clock +
5 x SLCK +
PLLCOUNT x SLCK
2.5 x PLL Clock +
4 x SLCK +
PLLCOUNT x SLCK
Table 28-2. Clock Switching Timings between Two PLLs (Worst Case)
Fro
mPLLA Clock PLLB Clock
To
PLLA Clock 2.5 x PLLA Clock +
4 x SLCK +
PLLACOUNT x SLCK
3 x PLLA Clock +
4 x SLCK +
1.5 x PLLA Clock
PLLB Clock 3 x PLLB Clock +
4 x SLCK +
1.5 x PLLB Clock
2.5 x PLLB Clock +
4 x SLCK +
PLLBCOUNT x SLCK
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28.2.14.2Clock Switching Waveforms
Figure 28-9. Switch Master Clock from Slow Clock to PLLx Clock
Figure 28-10.Switch Master Clock from Main Clock to Slow Clock
Slow Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
PLLx Clock
Slow Clock
Main Clock
MCKRDY
Master Clock
Write PMC_MCKR
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Figure 28-11.Change PLLx Programming
Figure 28-12.Programmable Clock Output Programming
Slow Clock
Slow Clock
PLLx Clock
LOCKx
MCKRDY
Master Clock
Write CKGR_PLLxR
PLLx Clock
PCKRDY
PCKx Output
Write PMC_PCKx
Write PMC_SCER
Write PMC_SCDR PCKx is disabled
PCKx is enabled
PLL Clock is selected
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28.2.15 Write Protection Registers
To prevent any single software error that may corrupt PMC behavior, certain address spaces can be
write protected by setting the WPEN bit in the “PMC Write Protect Mode Register” (PMC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PMC Write Protect
Status Register (PMC_WPSR) is set and the field WPVSRC indicates in which register the write
access has been attempted.
The WPVS flag is reset by writing the PMC Write Protect Mode Register (PMC_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
“PMC System Clock Enable Register”
“PMC System Clock Disable Register”
“PMC Peripheral Clock Enable Register 0”
“PMC Peripheral Clock Disable Register 0”
“PMC Clock Generator Main Oscillator Register”
“PMC Clock Generator PLLA Register”
“PMC Clock Generator PLLB Register”
“PMC Master Clock Register”
“PMC USB Clock Register”
“PMC Programmable Clock Register”
“PMC Fast Start-up Mode Register”
“PMC Fast Start-up Polarity Register”
“PMC Peripheral Clock Enable Register 1”
“PMC Peripheral Clock Disable Register 1”
“PMC Oscillator Calibration Register”
470
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16 Power Management Controller (PMC) User Interface
Table 28-3. Register Mapping
Offset Register Name Access Reset
0x0000 System Clock Enable Register PMC_SCER Write-only –
0x0004 System Clock Disable Register PMC_SCDR Write-only –
0x0008 System Clock Status Register PMC_SCSR Read-only 0x0000_0001
0x000C Reserved – – –
0x0010 Peripheral Clock Enable Register 0 PMC_PCER0 Write-only –
0x0014 Peripheral Clock Disable Register 0 PMC_PCDR0 Write-only –
0x0018 Peripheral Clock Status Register 0 PMC_PCSR0 Read-only 0x0000_0000
0x001C Reserved – – –
0x0020 Main Oscillator Register CKGR_MOR Read-write 0x0000_0008
0x0024 Main Clock Frequency Register CKGR_MCFR Read-write 0x0000_0000
0x0028 PLLA Register CKGR_PLLAR Read-write 0x0000_3F00
0x002C PLLB Register CKGR_PLLBR Read-write 0x0000_3F00
0x0030 Master Clock Register PMC_MCKR Read-write 0x0000_0001
0x0034 Reserved – – –
0x0038 USB Clock Register PMC_USB Read/Write 0x0000_0000
0x003C Reserved – – –
0x0040 Programmable Clock 0 Register PMC_PCK0 Read-write 0x0000_0000
0x0044 Programmable Clock 1 Register PMC_PCK1 Read-write 0x0000_0000
0x0048 Programmable Clock 2 Register PMC_PCK2 Read-write 0x0000_0000
0x004C - 0x005C Reserved – – –
0x0060 Interrupt Enable Register PMC_IER Write-only –
0x0064 Interrupt Disable Register PMC_IDR Write-only –
0x0068 Status Register PMC_SR Read-only 0x0001_0008
0x006C Interrupt Mask Register PMC_IMR Read-only 0x0000_0000
0x0070 Fast Start-up Mode Register PMC_FSMR Read-write 0x0000_0000
0x0074 Fast Start-up Polarity Register PMC_FSPR Read-write 0x0000_0000
0x0078 Fault Output Clear Register PMC_FOCR Write-only –
0x007C- 0x00E0 Reserved – – –
0x00E4 Write Protect Mode Register PMC_WPMR Read-write 0x0
0x00E8 Write Protect Status Register PMC_WPSR Read-only 0x0
0x00EC-0x00FC Reserved – – –
0x0100 Peripheral Clock Enable Register 1 PMC_PCER1 Write-only –
0x0104 Peripheral Clock Disable Register 1 PMC_PCDR1 Write-only –
0x0108 Peripheral Clock Status Register 1 PMC_PCSR1 Read-only 0x0000_0000
471
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Note: If an offset is not listed in the table it must be considered as “reserved”.
0x010C Reserved – – –
0x0110 Oscillator Calibration Register PMC_OCR Read-write 0x0040_4040
0x130 PLL Maximum Multiplier Value Register PMC_PMMR Read-Write 0x07FF07FF
Table 28-3. Register Mapping
Offset Register Name Access Reset
472
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.1PMC System Clock Enable Register
Name: PMC_SCER
Address: 0x400E0400
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• UDP: USB Device Port Clock Enable
0 = No effect.
1 = Enables the 48 MHz clock (UDPCK) of the USB Device Port.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – – PCK2 PCK1 PCK0
76543210
UDP–––––––
473
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• PCKx: Programmable Clock x Output Enable
0 = No effect.
1 = Enables the corresponding Programmable Clock output.
28.2.16.2PMC System Clock Disable Register
Name: PMC_SCDR
Address: 0x400E0404
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• UDP: USB Device Port Clock Disable
0 = No effect.
1 = Disables the 48 MHz clock (UDPCK) of the USB Device Port.
• PCKx: Programmable Clock x Output Disable
0 = No effect.
1 = Disables the corresponding Programmable Clock output.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – – PCK2 PCK1 PCK0
76543210
UDP–––––––
474
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.3PMC System Clock Status Register
Name: PMC_SCSR
Address: 0x400E0408
Access: Read-only
• UDP: USB Device Port Clock Status
0 = The 48 MHz clock (UDPCK) of the USB Device Port is disabled.
1 = The 48 MHz clock (UDPCK) of the USB Device Port is enabled.
• PCKx: Programmable Clock x Output Status
0 = The corresponding Programmable Clock output is disabled.
1 = The corresponding Programmable Clock output is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – – PCK2 PCK1 PCK0
76543210
UDP–––––––
475
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.4PMC Peripheral Clock Enable Register 0
Name: PMC_PCER0
Address: 0x400E0410
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• PIDx: Peripheral Clock x Enable
0 = No effect.
1 = Enables the corresponding peripheral clock.
Note: To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Other
peripherals can be enabled in PMC_PCER1 (Section 28.2.16.23 “PMC Peripheral Clock Enable Register 1”).
Note: Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
––––––––
476
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.5PMC Peripheral Clock Disable Register 0
Name: PMC_PCDR0
Address: 0x400E0414
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• PIDx: Peripheral Clock x Disable
0 = No effect.
1 = Disables the corresponding peripheral clock.
Note: To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Other
peripherals can be disabled in PMC_PCDR1 (Section 28.2.16.24 “PMC Peripheral Clock Disable Register 1”).
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
––––––––
477
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.6PMC Peripheral Clock Status Register 0
Name: PMC_PCSR0
Address: 0x400E0418
Access: Read-only
• PIDx: Peripheral Clock x Status
0 = The corresponding peripheral clock is disabled.
1 = The corresponding peripheral clock is enabled.
Note: To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Other
peripherals status can be read in PMC_PCSR1 (Section 28.2.16.25 “PMC Peripheral Clock Status Register 1”).
31 30 29 28 27 26 25 24
PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24
23 22 21 20 19 18 17 16
PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16
15 14 13 12 11 10 9 8
PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8
76543210
––––––––
478
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.7PMC Clock Generator Main Oscillator Register
Name: CKGR_MOR
Address: 0x400E0420
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• MOSCXTEN: Main Crystal Oscillator Enable
A crystal must be connected between XIN and XOUT.
0 = The Main Crystal Oscillator is disabled.
1 = The Main Crystal Oscillator is enabled. MOSCXTBY must be set to 0.
When MOSCXTEN is set, the MOSCXTS flag is set once the Main Crystal Oscillator start-up time is achieved.
• MOSCXTBY: Main Crystal Oscillator Bypass
0 = No effect.
1 = The Main Crystal Oscillator is bypassed. MOSCXTEN must be set to 0. An external clock must be connected on XIN.
When MOSCXTBY is set, the MOSCXTS flag in PMC_SR is automatically set.
Clearing MOSCXTEN and MOSCXTBY bits allows resetting the MOSCXTS flag.
• WAITMODE: Wait Mode Command
0 = No effect.
1 = Enters the device in Wait Mode.
Note: The WAITMODE bit is write-only.
• MOSCRCEN: Main On-Chip RC Oscillator Enable
0 = The Main On-Chip RC Oscillator is disabled.
1 = The Main On-Chip RC Oscillator is enabled.
When MOSCRCEN is set, the MOSCRCS flag is set once the Main On-Chip RC Oscillator start-up time is achieved.
31 30 29 28 27 26 25 24
– – – – – – CFDEN MOSCSEL
23 22 21 20 19 18 17 16
KEY
15 14 13 12 11 10 9 8
MOSCXTST
76543210
– MOSCRCF MOSCRCEN WAITMODE MOSCXTBY MOSCXTEN
479
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• MOSCRCF: Main On-Chip RC Oscillator Frequency Selection
At start-up, the Main On-Chip RC Oscillator frequency is 4 MHz.
Note: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR register. Therefore MOSCRCF and
MOSCRCEN cannot be changed at the same time.
• MOSCXTST: Main Crystal Oscillator Start-up Time
Specifies the number of Slow Clock cycles multiplied by 8 for the Main Crystal Oscillator start-up time.
• KEY: Write Access Password
• MOSCSEL: Main Oscillator Selection
0 = The Main On-Chip RC Oscillator is selected.
1 = The Main Crystal Oscillator is selected.
• CFDEN: Clock Failure Detector Enable
0 = The Clock Failure Detector is disabled.
1 = The Clock Failure Detector is enabled.
Note: 1. The slow RC oscillator must be enabled when the CFDEN is enabled.
2. The clock failure detection must be enabled only when system clock MCK selects the fast RC Oscillator.
3. Then the status register must be read 2 slow clock cycles after enabling.
Value Name Description
0x0 12_MHz The Fast RC Oscillator Frequency is at 12 MHz (default)
0x1 8_MHz The Fast RC Oscillator Frequency is at 8 MHz
0x2 4_MHz The Fast RC Oscillator Frequency is at 4 MHz
Value Name Description
0x37 PASSWD Writing any other value in this field aborts the write operation.
Always reads as 0.
480
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.8PMC Clock Generator Main Clock Frequency Register
Name: CKGR_MCFR
Address: 0x400E0424
Access: Read-Write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• MAINF: Main Clock Frequency
Gives the number of Main Clock cycles within 16 Slow Clock periods.
• MAINFRDY: Main Clock Ready
0 = MAINF value is not valid or the Main Oscillator is disabled or a measure has just been started by means of RCMEAS.
1 = The Main Oscillator has been enabled previously and MAINF value is available.
Note: To ensure that a correct value is read on the MAINF bitfield, the MAINFRDY flag must be read at 1 then another read
access must be performed on the register to get a stable value on the MAINF bitfield.
• RCMEAS: RC Oscillator Frequency Measure (write-only)
0 = No effect.
1 = Restarts measuring of the main RC frequency. MAINF will carry the new frequency as soon as a low to high transition occurs
on the MAINFRDY flag.
The measure is performed on the main frequency (i.e. not limited to RC oscillator only), but if the main clock frequency source is
the fast crystal oscillator, the restart of measuring is not needed because of the well known stability of crystal oscillators.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – RCMEAS – – – MAINFRDY
15 14 13 12 11 10 9 8
MAINF
76543210
MAINF
481
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.9PMC Clock Generator PLLA Register
Name: CKGR_PLLAR
Address: 0x400E0428
Access: Read-write
Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
•DIVA:PLLA Front_End Divider
0 = Divider output is stuck at 0 and PLLA is disabled.
1 = Divider is bypassed (divide by 1) PLLA is enabled
2 up to 255 = clock is divided by DIVA
• PLLACOUNT: PLLA Counter
Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• MULA: PLLA Multiplier
0 = The PLLA is deactivated (PLLA also disabled if DIVA = 0).
1 up to 80 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA + 1.
• ONE: Must Be Set to 1
Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
31 30 29 28 27 26 25 24
– – ONE – – MULA
23 22 21 20 19 18 17 16
MULA
15 14 13 12 11 10 9 8
– – PLLACOUNT
76543210
DIVA
482
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.10PMC Clock Generator PLLB Register
Name: CKGR_PLLBR
Address: 0x400E042C
Access: Read-write
Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• DIVB: PLLB Front-End Divider
0 = Divider output is stuck at 0 and PLLB is disabled.
1= Divider is bypassed (divide by 1)
2 up to 255 = clock is divided by DIVB
• PLLBCOUNT: PLLB Counter
Specifies the number of Slow Clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• MULB: PLLB Multiplier
0 = The PLLB is deactivated (PLLB also disabled if DIVB = 0).
1 up to 80 = The PLLB Clock frequency is the PLLB input frequency multiplied by MULB + 1.
31 30 29 28 27 26 25 24
– – – – – MULB
23 22 21 20 19 18 17 16
MULB
15 14 13 12 11 10 9 8
– – PLLBCOUNT
76543210
DIVB
483
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.11PMC Master Clock Register
Name: PMC_MCKR
Address: 0x400E0430
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• CSS: Master Clock Source Selection
• PRES: Processor Clock Prescaler
• PLLADIV2: PLLA Divisor by 2
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – PLLBDIV2 PLLADIV2 ––––
76543210
– PRES – – CSS
Value Name Description
0 SLOW_CLK Slow Clock is selected
1 MAIN_CLK Main Clock is selected
2 PLLA_CLK PLLA Clock is selected
3 PLLB_CLK PLLBClock is selected
Value Name Description
0 CLK_1 Selected clock
1 CLK_2 Selected clock divided by 2
2 CLK_4 Selected clock divided by 4
3 CLK_8 Selected clock divided by 8
4 CLK_16 Selected clock divided by 16
5 CLK_32 Selected clock divided by 32
6 CLK_64 Selected clock divided by 64
7 CLK_3 Selected clock divided by 3
PLLADIV2 PLLA Clock Division
0 PLLA clock frequency is divided by 1.
1 PLLA clock frequency is divided by 2.
484
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• PLLBDIV2: PLLB Divisor by 2
PLLBDIV2 PLLB Clock Division
0 PLLB clock frequency is divided by 1.
1 PLLB clock frequency is divided by 2.
485
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.12PMC USB Clock Register
Name: PMC_USB
Address: 0x400E0438
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• USBS: USB Input Clock Selection
0 = USB Clock Input is PLLA.
1 = USB Clock Input is PLLB
• USBDIV: Divider for USB Clock
USB Clock is Input clock divided by USBDIV+1.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – USBDIV
76543210
–––––––USBS
486
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.13PMC Programmable Clock Register
Name: PMC_PCKx
Address: 0x400E0440
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• CSS: Master Clock Source Selection
• PRES: Programmable Clock Prescaler
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– PRES – CSS
Value Name Description
0 SLOW_CLK Slow Clock is selected
1 MAIN_CLK Main Clock is selected
2 PLLA_CLK PLLA Clock is selected
3 PLLB_CLK PLLB Clock is selected
4 MCK Master Clock is selected
Value Name Description
0 CLK_1 Selected clock
1 CLK_2 Selected clock divided by 2
2 CLK_4 Selected clock divided by 4
3 CLK_8 Selected clock divided by 8
4 CLK_16 Selected clock divided by 16
5 CLK_32 Selected clock divided by 32
6 CLK_64 Selected clock divided by 64
487
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.14PMC Interrupt Enable Register
Name: PMC_IER
Address: 0x400E0460
Access: Write-only
• MOSCXTS: Main Crystal Oscillator Status Interrupt Enable
• LOCKA: PLLA Lock Interrupt Enable
• LOCKB: PLLB Lock Interrupt Enable
• MCKRDY: Master Clock Ready Interrupt Enable
• PCKRDYx: Programmable Clock Ready x Interrupt Enable
• MOSCSELS: Main Oscillator Selection Status Interrupt Enable
• MOSCRCS: Main On-Chip RC Status Interrupt Enable
• CFDEV: Clock Failure Detector Event Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – – CFDEV MOSCRCS MOSCSELS
15 14 13 12 11 10 9 8
– – – – – PCKRDY2 PCKRDY1 PCKRDY0
76543210
– – – – MCKRDY LOCKB LOCKA MOSCXTS
488
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.15PMC Interrupt Disable Register
Name: PMC_IDR
Address: 0x400E0464
Access: Write-only
• MOSCXTS: Main Crystal Oscillator Status Interrupt Disable
• LOCKA: PLLA Lock Interrupt Disable
• LOCKB: PLLB Lock Interrupt Disable
• MCKRDY: Master Clock Ready Interrupt Disable
• PCKRDYx: Programmable Clock Ready x Interrupt Disable
• MOSCSELS: Main Oscillator Selection Status Interrupt Disable
• MOSCRCS: Main On-Chip RC Status Interrupt Disable
• CFDEV: Clock Failure Detector Event Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – – CFDEV MOSCRCS MOSCSELS
15 14 13 12 11 10 9 8
– – – – – PCKRDY2 PCKRDY1 PCKRDY0
76543210
– – – – MCKRDY LOCKB LOCKA MOSCXTS
489
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.16PMC Status Register
Name: PMC_SR
Address: 0x400E0468
Access: Read-only
• MOSCXTS: Main XTAL Oscillator Status
0 = Main XTAL oscillator is not stabilized.
1 = Main XTAL oscillator is stabilized.
• LOCKA: PLLA Lock Status
0 = PLLA is not locked
1 = PLLA is locked.
• LOCKB: PLLB Lock Status
0 = PLLB is not locked
1 = PLLB is locked.
• MCKRDY: Master Clock Status
0 = Master Clock is not ready.
1 = Master Clock is ready.
• OSCSELS: Slow Clock Oscillator Selection
0 = Internal slow clock RC oscillator is selected.
1 = External slow clock 32 kHz oscillator is selected.
• PCKRDYx: Programmable Clock Ready Status
0 = Programmable Clock x is not ready.
1 = Programmable Clock x is ready.
• MOSCSELS: Main Oscillator Selection Status
0 = Selection is in progress.
1 = Selection is done.
• MOSCRCS: Main On-Chip RC Oscillator Status
0 = Main on-chip RC oscillator is not stabilized.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – FOS CFDS CFDEV MOSCRCS MOSCSELS
15 14 13 12 11 10 9 8
– – – – – PCKRDY2 PCKRDY1 PCKRDY0
76543210
OSCSELS – – – MCKRDY LOCKB LOCKA MOSCXTS
490
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
1 = Main on-chip RC oscillator is stabilized.
• CFDEV: Clock Failure Detector Event
0 = No clock failure detection of the fast crystal oscillator clock has occurred since the last read of PMC_SR.
1 = At least one clock failure detection of the fast crystal oscillator clock has occurred since the last read of PMC_SR.
• CFDS: Clock Failure Detector Status
0 = A clock failure of the fast crystal oscillator clock is not detected.
1 = A clock failure of the fast crystal oscillator clock is detected.
• FOS: Clock Failure Detector Fault Output Status
0 = The fault output of the clock failure detector is inactive.
1 = The fault output of the clock failure detector is active.
491
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.17PMC Interrupt Mask Register
Name: PMC_IMR
Address: 0x400E046C
Access: Read-only
• MOSCXTS: Main Crystal Oscillator Status Interrupt Mask
• LOCKA: PLLA Lock Interrupt Mask
• LOCKB: PLLB Lock Interrupt Mask
• MCKRDY: Master Clock Ready Interrupt Mask
• PCKRDYx: Programmable Clock Ready x Interrupt Mask
• MOSCSELS: Main Oscillator Selection Status Interrupt Mask
• MOSCRCS: Main On-Chip RC Status Interrupt Mask
• CFDEV: Clock Failure Detector Event Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – – CFDEV MOSCRCS MOSCSELS
15 14 13 12 11 10 9 8
– – – – – PCKRDY2 PCKRDY1 PCKRDY0
76543210
– – – – MCKRDY LOCKB LOCKA MOSCXTS
492
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.18PMC Fast Start-up Mode Register
Name: PMC_FSMR
Address: 0x400E0470
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• FSTT0 - FSTT15: Fast Start-up Input Enable 0 to 15
0 = The corresponding wake-up input has no effect on the Power Management Controller.
1 = The corresponding wake-up input enables a fast restart signal to the Power Management Controller.
• RTTAL: RTT Alarm Enable
0 = The RTT alarm has no effect on the Power Management Controller.
1 = The RTT alarm enables a fast restart signal to the Power Management Controller.
• RTCAL: RTC Alarm Enable
0 = The RTC alarm has no effect on the Power Management Controller.
1 = The RTC alarm enables a fast restart signal to the Power Management Controller.
• USBAL: USB Alarm Enable
0 = The USB alarm has no effect on the Power Management Controller.
1 = The USB alarm enables a fast restart signal to the Power Management Controller.
• LPM: Low Power Mode
0 = The WaitForInterrupt (WFI) or the WaitForEvent (WFE) instruction of the processor makes the processor enter Sleep Mode.
1 = The WaitForEvent (WFE) instruction of the processor makes the system to enter in Wait Mode.
• FLPM: Flash Low Power Mode
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– FLPM LPM – USBAL RTCAL RTTAL
15 14 13 12 11 10 9 8
FSTT15 FSTT14 FSTT13 FSTT12 FSTT11 FSTT10 FSTT9 FSTT8
76543210
FSTT7 FSTT6 FSTT5 FSTT4 FSTT3 FSTT2 FSTT1 FSTT0
Value Name Description
0 FLASH_STANDBY Flash is in Standby Mode when system enters Wait Mode
1 FLASH_DEEP_POWERDOWN Flash is in deep power down mode when system enters Wait Mode
2 FLASH_IDLE idle mode
493
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.19PMC Fast Start-up Polarity Register
Name: PMC_FSPR
Address: 0x400E0474
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• FSTPx: Fast Start-up Input Polarityx
Defines the active polarity of the corresponding wake-up input. If the corresponding wake-up input is enabled and at the FSTP
level, it enables a fast restart signal.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
FSTP15 FSTP14 FSTP13 FSTP12 FSTP11 FSTP10 FSTP9 FSTP8
76543210
FSTP7 FSTP6 FSTP5 FSTP4 FSTP3 FSTP2 FSTP1 FSTP0
494
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.20PMC Fault Output Clear Register
Name: PMC_FOCR
Address: 0x400E0478
Access: Write-only
• FOCLR: Fault Output Clear
Clears the clock failure detector fault output.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––FOCLR
495
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.21PMC Write Protect Mode Register
Name: PMC_WPMR
Address: 0x400E04E4
Access: Read-write
Reset: See Table 28-3
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x504D43 (“PMC” in ASCII).
Protects the registers:
•“PMC System Clock Enable Register”
•“PMC System Clock Disable Register”
•“PMC Peripheral Clock Enable Register 0”
•“PMC Peripheral Clock Disable Register 0”
•“PMC Clock Generator Main Oscillator Register”
•“PMC Clock Generator PLLA Register”
•“PMC Clock Generator PLLB Register”
•“PMC Master Clock Register”
•“PMC USB Clock Register”
•“PMC Programmable Clock Register”
•“PMC Fast Start-up Mode Register”
•“PMC Fast Start-up Polarity Register”
•“PMC Peripheral Clock Enable Register 1”
•“PMC Peripheral Clock Disable Register 1”
•“PMC Oscillator Calibration Register”
• WPKEY: Write Protect KEY
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
Value Name Description
0x504D43 PASSWD Writing any other value in this field aborts the write operation of the WPEN
bit. Always reads as 0.
496
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.22PMC Write Protect Status Register
Name: PMC_WPSR
Address: 0x400E04E8
Access: Read-only
Reset: See Table 28-3
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the PMC_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the PMC_WPSR register. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has
been attempted.
Reading PMC_WPSR automatically clears all fields.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
497
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.23PMC Peripheral Clock Enable Register 1
Name: PMC_PCER1
Address: 0x400E0500
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• PIDx: Peripheral Clock x Enable
0 = No effect.
1 = Enables the corresponding peripheral clock.
Notes: 1. To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
2. Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
28.2.16.24PMC Peripheral Clock Disable Register 1
Name: PMC_PCDR1
Address: 0x400E0504
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• PIDx: Peripheral Clock x Disable
0 = No effect.
1 = Disables the corresponding peripheral clock.
Note: To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––PID34PID33PID32
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––PID34PID33PID32
498
SAM4S [DATASHEET]
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28.2.16.25PMC Peripheral Clock Status Register 1
Name: PMC_PCSR1
Address: 0x400E0508
Access: Read-only
• PIDx: Peripheral Clock x Status
0 = The corresponding peripheral clock is disabled.
1 = The corresponding peripheral clock is enabled.
Note: To get PIDx, refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––PID34PID33PID32
499
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.16.26PMC Oscillator Calibration Register
Name: PMC_OCR
Address: 0x400E0510
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PMC Write Protect Mode Register” .
• CAL12: RC Oscillator Calibration bits for 12 MHz
Calibration bits applied to the RC Oscillator when SEL12 is set.
• SEL12: Selection of RC Oscillator Calibration bits for 12 MHz
0 = Default value stored in Flash memory.
1 = Value written by user in CAL12 field of this register.
• CAL8: RC Oscillator Calibration bits for 8 MHz
Calibration bits applied to the RC Oscillator when SEL8 is set.
• SEL8: Selection of RC Oscillator Calibration bits for 8 MHz
0 = Factory determined value stored in Flash memory.
1 = Value written by user in CAL8 field of this register.
• CAL4: RC Oscillator Calibration bits for 4 MHz
Calibration bits applied to the RC Oscillator when SEL4 is set.
• SEL4: Selection of RC Oscillator Calibration bits for 4 MHz
0 = Factory determined value stored in Flash memory.
1 = Value written by user in CAL4 field of this register.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
SEL4 CAL4
15 14 13 12 11 10 9 8
SEL8 CAL8
76543210
SEL12 CAL12
500
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
501
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
29. Chip Identifier (CHIPID)
29.1 Description
Chip Identifier registers permit recognition of the device and its revision. These registers provide the sizes and types of
the on-chip memories, as well as the set of embedded peripherals.
Two chip identifier registers are embedded: CHIPID_CIDR (Chip ID Register) and CHIPID_EXID (Extension ID). Both
registers contain a hard-wired value that is read-only. The first register contains the following fields:
EXT - shows the use of the extension identifier register
NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size
ARCH - identifies the set of embedded peripherals
SRAMSIZ - indicates the size of the embedded SRAM
EPROC - indicates the embedded ARM processor
VERSION - gives the revision of the silicon
The second register is device-dependent and reads 0 if the bit EXT is 0.
29.2 Embedded Characteristics
Chip ID Registers
Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals, Embedded
Processor
29.3 Chip Identifier (CHIPID) User Interface
Table 29-1. ATSAM4S Chip IDs Registers
Chip Name CHIPID_CIDR CHIPID_EXID
SAM4SD32C (Rev A) 0X29A7_0EE0 0x0
SAM4SD32B (Rev A) 0X2997_0EE0 0x0
SAM4SD16C (Rev A) 0X29A7_0CE0 0x0
SAM4SD16B (Rev A) 0X2997_0CE0 0x0
SAM4SA16C (Rev A) 0X28A7_0CE0 0x0
SAM4SA16B (Rev A) 0X2897_0CE0 0x0
SAM4S16B (Rev A) 0X289C_0CE0 0x0
SAM4S16C (Rev A) 0X28AC_0CE0 0x0
SAM4S8B (Rev A) 0X289C_0AE0 0x0
SAM4S8C (Rev A) 0X28AC_0AE0 0x0
Table 29-2. Register Mapping
Offset Register Name Access Reset
0x0 Chip ID Register CHIPID_CIDR Read-only –
0x4 Chip ID Extension Register CHIPID_EXID Read-only –
502
SAM4S [DATASHEET]
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29.3.1 Chip ID Register
Name: CHIPID_CIDR
Address: 0x400E0740
Access: Read-only
• VERSION: Version of the Device
Current version of the device.
• EPROC: Embedded Processor
• NVPSIZ: Nonvolatile Program Memory Size
31 30 29 28 27 26 25 24
EXT NVPTYP ARCH
23 22 21 20 19 18 17 16
ARCH SRAMSIZ
15 14 13 12 11 10 9 8
NVPSIZ2 NVPSIZ
76543210
EPROC VERSION
Value Name Description
1 ARM946ES ARM946ES
2 ARM7TDMI ARM7TDMI
3 CM3 Cortex-M3
4 ARM920T ARM920T
5 ARM926EJS ARM926EJS
6 CA5 Cortex-A5
7 CM4 Cortex-M4
Value Name Description
0 NONE None
1 8K 8 Kbytes
2 16K 16 Kbytes
3 32K 32 Kbytes
4 Reserved
5 64K 64 Kbytes
6 Reserved
7 128K 128 Kbytes
8 Reserved
9 256K 256 Kbytes
10 512K 512 Kbytes
11 Reserved
12 1024K 1024 Kbytes
503
SAM4S [DATASHEET]
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• NVPSIZ2: Second Nonvolatile Program Memory Size
• SRAMSIZ: Internal SRAM Size
13 Reserved
14 2048K 2048 Kbytes
15 Reserved
Value Name Description
0 NONE None
1 8K 8 Kbytes
2 16K 16 Kbytes
3 32K 32 Kbytes
4 Reserved
5 64K 64 Kbytes
6 Reserved
7 128K 128 Kbytes
8 Reserved
9 256K 256 Kbytes
10 512K 512 Kbytes
11 Reserved
12 1024K 1024 Kbytes
13 Reserved
14 2048K 2048 Kbytes
15 Reserved
Value Name Description
0 48K 48 Kbytes
1 192K 192 Kbytes
2 2K 2 Kbytes
3 6K 6 Kbytes
4 24K 24 Kbytes
5 4K 4 Kbytes
6 80K 80 Kbytes
7 160K 160 Kbytes
8 8K 8 Kbytes
9 16K 16 Kbytes
10 32K 32 Kbytes
11 64K 64 Kbytes
12 128K 128 Kbytes
Value Name Description
504
SAM4S [DATASHEET]
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• ARCH: Architecture Identifier
13 256K 256 Kbytes
14 96K 96 Kbytes
15 512K 512 Kbytes
Value Name Description
0x19 AT91SAM9xx AT91SAM9xx Series
0x29 AT91SAM9XExx AT91SAM9XExx Series
0x34 AT91x34 AT91x34 Series
0x37 CAP7 CAP7 Series
0x39 CAP9 CAP9 Series
0x3B CAP11 CAP11 Series
0x3C CM4P CM4P Series
0x40 AT91x40 AT91x40 Series
0x42 AT91x42 AT91x42 Series
0x55 AT91x55 AT91x55 Series
0x60 AT91SAM7Axx AT91SAM7Axx Series
0x61 AT91SAM7AQxx AT91SAM7AQxx Series
0x63 AT91x63 AT91x63 Series
0x64 SAM4CxxC SAM4CxC Series (100-pin version)
0x65 SAM4MxxC SAM4MxxC Series (100-pin version)
0x70 AT91SAM7Sxx AT91SAM7Sxx Series
0x71 AT91SAM7XCxx AT91SAM7XCxx Series
0x72 AT91SAM7SExx AT91SAM7SExx Series
0x73 AT91SAM7Lxx AT91SAM7Lxx Series
0x75 AT91SAM7Xxx AT91SAM7Xxx Series
0x76 AT91SAM7SLxx AT91SAM7SLxx Series
0x80 SAM3UxC SAM3UxC Series (100-pin version)
0x81 SAM3UxE SAM3UxE Series (144-pin version)
0x83 SAM3AxC SAM3AxC Series (100-pin version)
0x84 SAM3XxC SAM3XxC Series (100-pin version)
0x85 SAM3XxE SAM3XxE Series (144-pin version)
0x86 SAM3XxG SAM3XxG Series (208/217-pin version)
0x88 SAM3SxA SAM3SxASeries (48-pin version)
0x88 SAM4SxA SAM4SxA Series (48-pin version)
0x89 SAM3SxB SAM3SxB Series (64-pin version)
0x89 SAM4SxB SAM4SxB Series (64-pin version)
0x8A SAM3SxC SAM3SxC Series (100-pin version)
Value Name Description
505
SAM4S [DATASHEET]
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• NVPTYP: Nonvolatile Program Memory Type
• EXT: Extension Flag
0 = Chip ID has a single register definition without extension
1 = An extended Chip ID exists.
0x8A SAM4SxC SAM4SxC Series (100-pin version)
0x92 AT91x92 AT91x92 Series
0x93 SAM3NxA SAM3NxA Series (48-pin version)
0x94 SAM3NxB SAM3NxB Series (64-pin version)
0x95 SAM3NxC SAM3NxC Series (100-pin version)
0x99 SAM3SDxB SAM3SDxB Series (64-pin version)
0x9A SAM3SDxC SAM3SDxC Series (100-pin version)
0xA5 SAM5A SAM5A
0xB0 SAM4LxA SAM4LxA Series (48-pin version)
0xB1 SAM4LxB SAM4LxB Series (64-pin version)
0xB2 SAM4LxC SAM4LxC Series (100-pin version)
0xF0 AT75Cxx AT75Cxx Series
Value Name Description
0 ROM ROM
1 ROMLESS ROMless or on-chip Flash
4 SRAM SRAM emulating ROM
2 FLASH Embedded Flash Memory
3 ROM_FLASH ROM and Embedded Flash Memory
NVPSIZ is ROM size
NVPSIZ2 is Flash size
Value Name Description
506
SAM4S [DATASHEET]
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29.3.2 Chip ID Extension Register
Name: CHIPID_EXID
Address: 0x400E0744
Access: Read-only
• EXID: Chip ID Extension
Reads 0 if the EXT bit in CHIPID_CIDR is 0.
31 30 29 28 27 26 25 24
EXID
23 22 21 20 19 18 17 16
EXID
15 14 13 12 11 10 9 8
EXID
76543210
EXID
507
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30. Parallel Input/Output (PIO) Controller
30.1 Description
The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be
dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective
optimization of the pins of a product.
Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
Each I/O line of the PIO Controller features:
An input change interrupt enabling level change detection on any I/O line.
Additional Interrupt modes enabling rising edge, falling edge, low level or high level detection on any I/O line.
A glitch filter providing rejection of glitches lower than one-half of PIO clock cycle.
A debouncing filter providing rejection of unwanted pulses from key or push button operations.
Multi-drive capability similar to an open drain I/O line.
Control of the pull-up and pull-down of the I/O line.
Input visibility and output control.
The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.
An 8-bit parallel capture mode is also available which can be used to interface a CMOS digital image sensor, an ADC, a
DSP synchronous port in synchronous mode, etc...
30.2 Embedded Characteristics
Up to 32 Programmable I/O Lines
Fully Programmable through Set/Clear Registers
Multiplexing of Four Peripheral Functions per I/O Line
For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O)
Input Change Interrupt
Programmable Glitch Filter
Programmable Debouncing Filter
Multi-drive Option Enables Driving in Open Drain
Programmable Pull Up on Each I/O Line
Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time
Additional Interrupt Modes on a Programmable Event: Rising Edge, Falling Edge, Low Level or High Level
Lock of the Configuration by the Connected Peripheral
Synchronous Output, Provides Set and Clear of Several I/O lines in a Single Write
Write Protect Registers
Programmable Schmitt Trigger Inputs
Parallel Capture Mode
Can be used to interface a CMOS digital image sensor, an ADC....
One Clock, 8-bit Parallel Data and Two Data Enable on I/O Lines
Data Can be Sampled one time of out two (For Chrominance Sampling Only)
Supports Connection of one Peripheral DMA Controller Channel (PDC) Which Offers Buffer Reception
Without Processor Intervention
508
SAM4S [DATASHEET]
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30.3 Block Diagram
Figure 30-1. Block Diagram
Embedded
Peripheral
Embedded
Peripheral
PIO Interrupt
PIO Controller
Parallel Capture
Mode
Up to 32 pins
PMC
Up to 32
peripheral IOs
Up to 32
peripheral IOs
PIO Clock
APB
Data, Enable
PIN 31
PIN 1
PIN 0
Data, Enable
PDC
Data
Status
PIODCCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
Interrupt Controller
Table 30-1. Signal Description
Signal Name Signal Description Signal Type
PIODCCLK Parallel Capture Mode Clock Input
PIODC[7:0] Parallel Capture Mode Data Input
PIODCEN1 Parallel Capture Mode Data Enable 1 Input
PIODCEN2 Parallel Capture Mode Data Enable 2 Input
509
SAM4S [DATASHEET]
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Figure 30-2. Application Block Diagram
30.4 Product Dependencies
30.4.1 Pin Multiplexing
Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line
multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus product-dependent, the
hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their
application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the
PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin
is driven by the product.
30.4.2 External Interrupt Lines
The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is
not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt
lines (FIQ or IRQs) are used only as inputs.
30.4.3 Power Management
The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers
of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O
lines does not require the PIO Controller clock to be enabled.
However, when the clock is disabled, not all of the features of the PIO Controller are available, including glitch filtering.
Note that the Input Change Interrupt, Interrupt Modes on a programmable event and the read of the pin level require the
clock to be validated.
After a hardware reset, the PIO clock is disabled by default.
The user must configure the Power Management Controller before any access to the input line information.
30.4.4 Interrupt Generation
For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller
interrupt lines are connected among the interrupt sources. Refer to the PIO Controller peripheral identifier in the product
description to iden tify the i nterrupt sour ces dedi cated to the PIO Co ntroll ers. Using the PI O Contro ller requires t he
Interrupt Controller to be programmed first.
The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.
On-Chip Peripherals
PIO Controller
On-Chip Peripheral Drivers
Control Command
Driver
Keyboard Driver
Keyboard Driver General Purpose I/Os External Devices
510
SAM4S [DATASHEET]
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30.5 Functional Description
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is
represented in Figure 30-3. In this description each signal shown represents but one of up to 32 possible indexes.
Figure 30-3. I/O Line Control Logic
1
0
1
0
1
0
1
0
DQ DQ
DFF
1
0
1
0
11
00
01
10
Programmable
Glitch
or
Debouncing
Filter
PIO_PDSR[0] PIO_ISR[0]
PIO_IDR[0]
PIO_IMR[0]
PIO_IER[0]
PIO Interrupt
(Up to 32 possible inputs)
PIO_ISR[31]
PIO_IDR[31]
PIO_IMR[31]
PIO_IER[31]
Pad
PIO_PUDR[0]
PIO_PUSR[0]
PIO_PUER[0]
PIO_MDDR[0]
PIO_MDSR[0]
PIO_MDER[0]
PIO_CODR[0]
PIO_ODSR[0]
PIO_SODR[0]
PIO_PDR[0]
PIO_PSR[0]
PIO_PER[0]
PIO_ABCDSR1[0]
PIO_ODR[0]
PIO_OSR[0]
PIO_OER[0]
Resynchronization
Stage
Peripheral A Input
Peripheral D Output Enable
Peripheral A Output Enable
EVENT
DETECTOR
DFF
PIO_IFDR[0]
PIO_IFSR[0]
PIO_IFER[0]
PIO Clock
Clock
Divider
PIO_IFSCSR[0]
PIO_IFSCER[0]
PIO_IFSCDR[0]
PIO_SCDR
Slow Clock
Peripheral B Output Enable
Peripheral C Output Enable
11
00
01
10
Peripheral D Output
Peripheral A Output
Peripheral B Output
Peripheral C Output
PIO_ABCDSR2[0]
Peripheral B Input
Peripheral C Input
Peripheral D Input
511
SAM4S [DATASHEET]
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30.5.1 Pull-up and Pull-down Resistor Control
Each I/O line is designed with an embedded pull-up resistor and an embedded pull-down resistor. The pull-up resistor
can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable
Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status
Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. The
pull-down resistor can be enabled or disabled by writing respectively PIO_PPDER (Pull-down Enable Register) and
PIO_PPDDR (Pull-down Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in
PIO_PPDSR (Pull-down Status Register). Reading a 1 in PIO_PPDSR means the pull-up is disabled and reading a 0
means the pull-down is enabled.
Enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. In this case, the write of
PIO_PPDER for the concerned I/O line is discarded. Likewise, enabling the pull-up resistor while the pull-down resistor is
still enabled is not possible. In this case, the write of PIO_PUER for the concerned I/O line is discarded.
Control of the pull-up resistor is possible regardless of the configuration of the I/O line.
After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0, and all the pull-downs are disabled,
i.e. PIO_PPDSR resets at the value 0xFFFFFFFF.
30.5.2 I/O Line or Peripheral Function Selection
When a p in is mult iplex ed with on e or two per iphera l funct ions, th e select ion is con trolle d with th e regist ers PIO_ PER
(PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of
the set and clea r regi ster s and indica tes wh ethe r the pi n is control led by t he cor resp onding per ipheral or b y the PIO
Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the
PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers). A value of 1 indicates the pin is controlled by the PIO
controller.
If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have
no effect and PIO_PSR returns 1 for the corresponding bit.
After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some
events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must
be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus,
the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.
30.5.3 Peripheral A or B or C or D Selection
The PIO Controller provides multiplexing of up to four peripheral functions on a single pin. The selection is performed by
writing PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers).
For each pin:
The corresponding bit at level 0 in PIO_ABCDSR1 and the corresponding bit at level 0 in PIO_ABCDSR2 means
peripheral A is selected.
The corresponding bit at level 1 in PIO_ABCDSR1 and the corresponding bit at level 0 in PIO_ABCDSR2 means
peripheral B is selected.
The corresponding bit at level 0 in PIO_ABCDSR1 and the corresponding bit at level 1 in PIO_ABCDSR2 means
peripheral C is selected.
The corresponding bit at level 1 in PIO_ABCDSR1 and the corresponding bit at level 1 in PIO_ABCDSR2 means
peripheral D is selected.
Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The peripheral input lines are always
connected to the pin input.
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Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the configuration of the pin.
However, assignment of a pin to a peripheral function requires a write in the peripheral selection registers
(PIO_ABCDSR1 and PIO_ABCDSR2) in addition to a write in PIO_PDR.
After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are 0, thus indicating that all the PIO lines are configured on peripheral
A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode.
30.5.4 Output Control
When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O
line is controlled by the peripheral. Peripheral A or B or C or D depending on the value in PIO_ABCDSR1 and
PIO_ABCDSR2 (ABCD Select Registers) determines whether the pin is driven or not.
When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing
PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). The results of these write operations are
detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an
input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller.
The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR
(Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status
Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR
whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables
configuration of the I/O line prior to setting it to be managed by the PIO Controller.
Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven
on the I/O line.
30.5.5 Synchronous Data Output
Clearing one (or more) PIO line(s) and setting another one (or more) PIO line(s) synchronously cannot be done by using
PIO_SODR and PIO_CODR registers. It requires two successive write operations into two different registers. To
overcome this, the PIO Controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output
Data Status Register).Only bits unmasked by PIO_OWSR (Output Write Status Register) are written. The mask bits in
PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR
(Output Write Disable Register).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.
30.5.6 Multi Drive Control (Open Drain)
Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several
drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling
of the internal one) is generally required to guarantee a high level on the line.
The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable
Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a
peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external
drivers.
After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
30.5.7 Output Line Timings
Figure 30-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing
PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 30-4 also shows when the
feedback in PIO_PDSR is available.
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Figure 30-4. Output Line Timings
30.5.8 Inputs
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of
the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a
peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels
present on the I/O line at the time the clock was disabled.
30.5.9 Input Glitch and Debouncing Filters
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 Master Clock (MCK) and the debouncing filter can filter a
pulse of less than 1/2 Period of a Programmable Divided Slow Clock.
The selection between glitch filtering or debounce filtering is done by writing in the registers PIO_IFSCDR (PIO Input
Filter Slow Clock Disable Register) and PIO_IFSCER (PIO Input Filter Slow Clock Enable Register). Writing
PIO_IFSCDR and PIO_IFSCER respectively, sets and clears bits in PIO_IFSCSR.
The current selection status can be checked by reading the register PIO_IFSCSR (Input Filter Slow Clock Status
Register).
If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 Period of Master Clock.
If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2 Period of the
Programmable Divided Slow Clock.
For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV field of the PIO_SCDR
(Slow Clock Divider Register)
Tdiv_slclk = ((DIV+1)*2).Tslow_clock
When the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 Selected Clock Cycle
(Selected Clock represents MCK or Divided Slow Clock depending on PIO_IFSCDR and PIO_IFSCER programming) is
automatically rejected, while a pulse with a duration of 1 Selected Clock (MCK or Divided Slow Clock) cycle or more is
accepted. For pulse durations between 1/2 Selected Clock cycle and 1 Selected Clock cycle the pulse may or may not be
taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1
Selected Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Selected Clock
cycle.
2 cycles
APB Access
2 cycles
APB Access
MCK
Write PIO_SODR
Write PIO_ODSR at 1
PIO_ODSR
PIO_PDSR
Write PIO_CODR
Write PIO_ODSR at 0
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The filters also introduce some latencies, this is illustrated in Figure 30-5 and Figure 30-6.
The glitch filters are controlled by the register set: PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter
Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and
clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. It
acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and debouncing filters
require that the PIO Controller clock is enabled.
Figure 30-5. Input Glitch Filter Timing
Figure 30-6. Input Debouncing Filter Timing
30.5.10 Input Edge/Level Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line. The
Input Edge/Level Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable
Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit
in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive
samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available,
regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or
assigned to a peripheral function.
By default, the interrupt can be generated at any time an edge is detected on the input.
MCK
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle 1 cycle 1 cycle
up to 1.5 cycles
2 cycles
up to 2.5 cycles up to 2 cycles
1 cycle
1 cycle
PIO_IFCSR = 0
Divided Slow Clock
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle Tdiv_slclk
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
up to 2 cycles Tmck up to 2 cycles Tmck
up to 2 cycles Tmck
up to 2 cycles Tmck
up to 1.5 cycles Tdiv_slclk
PIO_IFCSR = 1
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Some additional Interrupt modes can be enabled/disabled by writing in the PIO_AIMER (Additional Interrupt Modes
Enable Register) and PIO_AIMDR (Additional Interrupt Modes Disable Register). The current state of this selection can
be read through the PIO_AIMMR (Additional Interrupt Modes Mask Register)
These Additional Modes are:
Rising Edge Detection
Falling Edge Detection
Low Level Detection
High Level Detection
In order to select an Additional Interrupt Mode:
The type of event detection (Edge or Level) must be selected by writing in the set of registers; PIO_ESR (Edge
Select Register) and PIO_LSR (Level Select Register) which enable respectively, the Edge and Level Detection.
The current status of this selection is accessible through the PIO_ELSR (Edge/Level Status Register).
The Polarity of the event detection (Rising/Falling Edge or High/Low Level) must be selected by writing in the set
of registers; PIO_FELLSR (Falling Edge /Low Level Select Register) and PIO_REHLSR (Rising Edge/High Level
Select Register) which allow to select Falling or Rising Edge (if Edge is selected in the PIO_ELSR) Edge or High or
Low Level Detection (if Level is selected in the PIO_ELSR). The current status of this selection is accessible
through the PIO_FRLHSR (Fall/Rise - Low/High Status Register).
When an input Edge or Level is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is
set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted.The interrupt signals of the
thirty-two channels are ORed-wired together to generate a single interrupt signal to the interrupt controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that
are pending when PIO_ISR is read must be handled. When an Interrupt is enabled on a “Level”, the interrupt is
generated as long as the interrupt source is not cleared, even if some read accesses in PIO_ISR are performed.
Figure 30-7. Event Detector on Input Lines (Figure represents line 0)
30.5.10.1Example
If generating an interrupt is required on the following:
Rising edge on PIO line 0
Falling edge on PIO line 1
Rising edge on PIO line 2
Event Detector
0
1
0
1
1
0
0
1
Edge
Detector
Falling Edge
Detector
Rising Edge
Detector
PIO_FELLSR[0]
PIO_FRLHSR[0]
PIO_REHLSR[0]
Low Level
Detector
High Level
Detector
PIO_ESR[0]
PIO_ELSR[0]
PIO_LSR[0]
PIO_AIMDR[0]
PIO_AIMMR[0]
PIO_AIMER[0]
Event detection on line 0
Resynchronized input on line 0
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Low Level on PIO line 3
High Level on PIO line 4
High Level on PIO line 5
Falling edge on PIO line 6
Rising edge on PIO line 7
Any edge on the other lines
The configuration required is described below.
30.5.10.2Interrupt Mode Configuration
All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER.
Then the Additional Interrupt Mode is enabled for line 0 to 7 by writing 32’h0000_00FF in PIO_AIMER.
30.5.10.3Edge or Level Detection Configuration
Lines 3, 4 and 5 are configured in Level detection by writing 32’h0000_0038 in PIO_LSR.
The other lines are configured in Edge detection by default, if they have not been previously configured. Otherwise, lines
0, 1, 2, 6 and 7 must be configured in Edge detection by writing 32’h0000_00C7 in PIO_ESR.
30.5.10.4Falling/Rising Edge or Low/High Level Detection Configuration.
Lines 0, 2, 4, 5 and 7 are configured in Rising Edge or High Level detection by writing 32’h0000_00B5 in PIO_REHLSR.
The other lines are configured in Falling Edge or Low Level detection by default, if they have not been previously
configured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low Level detection by writing
32’h0000_004A in PIO_FELLSR.
Figure 30-8. Input Change Interrupt Timings if there are no Additional Interrupt Modes
30.5.11 I/O Lines Lock
When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller PWM), it can become
locked by the action of this peripheral via an input of the PIO controller. When an I/O line is locked, the write of the
corresponding bit in the registers PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER,
PIO_ABCDSR1 and PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime which
I/O line i s lock ed by readin g the PI O Lock S tatu s register P IO_L OCKS R. Onc e an I/O l ine is l ocke d, the only wa y to
unlock it is to apply a hardware reset to the PIO Controller.
30.5.12 Programmable Schmitt Trigger
It is possible to configure each input for the Schmitt Trigger. By default the Schmitt trigger is active. Disabling the Schmitt
Trigger is requested when using the QTouch® Library.
MCK
Pin Level
Read PIO_ISR APB Access
PIO_ISR
APB Access
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30.5.13 Parallel Capture Mode
30.5.13.1Overview
The PIO Controller integrates an interface able to read data from a CMOS digital image sensor, a high-speed parallel
ADC, a DSP synchronous port in synchronous mode, etc.... For better understanding and to ease reading, the following
description uses an example with a CMOS digital image sensor.
30.5.13.2Functional Description
The CMOS digital image sensor provides a sensor clock, an 8-bit data synchronous with the sensor clock, and two data
enables which are synchronous with the sensor clock too.
Figure 30-9. PIO controller connection with CMOS digital image sensor
As soon as the parallel capture mode is enabled by writing the PCEN bit at 1 in PIO_PCMR (“PIO Parallel Capture Mode
Register” ), the I/O lines connected to the sensor clock (PIODCCLK), the sensor data (PIODC[7:0]) and the sensor data
enable signals (PIODCEN1 and PIODCEN2) are configured automatically as INPUTS. To know which I/O lines are
associated with the sensor clock, the sensor data and the sensor data enable signals, refer to the I/O multiplexing
table(s) in the product datasheet.
Once it is enabled, the parallel capture mode samples the data at rising edge of the sensor clock and resynchronizes it
with the PIO clock domain.
The size of the data which can be read in PIO_PCRHR (“PIO Parallel Capture Reception Holding Register” ) can b e
programmed thanks to the DSIZE field in PIO_PCMR. If this data size is larger than 8 bits, then the parallel capture mode
samples several sensor data to form a concatenated data of size defined by DSIZE. Then this data is stored in
PIO_PCRHR and the flag DRDY is set to 1 in PIO_PCISR (“PIO Parallel Capture Interrupt Status Register” ).
The parallel capture mode can be associated with a reception channel of the Peripheral DMA Controller (PDC). This
enables performing reception transfer from parallel capture mode to a memory buffer without any intervention from the
CPU. Transfer status signals from PDC are available in PIO_PCISR through the flags ENDRX and RXBUFF (see “PIO
Parallel Capture Interrupt Status Register” on page 557).
The parallel capture mode can take into account the sensor data enable signals or not. If the bit ALWYS is set to 0 in
PIO_PCMR, the parallel capture mode samples the sensor data at the rising edge of the sensor clock only if both data
enable signals are active (at 1). If the bit ALWYS is set to 1, the parallel capture mode samples the sensor data at the
rising edge of the sensor clock whichever the data enable signals are.
The parallel capture mode can sample the sensor data only one time out of two. This is particularly useful when the user
wants only to sample the luminance Y of a CMOS digital image sensor which outputs a YUV422 data stream. If the
HALFS bit is set to 0 in PIO_PCMR, the parallel capture mode samples the sensor data in the conditions described
above. If the HALFS bit is set to 1 in PIO_PCMR, the parallel capture mode samp les the sensor data in the conditions
described above, but only one time out of two. Depending on the FRSTS bit in PIO_PCMR, the sensor can either sample
PIO Controller
Parallel Capture
Mode CMOS Digital
Image Sensor
PDC
Data
Status
PIODCCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
PCLK
DATA[7:0]
VSYNC
HSYNC
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the even or odd sensor data. If sensor data are numbered in the order that they are received with an index from 0 to n, if
FRSTS = 0 then only data with an even index are sampled, if FRSTS = 1 then only data with an odd index are sampled.
If data is ready in PIO_PCRHR and it is not read before a new data is stored in PIO_PCRHR, then an overrun error
occurs. The previous data is lost and the OVRE flag in PIO_PCISR is set to 1. This flag is automatically reset when
PIO_PCISR is read (reset after read).
The flags DRDY, OVRE, ENDRX and RXBUFF can be a source of the PIO interrupt.
Figure 30-10.Parallel Capture Mode Waveforms (DSIZE = 2, ALWYS = 0, HALFS = 0)
Figure 30-11.Parallel Capture Mode Waveforms (DSIZE=2, ALWYS=1, HALFS=0)
0x23 0x34 0x450x12 0x56 0x67 0x780x89
0x5645_3423
MCK
PIODCCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
DRDY (PIO_PCISR)
RDATA (PIO_PCRHR)
0x01
Read of PIO_PCISR
0x23 0x34 0x450x12 0x56 0x67 0x780x89
0x3423_1201
MCK
PIODCCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
DRDY (PIO_PCISR)
RDATA (PIO_PCRHR)
0x01
Read of PIO_PCISR
0x7867_5645
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Figure 30-12.Parallel Capture Mode Waveforms (DSIZE=2, ALWYS=0, HALFS=1, FRSTS=0)
Figure 30-13.Parallel Capture Mode Waveforms (DSIZE=2, ALWYS=0, HALFS=1, FRSTS=1)
30.5.13.3Restrictions
Configuration fields DSIZE, ALWYS, HALFS and FRSTS in PIO_PCMR (“PIO Parallel Capture Mode Register” )
can be changed ONLY if the parallel capture mode is disabled at this time (PCEN = 0 in PIO_PCMR).
Frequency of PIO controller clock must be strictly superior to 2 times the frequency of the clock of the device which
generates the parallel data.
30.5.13.4Programming Sequence
Without PDC
1. Write PIO_PCIDR and PIO_PCIER (“PIO Parallel Capture Interrupt Disable Register” and “PIO Parallel Capture
Interrupt Enable Register” ) in order to configure the parallel capture mode interrupt mask.
2. Write PIO_PCMR (“PIO Parallel Capture Mode Register” ) to set the fields DSIZE, ALWYS, HALFS and FRSTS in
order to configure the parallel capture mode WITHOUT enabling the parallel capture mode.
0x23 0x34 0x450x12 0x56 0x67 0x780x89
0x6745_2301
MCK
PIODCCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
DRDY (PIO_PCISR)
RDATA (PIO_PCRHR)
0x01
Read of PIO_PCISR
0x23 0x34 0x450x12 0x56 0x67 0x780x89
0x7856_3412
MCK
PIODCCLK
PIODC[7:0]
PIODCEN1
PIODCEN2
DRDY (PIO_PCISR)
RDATA (PIO_PCRHR)
0x01
Read of PIO_PCISR
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3. Write PIO_PCMR to set the PCEN bit to 1 in order to enable the parallel capture mode WITHOUT changing the
previous configuration.
4. Wait for a data ready by polling the DRDY flag in PIO_PCISR (“PIO Parallel Capture Interrupt Status Register” ) or
by waiting the corresponding interrupt.
5. Check OVRE flag in PIO_PCISR.
6. Read the data in PIO_PCRHR (“PIO Parallel Capture Reception Holding Register” ).
7. If new data are expected go to step 4.
8. Write PIO_PCMR to set the PCEN bit to 0 in order to disable the parallel capture mode WITHOUT changing the
previous configuration.
With PDC
1. Write PIO_PCIDR and PIO_PCIER (“PIO Parallel Capture Interrupt Disable Register” and “PIO Parallel Capture
Interrupt Enable Register” ) in order to configure the parallel capture mode interrupt mask.
2. Configure PDC transfer in PDC registers.
3. Write PIO_PCMR (“PIO Parallel Capture Mode Register” ) to set the fields DSIZE, ALWYS, HALFS and FRSTS in
order to configure the parallel capture mode WITHOUT enabling the parallel capture mode.
4. Write PIO_PCMR to set PCEN bit to 1 in order to enable the parallel capture mode WITHOUT changing the previ-
ous configuration.
5. Wait for end of transfer by waiting the interrupt corresponding the flag ENDRX in PIO_PCISR (“PIO Parallel Cap-
ture Interrupt Status Register” ).
6. Check OVRE flag in PIO_PCISR.
7. If a new buffer transfer is expected go to step 5.
8. Write PIO_PCMR to set the PCEN bit to 0 in order to disable the parallel capture mode WITHOUT changing the
previous configuration.
30.5.14 Write Protection Registers
To prevent any single software error that may corrupt PIO behavior, certain ad dress spaces can be write-protected by
setting the WPEN bit in the “PIO Write Protect Mode Register” (PIO_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the PIO Write Protect Status Register
(PIO_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the PIO Write Protect Mode Register (PIO_WPMR) with the appropriate access key,
WPKEY.
The protected registers are:
“PIO Enable Register” on page 525
“PIO Disable Register” on page 525
“PIO Output Enable Register” on page 526
“PIO Output Disable Register” on page 527
“PIO Input Filter Enable Register” on page 528
“PIO Input Filter Disable Register” on page 528
“PIO Multi-driver Enable Register” on page 533
“PIO Multi-driver Disable Register” on page 534
“PIO Pull Up Disable Register” on page 535
“PIO Pull Up Enable Register” on page 535
“PIO Peripheral ABCD Select Register 1” on page 537
“PIO Peripheral ABCD Select Register 2” on page 538
“PIO Output Write Enable Register” on page 543
“PIO Output Write Disable Register” on page 543
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“PIO Pad Pull Down Disable Register” on page 541
“PIO Pad Pull Down Status Register” on page 542
“PIO Parallel Capture Mode Register” on page 553
30.6 I/O Lines Programming Example
The programing example as shown in Table 30-2 below is used to obtain the following configuration.
4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor
Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor, no pull-
down resistor
Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters
and input change interrupts
Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no
pull-up resistor, no glitch filter
I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor
I/O lines 20 to 23 assigned to peripheral B functions with pull-down resistor
I/O line 24 to 27 assigned to peripheral C with Input Change Interrupt, no pull-up resistor and no pull-down resistor
I/O line 28 to 31 assigned to peripheral D, no pull-up resistor and no pull-down resistor
Table 30-2. Programming Example
Register Value to be Written
PIO_PER 0x0000_FFFF
PIO_PDR 0xFFFF_0000
PIO_OER 0x0000_00FF
PIO_ODR 0xFFFF_FF00
PIO_IFER 0x0000_0F00
PIO_IFDR 0xFFFF_F0FF
PIO_SODR 0x0000_0000
PIO_CODR 0x0FFF_FFFF
PIO_IER 0x0F00_0F00
PIO_IDR 0xF0FF_F0FF
PIO_MDER 0x0000_000F
PIO_MDDR 0xFFFF_FFF0
PIO_PUDR 0xFFF0_00F0
PIO_PUER 0x000F_FF0F
PIO_PPDDR 0xFF0F_FFFF
PIO_PPDER 0x00F0_0000
PIO_ABCDSR1 0xF0F0_0000
PIO_ABCDSR2 0xFF00_0000
PIO_OWER 0x0000_000F
PIO_OWDR 0x0FFF_ FFF0
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30.7 Parallel Input/Output Controller (PIO) User Interface
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface
registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect.
Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO
Controller and PIO_PSR returns 1 systematically.
Table 30-3. Register Mapping
Offset Register Name Access Reset
0x0000 PIO Enable Register PIO_PER Write-only –
0x0004 PIO Disable Register PIO_PDR Write-only –
0x0008 PIO Status Register PIO_PSR Read-only (1)
0x000C Reserved
0x0010 Output Enable Register PIO_OER Write-only –
0x0014 Output Disable Register PIO_ODR Write-only –
0x0018 Output Status Register PIO_OSR Read-only 0x0000 0000
0x001C Reserved
0x0020 Glitch Input Filter Enable Register PIO_IFER Write-only –
0x0024 Glitch Input Filter Disable Register PIO_IFDR Write-only –
0x0028 Glitch Input Filter Status Register PIO_IFSR Read-only 0x0000 0000
0x002C Reserved
0x0030 Set Output Data Register PIO_SODR Write-only –
0x0034 Clear Output Data Register PIO_CODR Write-only
0x0038 Output Data Status Register PIO_ODSR Read-only
or(2)
Read-write –
0x003C Pin Data Status Register PIO_PDSR Read-only (3)
0x0040 Interrupt Enable Register PIO_IER Write-only –
0x0044 Interrupt Disable Register PIO_IDR Write-only –
0x0048 Interrupt Mask Register PIO_IMR Read-only 0x00000000
0x004C Interrupt Status Register(4) PIO_ISR Read-only 0x00000000
0x0050 Multi-driver Enable Register PIO_MDER Write-only –
0x0054 Multi-driver Disable Register PIO_MDDR Write-only –
0x0058 Multi-driver Status Register PIO_MDSR Read-only 0x00000000
0x005C Reserved
0x0060 Pull-up Disable Register PIO_PUDR Write-only –
0x0064 Pull-up Enable Register PIO_PUER Write-only –
0x0068 Pad Pull-up Status Register PIO_PUSR Read-only (1)
0x006C Reserved
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0x0070 Peripheral Select Register 1 PIO_ABCDSR1 Read-write 0x00000000
0x0074 Peripheral Select Register 2 PIO_ABCDSR2 Read-write 0x00000000
0x0078
to
0x007C Reserved
0x0080 Input Filter Slow Clock Disable Register PIO_IFSCDR Write-only –
0x0084 Input Filter Slow Clock Enable Register PIO_IFSCER Write-only –
0x0088 Input Filter Slow Clock Status Register PIO_IFSCSR Read-only 0x00000000
0x008C Slow Clock Divider Debouncing Register PIO_SCDR Read-write 0x00000000
0x0090 Pad Pull-down Disable Register PIO_PPDDR Write-only –
0x0094 Pad Pull-down Enable Register PIO_PPDER Write-only –
0x0098 Pad Pull-down Status Register PIO_PPDSR Read-only (1)
0x009C Reserved
0x00A0 Output Write Enable PIO_OWER Write-only –
0x00A4 Output Write Disable PIO_OWDR Write-only –
0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000
0x00AC Reserved
0x00B0 Additional Interrupt Modes Enable Register PIO_AIMER Write-only –
0x00B4 Additional Interrupt Modes Disables Register PIO_AIMDR Write-only –
0x00B8 Additional Interrupt Modes Mask Register PIO_AIMMR Read-only 0x00000000
0x00BC Reserved
0x00C0 Edge Select Register PIO_ESR Write-only –
0x00C4 Level Select Register PIO_LSR Write-only –
0x00C8 Edge/Level Status Register PIO_ELSR Read-only 0x00000000
0x00CC Reserved
0x00D0 Falling Edge/Low Level Select Register PIO_FELLSR Write-only –
0x00D4 Rising Edge/ High Level Select Register PIO_REHLSR Write-only –
0x00D8 Fall/Rise - Low/High Status Register PIO_FRLHSR Read-only 0x00000000
0x00DC Reserved
0x00E0 Lock Status PIO_LOCKSR Read-only 0x00000000
0x00E4 Write Protect Mode Register PIO_WPMR Read-write 0x0
0x00E8 Write Protect Status Register PIO_WPSR Read-only 0x0
0x00EC
to
0x00F8 Reserved
0x0100 Schmitt Trigger Register PIO_SCHMITT Read-write 0x00000000
0x0104-
0x010C Reserved
0x0110 Reserved
0x0114-
0x011C Reserved
Table 30-3. Register Mapping (Continued)
Offset Register Name Access Reset
524
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Notes: 1. Reset value depends on the product implementation.
2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the
PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was
disabled.
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
occurred.
Note: If an offset is not listed in the table it must be considered as reserved.
0x0120
to
0x014C Reserved
0x150 Parallel Capture Mode Register PIO_PCMR Read-write 0x00000000
0x154 Parallel Capture Interrupt Enable Register PIO_PCIER Write-only –
0x158 Parallel Capture Interrupt Disable Register PIO_PCIDR Write-only –
0x15C Parallel Capture Interrupt Mask Register PIO_PCIMR Read-only 0x00000000
0x160 Parallel Capture Interrupt Status Register PIO_PCISR Read-only 0x00000000
0x164 Parallel Capture Reception Holding Register PIO_PCRHR Read-only 0x00000000
0x0168
to
0x018C Reserved for PDC Registers
Table 30-3. Register Mapping (Continued)
Offset Register Name Access Reset
525
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.1 PIO Enable Register
Name: PIO_PER
Address: 0x400E0E00 (PIOA), 0x400E1000 (PIOB), 0x400E1200 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: PIO Enable
0: No effect.
1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
30.7.2 PIO Disable Register
Name: PIO_PDR
Address: 0x400E0E04 (PIOA), 0x400E1004 (PIOB), 0x400E1204 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: PIO Disable
0: No effect.
1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
526
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.3 PIO Status Register
Name: PIO_PSR
Address: 0x400E0E08 (PIOA), 0x400E1008 (PIOB), 0x400E1208 (PIOC)
Access: Read-only
• P0-P31: PIO Status
0: PIO is inactive on the corresponding I/O line (peripheral is active).
1: PIO is active on the corresponding I/O line (peripheral is inactive).
30.7.4 PIO Output Enable Register
Name: PIO_OER
Address: 0x400E0E10 (PIOA), 0x400E1010 (PIOB), 0x400E1210 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Output Enable
0: No effect.
1: Enables the output on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
527
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.5 PIO Output Disable Register
Name: PIO_ODR
Address: 0x400E0E14 (PIOA), 0x400E1014 (PIOB), 0x400E1214 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Output Disable
0: No effect.
1: Disables the output on the I/O line.
30.7.6 PIO Output Status Register
Name: PIO_OSR
Address: 0x400E0E18 (PIOA), 0x400E1018 (PIOB), 0x400E1218 (PIOC)
Access: Read-only
• P0-P31: Output Status
0: The I/O line is a pure input.
1: The I/O line is enabled in output.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
528
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.7 PIO Input Filter Enable Register
Name: PIO_IFER
Address: 0x400E0E20 (PIOA), 0x400E1020 (PIOB), 0x400E1220 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Input Filter Enable
0: No effect.
1: Enables the input glitch filter on the I/O line.
30.7.8 PIO Input Filter Disable Register
Name: PIO_IFDR
Address: 0x400E0E24 (PIOA), 0x400E1024 (PIOB), 0x400E1224 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Input Filter Disable
0: No effect.
1: Disables the input glitch filter on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
529
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.9 PIO Input Filter Status Register
Name: PIO_IFSR
Address: 0x400E0E28 (PIOA), 0x400E1028 (PIOB), 0x400E1228 (PIOC)
Access: Read-only
• P0-P31: Input Filer Status
0: The input glitch filter is disabled on the I/O line.
1: The input glitch filter is enabled on the I/O line.
30.7.10 PIO Set Output Data Register
Name: PIO_SODR
Address: 0x400E0E30 (PIOA), 0x400E1030 (PIOB), 0x400E1230 (PIOC)
Access: Write-only
• P0-P31: Set Output Data
0: No effect.
1: Sets the data to be driven on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
530
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.11 PIO Clear Output Data Register
Name: PIO_CODR
Address: 0x400E0E34 (PIOA), 0x400E1034 (PIOB), 0x400E1234 (PIOC)
Access: Write-only
• P0-P31: Clear Output Data
0: No effect.
1: Clears the data to be driven on the I/O line.
30.7.12 PIO Output Data Status Register
Name: PIO_ODSR
Address: 0x400E0E38 (PIOA), 0x400E1038 (PIOB), 0x400E1238 (PIOC)
Access: Read-only or Read-write
• P0-P31: Output Data Status
0: The data to be driven on the I/O line is 0.
1: The data to be driven on the I/O line is 1.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
531
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.13 PIO Pin Data Status Register
Name: PIO_PDSR
Address: 0x400E0E3C (PIOA), 0x400E103C (PIOB), 0x400E123C (PIOC)
Access: Read-only
• P0-P31: Output Data Status
0: The I/O line is at level 0.
1: The I/O line is at level 1.
30.7.14 PIO Interrupt Enable Register
Name: PIO_IER
Address: 0x400E0E40 (PIOA), 0x400E1040 (PIOB), 0x400E1240 (PIOC)
Access: Write-only
• P0-P31: Input Change Interrupt Enable
0: No effect.
1: Enables the Input Change Interrupt on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
532
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.15 PIO Interrupt Disable Register
Name: PIO_IDR
Address: 0x400E0E44 (PIOA), 0x400E1044 (PIOB), 0x400E1244 (PIOC)
Access: Write-only
• P0-P31: Input Change Interrupt Disable
0: No effect.
1: Disables the Input Change Interrupt on the I/O line.
30.7.16 PIO Interrupt Mask Register
Name: PIO_IMR
Address: 0x400E0E48 (PIOA), 0x400E1048 (PIOB), 0x400E1248 (PIOC)
Access: Read-only
• P0-P31: Input Change Interrupt Mask
0: Input Change Interrupt is disabled on the I/O line.
1: Input Change Interrupt is enabled on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
533
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.17 PIO Interrupt Status Register
Name: PIO_ISR
Address: 0x400E0E4C (PIOA), 0x400E104C (PIOB), 0x400E124C (PIOC)
Access: Read-only
• P0-P31: Input Change Interrupt Status
0: No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
1: At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
30.7.18 PIO Multi-driver Enable Register
Name: PIO_MDER
Address: 0x400E0E50 (PIOA), 0x400E1050 (PIOB), 0x400E1250 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Multi Drive Enable.
0: No effect.
1: Enables Multi Drive on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
534
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.19 PIO Multi-driver Disable Register
Name: PIO_MDDR
Address: 0x400E0E54 (PIOA), 0x400E1054 (PIOB), 0x400E1254 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Multi Drive Disable.
0: No effect.
1: Disables Multi Drive on the I/O line.
30.7.20 PIO Multi-driver Status Register
Name: PIO_MDSR
Address: 0x400E0E58 (PIOA), 0x400E1058 (PIOB), 0x400E1258 (PIOC)
Access: Read-only
• P0-P31: Multi Drive Status.
0: The Multi Drive is disabled on the I/O line. The pin is driven at high and low level.
1: The Multi Drive is enabled on the I/O line. The pin is driven at low level only.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
535
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.21 PIO Pull Up Disable Register
Name: PIO_PUDR
Address: 0x400E0E60 (PIOA), 0x400E1060 (PIOB), 0x400E1260 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Pull Up Disable.
0: No effect.
1: Disables the pull up resistor on the I/O line.
30.7.22 PIO Pull Up Enable Register
Name: PIO_PUER
Address: 0x400E0E64 (PIOA), 0x400E1064 (PIOB), 0x400E1264 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Pull Up Enable.
0: No effect.
1: Enables the pull up resistor on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
536
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.23 PIO Pull Up Status Register
Name: PIO_PUSR
Address: 0x400E0E68 (PIOA), 0x400E1068 (PIOB), 0x400E1268 (PIOC)
Access: Read-only
• P0-P31: Pull Up Status.
0: Pull Up resistor is enabled on the I/O line.
1: Pull Up resistor is disabled on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
537
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.24 PIO Peripheral ABCD Select Register 1
Name: PIO_ABCDSR1
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Peripheral Select.
If the same bit is set to 0 in PIO_ABCDSR2:
0: Assigns the I/O line to the Peripheral A function.
1: Assigns the I/O line to the Peripheral B function.
If the same bit is set to 1 in PIO_ABCDSR2:
0: Assigns the I/O line to the Peripheral C function.
1: Assigns the I/O line to the Peripheral D function.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
538
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.25 PIO Peripheral ABCD Select Register 2
Name: PIO_ABCDSR2
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Peripheral Select.
If the same bit is set to 0 in PIO_ABCDSR1:
0: Assigns the I/O line to the Peripheral A function.
1: Assigns the I/O line to the Peripheral C function.
If the same bit is set to 1 in PIO_ABCDSR1:
0: Assigns the I/O line to the Peripheral B function.
1: Assigns the I/O line to the Peripheral D function.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
539
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.26 PIO Input Filter Slow Clock Disable Register
Name: PIO_IFSCDR
Address: 0x400E0E80 (PIOA), 0x400E1080 (PIOB), 0x400E1280 (PIOC)
Access: Write-only
• P0-P31: PIO Clock Glitch Filtering Select.
0: No Effect.
1: The Glitch Filter is able to filter glitches with a duration < Tmck/2.
30.7.27 PIO Input Filter Slow Clock Enable Register
Name: PIO_IFSCER
Address: 0x400E0E84 (PIOA), 0x400E1084 (PIOB), 0x400E1284 (PIOC)
Access: Write-only
• P0-P31: Debouncing Filtering Select.
0: No Effect.
1: The Debouncing Filter is able to filter pulses with a duration < Tdiv_slclk/2.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
540
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.28 PIO Input Filter Slow Clock Status Register
Name: PIO_IFSCSR
Address: 0x400E0E88 (PIOA), 0x400E1088 (PIOB), 0x400E1288 (PIOC)
Access: Read-only
• P0-P31: Glitch or Debouncing Filter Selection Status
0: The Glitch Filter is able to filter glitches with a duration < Tmck2.
1: The Debouncing Filter is able to filter pulses with a duration < Tdiv_slclk/2.
30.7.29 PIO Slow Clock Divider Debouncing Register
Name: PIO_SCDR
Address: 0x400E0E8C (PIOA), 0x400E108C (PIOB), 0x400E128C (PIOC)
Access: Read-write
• DIVx: Slow Clock Divider Selection for Debouncing
Tdiv_slclk = 2*(DIV+1)*Tslow_clock.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–– DIV
76543210
DIV
541
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.30 PIO Pad Pull Down Disable Register
Name: PIO_PPDDR
Address: 0x400E0E90 (PIOA), 0x400E1090 (PIOB), 0x400E1290 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Pull Down Disable.
0: No effect.
1: Disables the pull down resistor on the I/O line.
30.7.31 PIO Pad Pull Down Enable Register
Name: PIO_PPDER
Address: 0x400E0E94 (PIOA), 0x400E1094 (PIOB), 0x400E1294 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Pull Down Enable.
0: No effect.
1: Enables the pull down resistor on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
542
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.32 PIO Pad Pull Down Status Register
Name: PIO_PPDSR
Address: 0x400E0E98 (PIOA), 0x400E1098 (PIOB), 0x400E1298 (PIOC)
Access: Read-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Pull Down Status.
0: Pull Down resistor is enabled on the I/O line.
1: Pull Down resistor is disabled on the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
543
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.33 PIO Output Write Enable Register
Name: PIO_OWER
Address: 0x400E0EA0 (PIOA), 0x400E10A0 (PIOB), 0x400E12A0 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Output Write Enable.
0: No effect.
1: Enables writing PIO_ODSR for the I/O line.
30.7.34 PIO Output Write Disable Register
Name: PIO_OWDR
Address: 0x400E0EA4 (PIOA), 0x400E10A4 (PIOB), 0x400E12A4 (PIOC)
Access: Write-only
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• P0-P31: Output Write Disable.
0: No effect.
1: Disables writing PIO_ODSR for the I/O line.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
544
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.35 PIO Output Write Status Register
Name: PIO_OWSR
Address: 0x400E0EA8 (PIOA), 0x400E10A8 (PIOB), 0x400E12A8 (PIOC)
Access: Read-only
• P0-P31: Output Write Status.
0: Writing PIO_ODSR does not affect the I/O line.
1: Writing PIO_ODSR affects the I/O line.
30.7.36 PIO Additional Interrupt Modes Enable Register
Name: PIO_AIMER
Address: 0x400E0EB0 (PIOA), 0x400E10B0 (PIOB), 0x400E12B0 (PIOC)
Access: Write-only
• P0-P31: Additional Interrupt Modes Enable.
0: No effect.
1: The interrupt source is the event described in PIO_ELSR and PIO_FRLHSR.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
545
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.37 PIO Additional Interrupt Modes Disable Register
Name: PIO_AIMDR
Address: 0x400E0EB4 (PIOA), 0x400E10B4 (PIOB), 0x400E12B4 (PIOC)
Access: Write-only
• P0-P31: Additional Interrupt Modes Disable.
0: No effect.
1: The interrupt mode is set to the default interrupt mode (Both Edge detection).
30.7.38 PIO Additional Interrupt Modes Mask Register
Name: PIO_AIMMR
Address: 0x400E0EB8 (PIOA), 0x400E10B8 (PIOB), 0x400E12B8 (PIOC)
Access: Read-only
• P0-P31: Peripheral CD Status.
0: The interrupt source is a Both Edge detection event
1: The interrupt source is described by the registers PIO_ELSR and PIO_FRLHSR
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
546
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.39 PIO Edge Select Register
Name: PIO_ESR
Address: 0x400E0EC0 (PIOA), 0x400E10C0 (PIOB), 0x400E12C0 (PIOC)
Access: Write-only
• P0-P31: Edge Interrupt Selection.
0: No effect.
1: The interrupt source is an Edge detection event.
30.7.40 PIO Level Select Register
Name: PIO_LSR
Address: 0x400E0EC4 (PIOA), 0x400E10C4 (PIOB), 0x400E12C4 (PIOC)
Access: Write-only
• P0-P31: Level Interrupt Selection.
0: No effect.
1: The interrupt source is a Level detection event.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
547
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.41 PIO Edge/Level Status Register
Name: PIO_ELSR
Address: 0x400E0EC8 (PIOA), 0x400E10C8 (PIOB), 0x400E12C8 (PIOC)
Access: Read-only
• P0-P31: Edge/Level Interrupt source selection.
0: The interrupt source is an Edge detection event.
1: The interrupt source is a Level detection event.
30.7.42 PIO Falling Edge/Low Level Select Register
Name: PIO_FELLSR
Address: 0x400E0ED0 (PIOA), 0x400E10D0 (PIOB), 0x400E12D0 (PIOC)
Access: Write-only
• P0-P31: Falling Edge/Low Level Interrupt Selection.
0: No effect.
1: The interrupt source is set to a Falling Edge detection or Low Level detection event, depending on PIO_ELSR.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
548
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.43 PIO Rising Edge/High Level Select Register
Name: PIO_REHLSR
Address: 0x400E0ED4 (PIOA), 0x400E10D4 (PIOB), 0x400E12D4 (PIOC)
Access: Write-only
• P0-P31: Rising Edge /High Level Interrupt Selection.
0: No effect.
1: The interrupt source is set to a Rising Edge detection or High Level detection event, depending on PIO_ELSR.
30.7.44 PIO Fall/Rise - Low/High Status Register
Name: PIO_FRLHSR
Address: 0x400E0ED8 (PIOA), 0x400E10D8 (PIOB), 0x400E12D8 (PIOC)
Access: Read-only
• P0-P31: Edge /Level Interrupt Source Selection.
0: The interrupt source is a Falling Edge detection (if PIO_ELSR = 0) or Low Level detection event (if PIO_ELSR = 1).
1: The interrupt source is a Rising Edge detection (if PIO_ELSR = 0) or High Level detection event (if PIO_ELSR = 1).
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
549
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.45 PIO Lock Status Register
Name: PIO_LOCKSR
Address: 0x400E0EE0 (PIOA), 0x400E10E0 (PIOB), 0x400E12E0 (PIOC)
Access: Read-only
• P0-P31: Lock Status.
0: The I/O line is not locked.
1: The I/O line is locked.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
550
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.46 PIO Write Protect Mode Register
Name: PIO_WPMR
Address: 0x400E0EE4 (PIOA), 0x400E10E4 (PIOB), 0x400E12E4 (PIOC)
Access: Read-write
Reset: See Table 30-3
For more information on Write Protection Registers, refer to Section 30.7 ”Parallel Input/Output Controller (PIO) User Interface”.
• WPEN: Write Protect Enable
0: Disables the Write Protect if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
1: Enables the Write Protect if WPKEY corresponds to 0x50494F (“PIO” in ASCII).
Protects the registers:
“PIO Enable Register” on page 525
“PIO Disable Register” on page 525
“PIO Output Enable Register” on page 526
“PIO Output Disable Register” on page 527
“PIO Input Filter Enable Register” on page 528
“PIO Input Filter Disable Register” on page 528
“PIO Multi-driver Enable Register” on page 533
“PIO Multi-driver Disable Register” on page 534
“PIO Pull Up Disable Register” on page 535
“PIO Pull Up Enable Register” on page 535
“PIO Peripheral ABCD Select Register 1” on page 537
“PIO Peripheral ABCD Select Register 2” on page 538
“PIO Output Write Enable Register” on page 543
“PIO Output Write Disable Register” on page 543
“PIO Pad Pull Down Disable Register” on page 541
“PIO Pad Pull Down Status Register” on page 542
“PIO Parallel Capture Mode Register” on page 553
• WPKEY: Write Protect KEY
Should be written at value 0x50494F (“PIO” in ASCII). Writing any other value in this field aborts the write operation of the WPEN
bit. Always reads as 0.
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––
WPEN
551
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.47 PIO Write Protect Status Register
Name: PIO_WPSR
Address: 0x400E0EE8 (PIOA), 0x400E10E8 (PIOB), 0x400E12E8 (PIOC)
Access: Read-only
Reset: See Table 30-3
• WPVS: Write Protect Violation Status
0: No Write Protect Violation has occurred since the last read of the PIO_WPSR register.
1: A Write Protect Violation has occurred since the last read of the PIO_WPSR register. If this violation is an unauthorized attempt
to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has
been attempted.
Note: Reading PIO_WPSR automatically clears all fields.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––
WPVS
552
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.48 PIO Schmitt Trigger Register
Name: PIO_SCHMITT
Address: 0x400E0F00 (PIOA), 0x400E1100 (PIOB), 0x400E1300 (PIOC)
Access: Read-write
Reset: See Table 30-3
• SCHMITTx [x=0..31]:
0: Schmitt Trigger is enabled.
1: Schmitt Trigger is disabled.
31 30 29 28 27 26 25 24
SCHMITT31 SCHMITT30 SCHMITT29 SCHMITT28 SCHMITT27 SCHMITT26 SCHMITT25 SCHMITT24
23 22 21 20 19 18 17 16
SCHMITT23 SCHMITT22 SCHMITT21 SCHMITT20 SCHMITT19 SCHMITT18 SCHMITT17 SCHMITT16
15 14 13 12 11 10 9 8
SCHMITT15 SCHMITT14 SCHMITT13 SCHMITT12 SCHMITT11 SCHMITT10 SCHMITT9 SCHMITT8
76543210
SCHMITT7 SCHMITT6 SCHMITT5 SCHMITT4 SCHMITT3 SCHMITT2 SCHMITT1 SCHMITT0
553
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.49 PIO Parallel Capture Mode Register
Name: PIO_PCMR
Address: 0x400E0F50 (PIOA), 0x400E1150 (PIOB), 0x400E1350 (PIOC)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “PIO Write Protect Mode Register” .
• PCEN: Parallel Capture Mode Enable
0: The parallel capture mode is disabled.
1: The parallel capture mode is enabled.
• DSIZE: Parallel Capture Mode Data Size
• ALWYS: Parallel Capture Mode Always Sampling
0: The parallel capture mode samples the data when both data enables are active.
1: The parallel capture mode samples the data whatever the data enables are.
• HALFS: Parallel Capture Mode Half Sampling
Independently from the ALWYS bit:
0: The parallel capture mode samples all the data.
1: The parallel capture mode samples the data only one time out of two.
• FRSTS: Parallel Capture Mode First Sample
This bit is useful only if the HALFS bit is set to 1. If data are numbered in the order that they are received with an index from 0 to n:
0: Only data with an even index are sampled.
1: Only data with an odd index are sampled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – FRSTS HALFS ALWYS –
76543210
– – DSIZE – – – PCEN
Value Name Description
0 BYTE The reception data in the PIO_PCRHR register is a BYTE (8-bit)
1 HALF-WORD The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit)
2 WORD The reception data in the PIO_PCRHR register is a WORD (32-bit)
3 - Reserved
554
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.50 PIO Parallel Capture Interrupt Enable Register
Name: PIO_PCIER
Address: 0x400E0F54 (PIOA), 0x400E1154 (PIOB), 0x400E1354 (PIOC)
Access: Write-only
• DRDY: Parallel Capture Mode Data Ready Interrupt Enable
• OVRE: Parallel Capture Mode Overrun Error Interrupt Enable
• ENDRX: End of Reception Transfer Interrupt Enable
• RXBUFF: Reception Buffer Full Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – RXBUFF ENDRX OVRE DRDY
555
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.51 PIO Parallel Capture Interrupt Disable Register
Name: PIO_PCIDR
Address: 0x400E0F58 (PIOA), 0x400E1158 (PIOB), 0x400E1358 (PIOC)
Access: Write-only
• DRDY: Parallel Capture Mode Data Ready Interrupt Disable
• OVRE: Parallel Capture Mode Overrun Error Interrupt Disable
• ENDRX: End of Reception Transfer Interrupt Disable
• RXBUFF: Reception Buffer Full Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – RXBUFF ENDRX OVRE DRDY
556
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.52 PIO Parallel Capture Interrupt Mask Register
Name: PIO_PCIMR
Address: 0x400E0F5C (PIOA), 0x400E115C (PIOB), 0x400E135C (PIOC)
Access: Read-only
• DRDY: Parallel Capture Mode Data Ready Interrupt Mask
• OVRE: Parallel Capture Mode Overrun Error Interrupt Mask
• ENDRX: End of Reception Transfer Interrupt Mask
• RXBUFF: Reception Buffer Full Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – RXBUFF ENDRX OVRE DRDY
557
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.53 PIO Parallel Capture Interrupt Status Register
Name: PIO_PCISR
Address: 0x400E0F60 (PIOA), 0x400E1160 (PIOB), 0x400E1360 (PIOC)
Access: Read-only
• DRDY: Parallel Capture Mode Data Ready
0: No new data is ready to be read since the last read of PIO_PCRHR.
1: A new data is ready to be read since the last read of PIO_PCRHR.
The DRDY flag is automatically reset when PIO_PCRHR is read or when the parallel capture mode is disabled.
• OVRE: Parallel Capture Mode Overrun Error.
0: No overrun error occurred since the last read of this register.
1: At least one overrun error occurred since the last read of this register.
The OVRE flag is automatically reset when this register is read or when the parallel capture mode is disabled.
• ENDRX: End of Reception Transfer.
0: The End of Transfer signal from the Reception PDC channel is inactive.
1: The End of Transfer signal from the Reception PDC channel is active.
• RXBUFF: Reception Buffer Full
0: The signal Buffer Full from the Reception PDC channel is inactive.
1: The signal Buffer Full from the Reception PDC channel is active.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – RXBUFF ENDRX OVRE DRDY
558
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
30.7.54 PIO Parallel Capture Reception Holding Register
Name: PIO_PCRHR
Address: 0x400E0F64 (PIOA), 0x400E1164 (PIOB), 0x400E1364 (PIOC)
Access: Read-only
• RDATA: Parallel Capture Mode Reception Data.
if DSIZE = 0 in PIO_PCMR, only the 8 LSBs of RDATA are useful.
if DSIZE = 1 in PIO_PCMR, only the 16 LSBs of RDATA are useful.
31 30 29 28 27 26 25 24
RDATA
23 22 21 20 19 18 17 16
RDATA
15 14 13 12 11 10 9 8
RDATA
76543210
RDATA
559
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
31. Synchronous Serial Controller (SSC)
31.1 Description
The Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports
many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short
Frame Sync, Long Frame Sync, etc.
The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter
each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the
Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync
signal.
The SSC high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit
rate data transfer without processor intervention.
Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following:
CODEC’s in master or slave mode
DAC through dedicated serial interface, particularly I2S
Magnetic card reader
31.2 Embedded Characteristics
Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master
or Slave Modes, I2S, TDM Buses, Magnetic Card Reader)
Contains an independent receiver and transmitter and a common clock divider
Offers configurable frame sync and data length
Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame
sync signal
Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
560
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
31.3 Block Diagram
Figure 31-1. Block Diagram
31.4 Application Block Diagram
Figure 31-2. Application Block Diagram
SSC Interface PIO
PDC
APB Bridge
MCK
System
Bus
Peripheral
Bus TF
TK
TD
RF
RK
RD
Interrupt Control
SSC Interrupt
PMC
Interrupt
Management
Power
Management Test
Management
SSC
Serial AUDIO
OS or RTOS Driver
Codec Frame
Management Line Interface
Time Slot
Management
561
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
31.5 Pin Name List
31.6 Product Dependencies
31.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC
peripheral mode.
Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the
SSC peripheral mode.
31.6.2 Power Management
The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller
(PMC), therefore the programmer must first configure the PMC to enable the SSC clock.
31.6.3 Interrupt
The SSC interface has an interrupt line connected to the interrupt controller. Handling interrupts requires programming
the interrupt controller before configuring the SSC.
All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked
SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading
the SSC interrupt status register.
Table 31-1. I/O Lines Description
Pin Name Pin Description Type
RF Receiver Frame Synchro Input/Output
RK Receiver Clock Input/Output
RD Receiver Data Input
TF Transmitter Frame Synchro Input/Output
TK Transmitter Clock Input/Output
TD Transmitter Data Output
Table 31-2. I/O Lines
Instance Signal I/O Line Peripheral
SSC RD PA18 A
SSC RF PA20 A
SSC RK PA19 A
SSC TD PA17 A
SSC TF PA15 A
SSC TK PA16 A
Table 31-3. Peripheral IDs
Instance ID
SSC 22
562
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
31.7 Functional Description
This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format,
Start, Transmitter, Receiver and Frame Sync.
The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to
use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by
programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter
and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows
the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the
master clock divided by 2.
Figure 31-3. SSC Functional Block Diagram
31.7.1 Clock Management
The transmitter clock can be generated by:
an external clock received on the TK I/O pad
the receiver clock
the internal clock divider
The receiver clock can be generated by:
an external clock received on the RK I/O pad
User
Interface
APB
MCK
Receive Clock
Controller
TXClock
RK Input
Clock Output
Controller
Frame Sync
Controller
Transmit Clock
Controller
Transmit ShiftRegister
St art
Select or
St art
Select or
Transmit Sync
Holding Register
Transmit Holding
Regi st er
RX clock
TXclock
TK Input
RD
RF
RK
Clock Output
Controller
Frame Sync
Controller
Recei ve Sh if t Regi st er
Receive Sync
Holding Register
Receive Hol di ng
Register
TD
TF
TK
RX Clock
Receiver
Transmitter
Data
Controller
TXEN
Data
Controller
RF
TF
RX St art
RXEN
RC0R
TXStart
Interrupt Control
To Interrupt Controller
Clock
Divider
RX St art
TXStart
563
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
the transmitter clock
the internal clock divider
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate
an external clock on the RK I/O pad.
This allows the SSC to support many Master and Slave Mode data transfers.
31.7.1.1Clock Divider
Figure 31-4. Divided Clock Block Diagram
The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in
the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to
both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains
inactive.
When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2
times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty
cycle for the Divided Clock regardless of whether the DIV value is even or odd.
Figure 31-5. Divided Clock Generation
31.7.1.2Transmitter Clock Management
The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O
pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock
can be inverted independently by the CKI bits in SSC_TCMR.
The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is
configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs.
Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO
field) might lead to unpredictable results.
MCK
Divided Clock
Clock Divider
/2 12-bit Counter
SSC_CMR
Master Clock
Divided Clock
DIV=1
Master Clock
Divided Clock
DIV=3
Divided Clock Frequency = MCK/2
Divided Clock Frequency = MCK/6
564
SAM4S [DATASHEET]
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Figure 31-6. Transmitter Clock Management
31.7.1.3Receiver Clock Management
The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O
pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can
be inverted independently by the CKI bits in SSC_RCMR.
The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is
configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs.
Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO
field) can lead to unpredictable results.
Figure 31-7. Receiver Clock Management
31.7.1.4Serial Clock Ratio Considerations
The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK
pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on
the RK pin is:
Master Clock divided by 2 if Receiver Frame Synchro is input
Master Clock divided by 3 if Receiver Frame Synchro is output
TK (pin)
Receiver
Clock
Divider
Clock
CKS
CKO Data Transfer
CKI CKG
Transmitter
Clock
Clock
Output
MUX Tri_state
Controller
Tri-state
Controller
INV
MUX
RK (pin)
Transmitter
Clock
Divider
Clock
CKS
CKO Data Transfer
CKI CKG
Receiver
Clock
Clock
Output
MUX Tri-state
Controller
Tri-state
Controller
INV
MUX
565
SAM4S [DATASHEET]
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In addition, the maximum clock speed allowed on the TK pin is:
Master Clock divided by 6 if Transmit Frame Synchro is input
Master Clock divided by 2 if Transmit Frame Synchro is output
31.7.2 Transmitter Operations
A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission.
The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 566.
The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on
page 567.
To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected
in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register
according to the data format selected.
When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When
the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and
additional data can be loaded in the holding register.
Figure 31-8. Transmitter Block Diagram
31.7.3 Receiver Operations
A received frame is triggered by a start event and can be followed by synchronization data before data transmission.
The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See “Start” on page 566.
The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on
page 567.
The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR.
The data is transferred from the shift register depending on the data format selected.
When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in
SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR
register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register.
Transmit Shift Register
TD
SSC_TFMR.FSLENSSC_TFMR.DATLEN
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
SSC_TFMR.DATNB
SSC_TFMR.DATDEF
SSC_TFMR.MSBF
SSC_TCMR.STTDLY = 0
SSC_TFMR.FSDEN 10
TX Controller
SSC_TCMR.START
RF
Start
Selector
TXEN
RX Start
TXEN
RF
Start
Selector
RXEN
RC0R
TX Start TX Start
Transmitter Clock
TX Controller counter reached STTDLY
SSC_RCMR.START
SSC_THR SSC_TSHR
SSC_CRTXEN
SSC_SRTXEN
SSC_CRTXDIS
566
SAM4S [DATASHEET]
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Figure 31-9. Receiver Block Diagram
31.7.4 Start
The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the
Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR.
Under the following conditions the start event is independently programmable:
Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts
as soon as the Receiver is enabled.
Synchronously with the transmitter/receiver
On detection of a falling/rising edge on TF/RF
On detection of a low level/high level on TF/RF
On detection of a level change or an edge on TF/RF
A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR).
Thus, the start could be on TF (Transmit) or RF (Receive).
Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions.
Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register
(TFMR/RFMR).
SSC_RFMR.MSBF
SSC_RFMR.DATNB
SSC_TCMR.START SSC_RCMR.START
SSC_RHRSSC_RSHR
SSC_RFMR.FSLEN SSC_RFMR.DATLEN
RX Controller counter reached STTDLY
RX Controller
RD
SSC_CR.RXEN
SSC_CR.RXDIS
SSC_SR.RXEN
Receiver Clock
RF
TXEN
RX Start
RF
RXEN
RC0R
SSC_RCMR.STTDLY = 0
Receive Shift Register
Start
Selector Start
Selector
RX Start
load load
567
SAM4S [DATASHEET]
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Figure 31-10.Transmit Start Mode
Figure 31-11.Receive Pulse/Edge Start Modes
31.7.5 Frame Sync
The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame
synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register
(SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform.
Programmable low or high levels during data transfer are supported.
Programmable high levels before the start of data transfers or toggling are also supported.
If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the
length of the pulse, from 1 bit time up to 256 bit time.
The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider
Selection (PERIOD) field in SSC_RCMR and SSC_TCMR.
X
TK
TF
(Input)
TD
(Output)
TD
(Output)
TD
(Output)
TD
(Output)
TD
(Output)
TD
(Output)
XBOB1
XBO B1
BO B1
BO B1
BO B1BO B1
BO B1B1
BO
X
X
X
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
Start = Falling Edge on TF
Start = Rising Edge onTF
Start = Low Level onTF
Start = High Level on TF
Start = Any Edge on TF
Start = Level Change on TF
X
RK
RF
(Input)
RD
(Input)
RD
(Input)
RD
(Input)
RD
(Input)
RD
(Input)
RD
(Input)
XBOB1
XBO B1
BO B1
BO B1
BO B1BO B1
BO B1B1
BO
X
X
X
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
Start = Falling Edge on RF
Start = Rising Edge on RF
Start = Low Level on RF
Start = High Level on RF
Start = Any Edge on RF
Start = Level Change on RF
568
SAM4S [DATASHEET]
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31.7.5.1Frame Sync Data
Frame Sync Data transmits or receives a specific tag during the Frame Sync signal.
During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding
Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be
sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and
has a maximum value of 16.
Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay
between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync
Holding Register through the Receive Shift Register.
The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in
SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual
data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is
transferred in the Transmit Register, then shifted out.
31.7.5.2Frame Sync Edge Detection
The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the
corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals
RF/TF).
31.7.6 Receive Compare Modes
Figure 31-12.Receive Compare Modes
31.7.6.1Compare Functions
Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined
by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the
comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new
sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this
start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0,
or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR.
31.7.7 Data Format
The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode
Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently
select:
the event that starts the data transfer (START)
the delay in number of bit periods between the start event and the first data bit (STTDLY)
the length of the data (DATLEN)
the number of data to be transferred for each start event (DATNB).
the length of synchronization transferred for each start event (FSLEN)
the bit sense: most or lowest significant bit first (MSBF)
CMP0 CMP3
CMP2
CMP1 Ignored B0 B2
B1
Start
RK
RD
(Input)
FSLEN
Up to 16 Bits
(4 in This Example)
STDLY DATLEN
569
SAM4S [DATASHEET]
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Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in
data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default
Value (DATDEF) bits in SSC_TFMR.
Figure 31-13.Transmit and Receive Frame Format in Edge/Pulse Start Modes
Note: 1. Example of input on falling edge of TF/RF.
Figure 31-14.Transmit Frame Format in Continuous Mode
Table 31-4. Data Frame Registers
Transmitter Receiver Field Length Comment
SSC_TFMR SSC_RFMR DATLEN Up to 32 Size of word
SSC_TFMR SSC_RFMR DATNB Up to 16 Number of words transmitted in frame
SSC_TFMR SSC_RFMR MSBF Most significant bit first
SSC_TFMR SSC_RFMR FSLEN Up to 16 Size of Synchro data register
SSC_TFMR DATDEF 0 or 1 Data default value ended
SSC_TFMR FSDEN Enable send SSC_TSHR
SSC_TCMR SSC_RCMR PERIOD Up to 512 Frame size
SSC_TCMR SSC_RCMR STTDLY Up to 255 Size of transmit start delay
Sync Data Default
STTDLY
Sync Data Ignored
RD
Default
Data
DATLEN
Data
Data
Data
DATLEN
Data
Data Default
Default
Ignored
Sync Data
Sync Data
FSLEN
TF/RF
(1)
Start
Start
From SSC_TSHR From SSC_THR
From SSC_THR
From SSC_THR
From SSC_THR
To SSC_RHR To SSC_RHRTo SSC_RSHR
TD
(If FSDEN = 0)
TD
(If FSDEN = 1)
DATNB
PERIOD
FromDATDEF FromDATDEF
From DATDEF From DATDEF
DATLEN
Data
DATLEN
Data Default
Start
From SSC_THR From SSC_THR
TD
Start: 1. TXEMPTY set to 1
2. Write into the SSC_THR
570
SAM4S [DATASHEET]
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Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmis-
sion. SyncData cannot be output in continuous mode.
Figure 31-15.Receive Frame Format in Continuous Mode
Note: 1. STTDLY is set to 0.
31.7.8 Loop Mode
The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode
(LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK.
31.7.9 Interrupt
Most bits in SSC_SR have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing
SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable,
respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask
Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the interrupt
controller.
Figure 31-16.Interrupt Block Diagram
Data
DATLEN
Data
DATLEN
Start = Enable Receiver
To SSC_RHR To SSC_RHR
RD
SSC_IMR
PDC
Interrupt
Control SSC Interrupt
Set
RXRDY
OVRUN
RXSYNC
Receiver
Transmitter
TXRDY
TXEMPTY
TXSYNC
TXBUFE
ENDTX
RXBUFF
ENDRX
Clear
SSC_IER SSC_IDR
571
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
31.8 SSC Application Examples
The SSC can support several serial communication modes used in audio or high speed serial links. Some standard
applications are shown in the following figures. All serial link applications supported by the SSC are not listed here.
Figure 31-17.Audio Application Block Diagram
Figure 31-18.Codec Application Block Diagram
SSC
RK
RF
RD
TD
TF
TK Clock SCK
Word Select WS
Data SD
I2S
RECEIVER
Clock SCK
Word Select WS
Data SD
Right Channel
Left Channel
MSB MSB
LSB
SSC
RK
RF
RD
TD
TF
TK Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data In
CODEC
Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data In
First Time Slot
Dstart Dend
572
SAM4S [DATASHEET]
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Figure 31-19.Time Slot Application Block Diagram
31.8.1 Write Protection Registers
To prevent any single software error that may corrupt SSC behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “SSC Write Protect Mode Register” (SSC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the SSC Write Protect Status Register
(US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the SSC Write Protect Mode Register (SSC_WPMR) with the appropriate access key,
WPKEY.
The protected registers are:
“SSC Clock Mode Register” on page 575
“SSC Receive Clock Mode Register” on page 576
“SSC Receive Frame Mode Register” on page 578
“SSC Transmit Clock Mode Register” on page 580
“SSC Transmit Frame Mode Register” on page 582
“SSC Receive Compare 0 Register” on page 586
“SSC Receive Compare 1 Register” on page 586
SSC
RK
RF
RD
TD
TF
TK SCLK
FSYNC
Data Out
Data in
CODEC
First
Time Slot
Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data in
CODEC
Second
Time Slot
First Time Slot Second Time Slot
Dstart Dend
573
SAM4S [DATASHEET]
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31.9 Synchronous Serial Controller (SSC) User Interface
Table 31-5. Register Mapping
Offset Register Name Access Reset
0x0 Control Register SSC_CR Write-only –
0x4 Clock Mode Register SSC_CMR Read-write 0x0
0x8 Reserved – – –
0xC Reserved – – –
0x10 Receive Clock Mode Register SSC_RCMR Read-write 0x0
0x14 Receive Frame Mode Register SSC_RFMR Read-write 0x0
0x18 Transmit Clock Mode Register SSC_TCMR Read-write 0x0
0x1C Transmit Frame Mode Register SSC_TFMR Read-write 0x0
0x20 Receive Holding Register SSC_RHR Read-only 0x0
0x24 Transmit Holding Register SSC_THR Write-only –
0x28 Reserved – – –
0x2C Reserved – – –
0x30 Receive Sync. Holding Register SSC_RSHR Read-only 0x0
0x34 Transmit Sync. Holding Register SSC_TSHR Read-write 0x0
0x38 Receive Compare 0 Register SSC_RC0R Read-write 0x0
0x3C Receive Compare 1 Register SSC_RC1R Read-write 0x0
0x40 Status Register SSC_SR Read-only 0x000000CC
0x44 Interrupt Enable Register SSC_IER Write-only –
0x48 Interrupt Disable Register SSC_IDR Write-only –
0x4C Interrupt Mask Register SSC_IMR Read-only 0x0
0xE4 Write Protect Mode Register SSC_WPMR Read-write 0x0
0xE8 Write Protect Status Register SSC_WPSR Read-only 0x0
0x50-0xFC Reserved – – –
0x100-0x128 Reserved for PDC registers. – – –
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31.9.1 SSC Control Register
Name: SSC_CR:
Address: 0x40004000
Access: Write-only
• RXEN: Receive Enable
0 = No effect.
1 = Enables Receive if RXDIS is not set.
• RXDIS: Receive Disable
0 = No effect.
1 = Disables Receive. If a character is currently being received, disables at end of current character reception.
• TXEN: Transmit Enable
0 = No effect.
1 = Enables Transmit if TXDIS is not set.
• TXDIS: Transmit Disable
0 = No effect.
1 = Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission.
• SWRST: Software Reset
0 = No effect.
1 = Performs a software reset. Has priority on any other bit in SSC_CR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
SWRST – – – – – TXDIS TXEN
76543210
– – – – – – RXDIS RXEN
575
SAM4S [DATASHEET]
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31.9.2 SSC Clock Mode Register
Name: SSC_CMR
Address: 0x40004004
Access: Read-write
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• DIV: Clock Divider
0 = The Clock Divider is not active.
Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The mini-
mum bit rate is MCK/2 x 4095 = MCK/8190.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––– DIV
76543210
DIV
576
SAM4S [DATASHEET]
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31.9.3 SSC Receive Clock Mode Register
Name: SSC_RCMR
Address: 0x40004010
Access: Read-write
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• CKS: Receive Clock Selection
• CKO: Receive Clock Output Mode Selection
• CKI: Receive Clock Inversion
0 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is
shifted out on Receive Clock rising edge.
1 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is
shifted out on Receive Clock falling edge.
CKI affects only the Receive Clock and not the output clock signal.
• CKG: Receive Clock Gating Selection
31 30 29 28 27 26 25 24
PERIOD
23 22 21 20 19 18 17 16
STTDLY
15 14 13 12 11 10 9 8
– – – STOP START
76543210
CKG CKI CKO CKS
Value Name Description
0 MCK Divided Clock
1TK TK Clock signal
2RK RK pin
Value Name Description
0 NONE None, RK pin is an input
1 CONTINUOUS Continuous Receive Clock, RK pin is an output
2 TRANSFER Receive Clock only during data transfers, RK pin is an output
Value Name Description
0 CONTINUOUS None
1 EN_RF_LOW Receive Clock enabled only if RF Pin is Low
2 EN_RF_HIGH Receive Clock enabled only if RF Pin is High
577
SAM4S [DATASHEET]
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• START: Receive Start Selection
• STOP: Receive Stop Selection
0 = After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a
new compare 0.
1 = After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• STTDLY: Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the
Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync
Data) reception.
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
Value Name Description
0 CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately
after the end of transfer of the previous data.
1 TRANSMIT Transmit start
2 RF_LOW Detection of a low level on RF signal
3 RF_HIGH Detection of a high level on RF signal
4 RF_FALLING Detection of a falling edge on RF signal
5 RF_RISING Detection of a rising edge on RF signal
6 RF_LEVEL Detection of any level change on RF signal
7 RF_EDGE Detection of any edge on RF signal
8 CMP_0 Compare 0
578
SAM4S [DATASHEET]
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31.9.4 SSC Receive Frame Mode Register
Name: SSC_RFMR
Address: 0x40004014
Access: Read-write
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• DATLEN: Data Length
0 = Forbidden value (1-bit data length not supported).
Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC
assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included),
half-words are transferred, and for any other value, 32-bit words are transferred.
• LOOP: Loop Mode
0 = Normal operating mode.
1 = RD is driven by TD, RF is driven by TF and TK drives RK.
• MSBF: Most Significant Bit First
0 = The lowest significant bit of the data register is sampled first in the bit stream.
1 = The most significant bit of the data register is sampled first in the bit stream.
• DATNB: Data Number per Frame
This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).
• FSLEN: Receive Frame Sync Length
This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the
START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Com-
pare 0 or Compare 1 register.
This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal.
Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Receive Clock periods.
31 30 29 28 27 26 25 24
FSLEN_EXT – – – FSEDGE
23 22 21 20 19 18 17 16
– FSOS FSLEN
15 14 13 12 11 10 9 8
–––– DATNB
76543210
MSBF – LOOP DATLEN
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SAM4S [DATASHEET]
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• FSOS: Receive Frame Sync Output Selection
• FSEDGE: Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
• FSLEN_EXT: FSLEN Field Extension
Extends FSLEN field. For details, refer to FSLEN bit description on page 578.
Value Name Description
0 NONE None, RF pin is an input
1 NEGATIVE Negative Pulse, RF pin is an output
2 POSITIVE Positive Pulse, RF pin is an output
3 LOW Driven Low during data transfer, RF pin is an output
4 HIGH Driven High during data transfer, RF pin is an output
5 TOGGLING Toggling at each start of data transfer, RF pin is an output
Value Name Description
0 POSITIVE Positive Edge Detection
1NEGATIVE Negative Edge Detection
580
SAM4S [DATASHEET]
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31.9.5 SSC Transmit Clock Mode Register
Name: SSC_TCMR
Address: 0x40004018
Access: Read-write
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• CKS: Transmit Clock Selection
• CKO: Transmit Clock Output Mode Selection
• CKI: Transmit Clock Inversion
0 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input
is sampled on Transmit clock rising edge.
1 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input
is sampled on Transmit clock falling edge.
CKI affects only the Transmit Clock and not the output clock signal.
• CKG: Transmit Clock Gating Selection
31 30 29 28 27 26 25 24
PERIOD
23 22 21 20 19 18 17 16
STTDLY
15 14 13 12 11 10 9 8
– – – – START
76543210
CKG CKI CKO CKS
Value Name Description
0 MCK Divided Clock
1RK RK Clock signal
2TK TK pin
Value Name Description
0 NONE None, TK pin is an input
1 CONTINUOUS Continuous Transmit Clock, TK pin is an output
2 TRANSFER Transmit Clock only during data transfers, TK pin is an output
Value Name Description
0 CONTINUOUS None
1 EN_TF_LOW Transmit Clock enabled only if TF pin is Low
2 EN_TF_HIGH Transmit Clock enabled only if TF pin is High
581
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• START: Transmit Start Selection
• STTDLY: Transmit Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of
data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied.
Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted
instead of the end of TAG.
• PERIOD: Transmit Period Divider Selection
This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is
generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.
Value Name Description
0 CONTINUOUS Continuous, as soon as a word is written in the SSC_THR
Register (if Transmit is enabled), and immediately after the
end of transfer of the previous data.
1 RECEIVE Receive start
2 TF_LOW Detection of a low level on TF signal
3 TF_HIGH Detection of a high level on TF signal
4 TF_FALLING Detection of a falling edge on TF signal
5 TF_RISING Detection of a rising edge on TF signal
6 TF_LEVEL Detection of any level change on TF signal
7 TF_EDGE Detection of any edge on TF signal
582
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
31.9.6 SSC Transmit Frame Mode Register
Name: SSC_TFMR
Address: 0x4000401C
Access: Read-write
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• DATLEN: Data Length
0 = Forbidden value (1-bit data length not supported).
Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC
assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15 (included),
half-words are transferred, and for any other value, 32-bit words are transferred.
• DATDEF: Data Default Value
This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO
Controller, the pin is enabled only if the SCC TD output is 1.
• MSBF: Most Significant Bit First
0 = The lowest significant bit of the data register is shifted out first in the bit stream.
1 = The most significant bit of the data register is shifted out first in the bit stream.
• DATNB: Data Number per frame
This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1).
• FSLEN: Transmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data
Register if FSDEN is 1.
This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal.
Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Transmit Clock period.
31 30 29 28 27 26 25 24
FSLEN_EXT – – – FSEDGE
23 22 21 20 19 18 17 16
FSDEN FSOS FSLEN
15 14 13 12 11 10 9 8
–––– DATNB
7654 3210
MSBF – DATDEF DATLEN
583
SAM4S [DATASHEET]
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• FSOS: Transmit Frame Sync Output Selection
• FSDEN: Frame Sync Data Enable
0 = The TD line is driven with the default value during the Transmit Frame Sync signal.
1 = SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
• FSEDGE: Frame Sync Edge Detection
Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
• FSLEN_EXT: FSLEN Field Extension
Extends FSLEN field. For details, refer to FSLEN bit description on page 582.
Value Name Description
0 NONE None, TF pin is an input
1 NEGATIVE Negative Pulse, TF pin is an output
2 POSITIVE Positive Pulse,TF pin is an output
3 LOW TF pin Driven Low during data transfer
4 HIGH TF pin Driven High during data transfer
5 TOGGLING TF pin Toggles at each start of data transfer
Value Name Description
0 POSITIVE Positive Edge Detection
1NEGATIVE Negative Edge Detection
584
SAM4S [DATASHEET]
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31.9.7 SSC Receive Holding Register
Name: SSC_RHR
Address: 0x40004020
Access: Read-only
• RDAT: Receive Data
Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
31.9.8 SSC Transmit Holding Register
Name: SSC_THR
Address: 0x40004024
Access: Write-only
• TDAT: Transmit Data
Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
31 30 29 28 27 26 25 24
RDAT
23 22 21 20 19 18 17 16
RDAT
15 14 13 12 11 10 9 8
RDAT
76543210
RDAT
31 30 29 28 27 26 25 24
TDAT
23 22 21 20 19 18 17 16
TDAT
15 14 13 12 11 10 9 8
TDAT
76543210
TDAT
585
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
31.9.9 SSC Receive Synchronization Holding Register
Name: SSC_RSHR
Address: 0x40004030
Access: Read-only
• RSDAT: Receive Synchronization Data
31.9.10 SSC Transmit Synchronization Holding Register
Name: SSC_TSHR
Address: 0x40004034
Access: Read-write
• TSDAT: Transmit Synchronization Data
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RSDAT
76543210
RSDAT
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TSDAT
76543210
TSDAT
586
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
31.9.11 SSC Receive Compare 0 Register
Name: SSC_RC0R
Address: 0x40004038
Access: Read-write
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• CP0: Receive Compare Data 0
31.9.12 SSC Receive Compare 1 Register
Name: SSC_RC1R
Address: 0x4000403C
Access: Read-write
This register can only be written if the WPEN bit is cleared in “SSC Write Protect Mode Register” .
• CP1: Receive Compare Data 1
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CP0
76543210
CP0
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CP1
76543210
CP1
587
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
31.9.13 SSC Status Register
Name: SSC_SR
Address: 0x40004040
Access: Read-only
• TXRDY: Transmit Ready
0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).
1 = SSC_THR is empty.
• TXEMPTY: Transmit Empty
0 = Data remains in SSC_THR or is currently transmitted from TSR.
1 = Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.
• ENDTX: End of Transmission
0 = The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.
1 = The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.
• TXBUFE: Transmit Buffer Empty
0 = SSC_TCR or SSC_TNCR have a value other than 0.
1 = Both SSC_TCR and SSC_TNCR have a value of 0.
• RXRDY: Receive Ready
0 = SSC_RHR is empty.
1 = Data has been received and loaded in SSC_RHR.
• OVRUN: Receive Overrun
0 = No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.
1 = Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.
• ENDRX: End of Reception
0 = Data is written on the Receive Counter Register or Receive Next Counter Register.
1 = End of PDC transfer when Receive Counter Register has arrived at zero.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – – – RXEN TXEN
15 14 13 12 11 10 9 8
– – – – RXSYN TXSYN CP1 CP0
76543210
RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY
588
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• RXBUFF: Receive Buffer Full
0 = SSC_RCR or SSC_RNCR have a value other than 0.
1 = Both SSC_RCR and SSC_RNCR have a value of 0.
• CP0: Compare 0
0 = A compare 0 has not occurred since the last read of the Status Register.
1 = A compare 0 has occurred since the last read of the Status Register.
• CP1: Compare 1
0 = A compare 1 has not occurred since the last read of the Status Register.
1 = A compare 1 has occurred since the last read of the Status Register.
• TXSYN: Transmit Sync
0 = A Tx Sync has not occurred since the last read of the Status Register.
1 = A Tx Sync has occurred since the last read of the Status Register.
• RXSYN: Receive Sync
0 = An Rx Sync has not occurred since the last read of the Status Register.
1 = An Rx Sync has occurred since the last read of the Status Register.
• TXEN: Transmit Enable
0 = Transmit is disabled.
1 = Transmit is enabled.
• RXEN: Receive Enable
0 = Receive is disabled.
1 = Receive is enabled.
589
SAM4S [DATASHEET]
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31.9.14 SSC Interrupt Enable Register
Name: SSC_IER
Address: 0x40004044
Access: Write-only
• TXRDY: Transmit Ready Interrupt Enable
0 = 0 = No effect.
1 = Enables the Transmit Ready Interrupt.
• TXEMPTY: Transmit Empty Interrupt Enable
0 = No effect.
1 = Enables the Transmit Empty Interrupt.
• ENDTX: End of Transmission Interrupt Enable
0 = No effect.
1 = Enables the End of Transmission Interrupt.
• TXBUFE: Transmit Buffer Empty Interrupt Enable
0 = No effect.
1 = Enables the Transmit Buffer Empty Interrupt
• RXRDY: Receive Ready Interrupt Enable
0 = No effect.
1 = Enables the Receive Ready Interrupt.
• OVRUN: Receive Overrun Interrupt Enable
0 = No effect.
1 = Enables the Receive Overrun Interrupt.
• ENDRX: End of Reception Interrupt Enable
0 = No effect.
1 = Enables the End of Reception Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – RXSYN TXSYN CP1 CP0
76543210
RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY
590
SAM4S [DATASHEET]
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• RXBUFF: Receive Buffer Full Interrupt Enable
0 = No effect.
1 = Enables the Receive Buffer Full Interrupt.
• CP0: Compare 0 Interrupt Enable
0 = No effect.
1 = Enables the Compare 0 Interrupt.
• CP1: Compare 1 Interrupt Enable
0 = No effect.
1 = Enables the Compare 1 Interrupt.
• TXSYN: Tx Sync Interrupt Enable
0 = No effect.
1 = Enables the Tx Sync Interrupt.
• RXSYN: Rx Sync Interrupt Enable
0 = No effect.
1 = Enables the Rx Sync Interrupt.
591
SAM4S [DATASHEET]
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31.9.15 SSC Interrupt Disable Register
Name: SSC_IDR
Address: 0x40004048
Access: Write-only
• TXRDY: Transmit Ready Interrupt Disable
0 = No effect.
1 = Disables the Transmit Ready Interrupt.
• TXEMPTY: Transmit Empty Interrupt Disable
0 = No effect.
1 = Disables the Transmit Empty Interrupt.
• ENDTX: End of Transmission Interrupt Disable
0 = No effect.
1 = Disables the End of Transmission Interrupt.
• TXBUFE: Transmit Buffer Empty Interrupt Disable
0 = No effect.
1 = Disables the Transmit Buffer Empty Interrupt.
• RXRDY: Receive Ready Interrupt Disable
0 = No effect.
1 = Disables the Receive Ready Interrupt.
• OVRUN: Receive Overrun Interrupt Disable
0 = No effect.
1 = Disables the Receive Overrun Interrupt.
• ENDRX: End of Reception Interrupt Disable
0 = No effect.
1 = Disables the End of Reception Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – RXSYN TXSYN CP1 CP0
76543210
RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY
592
SAM4S [DATASHEET]
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• RXBUFF: Receive Buffer Full Interrupt Disable
0 = No effect.
1 = Disables the Receive Buffer Full Interrupt.
• CP0: Compare 0 Interrupt Disable
0 = No effect.
1 = Disables the Compare 0 Interrupt.
• CP1: Compare 1 Interrupt Disable
0 = No effect.
1 = Disables the Compare 1 Interrupt.
• TXSYN: Tx Sync Interrupt Enable
0 = No effect.
1 = Disables the Tx Sync Interrupt.
• RXSYN: Rx Sync Interrupt Enable
0 = No effect.
1 = Disables the Rx Sync Interrupt.
593
SAM4S [DATASHEET]
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31.9.16 SSC Interrupt Mask Register
Name: SSC_IMR
Address: 0x4000404C
Access: Read-only
• TXRDY: Transmit Ready Interrupt Mask
0 = The Transmit Ready Interrupt is disabled.
1 = The Transmit Ready Interrupt is enabled.
• TXEMPTY: Transmit Empty Interrupt Mask
0 = The Transmit Empty Interrupt is disabled.
1 = The Transmit Empty Interrupt is enabled.
• ENDTX: End of Transmission Interrupt Mask
0 = The End of Transmission Interrupt is disabled.
1 = The End of Transmission Interrupt is enabled.
• TXBUFE: Transmit Buffer Empty Interrupt Mask
0 = The Transmit Buffer Empty Interrupt is disabled.
1 = The Transmit Buffer Empty Interrupt is enabled.
• RXRDY: Receive Ready Interrupt Mask
0 = The Receive Ready Interrupt is disabled.
1 = The Receive Ready Interrupt is enabled.
• OVRUN: Receive Overrun Interrupt Mask
0 = The Receive Overrun Interrupt is disabled.
1 = The Receive Overrun Interrupt is enabled.
• ENDRX: End of Reception Interrupt Mask
0 = The End of Reception Interrupt is disabled.
1 = The End of Reception Interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – RXSYN TXSYN CP1 CP0
76543210
RXBUFF ENDRX OVRUN RXRDY TXBUFE ENDTX TXEMPTY TXRDY
594
SAM4S [DATASHEET]
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• RXBUFF: Receive Buffer Full Interrupt Mask
0 = The Receive Buffer Full Interrupt is disabled.
1 = The Receive Buffer Full Interrupt is enabled.
• CP0: Compare 0 Interrupt Mask
0 = The Compare 0 Interrupt is disabled.
1 = The Compare 0 Interrupt is enabled.
• CP1: Compare 1 Interrupt Mask
0 = The Compare 1 Interrupt is disabled.
1 = The Compare 1 Interrupt is enabled.
• TXSYN: Tx Sync Interrupt Mask
0 = The Tx Sync Interrupt is disabled.
1 = The Tx Sync Interrupt is enabled.
• RXSYN: Rx Sync Interrupt Mask
0 = The Rx Sync Interrupt is disabled.
1 = The Rx Sync Interrupt is enabled.
595
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
31.9.17 SSC Write Protect Mode Register
Name: SSC_WPMR
Address: 0x400040E4
Access: Read-write
Reset: See Table 31-5
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x535343 (“SSC” in ASCII).
Protects the registers:
•“SSC Clock Mode Register” on page 575
•“SSC Receive Clock Mode Register” on page 576
•“SSC Receive Frame Mode Register” on page 578
•“SSC Transmit Clock Mode Register” on page 580
•“SSC Transmit Frame Mode Register” on page 582
•“SSC Receive Compare 0 Register” on page 586
•“SSC Receive Compare 1 Register” on page 586
• WPKEY: Write Protect KEY
Should be written at value 0x535343 (“SSC” in ASCII). Writing any other value in this field aborts the write operation of the WPEN
bit. Always reads as 0.
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
———————WPEN
596
SAM4S [DATASHEET]
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31.9.18 SSC Write Protect Status Register
Name: SSC_WPSR
Address: 0x400040E8
Access: Read-only
Reset: See Table 31-5
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the SSC_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the SSC_WPSR register. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has
been attempted.
Note: Reading SSC_WPSR automatically clears all fields.
31 30 29 28 27 26 25 24
————————
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
———————WPVS
597
SAM4S [DATASHEET]
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32. Serial Peripheral Interface (SPI)
32.1 Description
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external
devices in Master or Slave Mode. It also enables communication between processors if an external processor is
connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data
transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which
have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol
opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and
one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data
back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a
separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the
slave(s).
Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There
may be no more than one slave transmitting data during any particular transfer.
Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master
may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted.
Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
32.2 Embedded Characteristics
SPCK is asynchronous to bus/core clock in slave mode
Master Mode can run SPCK up to peripheral clock (bounded by maximum bus clock divided by 2)
Supports communication with serial external devices
Four chip selects with external decoder support allow communication with up to 15 peripherals
Serial memories, such as DataFlash® and 3-wire EEPROMs
Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors
External co-processors
Master or slave serial peripheral bus interface
8- to 16-bit programmable data length per chip select
Programmable phase and polarity per chip select
Programmable transfer delays between consecutive transfers and between clock and data per chip select
Programmable delay between consecutive transfers
Selectable mode fault detection
Connection to PDC channel capabilities optimizes data transfers
One channel for the receiver, one channel for the transmitter
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SAM4S [DATASHEET]
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32.3 Block Diagram
Figure 32-1. Block Diagram
32.4 Application Block Diagram
Figure 32-2. Application Block Diagram: Single Master/Multiple Slave Implementation
SPI Interface
Interrupt Control
PIO
PDC
PMC MCK
SPI Interrupt
SPCK
MISO
MOSI
NPCS0/NSS
NPCS1
NPCS2
NPCS3
APB
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
SPCK
MISO
MOSI
NSS
Slave 0
SPCK
MISO
MOSI
NSS
Slave 1
SPCK
MISO
MOSI
NSS
Slave 2
NC
NPCS3
599
SAM4S [DATASHEET]
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32.5 Signal Description
32.6 Product Dependencies
32.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiple xed with PIO lines. The programmer must
first program the PIO controllers to assign the SPI pins to their peripheral functions.
32.6.2 Power Management
The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the SPI clock.
Table 32-1. Signal Description
Pin Name Pin Description Type
Master Slave
MISO Master In Slave Out Input Output
MOSI Master Out Slave In Output Input
SPCK Serial Clock Output Input
NPCS1-NPCS3 Peripheral Chip Selects Output Unused
NPCS0/NSS Peripheral Chip Select/Slave Select Output Input
Table 32-2. I/O Lines
Instance Signal I/O Line Peripheral
SPI MISO PA12 A
SPI MOSI PA13 A
SPI NPCS0 PA11 A
SPI NPCS1 PA9 B
SPI NPCS1 PA31 A
SPI NPCS1 PB14 A
SPI NPCS1 PC4 B
SPI NPCS2 PA10 B
SPI NPCS2 PA30 B
SPI NPCS2 PB2 B
SPI NPCS3 PA3 B
SPI NPCS3 PA5 B
SPI NPCS3 PA22 B
SPI SPCK PA14 A
600
SAM4S [DATASHEET]
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32.6.3 Interrupt
The SPI interface has an interrupt line connected to the Interrupt Controller. Handling the SPI interrupt requires
programming the interrupt controller before configuring the SPI.
32.6.4 Peripheral DMA Controller (PDC)
The SPI interface can be used in conjunction with the PDC in order to reduce processor overhead. For a full description
of the PDC, refer to the corresponding section in the full datasheet.
32.7 Functional Description
32.7.1 Modes of Operation
The SPI operates in Master Mode or in Slave Mode.
Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3
are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line
driven as an output by the transmitter.
If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the
MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The
NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven
and can be used for other purposes.
The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only
in Master Mode.
32.7.2 Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL
bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine
the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states,
resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the
same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master
must reconfigure itself each time it needs to communicate with a different slave.
Table 32-4 shows the four modes and corresponding parameter settings.
Table 32-3. Peripheral IDs
Instance ID
SPI 21
Table 32-4. SPI Bus Protocol Mode
SPI Mode CPOL NCPHA Shift SPCK Edge Capture SPCK Edge SPCK Inactive Level
0 0 1 Falling Rising Low
1 0 0 Rising Falling Low
2 1 1 Rising Falling High
3 1 0 Falling Rising High
601
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 32-3 and Figure 32-4 show examples of data transfers.
Figure 32-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
Figure 32-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
6
*
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
MOSI
(from master)
MISO
(from slave)
NSS
(to slave)
SPCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
* Not defined, but normally MSB of previous character received.
1 2345 786
*
SPCK
(CPOL = 0)
SPCK
(CPOL = 1)
1 2345 7
MOSI
(from master)
MISO
(from slave)
NSS
(to slave)
SPCK cycle (for reference) 8
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
1
1
* Not defined but normally LSB of previous character transmitted.
2
2
6
602
SAM4S [DATASHEET]
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32.7.3 Master Mode Operations
When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate
generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip
select line to the slave and the serial clock signal (SPCK).
The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift
Register. The holding registers maintain the data flow at a constant rate.
After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The
written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift
Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Receiving data cannot
occur without transmitting data. If receiving mode is not needed, for example when communicating with a slave receiver
only (such as an LCD), the receive status flags in the status register can be discarded.
Before writing the TDR, the PCS field in the SPI_MR register must be set in order to select a slave.
After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The
written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift
Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot
occur without reception.
Before writing the TDR, the PCS field must be set in order to select a slave.
If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the
received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and
a new transfer starts.
The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data Register
Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used
to trigger the Transmit PDC channel.
The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is greater than
0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at
this time.
The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register
Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared.
If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES)
in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear
the OVRES bit.
Figure 32-5, shows a block diagram of the SPI when operating in Master Mode. Figure 32-6 on page 604 shows a flow
chart describing how transfers are handled.
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32.7.3.1Master Mode Block Diagram
Figure 32-5. Master Mode Block Diagram
Shift Register
SPCK
MOSI
LSB MSB
MISO
SPI_RDR RD
SPI
Clock
TDRE
SPI_TDR TD
RDRF
OVRES
SPI_CSR0..3
CPOL
NCPHA
BITS
MCK Baud Rate Generator
SPI_CSR0..3
SCBR
NPCS3
NPCS0
NPCS2
NPCS1
NPCS0
0
1
PS
SPI_MR PCS
SPI_TDR PCS
MODF
Current
Peripheral
SPI_RDR PCS
SPI_CSR0..3
CSAAT
PCSDEC
MODFDIS
MSTR
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32.7.3.2Master Mode Flow Diagram
Figure 32-6. Master Mode Flow Diagram
SPI Enable
CSAAT
PS
1
0
0
1
1
NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS)
Delay DLYBS
Serializer = SPI_TDR(TD)
TDRE = 1
Data Transfer
SPI_RDR(RD) = Serializer
RDRF = 1
TDRE
NPCS = 0xF
Delay DLYBCS
Fixed
peripheral
Variable
peripheral
Delay DLYBCT
0
1CSAAT
0
TDRE 1
0
PS 0
1
SPI_TDR(PCS)
= NPCS
no
yes SPI_MR(PCS)
= NPCS
no
NPCS = 0xF
Delay DLYBCS
NPCS = SPI_TDR(PCS)
NPCS = 0xF
Delay DLYBCS
NPCS = SPI_MR(PCS),
SPI_TDR(PCS)
Fixed
peripheral
Variable
peripheral
- NPCS defines the current Chip Select
- CSAAT, DLYBS, DLYBCT refer to the fields of the
Chip Select Register corresponding to the Current Chip Select
- When NPCS is 0xF, CSAAT is 0.
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Figure 32-7 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register
Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode
and no Peripheral Data Controller involved.
Figure 32-7. Status Register Flags Behavior
Figure 32-8 shows Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End of TX buffer (ENDTX),
RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags behavior within the SPI_SR (Status Register)
during an 8-bit data transfer in fixed mode with the Peripheral Data Controller involved. The PDC is programmed to
transfer and receive three data. The next pointer and counter are not used. The RDRF and TDRE are not shown
because these flags are managed by the PDC when using the PDC.
6
SPCK
MOSI
(from master)
MISO
(from slave)
NPCS0
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
1 2345 786
RDRF
TDRE
TXEMPTY
Write in
SPI_TDR
RDR read
shift register empty
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Figure 32-8. PDC Status Register Flags Behavior
32.7.3.3Clock Generation
The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255.
This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by
255.
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip
Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without
reprogramming.
32.7.3.4Transfer Delays
Figure 32-9 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be
programmed to modify the transfer waveforms:
The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the
Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one.
The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the
start of SPCK to be delayed after the chip select has been asserted.
The delay between consecutive transfers, independently programmable for each chip select by writing the
DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
MSB LSB654321
SPCK
MOSI
(from master)
NPCS0
MSB LSB654321
12 3
ENDTX
TXEMPTY
MSB LSB654321
MSB LSB654321
MISO
(from slave)
MSB LSB654321
MSB LSB654321
ENDRX
TXBUFE
RXBUFF
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Figure 32-9. Programmable Delays
32.7.3.5Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS
signals are high before and after each transfer.
Fixed Peripheral Select: SPI exchanges data with only one peripheral
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current
peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect.
Variable Peripheral Select: Data can be exchanged with more than one peripheral without having to reprogram the
NPCS field in the SPI_MR register.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current
peripheral. This means that the peripheral selection can be defined for each new data. The value to write in the SPI_TDR
register as the following format.
[xxxxxxx(7-bit) + LASTXFER(1-bit)(1)+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals to the chip select
to assert as defined in Section 32.8.4 (SPI Transmit Data Register) and LASTXFER bit at 0 or 1 depending on CSAAT
bit.
Note: 1. Optional.
CSAAT, LASTXFER and CSNAAT bits are discussed in Section 32.7.3.9 ”Peripheral Deselection with PDC” .
If LASTXFER is used, the command must be issued before writing the last character. Instead of LASTXFER, the user
can use the SPIDIS command. After the end of the PDC transfer, wait for the TXEMPTY flag, then write SPIDIS into the
SPI_CR register (this will not change the configuration register values); the NPCS will be deactivated after the last
character transfer. Then, another PDC transfer can be started if the SPIEN was previously written in the SPI_CR register.
32.7.3.6SPI Peripheral DMA Controller (PDC)
In both fixed and variable mode the Peripheral DMA Controller (PDC) can be used to reduce processor overhead.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as
the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral
selection requires the Mode Register to be reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode
Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is
destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and
LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO
and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the
buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the
processor.
DLYBCS DLYBS DLYBCT DLYBCT
Chip Select 1
Chip Select 2
SPCK
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Transfer Size
Depending on the data size to transmit, from 8 to 16 bits, the PDC manages automatically the type of pointer's size it has
to point to. The PDC will perform the following transfer size depending on the mode and number of bits per data.
Fixed Mode:
8-bit Data:
Byte transfer, PDC Pointer Address = Address + 1 byte,
PDC Counter = Counter - 1
8-bit to 16-bit Data:
2 bytes transfer. n-bit data transfer with don’t care data (MSB) filled with 0’s,
PDC Pointer Address = Address + 2 bytes,
PDC Counter = Counter - 1
Variable Mode:
In variable Mode, PDC Pointer Address = Address +4 bytes and PDC Counter = Counter - 1 for 8 to 16-bit transfer size.
When using the PDC, the TDRE and RDRF flags are handled by the PDC, thus the user’s application does not have to
check those bits. Only End of RX Buffer (ENDRX), End of TX Buffer (ENDTX), Buffer Full (RXBUFF), TX Buffer Empty
(TXBUFE) are significant. For further details about the Peripheral DMA Controller and user interface, refer to the PDC
section of the product datasheet.
32.7.3.7Peripheral Chip Select Decoding
The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to
NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writing the PCSDEC bit at 1 in the Mode
Register (SPI_MR).
When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one
NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven
low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field on NPCS lines of either the
Mode Register or the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any
transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the
characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded
peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible
peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. Figure 32-10 below shows such an
implementation.
If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must be disabled. This is not
needed for all other chip select lines since Mode Fault Detection is only on NPCS0.
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Figure 32-10.Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation
32.7.3.8Peripheral Deselection without PDC
During a transfer of more than one data on a Chip Select without thePDC, the SPI_TDR is loaded by the processor, the
flag TDRE rises as soon as the content of the SPI_TDR is transferred into the internal shift register. When this flag is
detected high, the SPI_TDR can be reloaded. If this reload by the processor occurs before the end of the current transfer
and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted
between the two transfers. But depending on the application software handling the SPI status register flags (by interrupt
or polling method) or servicing other interrupts or other tasks, the processor may not reload the SPI_TDR in time to keep
the chip select active (low). A null Delay Between Consecutive Transfer (DLYBCT) value in the SPI_CSR register, will
give even less time for the processor to reload the SPI_TDR. With some SPI slave peripherals, requiring the chip select
line to remain active (low) during a full set of transfers might lead to communication errors.
To facilitate interfacing with such devices, the Chip Select Register [CSR0...CSR3] can be programmed with the CSAAT
bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active)
until transfer to another chip select is required. Even if the SPI_TDR is not reloaded the chip select will remain active. To
have the chip select line to raise at the end of the transfer the Last transfer Bit (LASTXFER) in the SPI_MR register must
be set at 1 before writing the last data to transmit into the SPI_TDR.
32.7.3.9Peripheral Deselection with PDC
When the Peripheral DMA Controller is used, the chip select line will remain low during the whole transfer since the
TDRE flag is managed by the PDC itself. The reloading of the SPI_TDR by the PDC is done as soon as TDRE flag is set
to one. In this case the use of CSAAT bit might not be needed. However, it may happen that when other PDC channels
connected to other peripherals are in use as well, the SPI PDC might be delayed by another (PDC with a higher priority
on the bus). Having PDC buffers in slower memories like flash memory or SDRAM compared to fast internal SRAM, may
lengthen the reload time of the SPI_TDR by the PDC as well. This means that the SPI_TDR might not be reloaded in
time to keep the chip select line low. In this case the chip select line may toggle between data transfer and according to
some SPI Slave devices, the communication might get lost. The use of the CSAAT bit might be needed. When the
CSAAT bit is set at 0, the NPCS does not rise in all cases between two transfers on the same peripheral. During a
transfer on a Chip Select, the flag TDRE rises as soon as the content of the SPI_TDR is transferred into the internal
shifter. When this flag is detected the SPI_TDR can be reloaded. If this reload occurs before the end of the current
transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
SPCK
1-of-n Decoder/Demultiplexer
MISO MOSI
NSS
Slave 0
SPCK MISO MOSI
NSS
Slave 1
SPCK MISO MOSI
NSS
Slave 14
NPCS3
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asserted between the two transfers. This might lead to difficulties for interfacing with some serial peripherals requiring the
chip select to be de-asserted after each transfer. To facilitate interfacing with such devices, the Chip Select Register can
be programmed with the CSNAAT bit (Chip Select Not Active After Transfer) at 1. This allows to de-assert systematically
the chip select lines during a time DLYBCS. (The value of the CSNAAT bit is taken into account only if the CSAAT bit is
set at 0 for the same Chip Select).
Figure 32-11 shows different peripheral deselection cases and the effect of the CSAAT and CSNAAT bits.
Figure 32-11.Peripheral Deselection
A
NPCS[0..3]
Write SPI_TDR
TDRE
NPCS[0..3]
Write SPI_TDR
TDRE
NPCS[0..3]
Write SPI_TDR
TDRE
DLYBCS
PCS=A
DLYBCS
DLYBCT
A
PCS=B
B
DLYBCS
PCS=A
DLYBCS
DLYBCT
A
PCS=B
B
DLYBCS
DLYBCT
PCS=A
ADLYBCS
DLYBCT
A
PCS=A
AA
DLYBCT
AA
CSAAT = 0 and CSNAAT = 0
DLYBCT
AA
CSAAT = 1 and CSNAAT= 0 / 1
A
DLYBCS
PCS=A
DLYBCT
AA
CSAAT = 0 and CSNAAT = 1
NPCS[0..3]
Write SPI_TDR
TDRE
PCS=A
DLYBCT
AA
CSAAT = 0 and CSNAAT = 0
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32.7.3.10Mode Fault Detection
A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on
the NPCS0/NSS signal. In this case, multi-master configuration, NPCS0, MOSI, MISO and SPCK pins must be
configured in open drain (through the PIO controller). When a mode fault is detected, the MODF bit in the SPI_SR is set
until the SPI_SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR
(Control Register) at 1.
By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the
MODFDIS bit in the SPI Mode Register (SPI_MR).
32.7.4 SPI Slave Mode
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is
validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0
(SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL
bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI
is programmed in Slave Mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
(For more information on BITS field, see also, the (Note:) below the register table; Section 32.8.9 “SPI Chip Select
Register” on page 624.)
When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If
the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in
SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the
OVRES bit.
When a t ransfe r starts , the dat a shifte d out is the d ata pres ent in the S hift Re gister . If no data h as been wr itten in t he
Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last
reset, all bits are transmitted low, as the Shift Register resets at 0.
When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new
data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin.
When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises.
This enables frequent updates of critical variables with single transfers.
Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be
transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the
Shift Register is not modified and the last received character is retransmitted. In this case the Underrun Error Status Flag
(UNDES) is set in the SPI_SR.
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Figure 32-12 shows a block diagram of the SPI when operating in Slave Mode.
Figure 32-12.Slave Mode Functional Bloc Diagram
32.7.5 Write Protected Registers
To prevent any single software error that may corrupt SPI behavior, the registers listed below can be write-protected by
setting the WPEN bit in the SPI Write Protection Mode Register (SPI_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the SPI Write Protection Status Register
(SPI_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset after reading the SPI Write Protection Status Register (SPI_WPSR).
List of the write-protected registers:
Section 32.8.2 ”SPI Mode Register”
Section 32.8.9 ”SPI Chip Select Register”
Shift Register
SPCK
SPIENS
LSB MSB
NSS
MOSI
SPI_RDR RD
SPI
Clock
TDRE
SPI_TDR TD
RDRF
OVRES
SPI_CSR0
CPOL
NCPHA
BITS
SPIEN
SPIDIS
MISO
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32.8 Serial Peripheral Interface (SPI) User Interface
Table 32-5. Register Mapping
Offset Register Name Access Reset
0x00 Control Register SPI_CR Write-only ---
0x04 Mode Register SPI_MR Read-write 0x0
0x08 Receive Data Register SPI_RDR Read-only 0x0
0x0C Transmit Data Register SPI_TDR Write-only ---
0x10 Status Register SPI_SR Read-only 0x000000F0
0x14 Interrupt Enable Register SPI_IER Write-only ---
0x18 Interrupt Disable Register SPI_IDR Write-only ---
0x1C Interrupt Mask Register SPI_IMR Read-only 0x0
0x20 - 0x2C Reserved
0x30 Chip Select Register 0 SPI_CSR0 Read-write 0x0
0x34 Chip Select Register 1 SPI_CSR1 Read-write 0x0
0x38 Chip Select Register 2 SPI_CSR2 Read-write 0x0
0x3C Chip Select Register 3 SPI_CSR3 Read-write 0x0
0x4C - 0xE0 Reserved – – –
0xE4 Write Protection Control Register SPI_WPMR Read-write 0x0
0xE8 Write Protection Status Register SPI_WPSR Read-only 0x0
0x00E8 - 0x00F8 Reserved – – –
0x00FC Reserved – – –
0x100 - 0x124 Reserved for PDC Registers – – –
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32.8.1 SPI Control Register
Name: SPI_CR
Address: 0x40008000
Access: Write-only
• SPIEN: SPI Enable
0 = No effect.
1 = Enables the SPI to transfer and receive data.
• SPIDIS: SPI Disable
0 = No effect.
1 = Disables the SPI.
As soon as SPIDIS is set, SPI finishes its transfer.
All pins are set in input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the SPI is disabled.
If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.
• SWRST: SPI Software Reset
0 = No effect.
1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.
The SPI is in slave mode after software reset.
PDC channels are not affected by software reset.
• LASTXFER: Last Transfer
0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows
to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has
completed.
Refer to Section 32.7.3.5 ”Peripheral Selection” for more details.
31 30 29 28 27 26 25 24
–––––––LASTXFER
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SWRST–––––SPIDISSPIEN
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32.8.2 SPI Mode Register
Name: SPI_MR
Address: 0x40008004
Access: Read-write
This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”.
• MSTR: Master/Slave Mode
0 = SPI is in Slave mode.
1 = SPI is in Master mode.
• PS: Peripheral Select
0 = Fixed Peripheral Select.
1 = Variable Peripheral Select.
• PCSDEC: Chip Select Decode
0 = The chip selects are directly connected to a peripheral device.
1 = The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
• MODFDIS: Mode Fault Detection
0 = Mode fault detection is enabled.
1 = Mode fault detection is disabled.
• WDRBT: Wait Data Read Before Transfer
0 = No Effect. In master mode, a transfer can be initiated whatever the state of the Receive Data Register is.
1 = In Master Mode, a transfer can start only if the Receive Data Register is empty, i.e. does not contain any unread data. This
mode prevents overrun error in reception.
31 30 29 28 27 26 25 24
DLYBCS
23 22 21 20 19 18 17 16
–––– PCS
15 14 13 12 11 10 9 8
––––––––
76543210
LLB – WDRBT MODFDIS – PCSDEC PS MSTR
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• LLB: Local Loopback Enable
0 = Local loopback path disabled.
1 = Local loopback path enabled
LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.)
• PCS: Peripheral Chip Select
This field is only used if Fixed Peripheral Select is active (PS = 0).
If PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS.
• DLYBCS: Delay Between Chip Selects
This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlap-
ping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is less than or equal to six, six MCK periods will be inserted by default.
Otherwise, the following equation determines the delay:
Delay Between Chip Selects DLYBCS
MCK
-----------------------=
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32.8.3 SPI Receive Data Register
Name: SPI_RDR
Address: 0x40008008
Access: Read-only
• RD: Receive Data
Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
• PCS: Peripheral Chip Select
In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero.
Note: When using variable peripheral select mode (PS = 1 in SPI_MR) it is mandatory to also set the WDRBT field to 1 if the
SPI_RDR PCS field is to be processed.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––– PCS
15 14 13 12 11 10 9 8
RD
76543210
RD
618
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32.8.4 SPI Transmit Data Register
Name: SPI_TDR
Address: 0x4000800C
Access: Write-only
• TD: Transmit Data
Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit
data register in a right-justified format.
• PCS: Peripheral Chip Select
This field is only used if Variable Peripheral Select is active (PS = 1).
If PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS
• LASTXFER: Last Transfer
0 = No effect.
1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows
to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has
completed.
This field is only used if Variable Peripheral Select is active (PS = 1).
31 30 29 28 27 26 25 24
–––––––LASTXFER
23 22 21 20 19 18 17 16
–––– PCS
15 14 13 12 11 10 9 8
TD
76543210
TD
619
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32.8.5 SPI Status Register
Name: SPI_SR
Address: 0x40008010
Access: Read-only
• RDRF: Receive Data Register Full
0 = No data has been received since the last read of SPI_RDR
1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of
SPI_RDR.
• TDRE: Transmit Data Register Empty
0 = Data has been written to SPI_TDR and not yet transferred to the serializer.
1 = The last data written in the Transmit Data Register has been transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• MODF: Mode Fault Error
0 = No Mode Fault has been detected since the last read of SPI_SR.
1 = A Mode Fault occurred since the last read of the SPI_SR.
• OVRES: Overrun Error Status
0 = No overrun has been detected since the last read of SPI_SR.
1 = An overrun has occurred since the last read of SPI_SR.
An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR.
• ENDRX: End of RX buffer
0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).
1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1).
• ENDTX: End of TX buffer
0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).
1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1).
• RXBUFF: RX Buffer Full
0 = SPI_RCR(1) or SPI_RNCR(1) has a value other than 0.
1 = Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––SPIENS
15 14 13 12 11 10 9 8
–––––UNDES TXEMPTY NSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF
620
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• TXBUFE: TX Buffer Empty
0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0.
1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0.
• NSSR: NSS Rising
0 = No rising edge detected on NSS pin since last read.
1 = A rising edge occurred on NSS pin since last read.
• TXEMPTY: Transmission Registers Empty
0 = As soon as data is written in SPI_TDR.
1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such
delay.
• UNDES: Underrun Error Status (Slave Mode Only)
0 = No underrun has been detected since the last read of SPI_SR.
1 = A transfer begins whereas no data has been loaded in the Transmit Data Register.
• SPIENS: SPI Enable Status
0 = SPI is disabled.
1 = SPI is enabled.
Note: 1. SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC.
621
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32.8.6 SPI Interrupt Enable Register
Name: SPI_IER
Address: 0x40008014
Access: Write-only
0 = No effect.
1 = Enables the corresponding interrupt.
• RDRF: Receive Data Register Full Interrupt Enable
• TDRE: SPI Transmit Data Register Empty Interrupt Enable
• MODF: Mode Fault Error Interrupt Enable
• OVRES: Overrun Error Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
• NSSR: NSS Rising Interrupt Enable
• TXEMPTY: Transmission Registers Empty Enable
• UNDES: Underrun Error Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––UNDES TXEMPTY NSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF
622
SAM4S [DATASHEET]
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32.8.7 SPI Interrupt Disable Register
Name: SPI_IDR
Address: 0x40008018
Access: Write-only
0 = No effect.
1 = Disables the corresponding interrupt.
• RDRF: Receive Data Register Full Interrupt Disable
• TDRE: SPI Transmit Data Register Empty Interrupt Disable
• MODF: Mode Fault Error Interrupt Disable
• OVRES: Overrun Error Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
• NSSR: NSS Rising Interrupt Disable
• TXEMPTY: Transmission Registers Empty Disable
• UNDES: Underrun Error Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––UNDES TXEMPTY NSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF
623
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32.8.8 SPI Interrupt Mask Register
Name: SPI_IMR
Address: 0x4000801C
Access: Read-only
0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.
• RDRF: Receive Data Register Full Interrupt Mask
• TDRE: SPI Transmit Data Register Empty Interrupt Mask
• MODF: Mode Fault Error Interrupt Mask
• OVRES: Overrun Error Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
• NSSR: NSS Rising Interrupt Mask
• TXEMPTY: Transmission Registers Empty Mask
• UNDES: Underrun Error Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––UNDES TXEMPTY NSSR
76543210
TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF
624
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32.8.9 SPI Chip Select Register
Name: SPI_CSRx[x=0..3]
Address: 0x40008030
Access: Read/Write
This register can only be written if the WPEN bit is cleared in ”SPI Write Protection Mode Register”.
Note: SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with
the translated value unless the register is written.
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required
clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0 = The Peripheral Chip Select does not rise between two transfers if the SPI_TDR is reloaded before the end of the first transfer
and if the two transfers occur on the same Chip Select.
1 = The Peripheral Chip Select rises systematically after each transfer performed on the same slave. It remains active after the
end of transfer for a minimal duration of:
– (if DLYBCT field is different from 0)
– (if DLYBCT field equals 0)
• CSAAT: Chip Select Active After Transfer
0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested
on a different chip select.
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
76543210
BITS CSAAT CSNAAT NCPHA CPOL
DLYBCT
MCK
------------------------
DLYBCT 1+
MCK
----------------------------------
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• BITS: Bits Per Transfer
(See the (Note:) below the register table; Section 32.8.9 “SPI Chip Select Register” on page 624.)
The BITS field determines the number of data bits transferred. Reserved values should not be used.
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud
rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
Note: If one of the SCBR fields inSPI_CSRx is set to 1, the other SCBR fields in SPI_CSRx must be set to 1 as well, if they
are required to process transfers. If they are not used to transfer data, they can be set at any value.
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The
delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the char-
acter transfers.
Value Name Description
0 8_BIT 8 bits for transfer
1 9_BIT 9 bits for transfer
2 10_BIT 10 bits for transfer
3 11_BIT 11 bits for transfer
4 12_BIT 12 bits for transfer
5 13_BIT 13 bits for transfer
6 14_BIT 14 bits for transfer
7 15_BIT 15 bits for transfer
8 16_BIT 16 bits for transfer
9 – Reserved
10 – Reserved
11 – Reserved
12 – Reserved
13 – Reserved
14 – Reserved
15 – Reserved
SPCK Baudrate MCK
SCBR
---------------=
Delay Before SPCK DLYBS
MCK
-------------------=
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Otherwise, the following equation determines the delay:
Delay Between Consecutive Transfers 32 DLYBCT×MCK
-------------------------------------=
627
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32.8.10 SPI Write Protection Mode Register
Name: SPI_WPMR
Address: 0x400080E4
Access: Read-write
• WPEN: Write Protection Enable
0: The Write Protection is Disabled
1: The Write Protection is Enabled
• WPKEY: Write Protection Key Password
If a value is written in WPEN, the value is taken into account only if WPKEY is written with “SPI” (SPI written in ASCII Code, ie
0x535049 in hexadecimal).
List of the write-protected registers:
Section 32.8.2 ”SPI Mode Register”
Section 32.8.9 ”SPI Chip Select Register”
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
-------WPEN
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32.8.11 SPI Write Protection Status Register
Name: SPI_WPSR
Address: 0x400080E8
Access: Read-only
• WPVS: Write Protection Violation Status
0 = No Write Protect Violation has occurred since the last read of the SPI_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the SPI_WPSR register. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protection Violation Source
This Field indicates the APB Offset of the register concerned by the violation (SPI_MR or SPI_CSRx)
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––
WPVS
629
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33. Two-wire Interface (TWI)
33.1 Description
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and
one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with
any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot
Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master or a
slave with sequential or single-byte access. Multiple master capability is supported.
Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.
Below, Table 33-1 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full I2C compatible
device.
Note: 1. START + b000000001 + Ack + Sr
33.2 Embedded Characteristics
Master, Multi-Master and Slave Mode Operation
Compatibility with Atmel two-wire interface, serial memory and I2C compatible devices
One, two or three bytes for slave address
Sequential read/write operations
Bit Rate: Up to 400 kbit/s
General Call Supported in Slave Mode
Connecting to PDC channel capabilities optimizes data transfers in Master Mode only
One channel for the receiver, one channel for the transmitter
Next buffer support
Table 33-1. Atmel TWI compatibility with I2C Standard
I2C Standard Atmel TWI
Standard Mode Speed (100 kHz) Supported
Fast Mode Speed (400 kHz) Supported
7 or 10 bits Slave Addressing Supported
START BYTE(1) Not Supported
Repeated Start (Sr) Condition Supported
ACK and NACK Management Supported
Slope control and input filtering (Fast mode) Not Supported
Clock stretching Supported
Multi Master Capability Supported
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33.3 List of Abbreviations
33.4 Block Diagram
Figure 33-1. Block Diagram
Table 33-2. Abbreviations
Abbreviation Description
TWI Two-wire Interface
A Acknowledge
NA Non Acknowledge
P Stop
S Start
Sr Repeated Start
SADR Slave Address
ADR Any address except SADR
R Read
W Write
APB Bridge
PMC MCK
Two-wire
Interface
PIO
AIC
TWI
Interrupt
TWCK
TWD
APB Bridge
PMC MCK
Two-wire
Interface
PIO
Interrupt
Controller
TWI
Interrupt
TWCK
TWD
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33.5 Application Block Diagram
Figure 33-2. Application Block Diagram
33.5.1 I/O Lines Description
33.6 Product Dependencies
33.6.1 I/O Lines
Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up
resistor (see Figure 33-2 on page 631). When the bus is free, both lines are high. The output stages of devices
connected to the bus must have an open-drain or open-collector to perform the wired-AND function.
TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following
step:
Program the PIO controller to dedicate TWD and TWCK as peripheral lines.
The user must not program TWD and TWCK as open-drain. It is already done by the hardware.
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
Serial EEPROM ICRTC ICLCD
Controller
Slave 1 Slave 2 Slave 3
VDD
ICTemp.
Sensor
Slave 4
Rp: Pull up value as given by the I C Standard
Rp Rp
Table 33-3. I/O Lines Description
Pin Name Pin Description Type
TWD Two-wire Serial Data Input/Output
TWCK Two-wire Serial Clock Input/Output
Table 33-4. I/O Lines
Instance Signal I/O Line Peripheral
TWI0 TWCK0 PA4 A
TWI0 TWD0 PA3 A
TWI1 TWCK1 PB5 A
TWI1 TWD1 PB4 A
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33.6.2 Power Management
Enable the peripheral clock.
The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first
configure the PMC to enable the TWI clock.
33.6.3 Interrupt
The TWI interface has an interrupt line connected to the Interrupt Controller. In order to handle interrupts, the Interrupt
Controller must be programmed before configuring the TWI.
33.7 Functional Description
33.7.1 Transfer Format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an
acknowledgement. The number of bytes per transfer is unlimited (see Figure 33-4).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure 33-3).
A high-to-low transition on the TWD line while TWCK is high defines the START condition.
A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 33-3. START and STOP Conditions
Figure 33-4. Transfer Format
Table 33-5. Peripheral IDs
Instance ID
TWI0 19
TWI1 20
TWD
TWCK
Start Stop
TWD
TWCK
Start Address R/W Ack Data Ack Data Ack Stop
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33.7.2 Modes of Operation
The TWI has different modes of operations:
Master transmitter mode
Master receiver mode
Multi-master transmitter mode
Multi-master receiver mode
Slave transmitter mode
Slave receiver mode
These modes are described in the following chapters.
33.8 Master Mode
33.8.1 Definition
The Master is the device that starts a transfer, generates a clock and stops it.
33.8.2 Application Block Diagram
Figure 33-5. Master Mode Typical Application Block Diagram
33.8.3 Programming Master Mode
The following registers have to be programmed before entering Master mode:
1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to access slave devices in
read or write mode.
2. CKDIV + CHDIV + CLDIV: Clock Waveform.
3. SVDIS: Disable the slave mode.
4. MSEN: Enable the master mode.
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
Serial EEPROM ICRTC ICLCD
Controller
Slave 1 Slave 2 Slave 3
VDD
ICTemp.
Sensor
Slave 4
Rp: Pull up value as given by the I C Standard
Rp Rp
634
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33.8.4 Master Transmitter Mode
After the master initiates a Start condition when writing into the Transmit Holding Register, TWI_THR, it sends a 7-bit
slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following
the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR).
The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse),
the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The
master polls th e data line durin g this clock pulse a nd sets the Not Ack nowledge bit (NAC K) in the status register if the
slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the
interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in the TWI_THR, is then shifted
in the i nterna l shifte r and tran sferre d. When an a cknow ledge is d etecte d, the TXR DY bit is se t until a ne w write in t he
TWI_THR.
TXRDY is used as Transmit Ready for the PDC transmit channel.
While no new data is written in the TWI_THR, the Serial Clock Line is tied low. When new data is written in the TWI_THR,
the SCL is released and the data is sent. To generate a STOP event, the STOP command must be performed by writing
in the STOP field of TWI_CR.
After a Master Write transfer, the Serial Clock line is stretched (tied low) while no new data is written in the TWI_THR or
until a STOP command is performed.
See Figure 33-6, Figure 33-7, and Figure 33-8.
Figure 33-6. Master Write with One Data Byte
TXCOMP
TXRDY
Write THR (DATA)
STOP Command sent (write in TWI_CR)
TWD A DATA ASDADRW P
635
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Figure 33-7. Master Write with Multiple Data Bytes
Figure 33-8. Master Write with One Byte Internal Address and Multiple Data Bytes
A DATA n AS DADR W DATA n+1 A PDATA n+2 A
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1) Write THR (Data n+2)
Last data sent
STOP command performed
(by writing in the TWI_CR)
TWD
TWCK
A DATA n AS DADR W DATA n+1 A PDATA n+2 A
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1) Write THR (Data n+2)
Last data sent
STOP command performed
(by writing in the TWI_CR)
TWD IADR A
TWCK
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33.8.5 Master Receiver Mode
The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit
slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case
(MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH),
enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the
master sends an acknowledge condition to notify the slave that the data has been received except for the last data, after
the stop condition. See Figure 33-9. When the RXRDY bit is set in the status register, a character has been received in
the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be
set a t the sam e time. S ee Figure 33-9. When a multiple data byte read is performed, with or without internal address
(IADR), the STOP bit must be set after the next-to-last data received. See Figure 33-10. For Internal Address usage see
Section 33.8.6.
Figure 33-9. Master Read with One Data Byte
Figure 33-10.Master Read with Multiple Data Bytes
RXRDY is used as Receive Ready for the PDC receive channel.
AS DADR R DATA N P
TXCOMP
Write START
STOP Bit
RXRDY
Read RHR
TWD
N
AS DADR R DATA n A ADATA (n+1) A DATA (n+m)DATA (n+m)-1 PTWD
TXCOMP
Write START Bit
RXRDY
WriteSTOPBit
after next-to-last data read
Read RHR
DATA n Read RHR
DATA (n+1) Read RHR
DATA (n+m)-1 Read RHR
DATA (n+m)
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33.8.6 Internal Address
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave
address devices.
33.8.6.17-bit Slave Addressing
When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write)
accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. When
performing read operations with an internal address, the TWI performs a write operation to set the internal address into
the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR)
is sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 33-12. See Figure 33-11 and Figure
33-13 for Master Write operation with internal address.
The three internal address bytes are configurable through the Master Mode register (TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to 0.
In the figures below the following abbreviations are used:
Figure 33-11.Master Write with One, Two or Three Bytes Internal Address and One Data Byte
SStart
Sr Repeated Start
PStop
WWrite
RRead
AAcknowledge
NNot Acknowledge
DADR Device Address
IADR Internal Address
S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P
S DADR W A IADR(15:8) A IADR(7:0) A P
DATA A
A IADR(7:0) A P
DATA AS DADR W
TWD Three bytes internal address
Two bytes internal address
One byte internal address
TWD
TWD
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Figure 33-12.Master Read with One, Two or Three Bytes Internal Address and One Data Byte
33.8.6.210-bit Slave Addressing
For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave
address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and
IADR[23:16] can be used the same as in 7-bit Slave Addressing.
Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
1. Program IADRSZ = 1,
2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address)
Figure 33-13 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal
addresses to access the device.
Figure 33-13. Internal Address Usage
33.8.7 Using the Peripheral DMA Controller (PDC)
The use of the PDC significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequences:
33.8.7.1Data Transmit with the PDC
1. Initialize the transmit PDC (memory pointers, transfer size).
2. Configure the master mode.
3. Start the transfer by setting the PDC TXTEN bit.
4. Wait for the PDC ENDTX Flag either by using the polling method or ENDTX interrupt.
5. Disable the PDC by setting the PDC TXDIS bit.
S DADR WA IADR(23:16) A IADR(15:8) AIADR(7:0) A
S DADR W A IADR(15:8) A IADR(7:0) A
AIADR(7:0) A
S DADR W
DATA N P
Sr DADR R A
Sr DADR R A DATA N P
Sr DADR RA DATA NP
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
S
T
A
R
T
M
S
B
Device
Address
0
L
S
B
R
/
W
A
C
K
M
S
B
W
R
I
T
E
A
C
K
A
C
K
L
S
B
A
C
K
FIRST
WORD ADDRESS SECOND
WORD ADDRESS DATA
S
T
O
P
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SAM4S [DATASHEET]
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33.8.7.2Data Receive with the PDC
The PDC transfer size must be defined with the buffer size minus 2. The two remaining characters must be managed
without PDC to ensure that the exact number of bytes are received whatever the system bus latency conditions
encountered during the end of buffer transfer period.
1. Initialize the receive PDC (memory pointers, transfer size - 2).
2. Configure the master mode (DADR, CKDIV, etc.).
3. Start the transfer by setting the PDC RXTEN bit.
4. Wait for the PDC ENDRX Flag either by using polling method or ENDRX interrupt.
5. Disable the PDC by setting the PDC RXDIS bit.
6. Wait for the RXRDY flag in TWI_SR register
7. Set the STOP command in TWI_CR
8. Read the penultimate character in TWI_RHR
9. Wait for the RXRDY flag in TWI_SR register
10. Read the last character in TWI_RHR
33.8.8 SMBUS Quick Command (Master Mode Only)
The TWI interface can perform a Quick Command:
1. Configure the master mode (DADR, CKDIV, etc.).
2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to be sent.
3. Start the transfer by setting the QUICK bit in the TWI_CR.
Figure 33-14.SMBUS Quick Command
33.8.9 Read-write Flowcharts
The following flowcharts shown in Figure 33-16 on page 641, Figure 33-17 on page 642, Figure 33-18 on page 643,
Figure 33-19 on page 644 and Figure 33-20 on page 645 give examples for read and write operations. A polling or
interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register
(TWI_IER) be configured first.
TXCOMP
TXRDY
Write QUICK command in TWI_CR
TWD AS DADR R/W P
640
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Figure 33-15.TWI Write Operation with Single Data Byte without Internal Address
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Transfer direction bit
Write ==> bit MREAD = 0
Load Transmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1
Read Status register
TXCOMP = 1
Transfer finished
Yes
Yes
BEGIN
No
No
Write STOP Command
TWI_CR = STOP
641
SAM4S [DATASHEET]
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Figure 33-16.TWI Write Operation with Single Data Byte and Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address (DADR)
- Internal address size (IADRSZ)
- Transfer direction bit
Write ==> bit MREAD = 0
Load transmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1
Read Status register
TXCOMP = 1
Transfer finished
Set the internal address
TWI_IADR = address
Yes
Yes
No
No
Write STOP command
TWI_CR = STOP
642
SAM4S [DATASHEET]
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Figure 33-17.TWI Write Operation with Multiple Data Bytes with or without Internal Address
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Write ==> bit MREAD = 0
Internal address size = 0
Load Transmit register
TWI_THR=Datatosend
Read Status register
TXRDY = 1
Data to send
Read Status register
TXCOMP = 1
END
BEGIN
Set the internal address
TWI_IADR = address
Yes
TWI_THR = data to send
Yes
Yes
Yes
No
No
No
Write STOP Command
TWI_CR = STOP
Set TWI clock
(CLDIV, CHDIV, CKDIV) inTWI_CWGR
(Needed only once)
643
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Figure 33-18.TWI Read Operation with Single Data Byte without Internal Address
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Transfer direction bit
Read ==> bit MREAD = 1
Start the transfer
TWI_CR = START STOP
Read status register
RXRDY = 1
Read Status register
TXCOMP = 1
END
BEGIN
Yes
Yes
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Read Receive Holding Register
No
No
644
SAM4S [DATASHEET]
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Figure 33-19.TWI Read Operation with Single Data Byte and Internal Address
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (IADRSZ)
- Transfer direction bit
Read ==> bit MREAD = 1
Read Status register
TXCOMP = 1
END
BEGIN
Yes
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Yes
Set the internal address
TWI_IADR = address
Start the transfer
TWI_CR = START STOP
Read Status register
RXRDY = 1
Read Receive Holding register
No
No
645
SAM4S [DATASHEET]
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Figure 33-20.TWI Read Operation with Multiple Data Bytes with or without Internal Address
Internal address size = 0
Start the transfer
TWI_CR = START
Stop the transfer
TWI_CR = STOP
Read Status register
RXRDY = 1
Last data to read
but one
Read status register
TXCOMP = 1
END
Set the internal address
TWI_IADR = address
Yes
Yes
Yes
No
Yes
Read Receive Holding register (TWI_RHR)
No
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Read ==> bit MREAD = 1
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
No
Read Status register
RXRDY = 1
Yes
Read Receive Holding register (TWI_RHR)
No
646
SAM4S [DATASHEET]
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33.9 Multi-master Mode
33.9.1 Definition
More than one master may handle the bus at the same time without data corruption by using arbitration.
Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is
lost) for the master that intends to send a logical one while the other master sends a logical zero.
As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the
stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration.
Arbitration is illustrated in Figure 33-22 on page 647.
33.9.2 Different Multi-master Modes
Two multi-master modes may be distinguished:
1. TWI is considered as a Master only and will never be addressed.
2. TWI may be either a Master or a Slave and may be addressed.
Note: In both Multi-master modes arbitration is supported.
33.9.2.1TWI as Master Only
In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with the
ARBLST (ARBitration Lost) flag in addition.
If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer.
If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically waits
for a STOP condition on the bus to initiate the transfer (see Figure 33-21 on page 647).
Note: The state of the bus (busy or free) is not indicated in the user interface.
33.9.2.2TWI as Master or Slave
The automatic reversal from Master to Slave is not supported in case of a lost arbitration.
Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multi-master
mode described in the steps below.
1. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if TWI is addressed).
2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1.
3. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR).
4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the bus is
considered as free, TWI initiates the transfer.
5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the
user must monitor the ARBLST flag.
6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case where the
Master that won the arbitration wanted to access the TWI.
7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode.
Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is pro-
grammed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR.
647
SAM4S [DATASHEET]
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Figure 33-21.Programmer Sends Data While the Bus is Busy
Figure 33-22.Arbitration Cases
TWCK
TWD DATA sent by a master
STOP sent by the master START sent by the TWI
DATA sent by the TWI
Bus is busy
Bus is free
A transfer is programmed
(DADR + W + START + WriteTHR) Transfer is initiated
TWI DATA transfer Transfer is kept
Bus is considered as free
TWCK
Busisbusy Bus is free
A transfer is programmed
(DADR + W + START + Write THR) Transfer is initiated
TWI DATA transfer Transfer is kept
Bus is considered as free
Data from a Master
Data from TWI S0
S 0 0
1
1
1
ARBLST
S0
S 0 0
1
1
1
TWD S 0 0
1
11
11
Arbitration is lost
TWI stops sending data
P
S0
1
P0
11
11
Data from the master Data from the TWI
Arbitration is lost
The master stops sending data
Transfer is stopped Transfer is programmed again
(DADR + W + START + Write THR)
TWCK
TWD
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SAM4S [DATASHEET]
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The flowchart shown in Figure 33-23 on page 648 gives an example of read and write operations in Multi-master mode.
Figure 33-23.Multi-master Flowchart
Programm the SLAVE mode:
SADR + MSDIS + SVEN
SVACC=1
TXCOMP = 1
GACC = 1
Decoding of the
programming sequence
Prog seq
OK
Change SADR
SVREAD = 1
Read Status Register
RXRDY= 1
Read TWI_RHR
TXRDY= 1
EOSACC = 1
Write in TWI_THR
Need to perform
a master access
Program the Master mode
DADR + SVDIS + MSEN + CLK+R/W
Read Status Register
ARBLST = 1
MREAD = 1
TXRDY= 0
Write in TWI_THR
Data to send
RXRDY= 0
Read TWI_RHR Data to read
Read Status Register
TXCOMP = 0
GENERAL CALL TREATMENT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Stop Transfer
TWI_CR = STOP
No
No No
No
No
No
No
No
No
No
No
No
No
No No
No
START
649
SAM4S [DATASHEET]
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33.10 Slave Mode
33.10.1 Definition
The Slave Mode is defined as a mode where the device receives the clock and the address from another device called
the master.
In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP
conditions are always provided by the master).
33.10.2 Application Block Diagram
Figure 33-24.Slave Mode Typical Application Block Diagram
33.10.3 Programming Slave Mode
The following fields must be programmed before entering Slave mode:
1. SADR (TWI_SMR): The slave device address is used in order to be accessed by master devices in read or write
mode.
2. MSDIS (TWI_CR): Disable the master mode.
3. SVEN (TWI_CR): Enable the slave mode.
As the device receives the clock, values written in TWI_CWGR are not taken into account.
33.10.4 Receiving Data
After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave
address programmed in the SADR (Slave ADdress) field, SVACC (Slave ACCess) flag is set and SVREAD (S lave
READ) indicates the direction of the transfer.
SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected,
EOSACC (End Of Slave ACCess) flag is set.
33.10.4.1Read Sequence
In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR (TWI Transmit Holding
Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the
end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset.
As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when
the shift register is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set.
Note that a STOP or a repeated START always follows a NACK.
See Figure 33-25 on page 650.
Host with
TWI
Interface
TWD
TWCK
LCD Controller
Slave 1 Slave 2 Slave 3
RR
VDD
Host with TWI
Interface Host with TWI
Interface
Master
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33.10.4.2Write Sequence
In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a
character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the
TWI_RHR.
TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is
detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset.
See Figure 33-26 on page 651.
33.10.4.3Clock Synchronization Sequence
In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization.
Clock stretching information is given by the SCLWS (Clock Wait state) bit.
See Figure 33-28 on page 652 and Figure 33-29 on page 653.
33.10.4.4General Call
In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set.
After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new
address programming sequence.
See Figure 33-27 on page 651.
33.10.5 Data Transfer
33.10.5.1Read Operation
The read mode is defined as a data requirement from the master.
After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address
(SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer.
Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
Figure 33-25 on page 650 describes the write operation.
Figure 33-25.Read Access Ordered by a MASTER
Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been
acknowledged or non acknowledged.
Write THR Read RHR
SVREAD has to be taken into account only while SVACC is active
TWD
TXRDY
NACK
SVACC
SVREAD
EOSVACC
SADRS ADR R NA R A DATA A A DATA NA S/SrDATA NA P/S/Sr
SADR matches,
TWI answers with an ACK
SADR does not match,
TWI answers with a NACK ACK/NACK from the Master
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33.10.5.2Write Operation
The write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is
set and SVREAD indicates the direction of the transfer (SVREAD is low in this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
Figure 33-26 on page 651 describes the Write operation.
Figure 33-26.Write Access Ordered by a Master
Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is
read.
33.10.5.3General Call
The general call is performed in order to change the address of the slave.
If a GENERAL CALL is detected, GACC is set.
After the detection of General Call, it is up to the programmer to decode the commands which come afterwards.
In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if
the programming sequence matches.
Figure 33-27 on page 651 describes the General Call access.
Figure 33-27.Master Performs a General Call
Note: This method allows the user to create an own programming sequence by choosing the programming bytes and
the number of them. The programming sequence has to be provided to the master.
RXRDY
Read RHR
SVREAD has to be taken into account only while SVACC is active
TWD
SVACC
SVREAD
EOSVACC
SADR does not match,
TWI answers with a NACK
SADRS ADR W NA W A DATA A A DATA NA S/SrDATA NA P/S/Sr
SADR matches,
TWI answers with an ACK
0000000 + W
GENERAL CALL P
SA
GENERAL CALL Reset or write DADD A New SADR
DATA1 A DATA2 A
A
New SADR
Programming sequence
TXD
GCACC
SVACC
RESET command = 00000110X
WRITE command = 00000100X
Reset after read
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33.10.5.4Clock Synchronization
In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the
emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching
mechanism is implemented.
Clock Synchronization in Read Mode
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is
tied low until the shift register is loaded.
Figure 33-28 on page 652 describes the clock synchronization in Read mode.
Figure 33-28.Clock Synchronization in Read Mode
Notes: 1. TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been
acknowledged or non acknowledged.
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different
from SADR.
3. SCLWS is automatically set when the clock synchronization mechanism is started.
DATA1
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
SCLWS
SVACC
SVREAD
TXRDY
TWCK
TWI_THR
TXCOMP
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register Ack or Nack from the master
DATA0DATA0 DATA2
1
2
1
CLOCK is tied low by the TWI
as long as THR is empty
SSADR
SRDATA0AADATA1 ADATA2 NA S
XXXXXXX
2
Write THR
As soon as a START is detected
653
SAM4S [DATASHEET]
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Clock Synchronization in Write Mode
The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not
detected, it is tied low until TWI_RHR is read.
Figure 33-29 on page 653 describes the clock synchronization in Read mode.
Figure 33-29.Clock Synchronization in Write Mode
Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different
from SADR.
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the
mechanism is finished.
Rd DATA0 Rd DATA1 Rd DATA2
SVACC
SVREAD
RXRDY
SCLWS
TXCOMP
DATA1 DATA2
SCL is stretched on the last bit of DATA1
As soon as a START is detected
TWCK
TWD
TWI_RHR
CLOCK is tied low by the TWI as long as RHR is full
DATA0 is not read in the RHR
ADRS SADR W ADATA0A A DATA2DATA1 S
NA
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SAM4S [DATASHEET]
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33.10.5.5Reversal after a Repeated Start
Reversal of Read to Write
The master initiates the communication by a read command and finishes it by a write command.
Figure 33-30 on page 654 describes the repeated start + reversal from Read to Write mode.
Figure 33-30.Repeated Start + Reversal from Read to Write Mode
Note: 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected
again.
Reversal of Write to Read
The master initiates the communication by a write command and finishes it by a read command. Figure 33-31 on page
654 describes the repeated start + reversal from Write to Read mode.
Figure 33-31.Repeated Start + Reversal from Write to Read Mode
Notes: 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched
before the ACK.
2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again.
S SADR R ADATA0A DATA1 SADRSr
NA W A DATA2 A DATA3 A P
Cleared after read
DATA0 DATA1
DATA2 DATA3
SVACC
SVREAD
TWD
TWI_THR
TWI_RHR
EOSACC
TXRDY
RXRDY
TXCOMP
As soon as a START is detected
S SADR W ADATA0A DATA1 SADRSr
A
R A DATA2 A DATA3 NA P
Cleared after read
DATA0
DATA2 DATA3
DATA1
TXCOMP
TXRDY
RXRDY
As soon as a START is detected
Read TWI_RHR
SVACC
SVREAD
TWD
TWI_RHR
TWI_THR
EOSACC
655
SAM4S [DATASHEET]
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33.10.6 Read Write Flowcharts
The flowchart shown in Figure 33-32 on page 655 gives an example of read and write operations in Slave mode. A
polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable
register (TWI_IER) be configured first.
Figure 33-32.Read Write Flowchart in Slave Mode
Set the SLAVE mode:
SADR + MSDIS + SVEN
SVACC = 1
TXCOMP = 1
GACC = 1
Decoding of the
programming sequence
Prog seq
OK
Change SADR
SVREAD = 0
Read Status Register
RXRDY= 0
Read TWI_RHR
TXRDY= 1
EOSACC = 1
Write in TWI_THR
END
GENERAL CALL TREATMENT
No
No
No No
No
No
No
No
656
SAM4S [DATASHEET]
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33.11 Two-wire Interface (TWI) User Interface
Note: 1. All unlisted offset values are considered as “reserved”.
Table 33-6. Register Mapping
Offset Register Name Access Reset
0x00 Control Register TWI_CR Write-only N / A
0x04 Master Mode Register TWI_MMR Read-write 0x00000000
0x08 Slave Mode Register TWI_SMR Read-write 0x00000000
0x0C Internal Address Register TWI_IADR Read-write 0x00000000
0x10 Clock Waveform Generator Register TWI_CWGR Read-write 0x00000000
0x14 - 0x1C Reserved –––
0x20 Status Register TWI_SR Read-only 0x0000F009
0x24 Interrupt Enable Register TWI_IER Write-only N / A
0x28 Interrupt Disable Register TWI_IDR Write-only N / A
0x2C Interrupt Mask Register TWI_IMR Read-only 0x00000000
0x30 Receive Holding Register TWI_RHR Read-only 0x00000000
0x34 Transmit Holding Register TWI_THR Write-only 0x00000000
0xEC - 0xFC(1) Reserved – – –
0x100 - 0x128 Reserved for PDC registers – – –
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33.11.1 TWI Control Register
Name: TWI_CR
Address: 0x40018000 (0), 0x4001C000 (1)
Access: Write-only
Reset: 0x00000000
• START: Send a START Condition
0 = No effect.
1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write
operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR).
• STOP: Send a STOP Condition
0 = No effect.
1 = STOP Condition is sent just after completing the current byte transmission in master read mode.
– In single data byte master read, the START and STOP must both be set.
– In multiple data bytes master read, the STOP must be set after the last data received but one.
– In master read mode, if a NACK bit is received, the STOP is automatically performed.
– In master data write operation, a STOP condition will be sent after the transmission of the current data is
finished.
• MSEN: TWI Master Mode Enabled
0 = No effect.
1 = If MSDIS = 0, the master mode is enabled.
Note: Switching from Slave to Master mode is only permitted when TXCOMP = 1.
• MSDIS: TWI Master Mode Disabled
0 = No effect.
1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are trans-
mitted in case of write operation. In read operation, the character being transferred must be completely received before disabling.
• SVEN: TWI Slave Mode Enabled
0 = No effect.
1 = If SVDIS = 0, the slave mode is enabled.
Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SWRST QUICK SVDIS SVEN MSDIS MSEN STOP START
658
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• SVDIS: TWI Slave Mode Disabled
0 = No effect.
1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation.
In write operation, the character being transferred must be completely received before disabling.
• QUICK: SMBUS Quick Command
0 = No effect.
1 = If Master mode is enabled, a SMBUS Quick Command is sent.
• SWRST: Software Reset
0 = No effect.
1 = Equivalent to a system reset.
659
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
33.11.2 TWI Master Mode Register
Name: TWI_MMR
Address: 0x40018004 (0), 0x4001C004 (1)
Access: Read-write
Reset: 0x00000000
• IADRSZ: Internal Device Address Size
• MREAD: Master Read Direction
0 = Master write direction.
1 = Master read direction.
• DADR: Device Address
The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– DADR
15 14 13 12 11 10 9 8
– – – MREAD – – IADRSZ
76543210
––––––––
Value Name Description
0 NONE No internal device address
1 1_BYTE One-byte internal device address
2 2_BYTE Two-byte internal device address
3 3_BYTE Three-byte internal device address
660
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
33.11.3 TWI Slave Mode Register
Name: TWI_SMR
Address: 0x40018008 (0), 0x4001C008 (1)
Access: Read-write
Reset: 0x00000000
• SADR: Slave Address
The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode.
SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– SADR
15 14 13 12 11 10 9 8
––––––
76543210
––––––––
661
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
33.11.4 TWI Internal Address Register
Name: TWI_IADR
Address: 0x4001800C (0), 0x4001C00C (1)
Access: Read-write
Reset: 0x00000000
• IADR: Internal Address
0, 1, 2 or 3 bytes depending on IADRSZ.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
IADR
15 14 13 12 11 10 9 8
IADR
76543210
IADR
662
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
33.11.5 TWI Clock Waveform Generator Register
Name: TWI_CWGR
Address: 0x40018010 (0), 0x4001C010 (1)
Access: Read-write
Reset: 0x00000000
TWI_CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
• CHDIV: Clock High Divider
The SCL high period is defined as follows:
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CKDIV
15 14 13 12 11 10 9 8
CHDIV
76543210
CLDIV
Tlow CLDIV(2CKDIV
×()4)+TMCK
×=
Thigh CHDIV(2CKDIV
×()4)+TMCK
×=
663
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
33.11.6 TWI Status Register
Name: TWI_SR
Address: 0x40018020 (0), 0x4001C020 (1)
Access: Read-only
Reset: 0x0000F009
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in Figure 33-8 on page 635 and in Figure 33-10 on page 636.
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in Figure 33-28 on page 652, Figure 33-29 on page 653, Figure 33-30 on page
654 and Figure 33-31 on page 654.
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in Figure 33-10 on page 636.
RXRDY behavior in Slave mode can be seen in Figure 33-26 on page 651, Figure 33-29 on page 653, Figure 33-30 on page 654
and Figure 33-31 on page 654.
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the
same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in Figure 33.8.4 on page 634.
TXRDY used in Slave mode:
0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK).
1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCLWS ARBLST NACK
76543210
– OVRE GACC SVACC SVREAD TXRDY RXRDY TXCOMP
664
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the pro-
grammer must not fill TWI_THR to avoid losing it.
TXRDY behavior in Slave mode can be seen in Figure 33-25 on page 650, Figure 33-28 on page 652, Figure 33-30 on page 654
and Figure 33-31 on page 654.
• SVREAD: Slave Read (automatically set / reset)
This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
0 = Indicates that a write access is performed by a Master.
1 = Indicates that a read access is performed by a Master.
SVREAD behavior can be seen in Figure 33-25 on page 650, Figure 33-26 on page 651, Figure 33-30 on page 654 and Figure
33-31 on page 654.
• SVACC: Slave Access (automatically set / reset)
This bit is only used in Slave mode.
0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected.
1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or
a STOP condition is detected.
SVACC behavior can be seen in Figure 33-25 on page 650, Figure 33-26 on page 651, Figure 33-30 on page 654 and Figure 33-
31 on page 654.
• GACC: General Call Access (clear on read)
This bit is only used in Slave mode.
0 = No General Call has been detected.
1 = A General Call has been detected. After the detection of General Call, if need be, the programmer may acknowledge this
access and decode the following bytes and respond according to the value of the bytes.
GACC behavior can be seen in Figure 33-27 on page 651.
• OVRE: Overrun Error (clear on read)
This bit is only used in Master mode.
0 = TWI_RHR has not been loaded while RXRDY was set
1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
• NACK: Not Acknowledged (clear on read)
NACK used in Master mode:
0 = Each data byte has been correctly received by the far-end side TWI slave component.
1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.
NACK used in Slave Read mode:
0 = Each data byte has been correctly received by the Master.
1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill
TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it.
Note that in Slave Write mode all data are acknowledged by the TWI.
665
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• ARBLST: Arbitration Lost (clear on read)
This bit is only used in Master mode.
0: Arbitration won.
1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.
• SCLWS: Clock Wait State (automatically set / reset)
This bit is only used in Slave mode.
0 = The clock is not stretched.
1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character.
SCLWS behavior can be seen in Figure 33-28 on page 652 and Figure 33-29 on page 653.
• EOSACC: End Of Slave Access (clear on read)
This bit is only used in Slave mode.
0 = A slave access is being performing.
1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset.
EOSACC behavior can be seen in Figure 33-30 on page 654 and Figure 33-31 on page 654
• ENDRX: End of RX buffer
0 = The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR.
• ENDTX: End of TX buffer
0 = The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR.
• RXBUFF: RX Buffer Full
0 = TWI_RCR or TWI_RNCR have a value other than 0.
1 = Both TWI_RCR and TWI_RNCR have a value of 0.
• TXBUFE: TX Buffer Empty
0 = TWI_TCR or TWI_TNCR have a value other than 0.
1 = Both TWI_TCR and TWI_TNCR have a value of 0.
666
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
33.11.7 TWI Interrupt Enable Register
Name: TWI_IER
Address: 0x40018024 (0), 0x4001C024 (1)
Access: Write-only
Reset: 0x00000000
• TXCOMP: Transmission Completed Interrupt Enable
• RXRDY: Receive Holding Register Ready Interrupt Enable
• TXRDY: Transmit Holding Register Ready Interrupt Enable
• SVACC: Slave Access Interrupt Enable
• GACC: General Call Access Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• NACK: Not Acknowledge Interrupt Enable
• ARBLST: Arbitration Lost Interrupt Enable
• SCL_WS: Clock Wait State Interrupt Enable
• EOSACC: End Of Slave Access Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
76543210
– OVRE GACC SVACC – TXRDY RXRDY TXCOMP
667
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
33.11.8 TWI Interrupt Disable Register
Name: TWI_IDR
Address: 0x40018028 (0), 0x4001C028 (1)
Access: Write-only
Reset: 0x00000000
• TXCOMP: Transmission Completed Interrupt Disable
• RXRDY: Receive Holding Register Ready Interrupt Disable
• TXRDY: Transmit Holding Register Ready Interrupt Disable
• SVACC: Slave Access Interrupt Disable
• GACC: General Call Access Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• NACK: Not Acknowledge Interrupt Disable
• ARBLST: Arbitration Lost Interrupt Disable
• SCL_WS: Clock Wait State Interrupt Disable
• EOSACC: End Of Slave Access Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
76543210
– OVRE GACC SVACC – TXRDY RXRDY TXCOMP
668
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
33.11.9 TWI Interrupt Mask Register
Name: TWI_IMR
Address: 0x4001802C (0), 0x4001C02C (1)
Access: Read-only
Reset: 0x00000000
• TXCOMP: Transmission Completed Interrupt Mask
• RXRDY: Receive Holding Register Ready Interrupt Mask
• TXRDY: Transmit Holding Register Ready Interrupt Mask
• SVACC: Slave Access Interrupt Mask
• GACC: General Call Access Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• NACK: Not Acknowledge Interrupt Mask
• ARBLST: Arbitration Lost Interrupt Mask
• SCL_WS: Clock Wait State Interrupt Mask
• EOSACC: End Of Slave Access Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXBUFE RXBUFF ENDTX ENDRX EOSACC SCL_WS ARBLST NACK
76543210
– OVRE GACC SVACC – TXRDY RXRDY TXCOMP
669
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
33.11.10TWI Receive Holding Register
Name: TWI_RHR
Address: 0x40018030 (0), 0x4001C030 (1)
Access: Read-only
Reset: 0x00000000
• RXDATA: Master or Slave Receive Holding Data
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
RXDATA
670
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
33.11.11TWI Transmit Holding Register
Name: TWI_THR
Address: 0x40018034 (0), 0x4001C034 (1)
Access: Read-write
Reset: 0x00000000
• TXDATA: Master or Slave Transmit Holding Data
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
TXDATA
671
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
34. Universal Asynchronous Receiver Transmitter (UART)
34.1 Description
The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and
trace purposes and offers an ideal medium for in-situ programming solutions.
Moreover, the association with peripheral DMA controller (PDC) permits packet handling for these tasks with processor
time reduced to a minimum.
34.2 Embedded Characteristics
Two-pin UART
Independent receiver and transmitter with a common programmable Baud Rate Generator
Even, Odd, Mark or Space Parity Generation
Parity, Framing and Overrun Error Detection
Automatic Echo, Local Loopback and Remote Loopback Channel Modes
Support for two PDC channels with connection to receiver and transmitter
34.3 Block Diagram
Figure 34-1. UART Functional Block Diagram
Peripheral DMA Controller
Baud Rate
Generator
Transmit
Receive
Interrupt
Control
Peripheral
Bridge
Parallel
Input/
Output
UTXD
URXD
Power
Management
Controller
MCK
uart_irq
APB UART
Table 34-1. UART Pin Description
Pin Name Description Type
URXD UART Receive Data Input
UTXD UART Transmit Data Output
672
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
34.4 Product Dependencies
34.4.1 I/O Lines
The UART pins are multiplexed with PIO lines. The programmer must first configure the corresponding PIO Controller to
enable I/O line operations of the UART.
34.4.2 Power Management
The UART clock is controllable through the Power Management Controller. In this case, the programmer must first
configure the PMC to enable the UART clock. Usually, the peripheral identifier used for this purpose is 1.
34.4.3 Interrupt Source
The UART interrupt line is connected to one of the interrupt sources of the Interrupt Controller. Interrupt handling requires
programming of the Interrupt Controller before configuring the UART.
34.5 UART Operations
The UART operates in asynchronous mode only and supports only 8-bit character handling (with parity). It has no clock
pin.
The UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator.
Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible
with those of a standard USART.
34.5.1 Baud Rate Generator
The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter.
The baud rate clock is the master clock divided by 16 times the value (CD) written in UART_BRGR (Baud Rate
Generator Register). If UART_BRGR is set to 0, the baud rate clock is disabled and the UART remains inactive.
The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud rate is Master
Clock divided by (16 x 65536).
Table 34-2. I/O Lines
Instance Signal I/O Line Peripheral
UART0 URXD0 PA9 A
UART0 UTXD0 PA10 A
UART1 URXD1 PB2 A
UART1 UTXD1 PB3 A
Baud Rate MCK
16 CD×
-----------------------
=
673
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 34-2. Baud Rate Generator
34.5.2 Receiver
34.5.2.1Receiver Reset, Enable and Disable
After device reset, the UART receiver is disabled and must be enabled before being used. The receiver can be enabled
by writing the control register UART_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start
bit.
The programmer can disable the receiver by writing UART_CR with the bit RXDIS at 1. If the receiver is waiting for a start
bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits
for the stop bit before actually stopping its operation.
The programmer can also put the receiver in its reset state by writing UART_CR with the bit RSTRX at 1. In doing so, the
receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when
data is being processed, this data is lost.
34.5.2.2Start Detection and Data Sampling
The UART only supports asynchronous operations, and this affects only its receiver. The UART receiver detects the start
of a received character by sampling the URXD signal until it detects a valid start bit. A low level (space) on URXD is
interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud
rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit
period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the URXD at the theoretical midpoint of each bit. It is
assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit
period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the
start bit was detected.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 34-3. Start Bit Detection
MCK 16-bit Counter
0
Baud Rate
Clock
CD
CD
OUT
Divide
by 16
0
1
>1
Receiver
Sampling Cloc
k
Sampling Clock
URXD
True Start
Detection D0
Baud Rate
Clock
674
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 34-4. Character Reception
34.5.2.3Receiver Ready
When a complete character is received, it is transferred to the UART_RHR and the RXRDY status bit in UART_SR
(Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register UART_RHR is read.
Figure 34-5. Receiver Ready
34.5.2.4Receiver Overrun
If UART_RHR has not been read by the software (or the Peripheral Data Controller or DMA Controller) since the last
transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in UART_SR is set. OVRE is
cleared when the software writes the control register UART_CR with the bit RSTSTA (Reset Status) at 1.
Figure 34-6. Receiver Overrun
34.5.2.5Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field
PAR in UART_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in
UART_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register UART_CR is
written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is
written, the PARE bit remains at 1.
D0 D1 D2 D3 D4 D5 D6 D7
URXD
True Start Detection
Sampling Parity Bit Stop Bit
Example: 8-bit, parity enabled 1 stop
1 bit
period
0.5 bit
period
D0 D1 D2 D3 D4 D5 D6 D7 PS SD0 D1 D2 D3 D4 D5 D6 D7 P
URXD
Read UART_RHR
RXRDY
D0 D1 D2 D3 D4 D5 D6 D7 PS SD0 D1 D2 D3 D4 D5 D6 D7 P
URXD
RSTSTA
RXRDY
OVRE
stop stop
675
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 34-7. Parity Error
34.5.2.6Receiver Framing Error
When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is
also sampled and when it is detected at 0, the FRAME (Framing Error) bit in UART_SR is set at the same time the
RXRDY bit is set. The FRAME bit remains high until the control register UART_CR is written with the bit RSTSTA at 1.
Figure 34-8. Receiver Framing Error
34.5.3 Transmitter
34.5.3.1Transmitter Reset, Enable and Disable
After device reset, the UART transmitter is disabled and it must be enabled before being used. The transmitter is enabled
by writing the control register UART_CR with the bit TXEN at 1. From this command, the transmitter waits for a character
to be written in the Transmit Holding Register (UART_THR) before actually starting the transmission.
The programmer can disable the transmitter by writing UART_CR with the bit TXDIS at 1. If the transmitter is not
operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character
has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually
stopped.
The p rogra mmer c an also p ut the tr ansm itter i n its res et sta te by wri ting th e UART _CR wit h the bit R STTX a t 1. This
immediately stops the transmitter, whether or not it is processing characters.
34.5.3.2Transmit Format
The UART transmitter drives the pin UTXD at the baud rate clock speed. The line is driven depending on the format
defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from
the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown in the
following figure. The field PARE in the mode register UART_MR defines whether or not a parity bit is shifted out. When a
parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit.
stop
D0 D1 D2 D3 D4 D5 D6 D7 PS
URXD
RSTSTA
RXRDY
PARE
Wrong Parity Bit
D0 D1 D2 D3 D4 D5 D6 D7 PS
URXD
RSTSTA
RXRDY
FRAME
Stop Bit
Detected at 0
stop
676
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 34-9. Character Transmission
34.5.3.3Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register UART_SR. The
transmission starts when the programmer writes in the Transmit Holding Register (UART_THR), and after the written
character is transferred from UART_THR to the Shift Register. The TXRDY bit remains high until a second character is
written in UART_THR. As soon as the first character is completed, the last character written in UART_THR is transferred
into the shift register and TXRDY rises again, showing that the holding register is empty.
When both the Shift Register and UART_THR are empty, i.e., all the characters written in UART_THR have been
processed, the TXEMPTY bit rises after the last stop bit has been completed.
Figure 34-10.Transmitter Control
34.5.4 Peripheral DMA Controller
Both the receiver and the transmitter of the UART are connected to a Peripheral DMA Controller (PDC) channel.
The peripheral data controller channels are programmed via registers that are mapped within the UART user interface
from the offset 0x100. The status bits are reported in the UART status register (UART_SR) and can generate an
interrupt.
The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in UART_RHR.
The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of data in UART_THR.
D0 D1 D2 D3 D4 D5 D6 D7
UTXD
Start
Bit Parity
Bit Stop
Bit
Example: Parity enabled
Baud Rate
Clock
UART_THR
Shift Register
UTXD
TXRDY
TXEMPTY
Data 0 Data 1
Data 0
Data 0
Data 1
Data 1S SPP
Write Data 0
in UART_THR Write Data 1
in UART_THR
stop
stop
677
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
34.5.5 Test Modes
The UART supports three test modes. These modes of operation are programmed by using the field CHMODE (Channel
Mode) in the mode register (UART_MR).
The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the URXD line, it is sent to the
UTXD line. The transmitter operates normally, but has no effect on the UTXD line.
The Local Loopback mode allows the transmitted characters to be received. UTXD and URXD pins are not used and the
output of the transmitter is internally connected to the input of the receiver. The URXD pin level has no effect and the
UTXD line is held high, as in idle state.
The Remote Loopback mode directly connects the URXD pin to the UTXD line. The transmitter and the receiver are
disabled and have no effect. This mode allows a bit-by-bit retransmission.
Figure 34-11.Test Modes
Receiver
Transmitter Disabled
RXD
TXD
Receiver
Transmitter Disabled
RXD
TXD
VDD
Disabled
Receiver
Transmitter Disabled
RXD
TXD
Disabled
Automatic Echo
Local Loopback
Remote Loopback VDD
678
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
34.6 Universal Asynchronous Receiver Transmitter (UART) User Interface
Table 34-3. Register Mapping
Offset Register Name Access Reset
0x0000 Control Register UART_CR Write-only –
0x0004 Mode Register UART_MR Read-write 0x0
0x0008 Interrupt Enable Register UART_IER Write-only –
0x000C Interrupt Disable Register UART_IDR Write-only –
0x0010 Interrupt Mask Register UART_IMR Read-only 0x0
0x0014 Status Register UART_SR Read-only –
0x0018 Receive Holding Register UART_RHR Read-only 0x0
0x001C Transmit Holding Register UART_THR Write-only –
0x0020 Baud Rate Generator Register UART_BRGR Read-write 0x0
0x0024 - 0x003C Reserved – – –
0x004C - 0x00FC Reserved – – –
0x0100 - 0x0124 Reserved for PDC registers – – –
679
SAM4S [DATASHEET]
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34.6.1 UART Control Register
Name: UART_CR
Address: 0x400E0600 (0), 0x400E0800 (1)
Access: Write-only
• RSTRX: Reset Receiver
0 = No effect.
1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted.
• RSTTX: Reset Transmitter
0 = No effect.
1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted.
• RXEN: Receiver Enable
0 = No effect.
1 = The receiver is enabled if RXDIS is 0.
• RXDIS: Receiver Disable
0 = No effect.
1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the
receiver is stopped.
• TXEN: Transmitter Enable
0 = No effect.
1 = The transmitter is enabled if TXDIS is 0.
• TXDIS: Transmitter Disable
0 = No effect.
1 = The transmitter is disabled. If a character is being processed and a character has been written in the UART_THR and RSTTX
is not set, both characters are completed before the transmitter is stopped.
• RSTSTA: Reset Status Bits
0 = No effect.
1 = Resets the status bits PARE, FRAME and OVRE in the UART_SR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––
RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX ––
680
SAM4S [DATASHEET]
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34.6.2 UART Mode Register
Name: UART_MR
Address: 0x400E0604 (0), 0x400E0804 (1)
Access: Read-write
• PAR: Parity Type
• CHMODE: Channel Mode
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CHMODE –– PAR –
76543210
––––––––
Value Name Description
0 EVEN Even Parity
1 ODD Odd Parity
2 SPACE Space: parity forced to 0
3 MARK Mark: parity forced to 1
4 NO No Parity
Value Name Description
0 NORMAL Normal Mode
1 AUTOMATIC Automatic Echo
2 LOCAL_LOOPBACK Local Loopback
3 REMOTE_LOOPBACK Remote Loopback
681
SAM4S [DATASHEET]
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34.6.3 UART Interrupt Enable Register
Name: UART_IER
Address: 0x400E0608 (0), 0x400E0808 (1)
Access: Write-only
• RXRDY: Enable RXRDY Interrupt
• TXRDY: Enable TXRDY Interrupt
• ENDRX: Enable End of Receive Transfer Interrupt
• ENDTX: Enable End of Transmit Interrupt
• OVRE: Enable Overrun Error Interrupt
• FRAME: Enable Framing Error Interrupt
• PARE: Enable Parity Error Interrupt
• TXEMPTY: Enable TXEMPTY Interrupt
• TXBUFE: Enable Buffer Empty Interrupt
• RXBUFF: Enable Buffer Full Interrupt
0 = No effect.
1 = Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––
RXBUFF TXBUFE –TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
682
SAM4S [DATASHEET]
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34.6.4 UART Interrupt Disable Register
Name: UART_IDR
Address: 0x400E060C (0), 0x400E080C (1)
Access: Write-only
• RXRDY: Disable RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Disable End of Receive Transfer Interrupt
• ENDTX: Disable End of Transmit Interrupt
• OVRE: Disable Overrun Error Interrupt
• FRAME: Disable Framing Error Interrupt
• PARE: Disable Parity Error Interrupt
• TXEMPTY: Disable TXEMPTY Interrupt
• TXBUFE: Disable Buffer Empty Interrupt
• RXBUFF: Disable Buffer Full Interrupt
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––
RXBUFF TXBUFE –TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
683
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
34.6.5 UART Interrupt Mask Register
Name: UART_IMR
Address: 0x400E0610 (0), 0x400E0810 (1)
Access: Read-only
• RXRDY: Mask RXRDY Interrupt
• TXRDY: Disable TXRDY Interrupt
• ENDRX: Mask End of Receive Transfer Interrupt
• ENDTX: Mask End of Transmit Interrupt
• OVRE: Mask Overrun Error Interrupt
• FRAME: Mask Framing Error Interrupt
• PARE: Mask Parity Error Interrupt
• TXEMPTY: Mask TXEMPTY Interrupt
• TXBUFE: Mask TXBUFE Interrupt
• RXBUFF: Mask RXBUFF Interrupt
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––
RXBUFF TXBUFE –TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
684
SAM4S [DATASHEET]
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34.6.6 UART Status Register
Name: UART_SR
Address: 0x400E0614 (0), 0x400E0814 (1)
Access: Read-only
• RXRDY: Receiver Ready
0 = No character has been received since the last read of the UART_RHR or the receiver is disabled.
1 = At least one complete character has been received, transferred to UART_RHR and not yet read.
• TXRDY: Transmitter Ready
0 = A character has been written to UART_THR and not yet transferred to the Shift Register, or the transmitter is disabled.
1 = There is no character written to UART_THR not yet transferred to the Shift Register.
• ENDRX: End of Receiver Transfer
0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive.
1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active.
• ENDTX: End of Transmitter Transfer
0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive.
1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active.
• OVRE: Overrun Error
0 = No overrun error has occurred since the last RSTSTA.
1 = At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
0 = No framing error has occurred since the last RSTSTA.
1 = At least one framing error has occurred since the last RSTSTA.
• PARE: Parity Error
0 = No parity error has occurred since the last RSTSTA.
1 = At least one parity error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty
0 = There are characters in UART_THR, or characters being processed by the transmitter, or the transmitter is disabled.
1 = There are no characters in UART_THR and there are no characters being processed by the transmitter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––
RXBUFF TXBUFE –TXEMPTY –
76543210
PARE FRAME OVRE ENDTX ENDRX –TXRDY RXRDY
685
SAM4S [DATASHEET]
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• TXBUFE: Transmission Buffer Empty
0 = The buffer empty signal from the transmitter PDC channel is inactive.
1 = The buffer empty signal from the transmitter PDC channel is active.
• RXBUFF: Receive Buffer Full
0 = The buffer full signal from the receiver PDC channel is inactive.
1 = The buffer full signal from the receiver PDC channel is active.
686
SAM4S [DATASHEET]
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34.6.7 UART Receiver Holding Register
Name: UART_RHR
Address: 0x400E0618 (0), 0x400E0818 (1)
Access: Read-only
• RXCHR: Received Character
Last received character if RXRDY is set.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
RXCHR
687
SAM4S [DATASHEET]
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34.6.8 UART Transmit Holding Register
Name: UART_THR
Address: 0x400E061C (0), 0x400E081C (1)
Access: Write-only
• TXCHR: Character to be Transmitted
Next character to be transmitted after the current character if TXRDY is not set.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
TXCHR
688
SAM4S [DATASHEET]
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34.6.9 UART Baud Rate Generator Register
Name: UART_BRGR
Address: 0x400E0620 (0), 0x400E0820 (1)
Access: Read-write
• CD: Clock Divisor
0 = Baud Rate Clock is disabled
1 to 65,535 = MCK / (CD x 16)
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CD
76543210
CD
689
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35. Universal Synchronous Asynchronous Receiver Transmitter (USART)
35.1 Description
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal
synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop
bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications
with slow remote devices. Multidrop communications are also supported through address bit handling in reception and
transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485and SPI buses, with ISO7816 T = 0 or T =
1 smart card slots, infrared transceivers and connection to modem ports. The hardware handshaking feature enables an
out-of-band flow control by automatic management of the pins RTS and CTS.
The USART supports the connection to the Peripheral DMA Controller, which enab les data transfers to the transmitter
and from the receiver. The PDC provides chained buffer management without any intervention of the processor.
35.2 Embedded Characteristics
Programmable Baud Rate Generator
5- to 9-bit full-duplex synchronous or asynchronous serial communications
1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
Parity generation and error detection
Framing error detection, overrun error detection
MSB- or LSB-first
Optional break generation and detection
By 8 or by-16 over-sampling receiver frequency
Hardware handshaking RTS-CTS
Receiver time-out and transmitter timeguard
Optional Multi-drop Mode with address generation and detection
Optional Manchester Encoding
Full modem line support on USART1 (DCD-DSR-DTR-RI)
RS485 with driver control signal
ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
NACK handling, error counter with repetition and iteration limit
SPI Mode
Master or Slave
Serial Clock programmable Phase and Polarity
SPI Serial Clock (SCK) Frequency up to MCK/4
IrDA modulation and demodulation
Communication at up to 115.2 Kbps
Test Modes
Remote Loopback, Local Loopback, Automatic Echo
690
SAM4S [DATASHEET]
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35.3 Block Diagram
Figure 35-1. USART Block Diagram
Table 35-1. SPI Operating Mode
PIN USART SPI Slave SPI Master
RXD RXD MOSI MISO
TXD TXD MISO MOSI
RTS RTS – CS
CTS CTS CS –
(Peripheral) DMA
Controller
Channel Channel
Interrupt
Controller
Receiver
USART
Interrupt
RXD
TXD
SCK
USART PIO
Controller
CTS
RTS
DTR
DSR
DCD
RI
Transmitter
Modem
Signals
Control
Baud Rate
Generator
User Interface
PMC MCK
SLCK
DIV MCK/DIV
APB
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SAM4S [DATASHEET]
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35.4 Application Block Diagram
Figure 35-2. Application Block Diagram
35.5 I/O Lines Description
Smart
Card
Slot
USART
RS232
Drivers
Modem
RS485
Drivers
Differential
Bus
IrDA
Transceivers
Modem
Driver
Field Bus
Driver EMV
Driver IrDA
Driver
IrLAP
RS232
Drivers
Serial
Port
Serial
Driver
PPP
PSTN
SPI
Driver
SPI
Transceiver
Table 35-2. I/O Line Description
Name Description Type Active Level
SCK Serial Clock I/O
TXD Transmit Serial Data
or Master Out Slave In (MOSI) in SPI Master Mode
or Master In Slave Out (MISO) in SPI Slave Mode I/O
RXD Receive Serial Data
or Master In Slave Out (MISO) in SPI Master Mode
or Master Out Slave In (MOSI) in SPI Slave Mode Input
RI Ring Indicator Input Low
DSR Data Set Ready Input Low
DCD Data Carrier Detect Input Low
DTR Data Terminal Ready Output Low
CTS Clear to Send
or Slave Select (NSS) in SPI Slave Mode Input Low
RTS Request to Send
or Slave Select (NSS) in SPI Master Mode Output Low
692
SAM4S [DATASHEET]
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35.6 Product Dependencies
35.6.1 I/O Lines
The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the
PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the
application, they can be used for other purposes by the PIO Controller.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the
hardware handshaking feature or Modem mode is used, the internal pull up on TXD must also be enabled.
All the pins of the modems may or may not be implemented on the USART. Only USART1 fully equipped with all the
modem signals. On USARTs not equipped with the corresponding pin, the associated control bits and statuses have no
effect on the behavior of the USART.
35.6.2 Power Management
The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management
Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART
clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where
it left off.
Configuring the USART does not require the USART clock to be enabled.
Table 35-3. I/O Lines
Instance Signal I/O Line Peripheral
USART0 CTS0 PA8 A
USART0 RTS0 PA7 A
USART0 RXD0 PA5 A
USART0 SCK0 PA2 B
USART0 TXD0 PA6 A
USART1 CTS1 PA25 A
USART1 DCD1 PA26 A
USART1 DSR1 PA28 A
USART1 DTR1 PA27 A
USART1 RI1 PA29 A
USART1 RTS1 PA24 A
USART1 RXD1 PA21 A
USART1 SCK1 PA23 A
USART1 TXD1 PA22 A
693
SAM4S [DATASHEET]
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35.6.3 Interrupt
The USART interrupt line is connected on one of the internal sources of the Interrupt Controller.Using the USART
interrupt requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the USART
interrupt line in edge sensitive mode.
35.7 Functional Description
The USART is capable of managing several types of serial synchronous or asynchronous communications.
It supports the following communication modes:
5- to 9-bit full-duplex asynchronous serial communication
MSB- or LSB-first
1, 1.5 or 2 stop bits
Parity even, odd, marked, space or none
By 8 or by 16 over-sampling receiver frequency
Optional hardware handshaking
Optional modem signals management
Optional break management
Optional multidrop serial communication
High-speed 5- to 9-bit full-duplex synchronous serial communication
MSB- or LSB-first
1 or 2 stop bits
Parity even, odd, marked, space or none
By 8 or by 16 over-sampling frequency
Optional hardware handshaking
Optional modem signals management
Optional break management
Optional multidrop serial communication
RS485 with driver control signal
ISO7816, T0 or T1 protocols for interfacing with smart cards
NACK handling, error counter with repetition and iteration limit, inverted data.
InfraRed IrDA Modulation and Demodulation
SPI Mode
Master or Slave
Serial Clock Programmable Phase and Polarity
SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency MCK/6
Test modes
Remote loopback, local loopback, automatic echo
Table 35-4. Peripheral IDs
Instance ID
USART0 14
USART1 15
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35.7.1 Baud Rate Generator
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the
transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR)
between:
The Master Clock MCK
A division of the Master Clock, the divider being product dependent, but generally set to 8
The external clock, available on the SCK pin
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate
Generator Register (US_BRGR). If CD is programmed to 0, the Baud Rate Generator does not generate any clock. If CD
is programmed to 1, the divider is bypassed and becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must
be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 3 times lower
than MCK in USART mode, or 6 times lower in SPI mode.
Figure 35-3. Baud Rate Generator
35.7.1.1Baud Rate in Asynchronous Mode
If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field
programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a
sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is
performed at 16 times the baud rate clock.
The following formula performs the calculation of the Baud Rate.
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER
is programmed to 1.
Baud Rate Calculation Example
MCK/DIV 16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
MCK
SCK
USCLKS
OVER
SCK
SYNC
SYNC
USCLKS = 3
1
0
2
30
1
0
1
FIDI
Baudrate SelectedClock
82 Over–()CD()
--------------------------------------------=
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SAM4S [DATASHEET]
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Table 35-5 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This
table also shows the actual resulting baud rate and the error.
The baud rate is calculated with the following formula:
The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%.
35.7.1.2Fractional Baud Rate in Asynchronous Mode
The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only
integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator
that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the
reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register
(US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is
only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula:
Table 35-5. Baud Rate Example (OVER = 0)
Source Clock Expected Baud
Rate Calculation Result CD Actual Baud Rate Error
MHz Bit/s Bit/s
3 686 400 38 400 6.00 6 38 400.00 0.00%
4 915 200 38 400 8.00 8 38 400.00 0.00%
5 000 000 38 400 8.14 8 39 062.50 1.70%
7 372 800 38 400 12.00 12 38 400.00 0.00%
8 000 000 38 400 13.02 13 38 461.54 0.16%
12 000 000 38 400 19.53 20 37 500.00 2.40%
12 288 000 38 400 20.00 20 38 400.00 0.00%
14 318 180 38 400 23.30 23 38 908.10 1.31%
14 745 600 38 400 24.00 24 38 400.00 0.00%
18 432 000 38 400 30.00 30 38 400.00 0.00%
24 000 000 38 400 39.06 39 38 461.54 0.16%
24 576 000 38 400 40.00 40 38 400.00 0.00%
25 000 000 38 400 40.69 40 38 109.76 0.76%
32 000 000 38 400 52.08 52 38 461.54 0.16%
32 768 000 38 400 53.33 53 38 641.51 0.63%
33 000 000 38 400 53.71 54 38 194.44 0.54%
40 000 000 38 400 65.10 65 38 461.54 0.16%
50 000 000 38 400 81.38 81 38 580.25 0.47%
BaudRate MCK CD 16×⁄=
Error 1ExpectedBaudRate
ActualBaudRate
---------------------------------------------------
⎝⎠
⎛⎞
–=
Baudrate SelectedClock
82 Over–()CD FP
8
-------+
⎝⎠
⎛⎞
⎝⎠
⎛⎞
-----------------------------------------------------------------=
696
SAM4S [DATASHEET]
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The modified architecture is presented below:
Figure 35-4. Fractional Baud Rate Generator
35.7.1.3Baud Rate in Synchronous Mode or SPI Mode
If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in
US_BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the
USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must
be at least 3 times lower than the system clock. In synchronous mode master (USCLKS = 0 or 1, CLK0 set to 1), the
receive part limits the SCK maximum frequency to MCK/3 in USART mode, or MCK/6 in SPI mode.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD
must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the
Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd.
35.7.1.4Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
where:
B is the bit rate
Di is the bit-rate adjustment factor
Fi is the clock frequency division factor
f is the ISO7816 clock frequency (Hz)
Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 35-6.
MCK/DIV 16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
MCK
SCK
USCLKS
OVER
SCK
SYNC
SYNC
USCLKS = 3
1
0
2
30
1
0
1
FIDI
Glitch-free
Logic
Modulus
Control
FP
FP
BaudRate SelectedClock
CD
--------------------------------------=
B
Di
Fi
------ f×=
Table 35-6. Binary and Decimal Values for Di
DI field 0001 0010 0011 0100 0101 0110 1000 1001
Di (decimal) 1 2 4 8 16 32 12 20
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SAM4S [DATASHEET]
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Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 35-7.
Table 35-8 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock.
If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is
first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting
clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in
US_MR.
This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This
is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values
of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to
the expected value.
The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816
clock and the bit rate (Fi = 372, Di = 1).
Figure 35-5 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock.
Figure 35-5. Elementary Time Unit (ETU)
Table 35-7. Binary and Decimal Values for Fi
FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101
Fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048
Table 35-8. Possible Values for the Fi/Di Ratio
Fi/Di 372 558 774 1116 1488 1806 512 768 1024 1536 2048
1 372 558 744 1116 1488 1860 512 768 1024 1536 2048
2 186 279 372 558 744 930 256 384 512 768 1024
4 93 139.5 186 279 372 465 128 192 256 384 512
8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256
16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128
32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64
12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6
20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
1 ETU
ISO7816 Clock
on SCK
ISO7816 I/O Line
on TXD
FI_DI_RATIO
ISO7816 Clock Cycles
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SAM4S [DATASHEET]
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35.7.2 Receiver and Transmitter Control
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Regis ter
(US_CR). However, the receiver registers can be programmed before the receiver clock is enabled.
After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR).
However, the transmitter registers can be programmed before being enabled.
The Receiver and the Transmitter can be enabled together or independently.
At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the
corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the
status flag and reset internal state machines but the user interface configuration registers hold the value configured prior
to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately
stopped.
The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in
US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current
character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of
transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a
timeguard is programmed, it is handled normally.
35.7.3 Synchronous and Asynchronous Modes
35.7.3.1Transmitter Operations
The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1).
One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin
at each falling edge of the programmed serial clock.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are
selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in
US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which
data bit is sent first. If written to 1, the most significant bit is sent first. If written to 0, the less significant bit is sent first. The
number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode
only.
Figure 35-6. Character Transmit
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in
the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and
TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character
processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and
US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY
is low has no effect and the written character is lost.
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock
699
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 35-7. Transmitter Status
35.7.3.2Manchester Encoder
When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase
Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1. Depending on polarity
configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition
always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the
receiver has more error control since the expected input must show a change at the center of a bit cell. An example of
Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default
polarity of the encoder. Figure 35-8 illustrates this coding scheme.
Figure 35-8. NRZ to Manchester Encoding
The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame
delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined
pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is
not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE,
ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register, the field TX_PL is used to
configure the preamble length. Figure 35-9 illustrates and defines the valid patterns. To improve flexibility, the encoding
scheme can be configured using the TX_MPOL field in the US_MAN register. If the TX_MPOL field is set to zero
(default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If
the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a
zero-to-one transition.
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Start
Bit
Write
US_THR
D0 D1 D2 D3 D4 D5 D6 D7 Parity
Bit Stop
Bit
TXRDY
TXEMPTY
NRZ
encoded
data
Manchester
encoded
data
10110001
Txd
700
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 35-9. Preamble Patterns, Default Polarity Assumed
A start frame delimiter is to be configured using the ONEBIT field in the US_MR register. It consists of a user-defined
patt ern that i ndicat es the beg innin g of a valid d ata. Figure 35-10 illu strate s these pa ttern s. If the st art fram e delimi ter,
also known as the start bit, is one bit, (ONEBIT to 1), a logic zero is Manchester encoded and indicates that a new
character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync
(ONEBIT to 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new character. The sync
waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two
distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one
and a half bit times, then a transition to logic zero for the second one and a half bit times. If the MODSYNC field in the
US_MR regis ter is set to 1, the next char acter is a command. If i t is set to 0, the next chara cter is a data. When d irect
memory access is used, the MODSYNC field can be immediately updated with a modified character located in memory.
To enable this mode, VAR_SYNC field in US_MR register must be set to 1. In this case, the MODSYNC field in US_MR
is bypassed and the sync configuration is held in the TXSYNH in the US_THR register. The USART character format is
modified and includes sync information.
Manchester
encoded
data Txd SFD DATA
8 bit width ALL_ONE Preamble
Manchester
encoded
data Txd SFD DATA
8 bit width ALL_ZERO Preamble
Manchester
encoded
data Txd SFD DATA
8 bit width ZERO_ONE Preamble
Manchester
encoded
data Txd SFD DATA
8 bit width ONE_ZERO Preamble
701
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 35-10.Start Frame Delimiter
Drift Compensation
Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift.
To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X clock cycle
from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is
between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the
RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock
cycle. These intervals are considered to be drift and so corrective actions are automatically taken.
Figure 35-11.Bit Resynchronization
35.7.3.3Asynchronous Receiver
If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line.
The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register
(US_MR).
The receiver samples the RXD line. If the line is sampled during one half of a bit time to 0, a start bit is detected and data,
parity and stop bits are successively sampled on the bit rate clock.
If the oversampling is 16, (OVER to 0), a start is detected at the eighth sample to 0. Then, data bits, parity bit and stop bit
are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER to 1), a start bit is detected at the fourth
sample to 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle.
Manchester
encoded
data Txd
SFD
DATA
One bit start frame delimiter
Preamble Length
is set to 0
Manchester
encoded
data Txd
SFD
DATA
Command Sync
start frame delimiter
Manchester
encoded
data Txd
SFD
DATA
Data Sync
start frame delimiter
RXD
Oversampling
16x Clock
Sampling
point
Expected edge
Tolerance
Synchro.
Jump Sync
Jump
Synchro.
Error
Synchro.
Error
702
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e.
respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no
effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization
between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts
looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one
stop bit.
Figure 35-12 and Figure 35-13 illustrate start detection and character reception when USART operates in asynchronous
mode.
Figure 35-12.Asynchronous Start Detection
Figure 35-13.Asynchronous Character Reception
35.7.3.4Manchester Decoder
When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The decoder performs both
preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data.
An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use
RX_PL in US_MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is
detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in
US_MAN register. Depending on the desired application the preamble pattern matching is to be defined via the RX_PP
field in US_MAN. See Figure 35-9 for available preamble patterns.
Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is
set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a
sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If
Sampling
Clock (x16)
RXD
Start
Detection
Sampling
Baud Rate
Clock
RXD
Start
Rejection
Sampling
12345678
123456701234
123456789 10111213141516D0
Sampling
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Parity
Bit Stop
Bit
Example: 8-bit, Parity Enabled
Baud Rate
Clock
Start
Detection 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples
703
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
RXD is sampled during one quarter of a bit time to zero, a start bit is detected. See Figure 35-14. The sa mple pu lse
rejection mechanism applies.
In order to increase the compatibility the RXIDLV bit in the US_MAN register allows to inform the USART block of the Rx
line idle state value (Rx line undriven), it can be either level one (pull-up) or level zero (pull-down). By default this bit is set
to one (Rx line is at level 1 if undriven).
Figure 35-14.Asynchronous Start Bit Detection
The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then
three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the
same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-
synchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time.
If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into
NRZ data and passed to USART for processing. Figure 35-15 illustrates Manchester pattern mismatch. When incoming
data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a
lack of transition in the middle of a bit cell. In this case, MANE flag in US_CSR register is raised. It is cleared by writing
the Control Register (US_CR) with the RSTSTA bit to 1. See Figure 35-16 for an example of Manchester error detection
during data phase.
Figure 35-15.Preamble Pattern Mismatch
Manchester
encoded
data Txd
1234
Sampling
Clock
(16 x)
Start
Detection
Manchester
encoded
data Txd SFD DATA
Preamble Length is set to 8
Preamble Mismatch
invalid pattern
Preamble Mismatch
Manchester coding error
704
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 35-16.Manchester Error Flag
When the start frame delimiter is a sync pattern (ONEBIT field to 0), both command and data delimiter are supported. If a
valid sync is detected, the received character is written as RXCHR field in the US_RHR register and the RXSYNH is
updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a
data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in
the same register.
As the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-to-one transition.
35.7.3.5Radio Interface: Manchester Encoded USART Application
This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART.
These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes.
The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the
configuration in Figure 35-17.
Figure 35-17.Manchester Encoded Characters RF Transmission
The USART module is configured as a Manchester encoder/decoder. Looking at the downstream communication
channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined
Manchester
encoded
data Txd
SFD
Preamble Length
is set to 4 Elementary character bit time
Manchester
Coding Error
detected
sampling points
Preamble subpacket
and Start Frame Delimiter
were successfully
decoded
Entering USART character area
LNA
VCO
RF filter
Demod
control bi-dir
line
PA
RF filter
Mod
VCO
control
Manchester
decoder
Manchester
encoder
USART
Receiver
USART
Emitter
ASK/FSK
Upstream Receiver
ASK/FSK
downstream transmitter
Upstream
Emitter
Downstream
Receiver
Serial
Configuration
Interface
Fup frequency Carrier
Fdown frequency Carrier
705
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data
from a transmitter and signals due to noise. The Manchester stream is then modulated. See Figure 35-18 for an example
of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is
enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned
off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the
modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See Figure 35-19.
From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining
demodulated data stream. If a valid pattern is detected, the receiver switches to receiving mode. The demodulated
stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the
microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in
accordance with the RF IC configuration.
Figure 35-18.ASK Modulator Output
Figure 35-19.FSK Modulator Output
t
35.7.3.6Synchronous Receiver
In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a
low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver
waits for the next start bit. Synchronous mode operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.
Figure 35-20 illustrates a character reception in synchronous mode.
Manchester
encoded
data
default polarity
unipolar output Txd
ASK Modulator
Output
Uptstream Frequency F0
NRZ stream 10 0 1
Manchester
encoded
data
default polarity
unipolar output
Txd
FSK Modulator
Output
Uptstream Frequencies
[F0, F0+offset]
NRZ stream 10 0 1
706
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 35-20.Synchronous Mode Character Reception
35.7.3.7Receiver Operations
When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit
in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit
is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing
the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
Figure 35-21.Receiver Status
35.7.3.8Parity
The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR
field also enables the Multidrop mode, see “Multidrop Mode” on page 707. Even and odd parity bit generation and error
detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the character
data bit is even, and to 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of
received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity
generator of the transmitter drives the parity bit to 1 if a number of 1s in the character data bit is even, and to 0 if the
number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error
if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the
parity bit to 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 0. If the space
parity is used, the parity generator of the transmitter drives the parity bit to 0 for all characters. The receiver parity
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Sampling
Parity Bit Stop Bit
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
US_CR
RXRDY
OVRE
D0 D1 D2 D3 D4 D5 D6 D7
Start
Bit Parity
Bit Stop
Bit
RSTSTA = 1
Read
US_RHR
707
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
checker reports an error if the parity bit is sampled to 1. If parity is disabled, the transmitter does not generate any parity
bit and the receiver does not report any parity error.
Table 35-9 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the
configuration of the USART. Because there are two bits to 1, 1 bit is added when a parity is odd, or 0 is added when a
parity is even.
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR).
The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit to 1. Figure 35-22 illustrates
the parity bit status setting and clearing.
Figure 35-22.Parity Error
35.7.3.9Multidrop Mode
If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop
Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit to
0 and addresses are transmitted with the parity bit to 1.
If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and
the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit
to 1.
To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA to 1.
The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte
written to US_THR is transmitted as an address. Any character written in US_THR without having written the command
SENDA is transmitted normally with the parity to 0.
Table 35-9. Parity Bit Examples
Character Hexa Binary Parity Bit Parity Mode
A 0x41 0100 0001 1 Odd
A 0x41 0100 0001 0 Even
A 0x41 0100 0001 1 Mark
A 0x41 0100 0001 0 Space
A 0x41 0100 0001 None None
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Bit Bad
Parity
Bit
Stop
Bit
Baud Rate
Clock
Write
US_CR
PARE
RXRDY
RSTSTA = 1
708
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.7.3.10Transmitter Timeguard
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle
state actually acts as a long stop bit.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When
this field is programmed to zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after
each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits.
As illustrated in Figure 35-23, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a
timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains to 0 during the timeguard
transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is
completed as the timeguard is part of the current character being transmitted.
Figure 35-23.Timeguard Operations
Table 35-10 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function
of the Baud Rate.
35.7.3.11Receiver Time-out
The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the
RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can
generate an interrupt, thus indicating to the driver an end of frame.
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Start
Bit
TG=4
Write
US_THR
D0 D1 D2 D3 D4 D5 D6 D7 Parity
Bit Stop
Bit
TXRDY
TXEMPTY
TG=4
Table 35-10. Maximum Timeguard Length Depending on Baud Rate
Baud Rate Bit time Timeguard
Bit/sec μsms
1 200 833 212.50
9 600 104 26.56
14400 69.4 17.71
19200 52.1 13.28
28800 34.7 8.85
33400 29.9 7.63
56000 17.9 4.55
57600 17.4 4.43
115200 8.7 2.21
709
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the
Receiver Time-out Register (US_RTOR). If the TO field is programmed to 0, the Receiver Time-out is disabled and no
time-out is detected. The TIMEOUT bit in US_CSR remains to 0. Otherwise, the receiver loads a 16-bit counter with the
value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is
received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either:
Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR)
with the STTTO (Start Time-out) bit to 1. In this case, the idle state on RXD before a new character is received will
not provide a time-out. This prevents having to handle an interrupt before a character is received and allows
waiting for the next idle state on RXD after a frame is received.
Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload
and Start Time-out) bit to 1. If RETTO is performed, the counter starts counting down immediately from the value
TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no
key is pressed on a keyboard.
If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the
start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of
the end of frame when the idle state on RXD is detected.
If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a
periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard.
Figure 35-24 shows the block diagram of the Receiver Time-out feature.
Figure 35-24.Receiver Time-out Block Diagram
Table 35-11 gives the maximum time-out period for some standard baud rates.
Table 35-11. Maximum Time-out Period
Baud Rate Bit Time Time-out
bit/sec μsms
600 1 667 109 225
1 200 833 54 613
2 400 417 27 306
4 800 208 13 653
9 600 104 6 827
14400 69 4 551
19200 52 3 413
28800 35 2 276
33400 30 1 962
16-bit Time-out
Counter
0
TO
TIMEOUT
Baud Rate
Clock
=
Character
Received
RETTO
Load
Clock
16-bit
Value
STTTO
DQ
1
Clear
710
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.7.3.12Framing Error
The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is
detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized.
A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in
the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR)
with the RSTSTA bit to 1.
Figure 35-25.Framing Error Status
35.7.3.13Transmit Break
The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line
low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits
to 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition
to be removed.
A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit to 1. This can be performed at any
time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is
being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the
TXD line is held low.
Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed.
The break condition is removed by writing US_CR with the STPBRK bit to 1. If the STPBRK is requested before the end
of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the
break condition completes.
The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into
account only if the TXRDY bit in US_CSR is to 1 and the start of the break condition clears the TXRDY and TXEMPTY
bits as if a character is processed.
Writing US_ CR with both STTBRK and ST PBRK bits to 1 can lead to an unp redictable result . All STPBRK command s
requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a
break is pending, but not started, is ignored.
56000 18 1 170
57600 17 1 138
200000 5 328
Table 35-11. Maximum Time-out Period (Continued)
Baud Rate Bit Time Time-out
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
US_CR
FRAME
RXRDY
RSTSTA = 1
711
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After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter
ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is
programmed with a value higher than 12, the TXD line is held high for the timeguard period.
After holding the TXD line for this period, the transmitter resumes normal operations.
Figure 35-26 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD
line.
Figure 35-26.Break Transmission
35.7.3.14Receive Break
The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a
framing error with data to 0x00, but FRAME remains low.
When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the
Control Register (US_CR) with the bit RSTSTA to 1.
An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one
sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit.
35.7.3.15Hardware Handshaking
The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with
the remote device, as shown in Figure 35-27.
Figure 35-27.Connection with a Remote Device for Hardware Handshaking
Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode
Register (US_MR) to the value 0x2.
The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or
asynchr onous mode, excep t that the receiver drives t he RTS pin as described belo w and the level on the CT S pin
modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for
reception. The transmitter can handle hardware handshaking in any case.
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
US_CR
TXRDY
TXEMPTY
STPBRK = 1
STTBRK = 1
Break Transmission End of Break
USART
TXD
CTS
Remote
Device
RXD
TXDRXD
RTS
RTS
CTS
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Figure 35-28 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the
receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the
remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled,
the RTS falls, indicating to the remote device that it can st art transmitting. Defining a new buffer to the PDC clears the
status bit RXBUFF and, as a result, asserts the pin RTS low.
Figure 35-28.Receiver Behavior when Operating with Hardware Handshaking
Figure 35-29 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the
transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current
character and transmission of the next character happens as soon as the pin CTS falls.
Figure 35-29.Transmitter Behavior when Operating with Hardware Handshaking
35.7.4 ISO7816 Mode
The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and
Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the
ISO7816 specification are supported.
Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to
the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1.
35.7.4.1ISO7816 Mode Overview
The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of
the clock provided to the remote device (see “Baud Rate Generator” on page 694).
The USART connects to a smart card as shown in Figure 35-30. The TXD line becomes bidirectional and the Baud Rate
Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by
the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver.
The USART is considered as the master of the communication as it generates the clock.
Figure 35-30.Connection of a Smart Card to the USART
RTS
RXBUFF
Write
US_CR
RXEN=1
RXD RXDIS = 1
CTS
TXD
Smart
Card
SCK CLK
TXD I/O
USART
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When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits,
even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields.
MSBF c an be use d to tran smit LSB o r MSB fir st. Par ity Bit (P AR) can b e used to t ransmi t in norm al or inve rse mod e.
Refer to “USART Mode Register” on page 729 and “PAR: Parity Type” on page 730.
The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional
at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the
transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to
unpredictable results.
The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the
I/O line at their negative value.
35.7.4.2Protocol T = 0
In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts
two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time.
If no parity error is detected, the I/O line remains to 1 during the guard time and the transmitter can continue with the
transmission of the next character, as shown in Figure 35-31.
If a parity error is detected by the receiver, it drives the I/O line to 0 during the guard time, as shown in Figure 35-32. This
error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time
length is the same and is added to the error bit time which lasts 1 bit time.
When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding
Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle
the error.
Figure 35-31.T = 0 Protocol without Parity Error
Figure 35-32.T = 0 Protocol with Parity Error
Receive Error Counter
The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register.
The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field.
Receive NACK Inhibit
The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode
Register (US_MR). If INACK is to 1, no error signal is driven on the I/O line even if a parity bit is detected.
Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error
occurred and the RXRDY bit does rise.
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Parity
Bit
Baud Rate
Clock
Start
Bit Guard
Time 1 Next
Start
Bit
Guard
Time 2
D0 D1 D2 D3 D4 D5 D6 D7
I/O
Parity
Bit
Baud Rate
Clock
Start
Bit Guard
Time 1 Start
Bit
Guard
Time 2 D0 D1
Error
Repetition
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Transmit Character Repetition
When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving
on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value
higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions.
If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in
MAX_ITERATION.
When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register
(US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration
counter is cleared.
The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit to 1.
Disable Successive Receive NACK
The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by
setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in
the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an
acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set.
35.7.4.3Protocol T = 1
When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit.
The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the
Channel Status Register (US_CSR).
35.7.5 IrDA Mode
The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the
modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 35-33.
The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds
ranging from 2.4 Kb/s to 115.2 Kb/s.
The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8.
The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate
in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are
activated.
Figure 35-33.Connection to IrDA Transceivers
The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be
managed.
To receive IrDA signals, the following needs to be done:
Disable TX and Enable RX
IrDA
Transceivers
RXD RX
TXD TX
USART
Demodulator
Modulator
Receiver
Transmitter
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Configure the TXD pin as PIO and set it as an output to 0 (to avoid LED emission). Disable the internal pull-up
(better for power consumption).
Receive data
35.7.5.1IrDA Modulation
For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light
pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 35-12.
Figure 35-34 shows an example of character transmission.
Figure 35-34.IrDA Modulation
35.7.5.2IrDA Baud Rate
Table 35-13 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the
maximum acceptable error of ±1.87% must be met.
Table 35-12. IrDA Pulse Duration
Baud Rate Pulse Duration (3/16)
2.4 Kb/s 78.13 μs
9.6 Kb/s 19.53 μs
19.2 Kb/s 9.77 μs
38.4 Kb/s 4.88 μs
57.6 Kb/s 3.26 μs
115.2 Kb/s 1.63 μs
Bit Period Bit Period
3
16
Start
Bit Data Bits Stop
Bit
00
000
111 1
1
Transmitter
Output
TXD
Table 35-13. IrDA Baud Rate Error
Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time
3 686 400 115 200 2 0.00% 1.63
20 000 000 115 200 11 1.38% 1.63
32 768 000 115 200 18 1.25% 1.63
40 000 000 115 200 22 1.38% 1.63
3 686 400 57 600 4 0.00% 3.26
20 000 000 57 600 22 1.38% 3.26
32 768 000 57 600 36 1.25% 3.26
40 000 000 57 600 43 0.93% 3.26
3 686 400 38 400 6 0.00% 4.88
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35.7.5.3IrDA Demodulator
The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value
programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the
Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If
no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time.
Figure 35-35 illustrates the operations of the IrDA demodulator.
Figure 35-35.IrDA Demodulator Operations
As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a
value higher than 0 in order to assure IrDA communications operate correctly.
20 000 000 38 400 33 1.38% 4.88
32 768 000 38 400 53 0.63% 4.88
40 000 000 38 400 65 0.16% 4.88
3 686 400 19 200 12 0.00% 9.77
20 000 000 19 200 65 0.16% 9.77
32 768 000 19 200 107 0.31% 9.77
40 000 000 19 200 130 0.16% 9.77
3 686 400 9 600 24 0.00% 19.53
20 000 000 9 600 130 0.16% 19.53
32 768 000 9 600 213 0.16% 19.53
40 000 000 9 600 260 0.16% 19.53
3 686 400 2 400 96 0.00% 78.13
20 000 000 2 400 521 0.03% 78.13
32 768 000 2 400 853 0.04% 78.13
Table 35-13. IrDA Baud Rate Error (Continued)
Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time
MCK
RXD
Receiver
Input
Pulse
Rejected
65432 61
65432 0
Pulse
Accepted
Counter
Value
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35.7.6 RS485 Mode
The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART
behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The
difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled
by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 35-36.
Figure 35-36.Typical Connection to a RS485 Bus
The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value
0x1.
The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is
programmed so that the line can remain driven after the last character completion. Figure 35-37 gives an example of the
RTS waveform during a character transmission when the timeguard is enabled.
Figure 35-37.Example of RTS Drive with Timeguard
USART
RTS
TXD
RXD
Differential
Bus
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
TG=4
Write
US_THR
TXRDY
TXEMPTY
RTS
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35.7.7 Modem Mode
The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set
Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While
operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can
detect level change on DSR, DCD, CTS and RI.
Setting the USART in modem mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to
the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the
parameter configurations are available.
Table 35-14 gives the correspondence of the USART signals with modem connection standards.
The control of the DTR output pin is performed by writing the Control Regist er (US_CR) with the DTRDIS and DTREN
bits respectively to 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable
command forces the corresponding pin to its active level, i.e. low. RTS output pin is automatically controlled in this mode
The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC,
DCDIC and CTSIC bits in the Channel Status Register (US_CSR) are set respectively and can trigger an interrupt. The
status is automatically cleared when US_CSR is read. Furthermore, the CTS automatically disables the transmitter when
it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is
completed before the transmitter is actually disabled.
35.7.8 SPI Mode
The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external
devices in Master or Slave Mode. It also enables communication between processors if an external processor is
connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data
transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as “slaves'' which
have data shifted into and out by the master. Different CPUs can take turns being masters and one master may
simultaneously shift data into multiple slaves. (Multiple Master Protocol is the opposite of Single Master Protocol, where
one CPU is always the master while all of the others are always slaves.) However, only one slave may drive its output to
write data back to the master at any given time.
A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can address
only one SPI Slave because it can generate only one NSS signal.
The SPI system consists of two data lines and two control lines:
Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input of the
slave.
Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master.
Table 35-14. Circuit References
USART Pin V24 CCITT Direction
TXD 2 103 From terminal to modem
RTS 4 105 From terminal to modem
DTR 20 108.2 From terminal to modem
RXD 3 104 From modem to terminal
CTS 5 106 From terminal to modem
DSR 6 107 From terminal to modem
DCD 8 109 From terminal to modem
RI 22 125 From terminal to modem
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Serial Clock (SCK): This control line is driven by the master and regulates the flow of the data bits. The master
may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is transmitted.
Slave Select (NSS): This control line allows the master to select or deselect the slave.
35.7.8.1Modes of Operation
The USART can operate in SPI Master Mode or in SPI Slave Mode.
Operation in SPI Master Mode is programmed by writing to 0xE the USART_MODE field in the Mode Register. In this
case the SPI lines must be connected as described below:
The MOSI line is driven by the output pin TXD
The MISO line drives the input pin RXD
The SCK line is driven by the output pin SCK
The NSS line is driven by the output pin RTS
Operation in SPI Slave Mode is programmed by writing to 0xF the USART_MODE field in the Mode Register. In this case
the SPI lines must be connected as described below:
The MOSI line drives the input pin RXD
The MISO line is driven by the output pin TXD
The SCK line drives the input pin SCK
The NSS line drives the input pin CTS
In order to avoid unpredicted behavior, any change of the SPI Mode must be followed by a software reset of the
transmitter and of the receiver (except the initial configuration after a hardware reset).
35.7.8.2Baud Rate
In SPI Mode, the baudrate generator operates in the same way as in USART synchronous mode: See “Baud Rate in
Synchronous Mode or SPI Mode” on page 696. However, there are some restrictions:
In SPI Master Mode:
The external clock SCK must not be selected (USCLKS ≠ 0x3), and the bit CLKO must be set to “1” in the Mode
Register (US_MR), in order to generate correctly the serial clock on the SCK pin.
To obtain correct behavior of the receiver and the transmitter, the value programmed in CD must be superior or
equal to 6.
If the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even to ensure a 50:50
mark/space ratio on the SCK pin, this value can be odd if the internal clock is selected (MCK).
In SPI Slave Mode:
The external clock (SCK) selection is forced regardless of the value of the USCLKS field in the Mode Register
(US_MR). Likewise, the value written in US_BRGR has no effect, because the clock is provided directly by the
signal on the USART SCK pin.
To obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at least
6 times lower than the system clock.
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35.7.8.3Data Transfer
Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and
CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). The 9 bits are
selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI Mode
(Master or Slave).
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL
bit in the Mode Register. The clock phase is programmed with the CPHA bit. These two parameters determine the edges
of the clock signal upon which data is driven and sampled. Each of the two parameters has two possible states, resulting
in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same
parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must
reconfigure itself each time it needs to communicate with a different slave.
Figure 35-38.SPI Transfer Format (CPHA=1, 8 bits per transfer)
Table 35-15. SPI Bus Protocol Mode
SPI Bus Protocol Mode CPOL CPHA
001
100
211
310
6
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MOSI
SPI Master ->TXD
SPI Slave -> RXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference)
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
1 2345 786
MISO
SPI Master ->RXD
SPI Slave -> TXD
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Figure 35-39.SPI Transfer Format (CPHA=0, 8 bits per transfer)
35.7.8.4Receiver and Transmitter Control
See “Receiver and Transmitter Control” on page 698.
35.7.8.5Character Transmission
The characters are sent by writing in the Transmit Holding Register (US_THR). An additional condition for transmitting a
character can be added when the USART is configured in SPI master mode. In the USART_MR register, the value
configured on INACK field can prevent any character transmission (even if US_THR has been written) while the receiver
side is not ready (character not read). When WRDBT equals 0, the character is transmitted whatever the receiver status.
If WRDBT is set to 1, the transmitter waits for the receiver holding register to be read before transmitting the character
(RXRDY flag cleared), thus preventing any overflow (character loss) on the receiver side.
The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which
indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been
processed. When the current character processing is completed, the last character written in US_THR is transferred into
the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY
is low has no effect and the written character is lost.
If the USART is in SPI Slave Mode and if a character must be sent while the Transmit Holding Register (US_THR) is
empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE
bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
In SPI Master Mode, the slave select line (NSS) is asserted at low level 1 Tbit (Time bit) before the transmission of the
MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always
released between each character transmission and a minimum delay of 3 Tbits always inserted. However, in order to
address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can
be forced at low level by writing the Control Register (US_CR) with the RTSEN bit to 1. The slave select line (NSS) can
be released at high level only by writing the Control Register (US_CR) with the RTSDIS bit to 1 (for example, when all
data have been transferred to the slave device).
In SPI Slave Mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a character
transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit
before the first serial clock cycle corresponding to the MSB bit.
SCK
(CPOL = 0)
SCK
(CPOL = 1)
1 2345 7
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MISO
SPI Master -> RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference) 8
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
1
1
2
2
6
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35.7.8.6Character Reception
When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit
in the Status Register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is
set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing
the Control Register (US_CR) with the RSTSTA (Reset Status) bit to 1.
To ensure correct behavior of the receiver in SPI Slave Mode, the master device sending the frame must ensure a
minimum delay of 1 Tbit between each character transmission. The receiver does not require a falling edge of the slave
select line (NSS) to initiate a character reception but only a low level. However, this low level must be present on the
slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit.
35.7.8.7Receiver Timeout
Because the receiver baudrate clock is active only during data transfers in SPI Mode, a receiver timeout is impossible in
this mode, whatever the Time-out value is (field TO) in the Time-out Register (US_RTOR).
35.7.9 Test Modes
The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-
board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for
loopback internally or externally.
35.7.9.1Normal Mode
Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin.
Figure 35-40.Normal Mode Configuration
35.7.9.2Automatic Echo Mode
Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as
shown in Figure 35-41. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the
receiver input, thus the receiver remains active.
Figure 35-41.Automatic Echo Mode Configuration
35.7.9.3Local Loopback Mode
Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 35-42.
The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven
high, as in idle state.
Receiver
Transmitter
RXD
TXD
Receiver
Transmitter
RXD
TXD
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Figure 35-42.Local Loopback Mode Configuration
35.7.9.4Remote Loopback Mode
Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 35-43. The transmitter and the
receiver are disabled and have no effect. This mode allows bit-by-bit retransmission.
Figure 35-43.Remote Loopback Mode Configuration
35.7.10 Write Protection Registers
To prevent any single software error that may corrupt USART behavior, certain address spaces can be write-protected
by setting the WPEN bit in the USART Write Protect Mode Register (US_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the USART Write Protect Status Register
(US_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset by reading the USART Write Protect Mode Register (US_WPMR) with the
appropriate access key, WPKEY.
The protected registers are:
“USART Mode Register”
“USART Baud Rate Generator Register”
“USART Receiver Time-out Register”
“USART Transmitter Timeguard Register”
“USART FI DI RATIO Register”
“USART IrDA FILTER Register”
“USART Manchester Configuration Register”
Receiver
Transmitter
RXD
TXD
1
Receiver
Transmitter
RXD
TXD
1
724
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface
2. Values in the Version Register vary with the version of the IP block implementation.
Table 35-16. Register Mapping
Offset Register Name Access Reset
0x0000 Control Register US_CR Write-only –
0x0004 Mode Register US_MR Read-write –
0x0008 Interrupt Enable Register US_IER Write-only –
0x000C Interrupt Disable Register US_IDR Write-only –
0x0010 Interrupt Mask Register US_IMR Read-only 0x0
0x0014 Channel Status Register US_CSR Read-only –
0x0018 Receiver Holding Register US_RHR Read-only 0x0
0x001C Transmitter Holding Register US_THR Write-only –
0x0020 Baud Rate Generator Register US_BRGR Read-write 0x0
0x0024 Receiver Time-out Register US_RTOR Read-write 0x0
0x0028 Transmitter Timeguard Register US_TTGR Read-write 0x0
0x2C - 0x3C Reserved – – –
0x0040 FI DI Ratio Register US_FIDI Read-write 0x174
0x0044 Number of Errors Register US_NER Read-only –
0x0048 Reserved – – –
0x004C IrDA Filter Register US_IF Read-write 0x0
0x0050 Manchester Encoder Decoder Register US_MAN Read-write 0xB0011004
0xE4 Write Protect Mode Register US_WPMR Read-write 0x0
0xE8 Write Protect Status Register US_WPSR Read-only 0x0
0x5C - 0xF8 Reserved – – –
0xFC Version Register US_VERSION Read-only 0x–(2)
0x100 - 0x128 Reserved for PDC Registers – – –
725
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.1 USART Control Register
Name: US_CR
Address: 0x40024000 (0), 0x40028000 (1)
Access: Write-only
For SPI control, see “USART Control Register (SPI_MODE)” on page 727.
• RSTRX: Reset Receiver
0: No effect.
1: Resets the receiver.
• RSTTX: Reset Transmitter
0: No effect.
1: Resets the transmitter.
• RXEN: Receiver Enable
0: No effect.
1: Enables the receiver, if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: Disables the receiver.
• TXEN: Transmitter Enable
0: No effect.
1: Enables the transmitter if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: Disables the transmitter.
• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – RTSDIS RTSEN DTRDIS DTREN
15 14 13 12 11 10 9 8
RETTO RSTNACK RSTIT SENDA STTTO STPBRK STTBRK RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –
726
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• STTBRK: Start Break
0: No effect.
1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted.
No effect if a break is already being transmitted.
• STPBRK: Stop Break
0: No effect.
1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No
effect if no break is being transmitted.
• STTTO: Start Time-out
0: No effect.
1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR.
• SENDA: Send Address
0: No effect.
1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.
• RSTIT: Reset Iterations
0: No effect.
1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled.
• RSTNACK: Reset Non Acknowledge
0: No effect
1: Resets NACK in US_CSR.
• RETTO: Rearm Time-out
0: No effect
1: Restart Time-out
• DTREN: Data Terminal Ready Enable
0: No effect.
1: Drives the pin DTR to 0.
• DTRDIS: Data Terminal Ready Disable
0: No effect.
1: Drives the pin DTR to 1.
• RTSEN: Request to Send Enable
0: No effect.
1: Drives the pin RTS to 0.
• RTSDIS: Request to Send Disable
0: No effect.
1: Drives the pin RTS to 1.
727
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.2 USART Control Register (SPI_MODE)
Name: US_CR (SPI_MODE)
Address: 0x40024000 (0), 0x40028000 (1)
Access: Write-only
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 729.
• RSTRX: Reset Receiver
0: No effect.
1: Resets the receiver.
• RSTTX: Reset Transmitter
0: No effect.
1: Resets the transmitter.
• RXEN: Receiver Enable
0: No effect.
1: Enables the receiver, if RXDIS is 0.
• RXDIS: Receiver Disable
0: No effect.
1: Disables the receiver.
• TXEN: Transmitter Enable
0: No effect.
1: Enables the transmitter if TXDIS is 0.
• TXDIS: Transmitter Disable
0: No effect.
1: Disables the transmitter.
• RSTSTA: Reset Status Bits
0: No effect.
1: Resets the status bits OVRE, UNRE in US_CSR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – RCS FCS – –
15 14 13 12 11 10 9 8
–––––––RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –
728
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• FCS: Force SPI Chip Select
– Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE):
FCS = 0: No effect.
FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave
devices supporting the CSAAT Mode (Chip Select Active After Transfer).
• RCS: Release SPI Chip Select
– Applicable if USART operates in SPI Master Mode (USART_MODE = 0xE):
RCS = 0: No effect.
RCS = 1: Releases the Slave Select Line NSS (RTS pin).
729
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.3 USART Mode Register
Name: US_MR
Address: 0x40024004 (0), 0x40028004 (1)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756.
For SPI configuration, see “USART Mode Register (SPI_MODE)” on page 732.
• USART_MODE: USART Mode of Operation
• USCLKS: Clock Selection
31 30 29 28 27 26 25 24
ONEBIT MODSYNC MAN FILTER – MAX_ITERATION
23 22 21 20 19 18 17 16
INVDATA VAR_SYNC DSNACK INACK OVER CLKO MODE9 MSBF
15 14 13 12 11 10 9 8
CHMODE NBSTOP PAR SYNC
76543210
CHRL USCLKS USART_MODE
Value Name Description
0x0 NORMAL Normal mode
0x1 RS485 RS485
0x2 HW_HANDSHAKING Hardware Handshaking
0x3 MODEM Modem
0x4 IS07816_T_0 IS07816 Protocol: T = 0
0x6 IS07816_T_1 IS07816 Protocol: T = 1
0x8 IRDA IrDA
0xE SPI_MASTER SPI Master
0xF SPI_SLAVE SPI Slave
Value Name Description
0 MCK Master Clock MCK is selected
1 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected
3 SCK Serial Clock SLK is selected
730
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• CHRL: Character Length.
• SYNC: Synchronous Mode Select
0: USART operates in Asynchronous Mode.
1: USART operates in Synchronous Mode.
• PAR: Parity Type
• NBSTOP: Number of Stop Bits
• CHMODE: Channel Mode
• MSBF: Bit Order
0: Least Significant Bit is sent/received first.
1: Most Significant Bit is sent/received first.
• MODE9: 9-bit Character Length
0: CHRL defines character length.
1: 9-bit character length.
Value Name Description
0 5_BIT Character length is 5 bits
1 6_BIT Character length is 6 bits
2 7_BIT Character length is 7 bits
3 8_BIT Character length is 8 bits
Value Name Description
0 EVEN Even parity
1 ODD Odd parity
2 SPACE Parity forced to 0 (Space)
3 MARK Parity forced to 1 (Mark)
4 NO No parity
6 MULTIDROP Multidrop mode
Value Name Description
0 1_BIT 1 stop bit
1 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
2 2_BIT 2 stop bits
Value Name Description
0 NORMAL Normal Mode
1 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin.
2 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input.
3 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin.
731
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• CLKO: Clock Output Select
0: The USART does not drive the SCK pin.
1: The USART drives the SCK pin if USCLKS does not select the external clock SCK.
• OVER: Oversampling Mode
0: 16x Oversampling.
1: 8x Oversampling.
• INACK: Inhibit Non Acknowledge
0: The NACK is generated.
1: The NACK is not generated.
• DSNACK: Disable Successive NACK
0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set).
1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a
NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is
asserted.
• INVDATA: Inverted Data
0: The data field transmitted on TXD line is the same as the one written in US_THR register or the content read in US_RHR is the
same as RXD line. Normal mode of operation.
1: The data field transmitted on TXD line is inverted (voltage polarity only) compared to the value written on US_THR register or
the content read in US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line). Inverted Mode of opera-
tion, useful for contactless card application. To be used with configuration bit MSBF.
• VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter
0: User defined configuration of command or data sync field depending on MODSYNC value.
1: The sync field is updated when a character is written into US_THR register.
• MAX_ITERATION: Maximum Number of Automatic Iteration
0 - 7: Defines the maximum number of iterations in mode ISO7816, protocol T= 0.
• FILTER: Infrared Receive Line Filter
0: The USART does not filter the receive line.
1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
• MAN: Manchester Encoder/Decoder Enable
0: Manchester Encoder/Decoder are disabled.
1: Manchester Encoder/Decoder are enabled.
• MODSYNC: Manchester Synchronization Mode
0:The Manchester Start bit is a 0 to 1 transition
1: The Manchester Start bit is a 1 to 0 transition.
• ONEBIT: Start Frame Delimiter Selector
0: Start Frame delimiter is COMMAND or DATA SYNC.
1: Start Frame delimiter is One Bit.
732
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.4 USART Mode Register (SPI_MODE)
Name: US_MR (SPI_MODE)
Address: 0x40024004 (0), 0x40028004 (1)
Access: Read-write
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 729.
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756.
• USART_MODE: USART Mode of Operation
• USCLKS: Clock Selection
• CHRL: Character Length.
• CPHA: SPI Clock Phase
– Applicable if USART operates in SPI Mode (USART_MODE = 0xE or 0xF):
CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with
CPOL to produce the required clock/data relationship between master and slave devices.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – WRDBT – CPOL
15 14 13 12 11 10 9 8
–––––––CPHA
76543210
CHRL USCLKS USART_MODE
Value Name Description
0xE SPI_MASTER SPI Master
0xF SPI_SLAVE SPI Slave
Value Name Description
0 MCK Master Clock MCK is selected
1 DIV Internal Clock Divided MCK/DIV (DIV=8) is selected
3 SCK Serial Clock SLK is selected
Value Name Description
3 8_BIT Character length is 8 bits
733
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• CHMODE: Channel Mode
• CPOL: SPI Clock Polarity
– Applicable if USART operates in SPI Mode (Slave or Master, USART_MODE = 0xE or 0xF):
CPOL = 0: The inactive state value of SPCK is logic level zero.
CPOL = 1: The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required
clock/data relationship between master and slave devices.
• WRDBT: Wait Read Data Before Transfer
0: The character transmission starts as soon as a character is written into US_THR register (assuming TXRDY was set).
1: The character transmission starts when a character is written and only if RXRDY flag is cleared (Receiver Holding Register has
been read).
Value Name Description
0 NORMAL Normal Mode
1 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin.
2 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input.
3 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin.
734
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.5 USART Interrupt Enable Register
Name: US_IER
Address: 0x40024008 (0), 0x40028008 (1)
Access: Write-only
For SPI specific configuration, see “USART Interrupt Enable Register (SPI_MODE)” on page 736.
• RXRDY: RXRDY Interrupt Enable
• TXRDY: TXRDY Interrupt Enable
• RXBRK: Receiver Break Interrupt Enable
• ENDRX: End of Receive Transfer Interrupt Enable (available in all USART modes of operation)
• ENDTX: End of Transmit Interrupt Enable (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Enable
• PARE: Parity Error Interrupt Enable
• TIMEOUT: Time-out Interrupt Enable
• TXEMPTY: TXEMPTY Interrupt Enable
• ITER: Max number of Repetitions Reached Interrupt Enable
• TXBUFE: Buffer Empty Interrupt Enable (available in all USART modes of operation)
• RXBUFF: Buffer Full Interrupt Enable (available in all USART modes of operation)
• NACK: Non Acknowledge Interrupt Enable
• RIIC: Ring Indicator Input Change Enable
• DSRIC: Data Set Ready Input Change Enable
• DCDIC: Data Carrier Detect Input Change Interrupt Enable
31 30 29 28 27 26 25 24
–––––––MANE
23 22 21 20 19 18 17 16
– – – – CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
735
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• CTSIC: Clear to Send Input Change Interrupt Enable
• MANE: Manchester Error Interrupt Enable
0: No effect
1: Enables the corresponding interrupt.
736
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.6 USART Interrupt Enable Register (SPI_MODE)
Name: US_IER (SPI_MODE)
Address: 0x40024008 (0), 0x40028008 (1)
Access: Write-only
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 729.
• RXRDY: RXRDY Interrupt Enable
• TXRDY: TXRDY Interrupt Enable
• OVRE: Overrun Error Interrupt Enable
• TXEMPTY: TXEMPTY Interrupt Enable
• UNRE: SPI Underrun Error Interrupt Enable
0: No effect
1: Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – – UNRE TXEMPTY –
76543210
– – OVRE – – – TXRDY RXRDY
737
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.7 USART Interrupt Disable Register
Name: US_IDR
Address: 0x4002400C (0), 0x4002800C (1)
Access: Write-only
For SPI specific configuration, see “USART Interrupt Disable Register (SPI_MODE)” on page 739.
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• RXBRK: Receiver Break Interrupt Disable
• ENDRX: End of Receive Transfer Interrupt Disable (available in all USART modes of operation)
• ENDTX: End of Transmit Interrupt Disable (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Enable
• FRAME: Framing Error Interrupt Disable
• PARE: Parity Error Interrupt Disable
• TIMEOUT: Time-out Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• ITER: Max Number of Repetitions Reached Interrupt Disable
• TXBUFE: Buffer Empty Interrupt Disable (available in all USART modes of operation)
• RXBUFF: Buffer Full Interrupt Disable (available in all USART modes of operation)
• NACK: Non Acknowledge Interrupt Disable
• RIIC: Ring Indicator Input Change Disable
• DSRIC: Data Set Ready Input Change Disable
• DCDIC: Data Carrier Detect Input Change Interrupt Disable
31 30 29 28 27 26 25 24
–––––––MANE
23 22 21 20 19 18 17 16
– – – – CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
738
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• CTSIC: Clear to Send Input Change Interrupt Disable
• MANE: Manchester Error Interrupt Disable
0: No effect
1: Disables the corresponding interrupt.
739
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.8 USART Interrupt Disable Register (SPI_MODE)
Name: US_IDR (SPI_MODE)
Address: 0x4002400C (0), 0x4002800C (1)
Access: Write-only
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 729.
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• UNRE: SPI Underrun Error Interrupt Disable
0: No effect
1: Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – – UNRE TXEMPTY –
76543210
– – OVRE – – – TXRDY RXRDY
740
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.9 USART Interrupt Mask Register
Name: US_IMR
Address: 0x40024010 (0), 0x40028010 (1)
Access: Read-only
For SPI specific configuration, see “USART Interrupt Mask Register (SPI_MODE)” on page 742.
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• RXBRK: Receiver Break Interrupt Mask
• ENDRX: End of Receive Transfer Interrupt Mask (available in all USART modes of operation)
• ENDTX: End of Transmit Interrupt Mask (available in all USART modes of operation)
• OVRE: Overrun Error Interrupt Mask
• FRAME: Framing Error Interrupt Mask
• PARE: Parity Error Interrupt Mask
• TIMEOUT: Time-out Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• ITER: Max Number of Repetitions Reached Interrupt Mask
• TXBUFE: Buffer Empty Interrupt Mask (available in all USART modes of operation)
• RXBUFF: Buffer Full Interrupt Mask (available in all USART modes of operation)
• NACK: Non Acknowledge Interrupt Mask
• RIIC: Ring Indicator Input Change Mask
• DSRIC: Data Set Ready Input Change Mask
• DCDIC: Data Carrier Detect Input Change Interrupt Mask
31 30 29 28 27 26 25 24
–––––––MANE
23 22 21 20 19 18 17 16
– – – – CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
741
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• CTSIC: Clear to Send Input Change Interrupt Mask
• MANE: Manchester Error Interrupt Mask
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
742
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.10 USART Interrupt Mask Register (SPI_MODE)
Name: US_IMR (SPI_MODE)
Address: 0x40024010 (0), 0x40028010 (1)
Access: Read-only
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 729.
• RXRDY: RXRDY Interrupt Mask
• TXRDY: TXRDY Interrupt Mask
• OVRE: Overrun Error Interrupt Mask
• TXEMPTY: TXEMPTY Interrupt Mask
• UNRE: SPI Underrun Error Interrupt Mask
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – – UNRE TXEMPTY –
76543210
– – OVRE – – – TXRDY RXRDY
743
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.11 USART Channel Status Register
Name: US_CSR
Address: 0x40024014 (0), 0x40028014 (1)
Access: Read-only
For SPI specific configuration, see “USART Channel Status Register (SPI_MODE)” on page 746.
• RXRDY: Receiver Ready
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being
received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been
requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1.
1: There is no character in the US_THR.
• RXBRK: Break Received/End of Break
0: No Break received or End of Break detected since the last RSTSTA.
1: Break Received or End of Break detected since the last RSTSTA.
• ENDRX: End of Receiver Transfer
0: The End of Transfer signal from the Receive PDC channel is inactive.
1: The End of Transfer signal from the Receive PDC channel is active.
• ENDTX: End of Transmitter Transfer
0: The End of Transfer signal from the Transmit PDC channel is inactive.
1: The End of Transfer signal from the Transmit PDC channel is active.
• OVRE: Overrun Error
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
• FRAME: Framing Error
0: No stop bit has been detected low since the last RSTSTA.
1: At least one stop bit has been detected low since the last RSTSTA.
31 30 29 28 27 26 25 24
–––––––MANERR
23 22 21 20 19 18 17 16
CTS DCD DSR RI CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
– – NACK RXBUFF TXBUFE ITER TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE ENDTX ENDRX RXBRK TXRDY RXRDY
744
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• PARE: Parity Error
0: No parity error has been detected since the last RSTSTA.
1: At least one parity error has been detected since the last RSTSTA.
• TIMEOUT: Receiver Time-out
0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0.
1: There has been a time-out since the last Start Time-out command (STTTO in US_CR).
• TXEMPTY: Transmitter Empty
0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1: There are no characters in US_THR, nor in the Transmit Shift Register.
• ITER: Max Number of Repetitions Reached
0: Maximum number of repetitions has not been reached since the last RSTSTA.
1: Maximum number of repetitions has been reached since the last RSTSTA.
• TXBUFE: Transmission Buffer Empty
0: The signal Buffer Empty from the Transmit PDC channel is inactive.
1: The signal Buffer Empty from the Transmit PDC channel is active.
• RXBUFF: Reception Buffer Full
0: The signal Buffer Full from the Receive PDC channel is inactive.
1: The signal Buffer Full from the Receive PDC channel is active.
• NACK: Non Acknowledge Interrupt
0: Non Acknowledge has not been detected since the last RSTNACK.
1: At least one Non Acknowledge has been detected since the last RSTNACK.
• RIIC: Ring Indicator Input Change Flag
0: No input change has been detected on the RI pin since the last read of US_CSR.
1: At least one input change has been detected on the RI pin since the last read of US_CSR.
• DSRIC: Data Set Ready Input Change Flag
0: No input change has been detected on the DSR pin since the last read of US_CSR.
1: At least one input change has been detected on the DSR pin since the last read of US_CSR.
• DCDIC: Data Carrier Detect Input Change Flag
0: No input change has been detected on the DCD pin since the last read of US_CSR.
1: At least one input change has been detected on the DCD pin since the last read of US_CSR.
• CTSIC: Clear to Send Input Change Flag
0: No input change has been detected on the CTS pin since the last read of US_CSR.
1: At least one input change has been detected on the CTS pin since the last read of US_CSR.
745
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• RI: Image of RI Input
0: RI is set to 0.
1: RI is set to 1.
• DSR: Image of DSR Input
0: DSR is set to 0
1: DSR is set to 1.
• DCD: Image of DCD Input
0: DCD is set to 0.
1: DCD is set to 1.
• CTS: Image of CTS Input
0: CTS is set to 0.
1: CTS is set to 1.
• MANERR: Manchester Error
0: No Manchester error has been detected since the last RSTSTA.
1: At least one Manchester error has been detected since the last RSTSTA.
746
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.12 USART Channel Status Register (SPI_MODE)
Name: US_CSR (SPI_MODE)
Address: 0x40024014 (0), 0x40028014 (1)
Access: Read-only
This configuration is relevant only if USART_MODE=0xE or 0xF in “USART Mode Register” on page 729.
• RXRDY: Receiver Ready
0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being
received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled.
1: At least one complete character has been received and US_RHR has not yet been read.
• TXRDY: Transmitter Ready
0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As soon as
the transmitter is enabled, TXRDY becomes 1.
1: There is no character in the US_THR.
• OVRE: Overrun Error
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
• TXEMPTY: Transmitter Empty
0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled.
1: There are no characters in US_THR, nor in the Transmit Shift Register.
• UNRE: Underrun Error
0: No SPI underrun error has occurred since the last RSTSTA.
1: At least one SPI underrun error has occurred since the last RSTSTA.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – – UNRE TXEMPTY –
76543210
– – OVRE – – – TXRDY RXRDY
747
SAM4S [DATASHEET]
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35.8.13 USART Receive Holding Register
Name: US_RHR
Address: 0x40024018 (0), 0x40028018 (1)
Access: Read-only
• RXCHR: Received Character
Last character received if RXRDY is set.
• RXSYNH: Received Sync
0: Last Character received is a Data.
1: Last Character received is a Command.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RXSYNH – – ––––RXCHR
76543210
RXCHR
748
SAM4S [DATASHEET]
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35.8.14 USART Transmit Holding Register
Name: US_THR
Address: 0x4002401C (0), 0x4002801C (1)
Access: Write-only
• TXCHR: Character to be Transmitted
Next character to be transmitted after the current character if TXRDY is not set.
• TXSYNH: Sync Field to be Transmitted
0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.
1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXSYNH – – ––––TXCHR
76543210
TXCHR
749
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.15 USART Baud Rate Generator Register
Name: US_BRGR
Address: 0x40024020 (0), 0x40028020 (1)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756.
• CD: Clock Divider
• FP: Fractional Part
0: Fractional divider is disabled.
1 - 7: Baud rate resolution, defined by FP x 1/8.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––– FP
15 14 13 12 11 10 9 8
CD
76543210
CD
CD
USART_MODE ≠ISO7816
USART_MODE =
ISO7816
SYNC = 0
SYNC = 1
or
USART_MODE = SPI
(Master or Slave)
OVER = 0 OVER = 1
0 Baud Rate Clock Disabled
1 to 65535 Baud Rate =
Selected Clock/(16*CD) Baud Rate =
Selected Clock/(8*CD) Baud Rate =
Selected Clock /CD Baud Rate = Selected
Clock/(FI_DI_RATIO*CD)
750
SAM4S [DATASHEET]
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35.8.16 USART Receiver Time-out Register
Name: US_RTOR
Address: 0x40024024 (0), 0x40028024 (1)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756.
• TO: Time-out Value
0: The Receiver Time-out is disabled.
1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TO
76543210
TO
751
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.17 USART Transmitter Timeguard Register
Name: US_TTGR
Address: 0x40024028 (0), 0x40028028 (1)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756.
• TG: Timeguard Value
0: The Transmitter Timeguard is disabled.
1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
TG
752
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.8.18 USART FI DI RATIO Register
Name: US_FIDI
Address: 0x40024040 (0), 0x40028040 (1)
Access: Read-write
Reset Value: 0x174
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756.
• FI_DI_RATIO: FI Over DI Ratio Value
0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal.
1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – – FI_DI_RATIO
76543210
FI_DI_RATIO
753
SAM4S [DATASHEET]
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35.8.19 USART Number of Errors Register
Name: US_NER
Address: 0x40024044 (0), 0x40028044 (1)
Access: Read-only
This register is relevant only if USART_MODE=0x4 or 0x6 in “USART Mode Register” on page 729.
• NB_ERRORS: Number of Errors
Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
35.8.20 USART IrDA FILTER Register
Name: US_IF
Address: 0x4002404C (0), 0x4002804C (1)
Access: Read-write
This register is relevant only if USART_MODE=0x8 in “USART Mode Register” on page 729.
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756.
• IRDA_FILTER: IrDA Filter
Sets the filter of the IrDA demodulator.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
NB_ERRORS
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
IRDA_FILTER
754
SAM4S [DATASHEET]
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35.8.21 USART Manchester Configuration Register
Name: US_MAN
Address: 0x40024050 (0), 0x40028050 (1)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “USART Write Protect Mode Register” on page 756.
• TX_PL: Transmitter Preamble Length
0: The Transmitter Preamble pattern generation is disabled
1 - 15: The Preamble Length is TX_PL x Bit Period
• TX_PP: Transmitter Preamble Pattern
The following values assume that TX_MPOL field is not set:
• TX_MPOL: Transmitter Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• RX_PL: Receiver Preamble Length
0: The receiver preamble pattern detection is disabled
1 - 15: The detected preamble length is RX_PL x Bit Period
31 30 29 28 27 26 25 24
– DRIFT ONE RX_MPOL – – RX_PP
23 22 21 20 19 18 17 16
– – – – RX_PL
15 14 13 12 11 10 9 8
– – – TX_MPOL – – TX_PP
76543210
–––– TX_PL
Value Name Description
00 ALL_ONE The preamble is composed of ‘1’s
01 ALL_ZERO The preamble is composed of ‘0’s
10 ZERO_ONE The preamble is composed of ‘01’s
11 ONE_ZERO The preamble is composed of ‘10’s
755
SAM4S [DATASHEET]
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• RX_PP: Receiver Preamble Pattern detected
The following values assume that RX_MPOL field is not set:
• RX_MPOL: Receiver Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• ONE: Must Be Set to 1
Bit 29 must always be set to 1 when programming the US_MAN register.
• DRIFT: Drift Compensation
0: The USART can not recover from an important clock drift
1: The USART can recover from clock drift. The 16X clock mode must be enabled.
Value Name Description
00 ALL_ONE The preamble is composed of ‘1’s
01 ALL_ZERO The preamble is composed of ‘0’s
10 ZERO_ONE The preamble is composed of ‘01’s
11 ONE_ZERO The preamble is composed of ‘10’s
756
SAM4S [DATASHEET]
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35.8.22 USART Write Protect Mode Register
Name: US_WPMR
Address: 0x400240E4 (0), 0x400280E4 (1)
Access: Read-write
Reset: See Table 35-16
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x555341 (“USA” in ASCII).
Protects the registers:
•“USART Mode Register” on page 729
•“USART Baud Rate Generator Register” on page 749
•“USART Receiver Time-out Register” on page 750
•“USART Transmitter Timeguard Register” on page 751
•“USART FI DI RATIO Register” on page 752
•“USART IrDA FILTER Register” on page 753
•“USART Manchester Configuration Register” on page 754
• WPKEY: Write Protect KEY
Should be written at value 0x555341 (“USA” in ASCII). Writing any other value in this field aborts the write operation of the WPEN
bit. Always reads as 0.
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
———————WPEN
757
SAM4S [DATASHEET]
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35.8.23 USART Write Protect Status Register
Name: US_WPSR
Address: 0x400240E8 (0), 0x400280E8 (1)
Access: Read-only
Reset: See Table 35-16
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the US_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the US_WPSR register. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has
been attempted.
Note: Reading US_WPSR automatically clears all fields.
31 30 29 28 27 26 25 24
————————
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
———————WPVS
758
SAM4S [DATASHEET]
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35.8.24 USART Version Register
Name: US_VERSION
Address: 0x400240FC (0), 0x400280FC (1)
Access: Read-only
• VERSION: Hardware Module Version
Reserved. Value subject to change. No functionality associated. This is the Atmel internal version of the macrocell.
• MFN: Metal Fix Number
Reserved. Value subject to change. No functionality associated.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––– MFN
15 14 13 12 11 10 9 8
– – – – VERSION
76543210
VERSION
759
SAM4S [DATASHEET]
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36. Timer Counter (TC)
36.1 Description
The Timer Counter (TC) includes 3 identical 16-bit Timer Counter channels.
Each channel can be independently programmed to perform a wide range of functions including frequency
measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.
Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which
can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate
processor interrupts.
The Timer Counter (TC) embeds a quadrature decoder logic connected in front of the timers and driven by TIOA0, TIOB0
and TIOA1 inputs. When enabled, the quadrature decoder performs the input lines filtering, decoding of quadrature
signals and connects to the timers/counters in order to read the position and speed of the motor through the user
interface.
The Timer Counter block has two global registers which act upon all TC channels.
The Block Control Register allows the channels to be started simultaneously with the same instruction.
The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained.
Table 36-1 gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2.
Note: 1. When Slow Clock is selected for Master Clock (CSS = 0 in PMC Master Clock Register), TIMER_CLOCK5
input is equivalent to Master Clock.
36.2 Embedded Characteristics
Six 16-bit Timer Counter Channels
Wide range of functions including:
Frequency Measurement
Event Counting
Interval Measurement
Pulse Generation
Delay Timing
Pulse Width Modulation
Up/down Capabilities
Each channel is user-configurable and contains:
Three external clock inputs
Five internal clock inputs
Two multi-purpose input/output signals
Two global registers that act on all three TC Channels
Table 36-1. Timer Counter Clock Assignment
Name Definition
TIMER_CLOCK1 MCK/2
TIMER_CLOCK2 MCK/8
TIMER_CLOCK3 MCK/32
TIMER_CLOCK4 MCK/128
TIMER_CLOCK5(1) SLCK
760
SAM4S [DATASHEET]
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Quadrature decoder
Advanced line filtering
Position / revolution / speed
2-bit Gray Up/Down Counter for Stepper Motor
36.3 Block Diagram
Figure 36-1. Timer Counter Block Diagram
Note: The quadrature decoder logic connections are detailed in Figure 36-15 ”Predefined Connection of the Quadra-
ture Decoder with Timer Counters”
Timer/Counter
Channel 0
Timer/Counter
Channel 1
Timer/Counter
Channel 2
SYNC
Parallel I/O
Controller
TC1XC1S
TC0XC0S
TC2XC2S
INT0
INT1
INT2
TIOA0
TIOA1
TIOA2
TIOB0
TIOB1
TIOB2
XC0
XC1
XC2
XC0
XC1
XC2
XC0
XC1
XC2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TIOA1
TIOA2
TIOA0
TIOA2
TIOA0
TIOA1
Interrupt
Controller
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Timer Counter
TIOA
TIOB
TIOA
TIOB
TIOA
TIOB
SYNC
SYNC
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
TIMER_CLOCK1
FAULT
PWM
Table 36-2. Signal Name Description
Block/Channel Signal Name Description
Channel Signal
XC0, XC1, XC2 External Clock Inputs
TIOA Capture Mode: Timer Counter Input
Waveform Mode: Timer Counter Output
TIOB Capture Mode: Timer Counter Input
Waveform Mode: Timer Counter Input/Output
INT Interrupt Signal Output (internal signal)
SYNC Synchronization Input Signal (from configuration register)
761
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36.4 Pin Name List
36.5 Product Dependencies
36.5.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiple xed with PIO lines. The programmer must
first program the PIO controllers to assign the TC pins to their peripheral functions.
36.5.2 Power Management
The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC
to enable the Timer Counter clock.
Table 36-3. TC pin list
Pin Name Description Type
TCLK0-TCLK2 External Clock Input Input
TIOA0-TIOA2 I/O Line A I/O
TIOB0-TIOB2 I/O Line B I/O
Table 36-4. I/O Lines
Instance Signal I/O Line Peripheral
TC0 TCLK0 PA4 B
TC0 TCLK1 PA28 B
TC0 TCLK2 PA29 B
TC0 TIOA0 PA0 B
TC0 TIOA1 PA15 B
TC0 TIOA2 PA26 B
TC0 TIOB0 PA1 B
TC0 TIOB1 PA16 B
TC0 TIOB2 PA27 B
TC1 TCLK3 PC25 B
TC1 TCLK4 PC28 B
TC1 TCLK5 PC31 B
TC1 TIOA3 PC23 B
TC1 TIOA4 PC26 B
TC1 TIOA5 PC29 B
TC1 TIOB3 PC24 B
TC1 TIOB4 PC27 B
TC1 TIOB5 PC30 B
762
SAM4S [DATASHEET]
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36.5.3 Interrupt
The TC has an interrupt line connected to the Interrupt Controller (IC). Handling the TC interrupt requires programming
the IC before configuring the TC.
36.5.4 Fault Output
The TC has the FAULT output internally connected to the fault input of PWM. Refer to Section 36.6.17 ”Fault Mode”, and
to the product Pulse Width Modulation (PWM) implementation.
36.6 Functional Description
36.6.1 TC Description
The 3 channels of the Timer Counter are independent and identical in operation except when quadrature decoder is
enabled. The registers for channel programming are listed in Table 36-5 on page 783.
36.6.2 16-bit Counter
Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the
selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the
COVFS bit in TC_SR (Status Register) is set.
The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter
can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock.
36.6.3 Clock Selection
At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or
TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR
(Block Mode). See Figure 36-2 ”Clock Chaining Selection”.
Each channel can independently select an internal or external clock source for its counter:
• Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4,
TIMER_CLOCK5
• External clock signals: XC0, XC1 or XC2
This selection is made by the TCCLKS bits in the TC Channel Mode Register.
The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the
clock.
The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode
Register defines this signal (none, XC0, XC1, XC2). See Figure 36-3 ”Clock Selection”
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock
period. The external clock frequency must be at least 2.5 times lower than the master clock
763
SAM4S [DATASHEET]
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Figure 36-2. Clock Chaining Selection
Figure 36-3. Clock Selection
Timer/Counter
Channel 0
SYNC
TC0XC0S
TIOA0
TIOB0
XC0
XC1 = TCLK1
XC2 = TCLK2
TCLK0 TIOA1
TIOA2
Timer/Counter
Channel 1
SYNC
TC1XC1S
TIOA1
TIOB1
XC0 = TCLK0
XC1
XC2 = TCLK2
TCLK1 TIOA0
TIOA2
Timer/Counter
Channel 2
SYNC
TC2XC2S
TIOA2
TIOB2
XC0 = TCLK0
XC1 = TCLK1
XC2
TCLK2 TIOA0
TIOA1
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
TCCLKS
CLKI
Synchronous
Edge Detection
BURST
MCK
1
Selected
Clock
764
SAM4S [DATASHEET]
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36.6.4 Clock Control
The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See
Figure 36-4.
• The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control
Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In
Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When
disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-
enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register.
• The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the
clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP=1inTC_CMR) or a RC
compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect
only if the clock is enabled.
Figure 36-4. Clock Control
36.6.5 TC Operating Modes
Each channel can independently operate in two different modes:
• Capture Mode provides measurement on signals.
• Waveform Mode provides wave generation.
The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register.
In Capture Mode, TIOA and TIOB are configured as inputs.
In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the
external trigger.
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
Stop
Event Disable
Event
Counter
Clock
Selected
Clock Trigger
765
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36.6.6 Trigger
A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth
external trigger is available to each mode.
Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means
that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is
selected as the clock.
The following triggers are common to both modes:
• Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR.
• SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a
software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block
Control) with SYNC set.
• Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value
matches the RC value if CPCTRG is set in TC_CMR.
The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be
selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following
signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG
in TC_CMR.
If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be
detected.
36.6.7 Capture Operating Mode
This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register).
Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and
phase on TIOA and TIOB signals which are considered as inputs.
Figure 36-5 shows the configuration of the TC channel when programmed in Capture Mode.
36.6.8 Capture Registers A and B
Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value
when a programmable event occurs on the signal TIOA.
The LDRA parameter in TC_CMR defines the TIOA selected edge for the loading of register A, and the LDRB parameter
defines the TIOA selected edge for the loading of Register B.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status
Register). In this case, the old value is overwritten.
766
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36.6.9 Trigger Conditions
In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined.
The ABETRG bit in the TC_CMR register selects TIOA or TIOB input signal as an external trigger. The ETRGEDG
parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the
external trigger is disabled.
TIOA
RA
RB
Transfer to System Memory
Internal PDC trigger
RA RB RA RB
T1,T2,T3,T4 = System Bus load dependent (Tmin = 8 MCK)
T1 T2 T3 T4
ETRGEDG=3, LDRA=3, LDRB=0, ABETRG=0
TIOB
TIOA
RA
Transfer to System Memory
Internal PDC trigger
RA RA
T
1,T2,T3,T4 = System Bus load dependent (Tmin = 8 MCK)
T1 T2 T3 T
4
RA R
A
767
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 36-5. Capture Mode
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
BURST
TIOB
Register C
Capture
Register A Capture
Register B Compare RC =
Counter
ABETRG
SWTRG
ETRGEDG CPCTRG
TC1_IMR
Trig
LDRBS
LDRAS
ETRGS
TC1_SR
LOVRS
COVFS
SYNC
1
MTIOB
TIOA
MTIOA
LDRA
LDBSTOP
If RA is not loaded
or RB is Loaded If RA is Loaded
LDBDIS
CPCS
INT
Edge
Detector
Edge
Detector
LDRB
Edge
Detector
CLK OVF
RESET
Timer/Counter Channel
MCK
Synchronous
Edge Detection
768
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.6.10 Waveform Operating Mode
Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register).
In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently
programmable duty cycles, or generates different types of one-shot or repetitive pulses.
In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event
(EEVT parameter in TC_CMR).
Figure 36-6 shows the configuration of the TC channel when programmed in Waveform Operating Mode.
36.6.11 Waveform Selection
Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies.
With any selection, RA, RB and RC can all be used as compare registers.
RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured)
and RC Compare is used to control TIOA and/or TIOB outputs.
769
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 36-6. Waveform Mode
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
CPCDIS
BURST
TIOB
Register A Register B Register C
Compare RA = Compare RB = Compare RC =
CPCSTOP
Counter
EEVT
EEVTEDG
SYNC
SWTRG
ENETRG
WAVSEL
TC1_IMR
Trig
ACPC
ACPA
AEEVT
ASWTRG
BCPC
BCPB
BEEVT
BSWTRG
TIOA
MTIOA
TIOB
MTIOB
CPAS
COVFS
ETRGS
TC1_SR
CPCS
CPBS
CLK OVF
RESET
Output ControllerOutput Controller
INT
1
Edge
Detector
Timer/Counter Channel
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC0
XC1
XC2
WAVSEL
MCK
Synchronous
Edge Detection
770
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.6.11.1WAVSEL = 00
When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value
of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 36-7.
An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may
occur at any time. See Figure 36-8.
RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop
the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR).
Figure 36-7. WAVSEL= 00 without trigger
Figure 36-8. WAVSEL= 00 with trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with 0xFFFF
0xFFFF
Waveform Examples
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with 0xFFFF
0xFFFF
Waveform Examples
Counter cleared by trigger
771
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.6.11.2WAVSEL = 10
When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC
Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 36-9.
It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are
programmed correctly. See Figure 36-10.
In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock
(CPCDIS = 1 in TC_CMR).
Figure 36-9. WAVSEL = 10 Without Trigger
Figure 36-10.WAVSEL = 10 With Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with RC
0xFFFF
Waveform Examples
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with RC
0xFFFF
Waveform Examples
Counter cleared by trigger
772
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.6.11.3WAVSEL = 01
When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of
TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 36-11.
A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV
is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments.
See Figure 36-12.
RC Compare cannot be programmed to generate a trigger in this configuration.
At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS =
1).
Figure 36-11.WAVSEL = 01 Without Trigger
Figure 36-12.WAVSEL = 01 With Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter decremented by compare match with 0xFFFF
0xFFFF
Waveform Examples
Time
Counter Value
TIOB
TIOA
Counter decremented by compare match with 0xFFFF
0xFFFF
Waveform Examples
Counter decremented
by trigger
Counter incremented
by trigger
RC
RB
RA
773
SAM4S [DATASHEET]
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36.6.11.4WAVSEL = 11
When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is
decremented to 0, then re-incremented to RC and so on. See Figure 36-13.
A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV
is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments.
See Figure 36-14.
RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1).
Figure 36-13.WAVSEL = 11 Without Trigger
Figure 36-14.WAVSEL = 11 With Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter decremented by compare match with RC
0xFFFF
Waveform Examples
Time
Counter Value
TIOB
TIOA
Counter decremented by compare match with RC
0xFFFF
Waveform Examples
Counter decremented
by trigger
Counter incremented
by trigger
RC
RB
RA
774
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.6.12 External Event/Trigger Conditions
An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The
external event selected can then be used as a trigger.
The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for
each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register
B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a
waveform on TIOA.
When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR.
As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be
used as a trigger depending on the parameter WAVSEL.
36.6.13 Output Controller
Timer/Counter
Channel 0
TC_EMR0.TRIGSRCA
TIOA0
TIOA0
TC_EMR0.TRIGSRCB
TIOB0
TIOB0
Timer/Counter
Channel 1
TC_EMR1.TRIGSRCA
TIOA1
TIOA1
TC_EMR1.TRIGSRCB
TIOB1
TIOB1
Timer/Counter
Channel 2
TC_EMR2.TRIGSRCA
TIOA2
TIOA2
TC_EMR2TRIGSRCB
TIOB2
TIOB2
PWM comparator outputs (internal signals)
respectively source of PWMH/L[2:0]
Timer/Counter
775
SAM4S [DATASHEET]
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The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if
TIOB is defined as output (not as an external event).
The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls
TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as
defined in the corresponding parameter in TC_CMR.
36.6.14 Quadrature Decoder Logic
36.6.14.1Description
The quadrature decoder logic is driven by TIOA0, TIOB0, TIOB1 input pins and drives the timer/counter of channel 0 and
1. Channel 2 can be used as a time base in case of speed measurement requirements (refer to Figure 36.7 ”Timer
Counter (TC) User Interface”).
When writing 0 in the QDEN field of the TC_BMR register, the quadrature decoder logic is totally transparent.
TIOA0 and TIOB0 are to be driven by the 2 dedicated quadrature signals from a rotary sensor mounted on the shaft of
the off-chip motor.
A third signal from the rotary sensor can be processed through pin TIOB1 and is typically dedicated to be driven by an
index signal if it is provided by the sensor. This signal is not required to decode the quadrature signals PHA, PHB.
TCCLKS field of TC_CMR channels must be configured to select XC0 input (i.e. 0x101). TC0XC0S field has no effect as
soon as quadrature decoder is enabled.
Either speed or position/revolution can be measured. Position channel 0 accumulates the edges of PHA, PHB input
signals giving a high accuracy on motor position whereas channel 1 accumulates the index pulses of the sensor,
therefore the number of rotations. Concatenation of both values provides a high level of precision on motion system
position.
In speed mode, position cannot be measured but revolution can be measured.
Inputs from the rotary sensor can be filtered prior to down-stream processing. Accommodation of input polarity, phase
definition and other factors are configurable.
Interruptions can be generated on different events.
A compare function (using TC_RC register) is available on channel 0 (speed/position) or channel 1 (rotation) and can
generate an interrupt by means of the CPCS flag in the TC_SR registers.
776
SAM4S [DATASHEET]
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Figure 36-15.Predefined Connection of the Quadrature Decoder with Timer Counters
36.6.14.2Input Pre-processing
Input pre-processing consists of capabilities to take into account rotary sensor factors such as polarities and phase
definition followed by configurable digital filtering.
Each input can be negated and swapping PHA, PHB is also configurable.
By means of the MAXFILT field in TC_BMR, it is possible to configure a minimum duration for which the pulse is stated
as valid. When the filter is active, pulses with a duration lower than MAXFILT+1 * tMCK ns are not passed to down-
stream logic.
Filters can be disabled using the FILTER field in the TC_BMR register.
Timer/Counter
Channel 0
1
XC0
TIOA
TIOB
Timer/Counter
Channel 1
1
XC0
TIOB
QDEN
Timer/Counter
Channel 2
1
TIOB0 XC0
1
1
SPEEDEN
1XC0
Quadrature
Decoder
(Filter + Edge
Detect + QD)
PHA
PHB
IDX
TIOA0
TIOB0
TIOB1
TIOB1
TIOA0
Index
Speed/Position
Rotation
Speed Time Base
Reset pulse
Direction
PHEdges QDEN
777
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 36-16.Input Stage
Input filtering can efficiently remove spurious pulses that might be generated by the presence of particulate
contamination on the optical or magnetic disk of the rotary sensor.
Spurious pulses can also occur in environments with high levels of electro-magnetic interference. Or, simply if vibration
occurs even when rotation is fully stopped and the shaft of the motor is in such a position that the beginning of one of the
reflective or magnetic bars on the rotary sensor disk is aligned with the light or magnetic (Hall) receiver cell of the rotary
sensor. Any vibration can make the PHA, PHB signals toggle for a short duration.
1
1
1
MAXFILT
PHA
PHB
IDX
TIOA0
TIOB0
TIOB1
INVA
1
INVB
1
INVIDX
SWAP
1
IDXPHB
Filter
Filter
Filter 1
FILTER
Direction
and
Edge
Detection
IDX
PHedge
DIR
Input Pre-Processing
778
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 36-17.Filtering Examples
PHA,B
Filter Out
MCK MAXFILT=2
particulate contamination
PHA
PHB motor shaft stopped in such a position that
rotary sensor cell is aligned with an edge of the disk
rotation
PHA
PHB
PHB Edge area due to system vibration
Resulting PHA, PHB electrical waveforms
PHA
Optical/Magnetic disk strips
stop
PHB
mechanical shock on system
vibration
stop
PHA, PHB electrical waveforms after filtering
PHA
PHB
779
SAM4S [DATASHEET]
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36.6.14.3Direction Status and Change Detection
After filtering, the quadrature signals are analyzed to extract the rotation direction and edges of the 2 quadrature signals
detected in order to be counted by timer/counter logic downstream.
The direction status can be directly read at anytime on TC_QISR register. The polarity of the direction flag status
depends on the configuration written in TC_BMR register. INVA, INVB, INVIDX, SWAP modify the polarity of DIR flag.
Any change in rotation direction is reported on TC_QISR register and can generate an interrupt.
The direction change condition is reported as soon as 2 consecutive edges on a phase signal have sampled the same
value on the other phase signal and there is an edge on the other signal. The 2 consecutive edges of 1 phase signal
sampling the same value on other phase signal is not sufficient to declare a direction change, for the reason that
particulate contamination may mask one or more reflective bar on the optical or magnetic disk of the sensor. (Refer to
Figure 36-18 ”Rotation Change Detection” for waveforms.)
Figure 36-18.Rotation Change Detection
The direction change detection is disabled when QDTRANS is set to 1 in TC_BMR. In this case the DIR flag report must
not be used.
A quadrature error is also reported by the quadrature decoder logic. Rather than reporting an error only when 2 edges
occur at the same time on PHA and PHB, which is unlikely to occur in real life, there is a report if the time difference
between 2 edges on PHA, PHB is lower than a predefined value. This predefined value is configurable and corresponds
PHA
PHB
Direction Change under normal conditions
DIR
DIRCHG
change condition
Report Time
No direction change due to particulate contamination masking a reflective bar
PHA
PHB
DIR
DIRCHG spurious change condition (if detected in a simple way)
same phase
missing pulse
780
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
to (MAXFILT+1) * tMCK ns. After being filtered there is no reason to have 2 edges closer than (MAXFILT+1) * tMCK ns
under normal mode of operation. In the instance an anomaly occurs, a quadrature error is reported on QERR flag on
TC_QISR register.
Figure 36-19.Quadrature Error Detection
MAXFILT must be tuned according to several factors such as the system clock frequency (MCK), type of rotary sensor
and rotation speed to be achieved.
36.6.14.4Position and Rotation Measurement
When POSEN is set in TC_BMR register, position is processed on channel 0 (by means of the PHA,PHB edge
detections) and motor revolutions are accumulated in channel 1 timer/counter and can be read through TC_CV0 and/or
TC_CV1 register if the IDX signal is provided on TIOB1 input.
Channel 0 and 1 must be configured in capture mode (WAVE = 0 in TC_CMR0).
In parallel, the number of edges are accumulated on timer/counter channel 0 and can be read on the TC_CV0 register.
Therefore, the accurate position can be read on both TC_CV registers and concatenated to form a 32-bit word.
The timer/counter channel 0 is cleared for each increment of IDX count value.
Depending on the quadrature signals, the direction is decoded and allows to count up or down in timer/counter channels
0 and 1. The direction status is reported on TC_QISR register.
MCK MAXFILT = 2
PHA
PHB
Abnormally formatted optical disk strips (theoretical view)
PHA
PHB
strip edge inaccurary due to disk etching/printing process
resulting PHA, PHB electrical waveforms
PHA
PHB
Even with an abnorrmaly formatted disk, there is no occurence of PHA, PHB switching at the same time.
QERR
duration < MAXFILT
781
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.6.14.5Speed Measurement
When SPEEDEN is set in TC_BMR register, the speed measure is enabled on channel 0.
A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2 must be configured in
waveform mode (WAVE bit field set) in TC_CMR2 register. WAVSEL bit field must be defined with 0x10 to clear the
counter by comparison and matching with TC_RC value. ACPC field must be defined at 0x11 to toggle TIOA output.
This time base is automatically fed back to TIOA of channel 0 when QDEN and SPEEDEN are set.
Channel 0 must be configured in capture mode (WAVE = 0 in TC_CMR0). ABETRG bit field of TC_CMR0 must be
configured at 1 to get TIOA as a trigger for this channel.
EDGTRG can be set to 0x01, to clear the counter on a rising edge of the TIOA signal and L DRA field mu st be set
accordingly to 0x01, to load TC_RA0 at the same time as the counter is cleared (LDRB must be set to 0x01). As a
consequence, at the end of each time base period the differentiation required for the speed calculation is performed.
The process must be started by configuring the TC_CR register with CLKEN and SWTRG.
The speed can be read on TC_RA0 register in TC_CMR0.
Channel 1 can still be used to count the number of revolutions of the motor.
36.6.15 2-bit Gray Up/Down Counter for Stepper Motor
Each channel can be independently configured to generate a 2-bit gray count waveform on corresponding TIOA,TIOB
outputs by means of GCEN bit in TC_SMMRx registers.
Up or Down count can be defined by writing bit DOWN in TC_SMMRx registers.
It is mandatory to configure the channel in WAVE mode in TC_CMR register.
The period of the counters can be programmed on TC_RCx registers.
Figure 36-20.2-bit Gray Up/Down Counter.
36.6.16 Write Protection System
In order to bring security to the Timer Counter, a write protection system has been implemented.
The write protection mode prevent the write of TC_BMR, TC_FMR, TC_CMRx, TC_SMMRx, TC_RAx, TC_RBx,
TC_RCx registers. When this mode is enabled and one of the protected registers write, the register write request
canceled.
Due to the nature of the write protection feature, enabling and disabling the write protection mode requires the use of a
security code. Thus when enabling or disabling the write protection mode the WPKEY field of the TC_WPMR register
must be filled with the “TIM” ASCII code (corresponding to 0x54494D) otherwise the register write will be canceled.
TIOAx
TIOBx
DOWNx
TC_RCx
WAVEx = GCENx =1
782
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.6.17 Fault Mode
At anytime, the TC_RCx registers can be used to perform a comparison on the respective current channel counter value
(TC_CVx) with the value of TC_RCx register.
The CPCSx flags can be set accordingly and an interrupt can be generated.
This interrupt is processed but requires an unpredictable amount of time to be achieve the required action.
It is possible to trigger the FAULT output of the TIMER1 with CPCS from TC_SR0 register and/or CPCS from TC_SR1
register. Each source can be independently enabled/disabled by means of TC_FMR register.
This can be useful to detect an overflow on speed and/or position when QDEC is processed and to act immediately by
using the FAULT output.
Figure 36-21.Fault Output Generation
TC_SR0 flag CPCS
TC_FMR / ENCF0 FAULT (to PWM input)
OR
AND
AND
TC_SR1 flag CPCS
TC_FMR / ENCF1
783
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7 Timer Counter (TC) User Interface
Notes: 1. Channel index ranges from 0 to 2.
2. Read-only if WAVE = 0
Table 36-5. Register Mapping
Offset(1) Register Name Access Reset
0x00 + channel * 0x40 + 0x00 Channel Control Register TC_CCR Write-only –
0x00 + channel * 0x40 + 0x04 Channel Mode Register TC_CMR Read-write 0
0x00 + channel * 0x40 + 0x08 Stepper Motor Mode Register TC_SMMR Read-write 0
0x00 + channel * 0x40 + 0x0C Reserved
0x00 + channel * 0x40 + 0x10 Counter Value TC_CV Read-only 0
0x00 + channel * 0x40 + 0x14 Register A TC_RA Read-write(2) 0
0x00 + channel * 0x40 + 0x18 Register B TC_RB Read-write(2) 0
0x00 + channel * 0x40 + 0x1C Register C TC_RC Read-write 0
0x00 + channel * 0x40 + 0x20 Status Register TC_SR Read-only 0
0x00 + channel * 0x40 + 0x24 Interrupt Enable Register TC_IER Write-only –
0x00 + channel * 0x40 + 0x28 Interrupt Disable Register TC_IDR Write-only –
0x00 + channel * 0x40 + 0x2C Interrupt Mask Register TC_IMR Read-only 0
0xC0 Block Control Register TC_BCR Write-only –
0xC4 Block Mode Register TC_BMR Read-write 0
0xC8 QDEC Interrupt Enable Register TC_QIER Write-only –
0xCC QDEC Interrupt Disable Register TC_QIDR Write-only –
0xD0 QDEC Interrupt Mask Register TC_QIMR Read-only 0
0xD4 QDEC Interrupt Status Register TC_QISR Read-only 0
0xD8 Fault Mode Register TC_FMR Read-write 0
0xE4 Write Protect Mode Register TC_WPMR Read-write 0
0xE8 - 0xFC Reserved – – –
784
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.1 TC Channel Control Register
Name: TC_CCRx [x=0..2]
Address: 0x40010000 (0)[0], 0x40010040 (0)[1], 0x40010080 (0)[2], 0x40014000 (1)[0], 0x40014040 (1)[1],
0x40014080 (1)[2]
Access: Write-only
• CLKEN: Counter Clock Enable Command
0 = No effect.
1 = Enables the clock if CLKDIS is not 1.
• CLKDIS: Counter Clock Disable Command
0 = No effect.
1 = Disables the clock.
• SWTRG: Software Trigger Command
0 = No effect.
1 = A software trigger is performed: the counter is reset and the clock is started.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––SWTRGCLKDISCLKEN
785
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.2 TC Channel Mode Register: Capture Mode
Name: TC_CMRx [x=0..2] (WAVE = 0)
Address: 0x40010004 (0)[0], 0x40010044 (0)[1], 0x40010084 (0)[2], 0x40014004 (1)[0], 0x40014044 (1)[1],
0x40014084 (1)[2]
Access: Read-write
This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register” on page 808
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• LDBSTOP: Counter Clock Stopped with RB Loading
0 = Counter clock is not stopped when RB loading occurs.
1 = Counter clock is stopped when RB loading occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––– LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG – – – ABETRG ETRGEDG
76543210
LDBDIS LDBSTOP BURST CLKI TCCLKS
Value Name Description
0 TIMER_CLOCK1 Clock selected: TCLK1
1 TIMER_CLOCK2 Clock selected: TCLK2
2 TIMER_CLOCK3 Clock selected: TCLK3
3 TIMER_CLOCK4 Clock selected: TCLK4
4 TIMER_CLOCK5 Clock selected: TCLK5
5 XC0 Clock selected: XC0
6 XC1 Clock selected: XC1
7 XC2 Clock selected: XC2
Value Name Description
0 NONE The clock is not gated by an external signal.
1 XC0 XC0 is ANDed with the selected clock.
2 XC1 XC1 is ANDed with the selected clock.
3 XC2 XC2 is ANDed with the selected clock.
786
SAM4S [DATASHEET]
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• LDBDIS: Counter Clock Disable with RB Loading
0 = Counter clock is not disabled when RB loading occurs.
1 = Counter clock is disabled when RB loading occurs.
• ETRGEDG: External Trigger Edge Selection
• ABETRG: TIOA or TIOB External Trigger Selection
0 = TIOB is used as an external trigger.
1 = TIOA is used as an external trigger.
• CPCTRG: RC Compare Trigger Enable
0 = RC Compare has no effect on the counter and its clock.
1 = RC Compare resets the counter and starts the counter clock.
• WAVE: Waveform Mode
0 = Capture Mode is enabled.
1 = Capture Mode is disabled (Waveform Mode is enabled).
• LDRA: RA Loading Edge Selection
• LDRB: RB Loading Edge Selection
Value Name Description
0 NONE The clock is not gated by an external signal.
1 RISING Rising edge
2 FALLING Falling edge
3 EDGE Each edge
Value Name Description
0 NONE None
1 RISING Rising edge of TIOA
2 FALLING Falling edge of TIOA
3 EDGE Each edge of TIOA
Value Name Description
0 NONE None
1 RISING Rising edge of TIOA
2 FALLING Falling edge of TIOA
3 EDGE Each edge of TIOA
787
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.3 TC Channel Mode Register: Waveform Mode
Name: TC_CMRx [x=0..2] (WAVE = 1)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register” on page 808
• TCCLKS: Clock Selection
• CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• CPCSTOP: Counter Clock Stopped with RC Compare
0 = Counter clock is not stopped when counter reaches RC.
1 = Counter clock is stopped when counter reaches RC.
31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE WAVSEL ENETRG EEVT EEVTEDG
76543210
CPCDIS CPCSTOP BURST CLKI TCCLKS
Value Name Description
0 TIMER_CLOCK1 Clock selected: TCLK1
1 TIMER_CLOCK2 Clock selected: TCLK2
2 TIMER_CLOCK3 Clock selected: TCLK3
3 TIMER_CLOCK4 Clock selected: TCLK4
4 TIMER_CLOCK5 Clock selected: TCLK5
5 XC0 Clock selected: XC0
6 XC1 Clock selected: XC1
7 XC2 Clock selected: XC2
Value Name Description
0 NONE The clock is not gated by an external signal.
1 XC0 XC0 is ANDed with the selected clock.
2 XC1 XC1 is ANDed with the selected clock.
3 XC2 XC2 is ANDed with the selected clock.
788
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• CPCDIS: Counter Clock Disable with RC Compare
0 = Counter clock is not disabled when counter reaches RC.
1 = Counter clock is disabled when counter reaches RC.
• EEVTEDG: External Event Edge Selection
• EEVT: External Event Selection
Signal selected as external event.
Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and
subsequently no IRQs.
• ENETRG: External Event Trigger Enable
0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA
output.
1 = The external event resets the counter and starts the counter clock.
• WAVSEL: Waveform Selection
• WAVE: Waveform Mode
0 = Waveform Mode is disabled (Capture Mode is enabled).
1 = Waveform Mode is enabled.
Value Name Description
0 NONE None
1 RISING Rising edge
2 FALLING Falling edge
3 EDGE Each edge
Value Name Description TIOB Direction
0 TIOB TIOB(1) input
1 XC0 XC0 output
2 XC1 XC1 output
3 XC2 XC2 output
Value Name Description
0 UP UP mode without automatic trigger on RC Compare
1 UPDOWN UPDOWN mode without automatic trigger on RC Compare
2 UP_RC UP mode with automatic trigger on RC Compare
3 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare
789
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• ACPA: RA Compare Effect on TIOA
• ACPC: RC Compare Effect on TIOA
• AEEVT: External Event Effect on TIOA
• ASWTRG: Software Trigger Effect on TIOA
• BCPB: RB Compare Effect on TIOB
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
790
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• BCPC: RC Compare Effect on TIOB
• BEEVT: External Event Effect on TIOB
• BSWTRG: Software Trigger Effect on TIOB
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
Value Name Description
0 NONE None
1 SET Set
2 CLEAR Clear
3 TOGGLE Toggle
791
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.4 TC Stepper Motor Mode Register
Name: TC_SMMRx [x=0..2]
Address: 0x40010008 (0)[0], 0x40010048 (0)[1], 0x40010088 (0)[2], 0x40014008 (1)[0], 0x40014048 (1)[1],
0x40014088 (1)[2]
Access: Read-write
This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register” on page 808
• GCEN: Gray Count Enable
0 = TIOAx [x=0..2] and TIOBx [x=0..2] are driven by internal counter of channel x.
1 = TIOAx [x=0..2] and TIOBx [x=0..2] are driven by a 2-bit gray counter.
• DOWN: DOWN Count
0 = Up counter.
1 = Down counter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––– –
15 14 13 12 11 10 9 8
––––––––
76543210
– DOWN GCEN
792
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.5 TC Counter Value Register
Name: TC_CVx [x=0..2]
Address: 0x40010010 (0)[0], 0x40010050 (0)[1], 0x40010090 (0)[2], 0x40014010 (1)[0], 0x40014050 (1)[1],
0x40014090 (1)[2]
Access: Read-only
• CV: Counter Value
CV contains the counter value in real time.
31 30 29 28 27 26 25 24
CV
23 22 21 20 19 18 17 16
CV
15 14 13 12 11 10 9 8
CV
76543210
CV
793
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.6 TC Register A
Name: TC_RAx [x=0..2]
Address: 0x40010014 (0)[0], 0x40010054 (0)[1], 0x40010094 (0)[2], 0x40014014 (1)[0], 0x40014054 (1)[1],
0x40014094 (1)[2]
Access: Read-only if WAVE = 0, Read-write if WAVE = 1
This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register” on page 808
• RA: Register A
RA contains the Register A value in real time.
36.7.7 TC Register B
Name: TC_RBx [x=0..2]
Address: 0x40010018 (0)[0], 0x40010058 (0)[1], 0x40010098 (0)[2], 0x40014018 (1)[0], 0x40014058 (1)[1],
0x40014098 (1)[2]
Access: Read-only if WAVE = 0, Read-write if WAVE = 1
This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register” on page 808
• RB: Register B
RB contains the Register B value in real time.
31 30 29 28 27 26 25 24
RA
23 22 21 20 19 18 17 16
RA
15 14 13 12 11 10 9 8
RA
76543210
RA
31 30 29 28 27 26 25 24
RB
23 22 21 20 19 18 17 16
RB
15 14 13 12 11 10 9 8
RB
76543210
RB
794
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.8 TC Register C
Name: TC_RCx [x=0..2]
Address: 0x4001001C (0)[0], 0x4001005C (0)[1], 0x4001009C (0)[2], 0x4001401C (1)[0], 0x4001405C (1)[1],
0x4001409C (1)[2]
Access: Read-write
This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register” on page 808
• RC: Register C
RC contains the Register C value in real time.
31 30 29 28 27 26 25 24
RC
23 22 21 20 19 18 17 16
RC
15 14 13 12 11 10 9 8
RC
76543210
RC
795
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.9 TC Status Register
Name: TC_SRx [x=0..2]
Address: 0x40010020 (0)[0], 0x40010060 (0)[1], 0x400100A0 (0)[2], 0x40014020 (1)[0], 0x40014060 (1)[1],
0x400140A0 (1)[2]
Access: Read-only
• COVFS: Counter Overflow Status
0 = No counter overflow has occurred since the last read of the Status Register.
1 = A counter overflow has occurred since the last read of the Status Register.
• LOVRS: Load Overrun Status
0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Reg-
ister, if WAVE = 0.
• CPAS: RA Compare Status
0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.
• CPBS: RB Compare Status
0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.
• CPCS: RC Compare Status
0 = RC Compare has not occurred since the last read of the Status Register.
1 = RC Compare has occurred since the last read of the Status Register.
• LDRAS: RA Loading Status
0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
• LDRBS: RB Loading Status
0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––MTIOBMTIOACLKSTA
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
796
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• ETRGS: External Trigger Status
0 = External trigger has not occurred since the last read of the Status Register.
1 = External trigger has occurred since the last read of the Status Register.
• CLKSTA: Clock Enabling Status
0 = Clock is disabled.
1 = Clock is enabled.
• MTIOA: TIOA Mirror
0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.
1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.
• MTIOB: TIOB Mirror
0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.
1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.
797
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.10 TC Interrupt Enable Register
Name: TC_IERx [x=0..2]
Address: 0x40010024 (0)[0], 0x40010064 (0)[1], 0x400100A4 (0)[2], 0x40014024 (1)[0], 0x40014064 (1)[1],
0x400140A4 (1)[2]
Access: Write-only
• COVFS: Counter Overflow
0 = No effect.
1 = Enables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0 = No effect.
1 = Enables the Load Overrun Interrupt.
• CPAS: RA Compare
0 = No effect.
1 = Enables the RA Compare Interrupt.
• CPBS: RB Compare
0 = No effect.
1 = Enables the RB Compare Interrupt.
• CPCS: RC Compare
0 = No effect.
1 = Enables the RC Compare Interrupt.
• LDRAS: RA Loading
0 = No effect.
1 = Enables the RA Load Interrupt.
• LDRBS: RB Loading
0 = No effect.
1 = Enables the RB Load Interrupt.
• ETRGS: External Trigger
0 = No effect.
1 = Enables the External Trigger Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
798
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.11 TC Interrupt Disable Register
Name: TC_IDRx [x=0..2]
Address: 0x40010028 (0)[0], 0x40010068 (0)[1], 0x400100A8 (0)[2], 0x40014028 (1)[0], 0x40014068 (1)[1],
0x400140A8 (1)[2]
Access: Write-only
• COVFS: Counter Overflow
0 = No effect.
1 = Disables the Counter Overflow Interrupt.
• LOVRS: Load Overrun
0 = No effect.
1 = Disables the Load Overrun Interrupt (if WAVE = 0).
• CPAS: RA Compare
0 = No effect.
1 = Disables the RA Compare Interrupt (if WAVE = 1).
• CPBS: RB Compare
0 = No effect.
1 = Disables the RB Compare Interrupt (if WAVE = 1).
• CPCS: RC Compare
0 = No effect.
1 = Disables the RC Compare Interrupt.
• LDRAS: RA Loading
0 = No effect.
1 = Disables the RA Load Interrupt (if WAVE = 0).
• LDRBS: RB Loading
0 = No effect.
1 = Disables the RB Load Interrupt (if WAVE = 0).
• ETRGS: External Trigger
0 = No effect.
1 = Disables the External Trigger Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
799
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.12 TC Interrupt Mask Register
Name: TC_IMRx [x=0..2]
Address: 0x4001002C (0)[0], 0x4001006C (0)[1], 0x400100AC (0)[2], 0x4001402C (1)[0], 0x4001406C (1)[1],
0x400140AC (1)[2]
Access: Read-only
• COVFS: Counter Overflow
0 = The Counter Overflow Interrupt is disabled.
1 = The Counter Overflow Interrupt is enabled.
• LOVRS: Load Overrun
0 = The Load Overrun Interrupt is disabled.
1 = The Load Overrun Interrupt is enabled.
• CPAS: RA Compare
0 = The RA Compare Interrupt is disabled.
1 = The RA Compare Interrupt is enabled.
• CPBS: RB Compare
0 = The RB Compare Interrupt is disabled.
1 = The RB Compare Interrupt is enabled.
• CPCS: RC Compare
0 = The RC Compare Interrupt is disabled.
1 = The RC Compare Interrupt is enabled.
• LDRAS: RA Loading
0 = The Load RA Interrupt is disabled.
1 = The Load RA Interrupt is enabled.
• LDRBS: RB Loading
0 = The Load RB Interrupt is disabled.
1 = The Load RB Interrupt is enabled.
• ETRGS: External Trigger
0 = The External Trigger Interrupt is disabled.
1 = The External Trigger Interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
800
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.13 TC Block Control Register
Name: TC_BCR
Address: 0x400100C0 (0), 0x400140C0 (1)
Access: Write-only
• SYNC: Synchro Command
0 = No effect.
1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SYNC
801
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.14 TC Block Mode Register
Name: TC_BMR
Address: 0x400100C4 (0), 0x400140C4 (1)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register” on page 808.
• TC0XC0S: External Clock Signal 0 Selection
• TC1XC1S: External Clock Signal 1 Selection
• TC2XC2S: External Clock Signal 2 Selection
• QDEN: Quadrature Decoder ENabled
0 = Disabled.
1 = Enables the quadrature decoder logic (filter, edge detection and quadrature decoding).
Quadrature decoding (direction change) can be disabled using QDTRANS bit.
One of the POSEN or SPEEDEN bits must be also enabled.
31 30 29 28 27 26 25 24
–––––– MAXFILT
23 22 21 20 19 18 17 16
MAXFILT FILTER – IDXPHB SWAP
15 14 13 12 11 10 9 8
INVIDX INVB INVA EDGPHA QDTRANS SPEEDEN POSEN QDEN
76543210
– – TC2XC2S TC1XC1S TC0XC0S
Value Name Description
0 TCLK0 Signal connected to XC0: TCLK0
1 – Reserved
2 TIOA1 Signal connected to XC0: TIOA1
3 TIOA2 Signal connected to XC0: TIOA2
Value Name Description
0 TCLK1 Signal connected to XC1: TCLK1
1 – Reserved
2 TIOA0 Signal connected to XC1: TIOA0
3 TIOA2 Signal connected to XC1: TIOA2
Value Name Description
0 TCLK2 Signal connected to XC2: TCLK2
1 – Reserved
2 TIOA1 Signal connected to XC2: TIOA1
3 TIOA2 Signal connected to XC2: TIOA2
802
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• POSEN: POSition ENabled
0 = Disable position.
1 = Enables the position measure on channel 0 and 1.
• SPEEDEN: SPEED ENabled
0 = Disabled.
1 = Enables the speed measure on channel 0, the time base being provided by channel 2.
• QDTRANS: Quadrature Decoding TRANSparent
0 = Full quadrature decoding logic is active (direction change detected).
1 = Quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed.
• EDGPHA: EDGe on PHA count mode
0 = Edges are detected on both PHA and PHB.
1 = Edges are detected on PHA only.
• INVA: INVerted phA
0 = PHA (TIOA0) is directly driving quadrature decoder logic.
1 = PHA is inverted before driving quadrature decoder logic.
• INVB: INVerted phB
0 = PHB (TIOB0) is directly driving quadrature decoder logic.
1 = PHB is inverted before driving quadrature decoder logic.
• SWAP: SWAP PHA and PHB
0 = No swap between PHA and PHB.
1 = Swap PHA and PHB internally, prior to driving quadrature decoder logic.
• INVIDX: INVerted InDeX
0 = IDX (TIOA1) is directly driving quadrature logic.
1 = IDX is inverted before driving quadrature logic.
• IDXPHB: InDeX pin is PHB pin
0 = IDX pin of the rotary sensor must drive TIOA1.
1 = IDX pin of the rotary sensor must drive TIOB0.
• FILTER:
0 = IDX,PHA, PHB input pins are not filtered.
1 = IDX,PHA, PHB input pins are filtered using MAXFILT value.
• MAXFILT: MAXimum FILTer
1.. 63: Defines the filtering capabilities.
Pulses with a period shorter than MAXFILT+1 MCK clock cycles are discarded.
803
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.15 TC QDEC Interrupt Enable Register
Name: TC_QIER
Address: 0x400100C8 (0), 0x400140C8 (1)
Access: Write-only
• IDX: InDeX
0 = No effect.
1 = Enables the interrupt when a rising edge occurs on IDX input.
• DIRCHG: DIRection CHanGe
0 = No effect.
1 = Enables the interrupt when a change on rotation direction is detected.
• QERR: Quadrature ERRor
0 = No effect.
1 = Enables the interrupt when a quadrature error occurs on PHA,PHB.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––QERRDIRCHG IDX
804
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.16 TC QDEC Interrupt Disable Register
Name: TC_QIDR
Address: 0x400100CC (0), 0x400140CC (1)
Access: Write-only
• IDX: InDeX
0 = No effect.
1 = Disables the interrupt when a rising edge occurs on IDX input.
• DIRCHG: DIRection CHanGe
0 = No effect.
1 = Disables the interrupt when a change on rotation direction is detected.
• QERR: Quadrature ERRor
0 = No effect.
1 = Disables the interrupt when a quadrature error occurs on PHA, PHB.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––QERRDIRCHG IDX
805
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.17 TC QDEC Interrupt Mask Register
Name: TC_QIMR
Address: 0x400100D0 (0), 0x400140D0 (1)
Access: Read-only
• IDX: InDeX
0 = The interrupt on IDX input is disabled.
1 = The interrupt on IDX input is enabled.
• DIRCHG: DIRection CHanGe
0 = The interrupt on rotation direction change is disabled.
1 = The interrupt on rotation direction change is enabled.
• QERR: Quadrature ERRor
0 = The interrupt on quadrature error is disabled.
1 = The interrupt on quadrature error is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––QERRDIRCHG IDX
806
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.18 TC QDEC Interrupt Status Register
Name: TC_QISR
Address: 0x400100D4 (0), 0x400140D4 (1)
Access: Read-only
• IDX: InDeX
0 = No Index input change since the last read of TC_QISR.
1 = The IDX input has changed since the last read of TC_QISR.
• DIRCHG: DIRection CHanGe
0 = No change on rotation direction since the last read of TC_QISR.
1 = The rotation direction changed since the last read of TC_QISR.
• QERR: Quadrature ERRor
0 = No quadrature error since the last read of TC_QISR.
1 = A quadrature error occurred since the last read of TC_QISR.
• DIR: DIRection
Returns an image of the actual rotation direction.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––––DIR
76543210
–––––QERRDIRCHG IDX
807
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.19 TC Fault Mode Register
Name: TC_FMR
Address: 0x400100D8 (0), 0x400140D8 (1)
Access: Read-write
This register can only be written if the WPEN bit is cleared in “TC Write Protect Mode Register” on page 808
• ENCF0: ENable Compare Fault Channel 0
0 = Disables the FAULT output source (CPCS flag) from channel 0.
1 = Enables the FAULT output source (CPCS flag) from channel 0.
• ENCF1: ENable Compare Fault Channel 1
0 = Disables the FAULT output source (CPCS flag) from channel 1.
1 = Enables the FAULT output source (CPCS flag) from channel 1.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – – – ENCF1 ENCF0
808
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
36.7.20 TC Write Protect Mode Register
Name: TC_WPMR
Address: 0x400100E4 (0), 0x400140E4 (1)
Access: Read-write
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x54494D (“TIM” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x54494D (“TIM” in ASCII).
Protects the registers:
”TC Block Mode Register”
”TC Channel Mode Register: Capture Mode”
”TC Channel Mode Register: Waveform Mode”
”TC Fault Mode Register”
”TC Stepper Motor Mode Register”
”TC Register A”
”TC Register B”
”TC Register C”
• WPKEY: Write Protect KEY
Should be written at value 0x54494D (“TIM” in ASCII). Writing any other value in this field aborts the write operation of the WPEN
bit. Always reads as 0.
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
809
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37. High Speed MultiMedia Card Interface (HSMCI)
37.1 Description
The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD
Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
The HSMCI includes a command register, response registers, data registers, timeout counters and error detection logic
that automatically handle the transmission of commands and, when required, the reception of the associated responses
and data with a limited processor overhead.
The HSMCI supports stream, block and multi block data read and write, and is compatible with the Peripheral DMA
Controller (PDC) Channels, minimizing processor intervention for large buffer transfers.
The HSMCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 1 slot(s). Each slot may
be used to interface with a High Speed MultiMedia Card bus (up to 30 Cards) or with an SD Memory Card. Only one slot
can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection.
The SD Memory Card communication is based on a 9-pin interface (clock, comma nd, four data and three power lines)
and the High Speed MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one
reserved for future use).
The SD Memory Card interface also supports High Speed MultiMedia Card operations. The main differences between
SD and High Speed MultiMedia Cards are the initialization process and the bus topology.
HSMCI fully supports CE-ATA Revision 1.1, built on the MMC System Specification v4.0. The module includes dedicated
hardware to issue the command completion signal and capture the host command completion signal disable.
37.2 Embedded Characteristics
4-bit or 1-bit Interface
Compatibility with MultiMedia Card Specification Version 4.3
Compatibility with SD and SDHC Memory Card Specification Version 2.0
Compatibility with SDIO Specification Version V1.1.
Compatibility with CE-ATA Specification 1.1
Cards clock rate up to Master Clock divided by 2
Boot Operation Mode support
High Speed mode support
Embedded power management to slow down clock rate when not used
MCI has one slot supporting
One MultiMediaCard bus (up to 30 cards) or
One SD Memory Card
One SDIO Card
Support for stream, block and multi-block data read and write
810
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.3 Block Diagram
Figure 37-1. Block Diagram
37.4 Application Block Diagram
Figure 37-2. Application Block Diagram
HSMCI Interface
Interrupt Control
PIO
PDC
APB Bridge
PMC MCK
HSMCI Interrupt
MCCK(1)
MCCDA(1)
MCDA0(1)
MCDA1(1)
MCDA2(1)
MCDA3(1)
APB
2345617
MMC
23456178
SDCard
9
Physical Layer
HSMCI Interface
Application Layer
ex:File System, Audio, Security, etc.
91011 12138
811
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.5 Pin Name List
Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain.
2. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA, MCDAy to HSMCIx_DAy.
37.6 Product Dependencies
37.6.1 I/O Lines
The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The
programmer must first program the PIO controllers to assign the peripheral functions to HSMCI pins.
37.6.2 Power Management
The HSMCI is clocked through the Power Management Controller (PMC), so the programmer must first configure the
PMC to enable the HSMCI clock.
37.6.3 Interrupt
The HSMCI interface has an interrupt line connected to the interrupt controller.
Handling the HSMCI interrupt requires programming the interrupt controller before configuring the HSMCI.
Table 37-1. I/O Lines Description for 4-bit Configuration
Pin Name(2) Pin Description Type(1) Comments
MCCDA Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO
MCCK Clock I/O CLK of an MMC or SD Card/SDIO
MCDA0 - MCDA3 Data 0..3 of Slot A I/O/PP DAT[0..3] of an MMC
DAT[0..3] of an SD Card/SDIO
Table 37-2. I/O Lines
Instance Signal I/O Line Peripheral
HSMCI MCCDA PA28 C
HSMCI MCCK PA29 C
HSMCI MCDA0 PA30 C
HSMCI MCDA1 PA31 C
HSMCI MCDA2 PA26 C
HSMCI MCDA3 PA27 C
Table 37-3. Peripheral IDs
Instance ID
HSMCI 18
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37.7 Bus Topology
Figure 37-3. High Speed MultiMedia Memory Card Bus Topology
The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication
lines and four supply lines.
Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain.
2. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA, MCDAy to HSMCIx_DAy.
Table 37-4. Bus Topology
Pin
Number Name Type(1) Description HSMCI Pin Name(2)
(Slot z)
1 DAT[3] I/O/PP Data MCDz3
2 CMD I/O/PP/OD Command/response MCCDz
3 VSS1 S Supply voltage ground VSS
4 VDD S Supply voltage VDD
5 CLK I/O Clock MCCK
6 VSS2 S Supply voltage ground VSS
7 DAT[0] I/O/PP Data 0 MCDz0
8 DAT[1] I/O/PP Data 1 MCDz1
9 DAT[2] I/O/PP Data 2 MCDz2
10 DAT[4] I/O/PP Data 4 MCDz4
11 DAT[5] I/O/PP Data 5 MCDz5
12 DAT[6] I/O/PP Data 6 MCDz6
13 DAT[7] I/O/PP Data 7 MCDz7
2345617
MMC
91011 12138
813
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Figure 37-4. MMC Bus Connections (One Slot)
Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA MCDAy to HSMCIx_DAy.
Figure 37-5. SD Memory Card Bus Topology
The SD Memory Card bus includes the signals listed in Table 37-5.
Notes: 1. I: input, O: output, PP: Push Pull, OD: Open Drain.
2. When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA, MCDAy to HSMCIx_DAy.
Table 37-5. SD Memory Card Bus Signals
Pin
Number Name Type(1) Description HSMCI Pin Name(2)
(Slot z)
1 CD/DAT[3] I/O/PP Card detect/ Data line Bit 3 MCDz3
2 CMD PP Command/response MCCDz
3 VSS1 S Supply voltage ground VSS
4 VDD S Supply voltage VDD
5 CLK I/O Clock MCCK
6 VSS2 S Supply voltage ground VSS
7 DAT[0] I/O/PP Data line Bit 0 MCDz0
8 DAT[1] I/O/PP Data line Bit 1 or Interrupt MCDz1
9 DAT[2] I/O/PP Data line Bit 2 MCDz2
MCCDA
MCDA0
MCCK
HSMCI
2345617
MMC1
9 1011 1213 8
2345617
MMC2
9 1011 1213 8
2345617
MMC3
9 1011 1213 8
23456178
SD CARD
9
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Figure 37-6. SD Card Bus Connections with One Slot
Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to
HSMCIx_CDA MCDAy to HSMCIx_DAy.
When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the
HSMCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the
width is four bits. In the case of High Speed MultiMedia cards, only the data line 0 is used. The other data lines can be
used as independent PIOs.
37.8 High Speed MultiMedia Card Operations
After a power-on reset, the cards are initialized by a special message-based High Speed MultiMedia Card bus protocol.
Each message is represented by one of the following tokens:
Command: A command is a token that starts an operation. A command is sent from the host either to a single card
(addressed command) or to all connected cards (broadcast command). A command is transferred serially on the
CMD line.
Response: A response is a token which is sent from an addressed card or (synchronously) from all connected
cards to the host as an answer to a previously received command. A response is transferred serially on the CMD
line.
Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line.
Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to
all currently connected cards. Their unique CID number identifies individual cards.
The structure of commands, responses and data blocks is described in the High Speed MultiMedia Card System
Specification. See also Table 37-6 on page 815.
High Speed MultiMedia Card bus data transfers are composed of these tokens.
There are different types of operations. Addressed operations always contain a command and a response token. In
addition, some operations have a data token; the others transfer their information directly within the command or
response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are
transferred synchronous to the clock HSMCI Clock.
Two types of data transfer commands are defined:
Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop
command follows on the CMD line. This mode reduces the command overhead to an absolute minimum.
Block-oriented commands: These commands send a data block succeeded by CRC bits.
Both read and write operations allow either single or multiple block transmission. A multiple block transmission is
terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block
transmission has a pre-defined block count (See “Data Transfer Operation” on page 817.).
The HSMCI provides a set of registers to perform the entire range of High Speed MultiMedia Card operations.
37.8.1 Command - Response Operation
After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the HSMCI_CR Control Register.
The PWSEN bit saves power by dividing the HSMCI clock by 2PWSDIV + 1 when the bus is inactive.
2345617
MCDA0 - MCDA3
MCCDA
MCCK
8
SD CARD
9
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The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow stopping the HSMCI Clock
during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth.
All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMedia Card System Specification.
The two bus modes (open drain and push/pull) needed to process all the operations are defined in the HSMCI Command
Register. The HSMCI_CMDR allows a command to be carried out.
For example, to perform an ALL_SEND_CID command:
The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR Control Register are described in Table
37-6 and Table 37-7.
Note: 1. bcr means broadcast command with response.
The HSMCI_ARGR contains the argument field of the command.
To send a command, the user must perform the following steps:
Fill the argument register (HSMCI_ARGR) with the command argument.
Set the command register (HSMCI_CMDR) (see Table 37-7).
The command is sent immediately after writing the command register.
While the card maintains a busy indication (at the end of a STOP_TRANSMISSION command CMD12, for example), a
new command shall not be sent. The NOTBUSY flag in the status register (HSMCI_SR) is asserted when the card
releases the busy indication.
If the command requires a response, it can be read in the HSMCI Response Register (HSMCI_RSPR). The response
size can be from 48 bits up to 136 bits depending on the command. The HSMCI embeds an error detection to prevent
any corrupted data during the transfer.
Host Command NID Cycles CID
CMD S T Content CRC E Z ****** Z S T Content Z Z Z
Table 37-6. ALL_SEND_CID Command Description
CMD Index Type Argument Resp Abbreviation Command
Description
CMD2 bcr(1) [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send
their CID numbers on
the CMD line
Table 37-7. Fields and Values for HSMCI_CMDR Command Register
Field Value
CMDNB (command number) 2 (CMD2)
RSPTYP (response type) 2 (R2: 136 bits response)
SPCMD (special command) 0 (not a special command)
OPCMD (open drain command) 1
MAXLAT (max latency for command to response) 0 (NID cycles ==> 5 cycles)
TRCMD (transfer command) 0 (No transfer)
TRDIR (transfer direction) X (available only in transfer command)
TRTYP (transfer type) X (available only in transfer command)
IOSPCMD (SDIO special command) 0 (not a special command)
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The following flowchart shows how to send a command to the card and read the response if needed. In this example, the
status register bits are polled but setting the appropriate bits in the Interrupt Enable Register (HSMCI_IER) allows using
an interrupt method.
Figure 37-7. Command/Response Functional Flow Diagram
RETURN OK
RETURN ERROR(1)
RETURN OK
Set the command argument
HSMCI_ARGR = Argument
(1)
Set the command
HSMCI_CMDR = Command
Read HSMCI_SR
CMDRDY
Status error flags?
Read response if required
Yes
Wait for command
ready status flag
Check error bits in the
status register
(1)
0
1
Does the command involve
a busy indication? No
Read HSMCI_SR
0
NOTBUSY
1
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Note: 1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the High Speed
MultiMedia Card specification).
37.8.2 Data Transfer Operation
The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These
kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register
(HSMCI_CMDR).
These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in
HSMCI_MR, then all reads and writes use the PDC facilities.
In all cases, the block length (BLKLEN field) must be defined either in the Mode Register HSMCI_MR, or in the Block
Register HSMCI_BLKR. This field determines the size of the data block.
Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can
use either one at any time):
Open-ended/Infinite Multiple block read (or write):
The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously
transfer (or program) data blocks until a stop transmission command is received.
Multiple block read (or write) with pre-defined block count (since version 3.1 and higher):
The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop
command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In
order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the
HSMCI Block Register (HSMCI_BLKR). Otherwise the card will start an open-ended multiple block read. The
BCNT field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks). Programming
the value 0 in the BCNT field corresponds to an infinite block transfer.
37.8.3 Read Operation
The following flowchart shows how to read a single block with or without use of PDC facilities. In this example (see Figure
37-8), a polling method is used to wait for the end of read. Similarly, the user can configure the Interrupt Enable Register
(HSMCI_IER) to trigger an interrupt at the end of read.
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Figure 37-8. Read Functional Flow Diagram
Note: 1. It is assumed that this command has been correctly sent (see Figure 37-7).
Read status register HSMCI_SR
Send SELECT/DESELECT_CARD
command(1) to select the card
Send SET_BLOCKLEN command(1)
Read with PDC
Reset the PDCMODE bit
HSMCI_MR = PDCMODE
Set the block length (in bytes)
HSMCI_MR = (BlockLenght 16)
Number of words to read = 0
Poll the bit
RXRDY = 0
Read data = HSMCI_RDR
Number of words to read =
Number of words to read -1
Send READ_SINGLE_BLOCK
command(1)
Yes
Set the PDCMODE bit
HSMCI_MR = PDCMODE
Set the block length (in bytes)
HSMCI_MR = (BlockLength 16)
Configure the PDC channel
HSMCI_RPR = Data Buffer Address
HSMCI_RCR = BlockLength/4
HSMCI_PTCR = RXTEN
Send READ_SINGLE_BLOCK
command(1)
Read status register HSMCI_SR
Poll the bit
ENDRX = 0 Yes
RETURN
RETURN
YesNo
No
No
Yes
No
Number of words to read = BlockLength/4
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37.8.4 Write Operation
In write operation, the HSMCI Mode Register (HSMCI_MR) is used to define the padding value when writing non-multiple
block size. If the bit PDCPADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used.
If set, the bit PDCMODE enables PDC transfer.
The following flowchart (Figure 37-9) shows how to wri te a single block with or without use of PDC faciliti es. Polling or
interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register
(HSMCI_IMR).
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Figure 37-9. Write Functional Flow Diagram
Note: 1. It is assumed that this command has been correctly sent (see Figure 37-7).
The following flowchart (Figure 37-10) shows how to manage a multiple write block transfer with the PDC. Polling or
interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register
(HSMCI_IMR).
Send SELECT/DESELECT_CARD
command(1) to select the card
Send SET_BLOCKLEN command(1)
Write using PDC
Reset the PDCMODE bit
HSMCI_MR = PDCMODE
Set the block length
HSMCI_MR = (BlockLenght 16)
Send WRITE_SINGLE_BLOCK
command(1)
Set the PDCMODE bit
HSMCI_MR = PDCMODE
Set the block length
HSMCI_MR = (BlockLength 16)
Configure the PDC channel
HSMCI_TPR = Data Buffer Address
HSMCI_TCR = BlockLength/4
Send WRITE_SINGLE_BLOCK
command(1)
Read status register HSMCI_SR
Poll the bit
NOTBUSY= 0 Yes
RETURN
No Yes
No
Read status register HSMCI_SR
Number of words to write = 0
Poll the bit
TXRDY = 0
HSMCI_TDR = Data to write
Number of words to write =
Number of words to write -1
Yes
RETURN
No
Yes
No
Number of words to write = BlockLength/4
HSMCI_PTCR = TXTEN
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Figure 37-10.Multiple Write Functional Flow Diagram
Note: 1. It is assumed that this command has been correctly sent (see Figure 37-7).
Send SELECT/DESELECT_CARD
command(1) to select the card
Send SET_BLOCKLEN command(1)
Set the PDCMODE bit
HSMCI_MR = PDCMODE
Set the block length
HSMCI_MR = (BlockLength 16)
Configure the PDC channel
HSMCI_TPR = Data Buffer Address
HSMCI_TCR = BlockLength/4
Send WRITE_MULTIPLE_BLOCK
command(1)
Read status register HSMCI_SR
Poll the bit
BLKE = 0 Yes
No
HSMCI_PTCR = TXTEN
Poll the bit
NOTBUSY = 0 Yes
RETURN
No
Send STOP_TRANSMISSION
command(1)
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37.9 SD/SDIO Card Operation
The High Speed MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO
(SD Input Output) Card commands.
SD/SDIO cards are based on the MultiMedia Card (MMC) format, but are physically slightly thicker and feature higher
data transfer rates, a lock switch on the side to prevent accidental overwriting and security features. The physical form
factor, pin assignment and data transfer protocol are forward-compatible with the High Speed MultiMedia Card with some
additions. SD slots can actually be used for more than flash memory cards. Devices that support SDIO can use small
devices designed for the SD form factor, such as GPS receivers, Wi-Fi or Bluetooth adapters, modems, barcode readers,
IrDA adapters, FM radio tuners, RFID readers, digital cameras and more.
SD/SDIO is covered by numerous patents and trademarks, and licensing is only available through the Secure Digital
Card Association.
The SD/SDIO Card communication is based on a 9-pin interface (Clock, Command, 4 x Data and 3 x Power lines). The
communication protocol is defined as a part of this specification. The main difference between the SD/SDIO Card and the
High Speed MultiMedia Card is the initialization process.
The SD/SDIO Card Register (HSMCI_SDCR) allows selection of the Card Slot and the data bus width.
The SD/SDIO Card bus allows dynamic configuration of the number of data lines. After power up, by default, the
SD/SDIO Card uses only DAT0 for data transfer. After initialization, the host can change the bus width (number of active
data lines).
37.9.1 SDIO Data Transfer Type
SDIO cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format (1 to 511 blocks), while
the SD memory cards are fixed in the block transfer mode. The TRTYP field in the HSMCI Command Register
(HSMCI_CMDR) allows to choose between SDIO Byte or SDIO Block transfer.
The number of bytes/blocks to transfer is set through the BCNT field in the HSMCI Block Register (HSMCI_BLKR). In
SDIO Block mode, the field BLKLEN must be set to the data block size while this field is not used in SDIO Byte mode.
An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within a multi-function SDIO or
a Combo card, there are multiple devices (I/O and memory) that share access to the SD bus. In order to allow the sharing
of access to the host among multiple devices, SDIO and combo cards can implement the optional concept of
suspend/resume (Refer to the SDIO Specification for more details). To send a suspend or a resume command, the host
must set the SDIO Special Command field (IOSPCMD) in the HSMCI Command Register.
37.9.2 SDIO Interrupts
Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO Specification for more
details). In order to allow the SDIO card to interrupt the host, an interrupt function is added to a pin on the DAT[1] line to
signal the card’s interrupt to the host. An SDIO interrupt on each slot can be enabled through the HSMCI Interrupt Enable
Register. The SDIO interrupt is sampled regardless of the currently selected slot.
37.10 CE-ATA Operation
CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is mapped onto MMC
register space.
CE-ATA utilizes five MMC commands:
GO_IDLE_STATE (CMD0): used for hard reset.
STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be aborted.
FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, 8 bit access only.
RW_MULTIPLE_REGISTERS (CMD60): used to issue an ATA command or to access the control/status registers.
RW_MULTIPLE_BLOCK (CMD61): used to transfer data for an ATA command.
CE-ATA utilizes the same MMC command sequences for initialization as traditional MMC devices.
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37.10.1 Executing an ATA Polling Command
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8kB of DATA.
2. Read the ATA status register until DRQ is set.
3. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
4. Read the ATA status register until DRQ && BSY are set to 0.
37.10.2 Executing an ATA Interrupt Command
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8kB of DATA with nIEN field set to zero to
enable the command completion signal in the device.
2. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
3. Wait for Completion Signal Received Interrupt.
37.10.3 Aborting an ATA Command
If the host needs to abort an ATA command prior to the completion signal it must send a special command to avoid
potential collision on the command line. The SPCMD field of the HSMCI_CMDR mus t be set to 3 to issue the CE-ATA
completion Signal Disable Command.
37.10.4 CE-ATA Error Recovery
Several methods of ATA command failure may occur, including:
No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60).
CRC is invalid for an MMC command or response.
CRC16 is invalid for an MMC data packet.
ATA Status register reflects an error by setting the ERR bit to one.
The command completion signal does not arrive within a host specified time out period.
Error conditions are expected to happen infrequently. Thus, a robust error re covery mechanism may be used for each
error event. The recommended error recovery procedure after a timeout is:
Issue the command completion signal disable if nIEN was cleared to zero and the RW_MULTIPLE_BLOCK
(CMD61) response has been received.
Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response.
Issue a software reset to the CE-ATA device using FAST_IO (CMD39).
If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA commands. However, if the
error recovery procedure does not work as expected or there is another timeout, the next step is to issue
GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE (CMD0) is a hard reset to the device and completely resets
all device states.
Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed again. If the CE-ATA
device completes all MMC commands correctly but fails the ATA command with the ERR bit set in the ATA Status
register, no error recovery action is required. The ATA command itself failed implying that the device could not complete
the action requested, however, there was no communication or protocol failure. After the device signals an error by
setting the ERR bit to one in the ATA Status register, the host may attempt to retry the command.
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37.11 HSMCI Boot Operation Mode
In boot operation mode, the processor can read boot data from the slave (MMC device) by keeping the CMD line low
after power-on before issuing CMD1. The data can be read from either the boot area or user area, depending on register
setting. As it is not possible to boot directly on SD-CARD, a preliminary boot code must be stored in internal Flash.
37.11.1 Boot Procedure, Processor Mode
1. Configure the HSMCI data bus width programming SDCBUS Field in the HSMCI_SDCR register. The
BOOT_BUS_WIDTH field located in the device Extended CSD register must be set accordingly.
2. Set the byte count to 512 bytes and the block count to the desired number of blocks, writing BLKLEN and BCNT
fields of the HSMCI_BLKR Register.
3. Issue the Boot Operation Request command by writing to the HSMCI_CMDR register with SPCMD field set to
BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”.
4. The BOOT_ACK field located in the HSMCI_CMDR register must be set to one, if the BOOT_ACK field of the
MMC device located in the Extended CSD register is set to one.
5. Host processor can copy boot data sequentially as soon as the RXRDY flag is asserted.
6. When Data transfer is completed, host processor shall terminate the boot stream by writing the HSMCI_CMDR
register with SPCMD field set to BOOTEND.
37.12 HSMCI Transfer Done Timings
37.12.1 Definition
The XFRDONE flag in the HSMCI_SR indicates exactly when the read or write sequence is finished.
37.12.2 Read Access
During a read access, the XFRDONE flag behaves as shown in Figure 37-11.
Figure 37-11.XFRDONE During a Read Access
CMD line
HSMCI read CMD
Card response
CMDRDY flag
Data
1st Block Last Block
Not busy flag
XFRDONE flag
The CMDRDY flag is released 8 tbit after the end of the card response.
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37.12.3 Write Access
During a write access, the XFRDONE flag behaves as shown in Figure 37-12.
Figure 37-12.XFRDONE During a Write Access
37.13 Write Protection Registers
To prevent any single software error that may corrupt HSMCI behavior, the entire HSMCI address space from address
offset 0x000 to 0x00FC can be write-protected by setting the WPEN bit in the “HSMCI Write Protect Mode Register”
(HSMCI_WPMR).
If a write access to anywhere in the HSMCI address space from address offset 0x000 to 0x00FC is detected, then the
WPVS flag in the HSMCI Write Protect Status Register (HSMCI_WPSR) is set and the field WPVSRC indicates in which
register the write access has been attempted.
The WPVS flag is reset by writing the HSMCI Write Protect Mode Register (HSMCI_WPMR) with the appropriate access
key, WPKEY.
The protected registers are:
“HSMCI Mode Register” on page 828
“HSMCI Data Timeout Register” on page 830
“HSMCI SDCard/SDIO Register” on page 831
“HSMCI Completion Signal Timeout Register” on page 836
“HSMCI Configuration Register” on page 850
CMD line
Card response
CMDRDY flag
Data bus - D0
1st Block
Not busy flag
XFRDONE flag
The CMDRDY flag is released 8 tbit after the end of the card response.
Last Block
D0
1st Block Last Block
D0 is tied by the card
D0 is released
HSMCI write CMD
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37.14 High Speed MultiMedia Card Interface (HSMCI) User Interface
Notes: 1. The Response Register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to
0x2C). N depends on the size of the response.
Table 37-8. Register Mapping
Offset Register Name Access Reset
0x00 Control Register HSMCI_CR Write –
0x04 Mode Register HSMCI_MR Read-write 0x0
0x08 Data Timeout Register HSMCI_DTOR Read-write 0x0
0x0C SD/SDIO Card Register HSMCI_SDCR Read-write 0x0
0x10 Argument Register HSMCI_ARGR Read-write 0x0
0x14 Command Register HSMCI_CMDR Write –
0x18 Block Register HSMCI_BLKR Read-write 0x0
0x1C Completion Signal Timeout Register HSMCI_CSTOR Read-write 0x0
0x20 Response Register(1) HSMCI_RSPR Read 0x0
0x24 Response Register(1) HSMCI_RSPR Read 0x0
0x28 Response Register(1) HSMCI_RSPR Read 0x0
0x2C Response Register(1) HSMCI_RSPR Read 0x0
0x30 Receive Data Register HSMCI_RDR Read 0x0
0x34 Transmit Data Register HSMCI_TDR Write –
0x38 - 0x3C Reserved – – –
0x40 Status Register HSMCI_SR Read 0xC0E5
0x44 Interrupt Enable Register HSMCI_IER Write –
0x48 Interrupt Disable Register HSMCI_IDR Write –
0x4C Interrupt Mask Register HSMCI_IMR Read 0x0
0x50 Reserved – – –
0x54 Configuration Register HSMCI_CFG Read-write 0x00
0x58-0xE0 Reserved – – –
0xE4 Write Protection Mode Register HSMCI_WPMR Read-write –
0xE8 Write Protection Status Register HSMCI_WPSR Read-only –
0xEC - 0xFC Reserved – – –
0x100-0x128 Reserved for PDC registers – – –
0x12Cx1FC Reserved – – –
0x200 FIFO Memory Aperture0 HSMCI_FIFO0 Read-write 0x0
... ... ... ... ...
0x5FC FIFO Memory Aperture255 HSMCI_FIFO255 Read-write 0x0
827
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.1 HSMCI Control Register
Name: HSMCI_CR
Address: 0x40000000
Access: Write-only
• MCIEN: Multi-Media Interface Enable
0 = No effect.
1 = Enables the Multi-Media Interface if MCDIS is 0.
• MCIDIS: Multi-Media Interface Disable
0 = No effect.
1 = Disables the Multi-Media Interface.
• PWSEN: Power Save Mode Enable
0 = No effect.
1 = Enables the Power Saving Mode if PWSDIS is 0.
Warning: Before enabling this mode, the user must set a value different from 0 in the PWSDIV field (Mode Register,
HSMCI_MR).
• PWSDIS: Power Save Mode Disable
0 = No effect.
1 = Disables the Power Saving Mode.
• SWRST: Software Reset
0 = No effect.
1 = Resets the HSMCI. A software triggered hardware reset of the HSMCI interface is performed.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SWRST – – – PWSDIS PWSEN MCIDIS MCIEN
828
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.2 HSMCI Mode Register
Name: HSMCI_MR
Address: 0x40000004
Access: Read-write
This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 851.
• CLKDIV: Clock Divider
High Speed MultiMedia Card Interface clock (MCCK or HSMCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)).
• PWSDIV: Power Saving Divider
High Speed MultiMedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode.
Warning: This value must be different from 0 before enabling the Power Save Mode in the HSMCI_CR (HSMCI_PWSEN bit).
• RDPROOF: Read Proof Enable
Enabling Read Proof allows to stop the HSMCI Clock during read access if the internal FIFO is full. This will guarantee data integ-
rity, not bandwidth.
0 = Disables Read Proof.
1 = Enables Read Proof.
• WRPROOF: Write Proof Enable
Enabling Write Proof allows to stop the HSMCI Clock during write access if the internal FIFO is full. This will guarantee data integ-
rity, not bandwidth.
0 = Disables Write Proof.
1 = Enables Write Proof.
• FBYTE: Force Byte Transfer
Enabling Force Byte Transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported.
Warning: BLKLEN value depends on FBYTE.
0 = Disables Force Byte Transfer.
1 = Enables Force Byte Transfer.
• PADV: Padding Value
0 = 0x00 value is used when padding data in write transfer.
1 = 0xFF value is used when padding data in write transfer.
PADV may be only in manual transfer.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
PDCMODE PADV FBYTE WRPROOF RDPROOF PWSDIV
76543210
CLKDIV
829
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• PDCMODE: PDC-oriented Mode
0 = Disables PDC transfer
1 = Enables PDC transfer. In this case, UNRE and OVRE flags in the MCI Mode Register (MCI_SR) are deactivated after the
PDC transfer has been completed.
830
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.3 HSMCI Data Timeout Register
Name: HSMCI_DTOR
Address: 0x40000008
Access: Read-write
This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 851.
• DTOCYC: Data Timeout Cycle Number
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers. It
equals (DTOCYC x Multiplier).
• DTOMUL: Data Timeout Multiplier
Multiplier is defined by DTOMUL as shown in the following table:
If the data time-out set by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error flag (DTOE) in the HSMCI Status
Register (HSMCI_SR) rises.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– DTOMUL DTOCYC
Value Name Description
0 1 DTOCYC
1 16 DTOCYC x 16
2 128 DTOCYC x 128
3 256 DTOCYC x 256
4 1024 DTOCYC x 1024
5 4096 DTOCYC x 4096
6 65536 DTOCYC x 65536
7 1048576 DTOCYC x 1048576
831
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.4 HSMCI SDCard/SDIO Register
Name: HSMCI_SDCR
Address: 0x4000000C
Access: Read-write
This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 851.
• SDCSEL: SDCard/SDIO Slot
• SDCBUS: SDCard/SDIO Bus Width
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
SDCBUS – – – – SDCSEL
Value Name Description
0 SLOTA Slot A is selected.
1 SLOTB –
2 SLOTC –
3 SLOTD –
Value Name Description
01
1bit
1–
Reserved
244bit
388bit
832
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.5 HSMCI Argument Register
Name: HSMCI_ARGR
Address: 0x40000010
Access: Read-write
• ARG: Command Argument
31 30 29 28 27 26 25 24
ARG
23 22 21 20 19 18 17 16
ARG
15 14 13 12 11 10 9 8
ARG
76543210
ARG
833
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.6 HSMCI Command Register
Name: HSMCI_CMDR
Address: 0x40000014
Access: Write-only
This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is only writable by
an interrupt response (field SPCMD). This means that the current command execution cannot be interrupted or modified.
• CMDNB: Command Number
This is the command index.
• RSPTYP: Response Type
• SPCMD: Special Command
31 30 29 28 27 26 25 24
– – – – BOOT_ACK ATACS IOSPCMD
23 22 21 20 19 18 17 16
– – TRTYP TRDIR TRCMD
15 14 13 12 11 10 9 8
– – – MAXLAT OPDCMD SPCMD
76543210
RSPTYP CMDNB
Value Name Description
0 NORESP No response.
1 48_BIT 48-bit response.
2 136_BIT 136-bit response.
3 R1B R1b response type
Value Name Description
0 STD Not a special CMD.
1 INIT Initialization CMD:
74 clock cycles for initialization sequence.
2 SYNC Synchronized CMD:
Wait for the end of the current data block transfer before sending the pending command.
3 CE_ATA CE-ATA Completion Signal disable Command.
The host cancels the ability for the device to return a command completion signal on the
command line.
4 IT_CMD Interrupt command:
Corresponds to the Interrupt Mode (CMD40).
5 IT_RESP Interrupt response:
Corresponds to the Interrupt Mode (CMD40).
6 BOR Boot Operation Request.
Start a boot operation mode, the host processor can read boot data from the MMC device directly.
7 EBO End Boot Operation.
This command allows the host processor to terminate the boot operation mode.
834
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• OPDCMD: Open Drain Command
0 (PUSHPULL) = Push pull command.
1 (OPENDRAIN) = Open drain command.
• MAXLAT: Max Latency for Command to Response
0 (5) = 5-cycle max latency.
1 (64) = 64-cycle max latency.
• TRCMD: Transfer Command
• TRDIR: Transfer Direction
0 (WRITE) = Write.
1 (READ) = Read.
• TRTYP: Transfer Type
• IOSPCMD: SDIO Special Command
• ATACS: ATA with Command Completion Signal
0 (NORMAL) = Normal operation mode.
1 (COMPLETION) = This bit indicates that a completion signal is expected within a programmed amount of time
(HSMCI_CSTOR).
• BOOT_ACK: Boot Operation Acknowledge.
The master can choose to receive the boot acknowledge from the slave when a Boot Request command is issued. When set to
one this field indicates that a Boot acknowledge is expected within a programmable amount of time defined with DTOMUL and
DTOCYC fields located in the HSMCI_DTOR register. If the acknowledge pattern is not received then an acknowledge timeout
error is raised. If the acknowledge pattern is corrupted then an acknowledge pattern error is set.
Value Name Description
0 NO_DATA No data transfer
1 START_DATA Start data transfer
2 STOP_DATA Stop data transfer
3 – Reserved
Value Name Description
0 SINGLE MMC/SD Card Single Block
1 MULTIPLE MMC/SD Card Multiple Block
2 STREAM MMC Stream
4 BYTE SDIO Byte
5 BLOCK SDIO Block
Value Name Description
0 STD Not an SDIO Special Command
1 SUSPEND SDIO Suspend Command
2 RESUME SDIO Resume Command
835
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.7 HSMCI Block Register
Name: HSMCI_BLKR
Address: 0x40000018
Access: Read-write
• BCNT: MMC/SDIO Block Count - SDIO Byte Count
This field determines the number of data byte(s) or block(s) to transfer.
The transfer data type and the authorized values for BCNT field are determined by the TRTYP field in the HSMCI Command Reg-
ister (HSMCI_CMDR).
When TRTYP=1 (MMC/SDCARD Multiple Block), BCNT can be programmed from 1 to 65535, 0 corresponds to an infinite block
transfer.
When TRTYP=4 (SDIO Byte), BCNT can be programmed from 1 to 511, 0 corresponds to 512-byte transfer. Values in range 512
to 65536 are forbidden.
When TRTYP=5 (SDIO Block), BCNT can be programmed from 1 to 511, 0 corresponds to an infinite block transfer. Values in
range 512 to 65536 are forbidden.
Warning: In SDIO Byte and Block modes (TRTYP=4 or 5), writing the 7 last bits of BCNT field with a value which differs from 0 is
forbidden and may lead to unpredictable results.
• BLKLEN: Data Block Length
This field determines the size of the data block.
This field is also accessible in the HSMCI Mode Register (HSMCI_MR).
Bits 16 and 17 must be set to 0 if FBYTE is disabled.
Note: In SDIO Byte mode, BLKLEN field is not used.
31 30 29 28 27 26 25 24
BLKLEN
23 22 21 20 19 18 17 16
BLKLEN
15 14 13 12 11 10 9 8
BCNT
76543210
BCNT
836
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.8 HSMCI Completion Signal Timeout Register
Name: HSMCI_CSTOR
Address: 0x4000001C
Access: Read-write
This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 851.
• CSTOCYC: Completion Signal Timeout Cycle Number
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers. Its
value is calculated by (CSTOCYC x Multiplier).
• CSTOMUL: Completion Signal Timeout Multiplier
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block transfers. Its
value is calculated by (CSTOCYC x Multiplier).
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between the end of the data transfer
and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If a non-DATA
ATA command is issued, the HSMCI starts waiting immediately after the end of the response until the completion signal.
Multiplier is defined by CSTOMUL as shown in the following table:
If the data time-out set by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error flag (CSTOE) in
the HSMCI Status Register (HSMCI_SR) rises.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– CSTOMUL CSTOCYC
Value Name Description
0 1 CSTOCYC x 1
1 16 CSTOCYC x 16
2 128 CSTOCYC x 128
3 256 CSTOCYC x 256
4 1024 CSTOCYC x 1024
5 4096 CSTOCYC x 4096
6 65536 CSTOCYC x 65536
7 1048576 CSTOCYC x 1048576
837
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.9 HSMCI Response Register
Name: HSMCI_RSPR
Address: 0x40000020
Access: Read-only
• RSP: Response
Note: 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses (0x20 to
0x2C).
N depends on the size of the response.
31 30 29 28 27 26 25 24
RSP
23 22 21 20 19 18 17 16
RSP
15 14 13 12 11 10 9 8
RSP
76543210
RSP
838
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.10HSMCI Receive Data Register
Name: HSMCI_RDR
Address: 0x40000030
Access: Read-only
• DATA: Data to Read
31 30 29 28 27 26 25 24
DATA
23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8
DATA
76543210
DATA
839
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.11HSMCI Transmit Data Register
Name: HSMCI_TDR
Address: 0x40000034
Access: Write-only
• DATA: Data to Write
31 30 29 28 27 26 25 24
DATA
23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8
DATA
76543210
DATA
840
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.12HSMCI Status Register
Name: HSMCI_SR
Address: 0x40000040
Access: Read-only
• CMDRDY: Command Ready
0 = A command is in progress.
1 = The last command has been sent. Cleared when writing in the HSMCI_CMDR.
• RXRDY: Receiver Ready
0 = Data has not yet been received since the last read of HSMCI_RDR.
1 = Data has been received since the last read of HSMCI_RDR.
• TXRDY: Transmit Ready
0= The last data written in HSMCI_TDR has not yet been transferred in the Shift Register.
1= The last data written in HSMCI_TDR has been transferred in the Shift Register.
• BLKE: Data Block Ended
This flag must be used only for Write Operations.
0 = A data block transfer is not yet finished. Cleared when reading the HSMCI_SR.
1 = A data block transfer has ended, including the CRC16 Status transmission.
the flag is set for each transmitted CRC Status.
Refer to the MMC or SD Specification for more details concerning the CRC Status.
• DTIP: Data Transfer in Progress
0 = No data transfer in progress.
1 = The current data transfer is still in progress, including CRC16 calculation. Cleared at the end of the CRC16 calculation.
• NOTBUSY: HSMCI Not Busy
A block write operation uses a simple busy signalling of the write operation duration on the data (DAT0) line: during a data trans-
fer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line
(DAT0) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer
block length becomes free.
Refer to the MMC or SD Specification for more details concerning the busy behavior.
For all the read operations, the NOTBUSY flag is cleared at the end of the host command.
For the Infinite Read Multiple Blocks, the NOTBUSY flag is set at the end of the STOP_TRANSMISSION host command
(CMD12).
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY – –
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFE RXBUFF CSRCV SDIOWAIT – – – SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
841
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block.
For the Multiple Block Reads with pre-defined block count, the NOTBUSY flag is set at the end of the last received data block.
The NOTBUSY flag allows to deal with these different states.
0 = The HSMCI is not ready for new data transfer. Cleared at the end of the card response.
1 = The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free
internal data receive buffer of the card.
• ENDRX: End of RX Buffer
0 = The Receive Counter Register has not reached 0 since the last write in HSMCI_RCR or HSMCI_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in HSMCI_RCR or HSMCI_RNCR.
• ENDTX: End of TX Buffer
0 = The Transmit Counter Register has not reached 0 since the last write in HSMCI_TCR or HSMCI_TNCR.
1 = The Transmit Counter Register has reached 0 since the last write in HSMCI_TCR or HSMCI_TNCR.
Note: BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines
and not only transferred from the PDC to the HSMCI Controller.
• SDIOIRQA: SDIO Interrupt for Slot A
0 = No interrupt detected on SDIO Slot A.
1 = An SDIO Interrupt on Slot A occurred. Cleared when reading the HSMCI_SR.
• SDIOWAIT: SDIO Read Wait Operation Status
0 = Normal Bus operation.
1 = The data bus has entered IO wait state.
• CSRCV: CE-ATA Completion Signal Received
0 = No completion signal received since last status read operation.
1 = The device has issued a command completion signal on the command line. Cleared by reading in the HSMCI_SR register.
• RXBUFF: RX Buffer Full
0 = HSMCI_RCR or HSMCI_RNCR has a value other than 0.
1 = Both HSMCI_RCR and HSMCI_RNCR have a value of 0.
• TXBUFE: TX Buffer Empty
0 = HSMCI_TCR or HSMCI_TNCR has a value other than 0.
1 = Both HSMCI_TCR and HSMCI_TNCR have a value of 0.
Note: BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines
and not only transferred from the PDC to the HSMCI Controller.
• RINDE: Response Index Error
0 = No error.
1 = A mismatch is detected between the command index sent and the response index received. Cleared when writing in the
HSMCI_CMDR.
• RDIRE: Response Direction Error
0 = No error.
1 = The direction bit from card to host in the response has not been detected.
842
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• RCRCE: Response CRC Error
0 = No error.
1 = A CRC7 error has been detected in the response. Cleared when writing in the HSMCI_CMDR.
• RENDE: Response End Bit Error
0 = No error.
1 = The end bit of the response has not been detected. Cleared when writing in the HSMCI_CMDR.
• RTOE: Response Time-out Error
0 = No error.
1 = The response time-out set by MAXLAT in the HSMCI_CMDR has been exceeded. Cleared when writing in the
HSMCI_CMDR.
• DCRCE: Data CRC Error
0 = No error.
1 = A CRC16 error has been detected in the last data block. Cleared by reading in the HSMCI_SR register.
• DTOE: Data Time-out Error
0 = No error.
1 = The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded. Cleared by reading in the
HSMCI_SR register.
• CSTOE: Completion Signal Time-out Error
0 = No error.
1 = The completion signal time-out set by CSTOCYC and CSTOMUL in HSMCI_CSTOR has been exceeded. Cleared by reading
in the HSMCI_SR register. Cleared by reading in the HSMCI_SR register.
• FIFOEMPTY: FIFO empty flag
0 = FIFO contains at least one byte.
1 = FIFO is empty.
• XFRDONE: Transfer Done flag
0 = A transfer is in progress.
1 = Command Register is ready to operate and the data bus is in the idle state.
• ACKRCV: Boot Operation Acknowledge Received
0 = No Boot acknowledge received since the last read of the status register.
1 = A Boot acknowledge signal has been received. Cleared by reading the HSMCI_SR register.
• ACKRCVE: Boot Operation Acknowledge Error
0 = No error
1 = Corrupted Boot Acknowledge signal received.
843
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• OVRE: Overrun
0 = No error.
1 = At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command.
When FERRCTRL in HSMCI_CFG is set to 1, OVRE becomes reset after read.
• UNRE: Underrun
0 = No error.
1 = At least one 8-bit data has been sent without valid information (not written). Cleared when sending a new data transfer com-
mand or when setting FERRCTRL in HSMCI_CFG to 1.
When FERRCTRL in HSMCI_CFG is set to 1, UNRE becomes reset after read.
844
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.13HSMCI Interrupt Enable Register
Name: HSMCI_IER
Address: 0x40000044
Access: Write-only
• CMDRDY: Command Ready Interrupt Enable
• RXRDY: Receiver Ready Interrupt Enable
• TXRDY: Transmit Ready Interrupt Enable
• BLKE: Data Block Ended Interrupt Enable
• DTIP: Data Transfer in Progress Interrupt Enable
• NOTBUSY: Data Not Busy Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• SDIOIRQA: SDIO Interrupt for Slot A Interrupt Enable
• SDIOWAIT: SDIO Read Wait Operation Status Interrupt Enable
• CSRCV: Completion Signal Received Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
• RINDE: Response Index Error Interrupt Enable
• RDIRE: Response Direction Error Interrupt Enable
• RCRCE: Response CRC Error Interrupt Enable
• RENDE: Response End Bit Error Interrupt Enable
• RTOE: Response Time-out Error Interrupt Enable
• DCRCE: Data CRC Error Interrupt Enable
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY – –
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFE RXBUFF CSRCV SDIOWAIT – – – SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
845
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• DTOE: Data Time-out Error Interrupt Enable
• CSTOE: Completion Signal Timeout Error Interrupt Enable
• FIFOEMPTY: FIFO empty Interrupt enable
• XFRDONE: Transfer Done Interrupt enable
• ACKRCV: Boot Acknowledge Interrupt Enable
• ACKRCVE: Boot Acknowledge Error Interrupt Enable
• OVRE: Overrun Interrupt Enable
• UNRE: Underrun Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
846
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.14HSMCI Interrupt Disable Register
Name: HSMCI_IDR
Address: 0x40000048
Access: Write-only
• CMDRDY: Command Ready Interrupt Disable
• RXRDY: Receiver Ready Interrupt Disable
• TXRDY: Transmit Ready Interrupt Disable
• BLKE: Data Block Ended Interrupt Disable
• DTIP: Data Transfer in Progress Interrupt Disable
• NOTBUSY: Data Not Busy Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• SDIOIRQA: SDIO Interrupt for Slot A Interrupt Disable
• SDIOWAIT: SDIO Read Wait Operation Status Interrupt Disable
• CSRCV: Completion Signal received interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
• RINDE: Response Index Error Interrupt Disable
• RDIRE: Response Direction Error Interrupt Disable
• RCRCE: Response CRC Error Interrupt Disable
• RENDE: Response End Bit Error Interrupt Disable
• RTOE: Response Time-out Error Interrupt Disable
• DCRCE: Data CRC Error Interrupt Disable
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY – –
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFE RXBUFF CSRCV SDIOWAIT – – – SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
847
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• DTOE: Data Time-out Error Interrupt Disable
• CSTOE: Completion Signal Time out Error Interrupt Disable
• FIFOEMPTY: FIFO empty Interrupt Disable
• XFRDONE: Transfer Done Interrupt Disable
• ACKRCV: Boot Acknowledge Interrupt Disable
• ACKRCVE: Boot Acknowledge Error Interrupt Disable
• OVRE: Overrun Interrupt Disable
• UNRE: Underrun Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
848
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
37.14.15HSMCI Interrupt Mask Register
Name: HSMCI_IMR
Address: 0x4000004C
Access: Read-only
• CMDRDY: Command Ready Interrupt Mask
• RXRDY: Receiver Ready Interrupt Mask
• TXRDY: Transmit Ready Interrupt Mask
• BLKE: Data Block Ended Interrupt Mask
• DTIP: Data Transfer in Progress Interrupt Mask
• NOTBUSY: Data Not Busy Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• SDIOIRQA: SDIO Interrupt for Slot A Interrupt Mask
• SDIOWAIT: SDIO Read Wait Operation Status Interrupt Mask
• CSRCV: Completion Signal Received Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
• RINDE: Response Index Error Interrupt Mask
• RDIRE: Response Direction Error Interrupt Mask
• RCRCE: Response CRC Error Interrupt Mask
• RENDE: Response End Bit Error Interrupt Mask
• RTOE: Response Time-out Error Interrupt Mask
• DCRCE: Data CRC Error Interrupt Mask
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY – –
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFE RXBUFF CSRCV SDIOWAIT – – – SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
849
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• DTOE: Data Time-out Error Interrupt Mask
• CSTOE: Completion Signal Time-out Error Interrupt Mask
• FIFOEMPTY: FIFO Empty Interrupt Mask
• XFRDONE: Transfer Done Interrupt Mask
• ACKRCV: Boot Operation Acknowledge Received Interrupt Mask
• ACKRCVE: Boot Operation Acknowledge Error Interrupt Mask
• OVRE: Overrun Interrupt Mask
• UNRE: Underrun Interrupt Mask
0 = The corresponding interrupt is not enabled.
1 = The corresponding interrupt is enabled.
850
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37.14.16HSMCI Configuration Register
Name: HSMCI_CFG
Address: 0x40000054
Access: Read-write
This register can only be written if the WPEN bit is cleared in “HSMCI Write Protect Mode Register” on page 851.
• FIFOMODE: HSMCI Internal FIFO control mode
0 = A write transfer starts when a sufficient amount of data is written into the FIFO.
When the block length is greater than or equal to 3/4 of the HSMCI internal FIFO size, then the write transfer starts as soon as
half the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write transfer starts as
soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data is written in the
internal FIFO.
1 = A write transfer starts as soon as one data is written into the FIFO.
• FERRCTRL: Flow Error flag reset control mode
0= When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag.
1= When an underflow/overflow condition flag is set, a read status resets the flag.
• HSMODE: High Speed Mode
0= Default bus timing mode.
1= If set to one, the host controller outputs command line and data lines on the rising edge of the card clock. The Host driver shall
check the high speed support in the card registers.
• LSYNC: Synchronize on the last block
0= The pending command is sent at the end of the current data block.
1= The pending command is sent at the end of the block transfer when the transfer length is not infinite. (block count shall be dif-
ferent from zero)
31 30 29 28 27 26 25 24
––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – LSYNC – – – HSMODE
76543210
– – – FERRCTRL – – – FIFOMODE
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37.14.17HSMCI Write Protect Mode Register
Name: HSMCI_WPMR
Address: 0x400000E4
Access: Read-write
• WP_EN: Write Protection Enable
0 = Disables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII).
1 = Enables the Write Protection if WP_KEY corresponds to 0x4D4349 (“MCI’ in ASCII).
• WP_KEY: Write Protection Key password
Should be written at value 0x4D4349 (ASCII code for “MCI”). Writing any other value in this field has no effect.
Protects the registers:
•“HSMCI Mode Register” on page 828
•“HSMCI Data Timeout Register” on page 830
•“HSMCI SDCard/SDIO Register” on page 831
•“HSMCI Completion Signal Timeout Register” on page 836
•“HSMCI Configuration Register” on page 850
31 30 29 28 27 26 25 24
WP_KEY (0x4D => “M”)
23 22 21 20 19 18 17 16
WP_KEY (0x43 => C”)
15 14 13 12 11 10 9 8
WP_KEY (0x49 => “I”)
76543210
WP_EN
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37.14.18HSMCI Write Protect Status Register
Name: HSMCI_WPSR
Address: 0x400000E8
Access: Read-only
• WP_VS: Write Protection Violation Status
• WP_VSRC: Write Protection Violation SouRCe
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has
been attempted.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WP_VSRC
15 14 13 12 11 10 9 8
WP_VSRC
76543210
– – – – WP_VS
Value Name Description
0 NONE No Write Protection Violation occurred since the last read of this
register (WP_SR)
1 WRITE Write Protection detected unauthorized attempt to write a control
register had occurred (since the last read.)
2 RESET Software reset had been performed while Write Protection was
enabled (since the last read).
3 BOTH Both Write Protection violation and software reset with Write
Protection enabled have occurred since the last read.
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38. Pulse Width Modulation Controller (PWM)
38.1 Description
The PWM macrocell controls 4 channels independently. Each channel controls two complementary square output
waveforms. Characteristics of the output waveforms such as period, duty-cycle, polarity and dead-times (also called
dead-bands or non-overlapping times) are configured through the user interface. Each channel selects and uses one of
the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the
PWM master clock (MCK).
All PWM macrocell accesses are made through registers mapped on the peripheral bus. All channels integrate a double
buffering system in order to prevent an unexpected output waveform while modifying the period, the duty-cycle or the
dead-times.
Channels can be linked together as synchronous channels to be able to update their duty-cycle or dead-times at the
same time.
The update of duty-cycles of synchronous channels can be performed by the Peripheral DMA Controller Channel (PDC)
which offers buffer transfer without processor Intervention.
The PWM macrocell provides 8 independent comparison units capable of comparing a programmed value to the counter
of the synchronous channels (counter of channel 0). These comparisons are intended to generate software interrupts, to
trigger pulses on the 2 independent event lines (in order to synchronize ADC conversions with a lot of flexibility
independently of the PWM outputs) and to trigger PDC transfer requests.
The PWM outputs can be overridden synchronously or asynchronously to their channel counter.
The PWM block provides a fault protection mechanism with 6 fault inputs, capable t o dete ct a fault co ndit ion and to
override the PWM outputs asynchronously (outputs forced to 0, 1).
For safety usage, some configuration registers are write-protected.
38.2 Embedded Characteristics
One Four-channel 16-bit PWM Controller, 16-bit counter per channel
Common clock generator, providing Thirteen Different Clocks
A Modulo n counter providing eleven clocks
Two independent Linear Dividers working on modulo n counter outputs
High Frequency Asynchronous clocking mode
Independent channel programming
Independent Enable Disable Commands
Independent Clock Selection
Independent Period and Duty Cycle, with Double Buffering
Programmable selection of the output waveform polarity
Programmable center or left aligned output waveform
Independent Output Override for each channel
Independent complementary Outputs with 12-bit dead time generator for each channel
Independent Enable Disable Commands
Independent Clock Selection
Independent Period and Duty Cycle, with Double Buffering
Synchronous Channel mode
Synchronous Channels share the same counter
Mode to update the synchronous channels registers after a programmable number of periods
Connection to one PDC channel
Provides Buffer transfer without processor intervention, to update duty cycle of synchronous channels
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Two independent event lines which can send up to 4 triggers on ADC within a period
One programmable Fault Input providing an asynchronous protection of outputs
Stepper motor control (2 Channels)
38.3 Block Diagram
Figure 38-1. Pulse Width Modulation Controller Block Diagram
38.4 I/O Lines Description
Each channel outputs two complementary external I/O lines.
APB
ADC
Comparison
Units
Interrupt
Controller
Interrupt Generator
event line 0
event line 1
Event s
Generator event line x
Comparat or
Clock
Sel ect o r Counter
Channel 0
Duty-Cycle
Peri od
Update
APB
Interface
CLOCK
Generator
PIO
PMC
Dead-Time
Generator Output
Override Faul t
Protection
PIO
Comparat or Dead-Time
Generator Output
Override Faul t
Protection
Counter
Channel x
Duty-Cycle
Peri od
Update
Clock
Sel ect o r
Channel x
OCx
DTOHx
DTOLx
OOOHxPWMHx
PWMLx
OOOLx
MUX
SYNCx
PWM Controller
MCK
Channel 0
OC0
DTOH0
DTOL0
OOOH0 PWMH0
PWML0
OOOL0
PWMHx
PWML
x
PWMH
0
PWML
0
PWMFI0
PWMFIx
Table 38-1. I/O Line Description
Name Description Type
PWMHx PWM Waveform Output High for channel x Output
PWMLx PWM Waveform Output Low for channel x Output
PWMFIx PWM Fault Input x Input
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38.5 Product Dependencies
38.5.1 I/O Lines
The pins used for interfacing the PWM are multiplexed with PIO lines. The programmer must first program the PIO
controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the
application, they can be used for other purposes by the PIO controller.
All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines
will be assigned to PWM outputs.
Table 38-2. I/O Lines
Instance Signal I/O Line Peripheral
PWM PWMFI0 PA9 C
PWM PWMH0 PA0 A
PWM PWMH0 PA11 B
PWM PWMH0 PA23 B
PWM PWMH0 PB0 A
PWM PWMH0 PC18 B
PWM PWMH1 PA1 A
PWM PWMH1 PA12 B
PWM PWMH1 PA24 B
PWM PWMH1 PB1 A
PWM PWMH1 PC19 B
PWM PWMH2 PA2 A
PWM PWMH2 PA13 B
PWM PWMH2 PA25 B
PWM PWMH2 PB4 B
PWM PWMH2 PC20 B
PWM PWMH3 PA7 B
PWM PWMH3 PA14 B
PWM PWMH3 PA17 C
PWM PWMH3 PB14 B
PWM PWMH3 PC21 B
PWM PWML0 PA19 B
PWM PWML0 PB5 B
PWM PWML0 PC0 B
PWM PWML0 PC13 B
PWM PWML1 PA20 B
PWM PWML1 PB12 A
PWM PWML1 PC1 B
PWM PWML1 PC15 B
PWM PWML2 PA16 C
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38.5.2 Power Management
The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management
Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock
can be stopped when not needed and be restarted later. In this case, the PWM will resume its operations where it left off.
In the PWM description, Master Clock (MCK) is the clock of the peripheral bus to which the PWM is connected.
38.5.3 Interrupt Sources
The PWM interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the PWM interrupt
requires the Interrupt Controller to be programmed first. Note that it is not recommended to use the PWM interrupt line in
edge sensitive mode.
38.5.4 Fault Inputs
The PWM has the FAULT inputs connected to the different modules. Please refer to the implementation of these module
within the product for detailed information about the fault generation procedure. The PWM receives faults from PIO
inputs, PMC, ADC controller, Analog Comparator Controller and Timer/Counters.
Note: 1. FPOL bit in PWMC_FMR.
38.6 Functional Description
The PWM macrocell is primarily composed of a clock generator module and 4 channels.
Clocked by the master clock (MCK), the clock generator module provides 13 clocks.
Each channel can independently choose one of the clock generator outputs.
Each channel generates an output waveform with attributes that can be defined independently for each channel
through the user interface registers.
PWM PWML2 PA30 A
PWM PWML2 PB13 A
PWM PWML2 PC2 B
PWM PWML3 PA15 C
PWM PWML3 PC3 B
PWM PWML3 PC22 B
Table 38-2. I/O Lines
Table 38-3. Peripheral IDs
Instance ID
PWM 31
Table 38-4. Fault Inputs
Fault Inputs External PWM Fault Input Number Polarity Level(1) Fault Input ID
PA9 PWMFI0 User Defined 0
Main OSC (PMC) – 1 1
ADC – 1 2
Analog Comparator – 1 3
Timer0 – 1 4
Timer1 – 1 5
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38.6.1 PWM Clock Generator
Figure 38-2. Functional View of the Clock Generator Block Diagram
The PWM master clock (MCK) is divided in the clock generator module to provide different clocks available for all
channels. Each channel can independently select one of the divided clocks.
The clock generator is divided in three blocks:
a modulo n counter which provides 11 clocks: FMCK, FMCK/2, FMCK/4, FMCK/8, FMCK/16, FMCK/32, FMCK/64,
FMCK/128, FMCK/256, FMCK/512, FMCK/1024
two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB
Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be
divided is made according to the PREA (PREB) field of the PWM Clock register (PWM_CLK). The resulting clock clkA
(clkB) is the clock selected divided by DIVA (DIVB) field value.
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to 0. This implies that after reset clkA (clkB)
are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock ”MCK”. This situation is also true when
the PWM master clock is turned off through the Power Management Controller.
CAUTION:
Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management
Controller (PMC).
modulo n counter
MCK/2
MCK/4
MCK/16
MCK/32
MCK/64
MCK/8
Divider A clkA
DIVA
PWM_MR
MCK
MCK/128
MCK/256
MCK/512
MCK/1024
PREA
Divider B clkB
DIVB
PWM_MR
PREB
MCK
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38.6.2 PWM Channel
38.6.2.1Channel Block Diagram
Figure 38-3. Functional View of the Channel Block Diagram
Each of the 4 channels is composed of six blocks:
A clock selector which selects one of the clocks provided by the clock generator (described in Section 38.6.1 on
page 857).
A counter clocked by the output of the clock selector. This counter is incremented or decremented according to the
channel configuration and comparators matches. The size of the counter is 16 bits.
A comparator used to compute the OCx output waveform according to the counter value and the configuration.
The counter value can be the one of the channel counter or the one of the channel 0 counter according to SYNCx
bit in the “PWM Sync Channels Mode Register” on page 890 (PWM_SCM).
A 2-bit configurable gray counter enables the stepper motor driver. One gray counter drives 2 channels.
A dead-time generator providing two complementary outputs (DTOHx/DTOLx) which allows to drive external
power control switches safely.
An output override block that can force the two complementary outputs to a programmed value (OOOHx/OOOLx).
An asynchronous fault protection mechanism that has the highest priority to override the two complementary
outputs (PWMHx/PWMLx) in case of fault detection (outputs forced to 0, 1).
38.6.2.2Comparator
The comparator continuously compares its counter value with the channel period defined by CPRD in the “PWM Channel
Period Register” on page 922 (PWM_CPRDx) and the duty-cycle defined by CDTY in the “PWM Channel Duty Cycle
Register” on page 920 (PWM_CDTYx) to generate an output signal OCx accordingly.
The different properties of the waveform of the output OCx are:
the clock selection. The channel counter is clocked by one of the clocks provided by the clock generator
described in the previous section. This channel parameter is defined in the CPRE field of the “PWM Channel Mode
Register” on page 918 (PWM_CMRx). This field is reset at 0.
Comparator
x
Clock
Select or
Cha nnel x
Dead-Time
Generator Output
Override
OCx DTOHx
DTOLx Fault
Protection
OOOHx PWMHx
PWMLx
OOOLx
Counter
Channel x
Duty-Cycle
Period
Update
Counter
Cha nne l 0
MUX SYNCx
Dead-Time
Generator Output
Override
OCy DTOHy
DTOLy Fault
Protection
OOOHy PWMHy
PWMLy
OOOLy
Channel y (= x+1)
MUX MUX
2-bit gray
counter z
Comparator
y
from
Clock
Generator
from APB
Peripheral Bus
z = 0 (x = 0, y = 1),
z = 1 (x = 2, y = 3),
z = 2 (x = 4, y = 5),
z = 3 (x = 6, y = 7)
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the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be
calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64,
128, 256, 512, or 1024), the resulting period formula will be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center aligned then the output waveform period depends on the counter source clock and can
be calculated:
By using the PWM master clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
the waveform duty-cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is
defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level.
the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be
used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx
register. The default mode is left aligned.
X CPRD×()
MCK
--------------------------------
CRPD DIVA×()
MCK
------------------------------------------ CRPD DIVB×()
MCK
------------------------------------------
2X CPRD××()
MCK
------------------------------------------
2CPRD DIVA××()
MCK
----------------------------------------------------2CPRD×DIVB×()
MCK
----------------------------------------------------
duty cycle period 1 fchannel_x_clock CDTY×⁄–()
period
---------------------------------------------------------------------------------------------------------
=
duty cycle period 2⁄()1 fchannel_x_clock CDTY×⁄–())
period 2⁄()
------------------------------------------------------------------------------------------------------------------------
=
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Figure 38-4. Non Overlapped Center Aligned Waveforms
Note: 1. See Figure 38-5 on page 861 for a detailed description of center aligned waveforms.
When center aligned, the channel counter increases up to CPRD and decreases down to 0. This ends the period.
When left aligned, the channel counter increases up to CPRD and is reset. This ends the period.
Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel.
Waveforms are fixed at 0 when:
CDTY = CPRD and CPOL = 0
CDTY = 0 and CPOL = 1
Waveforms are fixed at 1 (once the channel is enabled) when:
CDTY = 0 and CPOL = 0
CDTY = CPRD and CPOL = 1
The waveform polarity must be set before enabling the channel. This immediately affects the channel output level.
Modifying CPOL in “PWM Channel Mode Register” on page 918 while the channel is enabled can lead to an unexpected
behavior of the device being driven by PWM.
Besides generating output signals OCx, the comparator generates interrupts in function of the counter value. When the
output waveform is left aligned, the interrupt occurs at the end of the counter period. When the output waveform is center
aligned, the bit CES of the PWM_CMRx register defines when the channel counter interrupt occurs. If CES is set to 0, the
interrupt occurs at the end of the counter period. If CES is set to 1, the interrupt occurs at the end of the counter period
and at half of the counter period.
Figure 38-5 “Waveform Properties” illustrates the counter interrupts in function of the configuration.
OC0
OC1
Period
No overlap
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Figure 38-5. Waveform Properties
38.6.2.32-bit Gray Up/Down Counter for Stepper Motor
It is possible to configure a couple of channels to provide a 2-bit gray count waveform on 2 outputs. Dead-Time
Generator and other downstream logic can be configured on these channels.
Up or down count mode can be configured on-the-fly by means of PWM_SMMR configuration registers.
When GCEN0 is set to 1, channels 0 and 1 outputs are driven with gray counter.
Channel x
slected clock
CHIDx(PWM_SR)
Center Aligned
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
PWM_CCNTx
Output Waveform OCx
CPOL(PWM_CMRx) = 0
Output Waveform OCx
CPOL(PWM_CMRx) = 1
Counter Event
CHIDx(PWM_ISR)
CES(PWM_CMRx) = 0
Left Aligned
CPRD(PWM_CPRDx)
CDTY(PWM_CDTYx)
PWM_CCNTx
Output Waveform OCx
CPOL(PWM_CMRx) = 0
Output Waveform OCx
CPOL(PWM_CMRx) = 1
CALG(PWM_CMRx) = 0
CALG(PWM_CMRx) = 1
Period
Period
CHIDx(PWM_ENA)
CHIDx(PWM_DIS)
Counter Event
CHIDx(PWM_ISR)
CES(PWM_CMRx) = 1
Counter Event
CHIDx(PWM_ISR)
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Figure 38-6. 2-bit Gray Up/Down Counter
38.6.2.4Dead-Time Generator
The dead-time generator uses the comparator output OCx to provide the two complementary outputs DTOHx and
DTOLx, which allows the PWM macrocell to drive external power control switches safely. When the dead-time generator
is enabled by setting the bit DTE to 1 or 0 in the “PWM Channel Mode Register” (PWM_CMRx), dead-times (also called
dead-bands or non-overlapping times) are inserted betwee n the edges of the two c omplementar y outputs DTOHx a nd
DTOLx. Note that enabling or disabling the dead-time generator is allowed only if the channel is disabled.
The dead-time is adjustable by the “PWM Channel Dead Time Register” (PWM_DTx). Both outputs of the dead-time
generator can be adjusted separately by DTH and DTL. The dead-time values can be updated synchronously to the
PWM period by using the “PWM Channel Dead Time Update Register” (PWM_DTUPDx).
The dead-time is based on a specific counter which uses the same selected clock that feeds the channel counter of the
comparator. Depending on the edge and the configuration of the dead-time, DTOHx and DTOLx are delayed until the
counter has reached the value defined by DTH or DTL. An inverted configuration bit (DTHI and DTLI bit in the
PWM_CMRx register) is provided for each output to invert the dead-time outputs. The following figure shows the
waveform of the dead-time generator.
PWMH0
DOWNx
GCEN0 = 1
PWMH1
PWML0
PWML1
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Figure 38-7. Complementary Output Waveforms
38.6.2.5Output Override
The two complementary outputs DTOHx and DTOLx of the dead-time generator can be forced to a value defined by the
software.
Figure 38-8. Override Output Selection
The fields OSHx and OSLx in the “PWM Output Selection Register” (PWM_OS) allow the outputs of the dead-time
generator DTOHx and DTOLx to be overridden by the value defined in the fields OOVHx and OOVLx in the“PWM Output
Override Value Register” (PWM_OOV).
The set registers “PWM Output Selection Set Register” and “PWM Output Selection Set Update Register” (PWM_OSS
and PWM_OSSUPD) enable the override of the outputs of a channel regardless of other channels. In the same way, the
clear registers “PWM Output Selection Clear Register” and “PWM Output Selection Clear Update Register” (PWM_OSC
and PWM_OSCUPD) disable the override of the outputs of a channel regardless of other channels.
By using buffer registers PWM_OSSUPD and PWM_OSCUPD, the output selection of PWM outputs is done
synchronously to the channel counter, at the beginning of the next PWM period.
DTHx DTLx
output waveform OCx
CPOLx = 0
output waveform DTOHx
DTHIx = 0
output waveform DTOLx
DTLIx = 0
output waveform DTOHx
DTHIx = 1
output waveform DTOLx
DTLIx = 1
DTHx DTLx
output waveform OCx
CPOLx = 1
output waveform DTOHx
DTHIx = 0
output waveform DTOLx
DTLIx = 0
output waveform DTOHx
DTHIx = 1
output waveform DTOLx
DTLIx = 1
DTOHx
OOVHx
OOOHx
OSHx
0
1
DTOLx
OOVLx
OOOLx
OSLx
0
1
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By using registers PWM_OSS and PWM_OSC, the output selection of PWM outputs is done asynchronously to the
channel counter, as soon as the register is written.
The value of the current output selection can be read in PWM_OS.
While overriding PWM outputs, the channel counters continue to run, only the PWM outputs are forced to user defined
values.
38.6.2.6Fault Protection
6 inputs provide fault protection which can force any of the PWM output pair to a programmable value. This mechanism
has priority over output overriding.
Figure 38-9. Fault Protection
The polarity level of the fault inputs is configured by the FPOL field in the “PWM Fault Mode Register” (PWM_FMR). For
fault inputs coming from internal peripherals such as ADC, Timer Counter, to name but a few, the polarity level must be
FPOL = 1. For fault inputs coming from external GPIO pins the polarity level depends on the user's implementation.
The configuration of the Fault Activation Mode (FMOD bit in PWMC_FMR) depends on the peripheral generating the
fault. If the corresponding peripheral does not have “Fault Clear” management, then the FMOD configuration to use must
be FMOD = 1, to avoid spurious fault detection. Check the corresponding peripheral documentation for details on
handling fault generation.
The fault inputs can be glitch filtered or not in function of the FFIL field in the PWM_FMR register. When the filter is
activated, glitches on fault inputs with a width inferior to the PWM master clock (MCK) period are rejected.
A fault becomes active as soon as its corresponding fault input has a transition to the programmed polarity level. If the
corresponding bit FMOD is set to 0 in the PWM_FMR register, the fault remains active as long as the fault input is at this
polarity level. If the corresponding FMOD bit is set to 1, the fault remains active until the fault input is not at this polarity
level anymore and until it is cleared by writing the corresponding bit FCLR in the “PWM Fault Clear Register”
(PWM_FSCR). By reading the “PWM Fault Status Register” (PWM_FSR), the user can read the current level of the fault
inputs by means of the field FIV, and can know which fault is currently active thanks to the FS field.
Each fault can be taken into account or not by the fault protection mechanism in each channel. To be taken into account
in the channel x, the fault y must be enabled by the bit FPEx[y] in the “PWM Fault Protection Enable Registers”
(PWM_FPE1). However the synchronous channels (see Section 38.6.2.7 “Synchronous Channels”) do not use their own
fault enable bits, but those of the channel 0 (bits FPE0[y]).
The fault protection on a channel is triggered when this channel is enabled and when any one of the faults that are
enabled for this channel is active. It can be triggered even if the PWM master clock (MCK) is not running but only by a
fault input that is not glitch filtered.
FIV0
fault input 0
Fault protection
on PWM
channel x
Glitch
Filter
FFIL0
fromfault0
fromfaulty
1
0=
FPOL0 FMOD0
1
0Fault 0 Status
FS0
FIV1
Glitch
Filter
FFIL1
1
0=
FPOL1
SET
CLR
FMOD1
1
0
OUT
Fault 1 Status
FS1
fault input 1 fromfault1 1
0
0
1
From Output
Override
OOHx
OOLx
From Output
Override
FPVHx
FPVLx
PWMHx
PWMLx
fault input y
FMOD1
SET
CLR
Write FCLR0 at 1
OUT
FMOD0
Write FCLR1 at 1
SYNCx
1
0
FPEx[0]
FPE0[0]
SYNCx
1
0
FPEx[1]
FPE0[1]
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When the fault protection is triggered on a channel, the fault protection mechanism resets the counter of this channel and
for ces the c hanne l outpu ts to the v alues d efined b y the fie lds FPV Hx and FP VLx in th e “PWM Fault Protection Value
Register” (PWM_FPV). The output forcing is made asynchronously to the channel counter.
CAUTION:
To prevent an unexpected activation of the status flag FSy in the PWM_FSR register, the FMODy bit can be set to
“1” only if the FPOLy bit has been previously configured to its final value.
To prevent an unexpected activation of the Fault Protection on the channel x, the bit FPEx[y] can be set to “1” only
if the FPOLy bit has been previously configured to its final value.
If a comparison unit is enabled (see Section 38.6.3 “PWM Comparison Units”) and if a fault is triggered in the channel 0,
in this case the comparison cannot match.
As soon as the fault protection is triggered on a channel, an interrupt (different from the interrupt generated at the end of
the PWM period) can be generated but only if it is enabled and not masked. The interrupt is reset by reading the interrupt
status register, even if the fault which has caused the trigger of the fault protection is kept active.
38.6.2.7Synchronous Channels
Some channels can be linked together as synchronous channels. They have the same source clock, the same period,
the same alignment and are started together. In this way, their counters are synchronized together.
The synchronous channels are defined by the SYNCx bits in the “PWM Sync Channels Mode Register” (PWM_SCM).
Only one group of synchronous channels is allowed.
When a channel is defined as a synchronous channel, the channel 0 is automatically defined as a synchronous channel
too, because the channel 0 counter configuration is used by all the synchronous channels.
If a channel x is defined as a synchronous channel, it uses the following configuration fields of the channel 0 instead of its
own:
CPRE0 field in PWM_CMR0 register instead of CPREx field in PWM_CMRx register (same source clock)
CPRD0 field in PWM_CMR0 register instead of CPRDx field in PWM_CMRx register (same period)
CALG0 field in PWM_CMR0 register instead of CALGx field in PWM_CMRx register (same alignment)
Thus writing these fields of a synchronous channel has no effect on the output waveform of this channel (except channel
0 of course).
Because counters of synchronous channels must start at the same time, they are all enabled together by enabling the
channel 0 (by the CHID0 bit in PWM_ENA register). In the same way, they are all disabled together by disabling channel
0 (by the CHID0 bit in PWM_DIS register). However, a synchronous channel x different from channel 0 can be enabled or
disabled independently from others (by the CHIDx bit in PWM_ENA and PWM_DIS registers).
Defining a channel as a synchronous channel while it is an asynchronous channel (by writing the bit SYNCx to 1 while it
was at 0) is allowed only if the channel is disabled at this time (CHIDx = 0 in PWM_SR register). In the same way, defining
a channel as an asynchronous channel while it is a synchronous channel (by writing the SYNCx bit to 0 while it was 1) is
allowed only if the channel is disabled at this time.
The field UPDM (Update Mode) in the PWM_SCM register allow to select one of the three methods to update the
registers of the synchronous channels:
Method 1 (UPDM = 0): the period value, the duty-cycle values and the dead-time values must be written by the
CPU in their respective update registers (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and
PWM_DTUPDx).The update is triggered at the next PWM period as soon as the bit UPDULOCK in the “PWM
Sync Channels Update Control Register” (PWM_SCUC) is set to 1 (see “Method 1: Manual write of duty-cycle
values and manual trigger of the update” on page 866).
Method 2 (UPDM = 1): the period value, the duty-cycle values, the dead-time values and the update period value
must be written by the CPU in their respective update registers (respectively PWM_CPRDUPDx,
PWM_CDTYUPDx and PWM_DTUPD). The update of the period value and of the dead-time values is triggered at
the next PWM period as soon as the bit UPDULOCK in the “PWM Sync Channels Update Control Register”
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(PWM_SCUC) is set to 1. The update of the duty-cycle values and the update period value is triggered
automatically after an update period defined by the field UPR in the “PWM Sync Channels Update Period
Register” (PWM_SCUP) (see “Method 2: Manual write of duty-cycle values and automatic trigger of the update”
on page 867).
Method 3 (UPDM = 2): same as Method 2 apart from the fact that the duty-cycle values of ALL synchronous
channels are written by the Peripheral DMA Controller (PDC) (see “Method 3: Automatic write of duty-cycle values
and automatic trigger of the update” on page 868). The user can choose to synchronize the PDC transfer request
with a comparison match (see Section 38.6.3 “PWM Comparison Units”), by the fields PTRM and PTRCS in the
PWM_SCM register.
Method 1: Manual write of duty-cycle values and manual trigger of the update
In this mode, the update of the period value, the duty-cycle values and the dead-time values must be done by writing in
their respective update registers with the CPU (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and
PWM_DTUPDx).
To trigger the update, the user must use the bit UPDULOCK of the “PWM Sync Channels Update Control Register”
(PWM_SCUC) which allows to update synchronously (at the same PWM period) the synchronous channels:
If the bit UPDULOCK is set to 1, the update is done at the next PWM period of the synchronous channels.
If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
After writing the UPDULOCK bit to 1, it is held at this value until the update occurs, then it is read 0.
Sequence for Method 1:
1. Select the manual write of duty-cycle values and the manual update by setting the UPDM field to 0 in the
PWM_SCM register
2. Define the synchronous channels by the SYNCx bits in the PWM_SCM register.
3. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
Table 38-5. Summary of the Update of Registers of Synchronous Channels
UPDM=0 UPDM=1 UPDM=2
Period Value
(PWM_CPRDUPDx)
Write by the CPU
Update is triggered at the
next PWM period as soon as
the bit UPDULOCK is set to 1
Dead-Time Values
(PWM_DTUPDx)
Write by the CPU
Update is triggered at the
next PWM period as soon as
the bit UPDULOCK is set to 1
Duty-Cycle Values
(PWM_CDTYUPDx)
Write by the CPU Write by the CPU Write by the PDC
Update is triggered at the next
PWM period as soon as the bit
UPDULOCK is set to 1
Update is triggered at the next
PWM period as soon as the update period
counter has reached the value UPR
Update Period Value
(PWM_SCUPUPD)
Not applicable Write by the CPU
Not applicable Update is triggered at the next
PWM period as soon as the update period
counter has reached the value UPR
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4. If an update of the period value and/or the duty-cycle values and/or the dead-time values is required, write regis-
ters that need to be updated (PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx).
5. Set UPDULOCK to 1 in PWM_SCUC.
6. The update of the registers will occur at the beginning of the next PWM period. At this moment the UPDULOCK bit
is reset, go to Step 4.) for new values.
Figure 38-10.Method 1 (UPDM = 0)
Method 2: Manual write of duty-cycle values and automatic trigger of the update
In this mode, the update of the period value, the duty-cycle values, the dead-time values and the update period value
must be done by writing in their respective update registers with the CPU (respectively PWM_CPRDUPDx,
PWM_CDTYUPDx, PWM_DTUPDx and PWM_SCUPUPD).
To trigger the update of the period value and the dead-time values, the user must use the bit UPDULOCK of the “PWM
Sync Channels Update Control Register” (PWM_SCUC) which allows to update synchronously (at the same PWM
period) the synchronous channels:
If the bit UPDULOCK is set to 1, the update is done at the next PWM period of the synchronous channels.
If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
After writing the UPDULOCK bit to 1, it is held at this value until the update occurs, then it is read 0.
The update of the duty-cycle values and the update period is triggered automatically after an update period.
To co nfigu re the au tomat ic upda te, the u ser mus t defin e a value f or the Up date Pe riod by t he UPR fi eld in th e “PWM
Sync Channels Update Period Register” (PWM_SCUP). The PWM controller waits UPR+1 period of synchronous
channels before updating automatically the duty values and the update period value.
The status of the duty-cycle value write is reported in the “PWM Interrupt Status Register 2” (PWM_ISR2) by the
following flags:
WRDY: this flag is set to 1 when the PWM Controller is ready to receive new duty-cycle values and a new update
period value. It is reset to 0 when the PWM_ISR2 register is read.
Depending on the interrupt mask in the PWM_IMR2 register, an interrupt can be generated by these flags.
Sequence for Method 2:
1. Select the manual write of duty-cycle values and the automatic update by setting the field UPDM to 1 in the
PWM_SCM register
2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register.
3. Define the update period by the field UPR in the PWM_SCUP register.
4. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
5. If an update of the period value and/or of the dead-time values is required, write registers that need to be updated
(PWM_CPRDUPDx, PWM_DTUPDx), else go to Step 8.
6. Set UPDULOCK to 1 in PWM_SCUC.
CCNT0
CDTYUPD 0x20 0x40 0x60
UPDULOCK
CDTY 0x20 0x40 0x60
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7. The update of these registers will occur at the beginning of the next PWM period. At this moment the bit UPDU-
LOCK is reset, go to Step 5. for new values.
8. If an update of the duty-cycle values and/or the update period is required, check first that write of new update val-
ues is possible by polling the flag WRDY (or by waiting for the corresponding interrupt) in the PWM_ISR2 register.
9. Write registers that need to be updated (PWM_CDTYUPDx, PWM_SCUPUPD).
10. The update of these registers will occur at the next PWM period of the synchronous channels when the Update
Period is elapsed. Go to Step 8. for new values.
Figure 38-11.Method 2 (UPDM=1)
Method 3: Automatic write of duty-cycle values and automatic trigger of the update
In this mode, the update of the duty cycle values is made automatically by the Peripheral DMA Controller (PDC). The
update of the period value, the dead-time values and the update period value must be done by writing in their respective
update registers with the CPU (respectively PWM_CPRDUPDx, PWM_DTUPDx and PWM_SCUPUPD).
To trigger the update of the period value and the dead-time values, the user must use the bit UPDULOCK which allows to
update synchronously (at the same PWM period) the synchronous channels:
If the bit UPDULOCK is set to 1, the update is done at the next PWM period of the synchronous channels.
If the UPDULOCK bit is not set to 1, the update is locked and cannot be performed.
After writing the UPDULOCK bit to 1, it is held at this value until the update occurs, then it is read 0.
The update of the duty-cycle values and the update period value is triggered automatically after an update period.
To co nfigu re the au tomat ic upda te, the u ser mus t defin e a value f or the Up date Pe riod by t he fiel d UPR in th e “PWM
Sync Channels Update Period Register” (PWM_SCUP). The PWM controller waits UPR+1 periods of synchronous
channels before updating automatically the duty values and the update period value.
Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly reduces
the number of clock cycles required for a data transfer, which improves microcontroller performance.
The PDC must write the duty-cycle values in the synchronous channels index order. For example if the channels 0, 1 and
3 are synchronous channels, the PDC must write the duty-cycle of the channel 0 first, then the duty-cycle of the channel
1, and finally the duty-cycle of the channel 3.
The status of the PDC transfer is reported in the “PWM Interrupt Status Register 2” (PWM_ISR2) by the following flags:
WRDY: this flag is set to 1 when the PWM Controller is ready to receive new duty-cycle values and a new update
period value. It is reset to 0 when the PWM_ISR2 register is read. The user can choose to synchronize the WRDY
CCNT0
CDTYUPD 0x20 0x40 0x60
UPRCNT 0x0 0x1 0x0 0x1 0x0 0x1
CDTY 0x20 0x40
UPRUPD 0x1 0x3
WRDY
0x60
0x0 0x1 0x2 0x3 0x0 0x1 0x2
UPR 0x1 0x3
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flag and the PDC transfer request with a comparison match (see Section 38.6.3 “PWM Comparison Units”), by the
fields PTRM and PTRCS in the PWM_SCM register.
ENDTX: this flag is set to 1 when a PDC transfer is completed
TXBUFE: this flag is set to 1 when the PDC buffer is empty (no pending PDC transfers)
UNRE: this flag is set to 1 when the update period defined by the UPR field has elapsed while the whole data has
not been written by the PDC. It is reset to 0 when the PWM_ISR2 register is read.
Depending on the interrupt mask in the PWM_IMR2 register, an interrupt can be generated by these flags.
Sequence for Method 3:
1. Select the automatic write of duty-cycle values and automatic update by setting the field UPDM to 2 in the
PWM_SCM register.
2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register.
3. Define the update period by the field UPR in the PWM_SCUP register.
4. Define when the WRDY flag and the corresponding PDC transfer request must be set in the update period by the
PTRM bit and the PTRCS field in the PWM_SCM register (at the end of the update period or when a comparison
matches).
5. Define the PDC transfer settings for the duty-cycle values and enable it in the PDC registers
6. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
7. If an update of the period value and/or of the dead-time values is required, write registers that need to be updated
(PWM_CPRDUPDx, PWM_DTUPDx), else go to Step 10.
8. Set UPDULOCK to 1 in PWM_SCUC.
9. The update of these registers will occur at the beginning of the next PWM period. At this moment the bit UPDU-
LOCK is reset, go to Step 7. for new values.
10. If an update of the update period value is required, check first that write of a new update value is possible by poll-
ing the flag WRDY (or by waiting for the corresponding interrupt) in the PWM_ISR2 register, else go to Step 13.
11. Write the register that needs to be updated (PWM_SCUPUPD).
12. The update of this register will occur at the next PWM period of the synchronous channels when the Update Period
is elapsed. Go to Step 10. for new values.
13. Check the end of the PDC transfer by the flag ENDTX. If the transfer has ended, define a new PDC transfer in the
PDC registers for new duty-cycle values. Go to Step 5.
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Figure 38-12.Method 3 (UPDM=2 and PTRM=0)
Figure 38-13.Method 3 (UPDM=2 and PTRM=1 and PTRCS=0)
CCNT0
CDTYUPD 0x20 0x40 0x60
UPRCNT 0x0 0x1 0x0 0x1 0x0 0x1
CDTY
UPRUPD 0x1 0x3
transfer request
WRDY
0x0 0x1 0x2 0x3 0x0 0x1 0x2
UPR 0x1 0x3
0x80 0xA0 0xB0
0x20 0x40 0x60 0x80 0xA0
CCNT0
CDTYUPD 0x20 0x40 0x60
UPRCNT 0x0 0x1 0x0 0x1 0x0 0x1
CDTY
UPRUPD 0x1 0x3
CMP0 match
transfer request
WRDY
0x0 0x1 0x2 0x3 0x0 0x1 0x2
UPR 0x1 0x3
0x80 0xA0 0xB0
0x20 0x40 0x60 0x80 0xA0
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38.6.3 PWM Comparison Units
The PWM provides 8 independent comparison units able to compare a programmed value with the current value of the
channel 0 counter (which is the channel counter of all synchronous channels, Section 38.6.2.7 “Synchronous Channels”).
These comparisons are intended to generate pulses on the event lines (used to synchronize ADC, see Section 38.6.4
“PWM Event Lines”), to generate software interrupts and to trigger PDC transfer requests for the synchronous channels
(see “Method 3: Automatic write of duty-cycle values and automatic trigger of the update” on page 868).
Figure 38-14.Comparison Unit Block Diagram
The comparison x matches when it is enabled by the bit CEN in the “PWM Comparison x Mode Register”
(PWM_CMPMx for the comparison x) and when the counter of the channel 0 reaches the comparison value defined by
the field CV in “PWM Comparison x Value Register” (PWM_CMPVx for the comparison x). If the counter of the channel
0 is center aligned (CALG = 1 in “PWM Channel Mode Register” ), the bit CVM (in PWM_CMPVx) defines if the
comparison is made when the counter is counting up or counting down (in left alignment mode CALG=0, this bit is
useless).
If a fault is active on the channel 0, the comparison is disabled and cannot match (see Section 38.6.2.6 “Fault
Protection”).
The user can define the periodicity of the comparison x by the fields CTR and CPR (in PWM_CMPVx). The comparison
is performed periodically once every CPR+1 periods of the counter of the channel 0, when the value of the comparison
period counter CPRCNT (in PWM_CMPMx) reaches the value defined by CTR. CPR is the maximum value of the
comparison period counter CPRCNT. If CPR=CTR=0, the comparison is performed at each period of the counter of the
channel 0.
The comparison x configuration can be modified while the channel 0 is enabled by using the “PWM Comparison x Mode
Update Register” (PWM_CMPMUPDx registers for the comparison x). In the same way, the comparison x value can be
modified while the channel 0 is enabled by using the “PWM Comparison x Value Update Register” (PWM_CMPVUPDx
registers for the comparison x).
The update of the comparison x configuration and the comparison x value is triggered periodically after the comparison x
update period. It is defined by the field CUPR in the PWM_CMPMx. The comparison unit has an update period counter
independent from the period counter to trigger this update. When the value of the comparison update period counter
CUPRCNT (in PWM_CMPMx) reaches the value defined by CUPR, the update is triggered. The comparison x update
period CUPR itself can be updated while the channel 0 is enabled by using the PWM_CMPMUPDx register.
CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be followed by a write of the
register PWM_CMPMUPDx.
=
fault on channel 0
CNT [PWM_CCNT0]
CNT [PWM_CCNT0] is decrementing
CALG [PWM_CMR0]
CV [PWM_CMPVx]
=1
0
1
Comparison x
CVM [PWM_CMPVx]
=
CPRCNT [PWM_CMPMx]
CTR [PWM_CMPMx]
CEN [PWM_CMPM]x
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The comparison match and the comparison update can be source of an interrupt, but only if it is enabled and not
masked. These interrupts can be enabled by the “PWM Interrupt Enable Register 2” and disabled by the “PWM Interrupt
Disable Register 2” . The comparison match interrupt and the comparison update interrupt are reset by reading the
“PWM Interrupt Status Register 2” .
Figure 38-15.Comparison Waveform
CCNT0
CVUPD
0x6 0x2
CVMVUPD
CV
0x6 0x2
0x6
0x6
CVM
Comparison Update
CMPU
CTRUPD
0x1 0x2
CPR
0x1 0x3
0x0 0x1 0x0 0x1 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3
CPRCNT
0x0 0x1 0x2 0x3 0x0 0x1 0x2
0x0
0x1 0x2 0x0 0x1
CUPRCNT
CPRUPD
0x1 0x3
CUPRUPD
0x3 0x2
CTR
0x1 0x2
CUPR
0x3 0x2
Comparison Match
CMPM
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38.6.4 PWM Event Lines
The PWM provides 2 independent event lines intended to trigger actions in other peripherals (in particular for ADC
(Analog-to-Digital Converter)).
A pulse (one cycle of the master clock (MCK)) is generated on an event line, when at least one of the selected
comparisons is matching. The comparisons can be selected or unselected independently by the CSEL bits in the “PWM
Event Line x Register” (PWM_ELMRx for the Event Line x).
Figure 38-16.Event Line Block Diagram
38.6.5 PWM Controller Operations
38.6.5.1Initialization
Before enabling the channels, they must have been configured by the software application:
Unlock User Interface by writing the WPCMD field in the PWM_WPCR Register.
Configuration of the clock generator (DIVA, PREA, DIVB, PREB in the PWM_CLK register if required).
Selection of the clock for each channel (CPRE field in the PWM_CMRx register)
Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register)
Selection of the counter event selection (if CALG = 1) for each channel (CES field in the PWM_CMRx register)
Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register)
Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx
register is possible while the channel is disabled. After validation of the channel, the user must use
PWM_CPRDUPDx register to update PWM_CPRDx as explained below.
Configuration of the duty-cycle for each channel (CDTY in the PWM_CDTYx register). Writing in PWM_CDTYx
register is possible while the channel is disabled. After validation of the channel, the user must use
PWM_CDTYUPDx register to update PWM_CDTYx as explained below.
Configuration of the dead-time generator for each channel (DTH and DTL in PWM_DTx) if enabled (DTE bit in the
PWM_CMRx register). Writing in the PWM_DTx register is possible while the channel is disabled. After validation
of the channel, the user must use PWM_DTUPDx register to update PWM_DTx
Selection of the synchronous channels (SYNCx in the PWM_SCM register)
Selection of the moment when the WRDY flag and the corresponding PDC transfer request are set (PTRM and
PTRCS in the PWM_SCM register)
Configuration of the update mode (UPDM in the PWM_SCM register)
Configuration of the update period (UPR in the PWM_SCUP register) if needed.
Configuration of the comparisons (PWM_CMPVx and PWM_CMPMx).
Configuration of the event lines (PWM_ELMRx).
Configuration of the fault inputs polarity (FPOL in PWM_FMR)
Configuration of the fault protection (FMOD and FFIL in PWM_FMR, PWM_FPV and PWM_FPE1)
PULSE
GENERATOR Event Line x
CSEL0 (PWM_ELMRx)
CMPM0 (PWM_ISR2)
CSEL1 (PWM_ELMRx)
CMPM1 (PWM_ISR2)
CSEL2 (PWM_ELMRx)
CMPM2 (PWM_ISR2)
CSEL7 (PWM_ELMRx)
CMPM7 (PWM_ISR2)
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Enable of the Interrupts (writing CHIDx and FCHIDx in PWM_IER1 register, and writing WRDYE, ENDTXE,
TXBUFE, UNRE, CMPMx and CMPUx in PWM_IER2 register)
Enable of the PWM channels (writing CHIDx in the PWM_ENA register)
38.6.5.2Source Clock Selection Criteria
The large number of source clocks can make selection difficult. The relationship between the value in the “PWM Channel
Period Register” (PWM_CPRDx) and the “PWM Channel Duty Cycle Register” (PWM_CDTYx) can help the user in
choosing. The event number written in the Period Register gives the PWM accuracy. The Duty-Cycle quantum cannot be
lower than 1/CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy.
For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value from between 1 up to 14 in
PWM_CDTYx Register. The resulting duty-cycle quantum cannot be lower than 1/15 of the PWM period.
38.6.5.3Changing the Duty-Cycle, the Period and the Dead-Times
It is possible to modulate the output waveform duty-cycle, period and dead-times.
To prevent unexpected output waveform, the user must use the “PWM Channel Duty Cycle Update Register” , the “PWM
Channel Period Update Register” a nd t he “PWM Channel Dead Time Update Register” (PWM_CDTYUPDx,
PWM_CPRDUPDx and PWM_DTUPDx) to change waveform parameters while the channel is still enabled.
If the channel is an asynchronous channel (SYNCx = 0 in “PWM Sync Channels Mode Register” (PWM_SCM)),
these registers hold the new period, duty-cycle and dead-times values until the end of the current PWM period and
update the values for the next period.
If the channel is a synchronous channel and update method 0 is selected (SYNCx = 1 and UPDM = 0 in
PWM_SCM register), these registers hold the new period, duty-cycle and dead-times values until the bit
UPDULOCK is written at “1” (in “PWM Sync Channels Update Control Register” (PWM_SCUC)) and the end of
the current PWM period, then update the values for the next period.
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If the channel is a synchronous channel and update method 1 or 2 is selected (SYNCx=1 and UPDM=1 or 2 in
PWM_SCM register):
registers PWM_CPRDUPDx and PWM_DTUPDx hold the new period and dead-times values until the bit
UPDULOCK is written at “1” (in PWM_SCUC register) and the end of the current PWM period, then update
the values for the next period.
register PWM_CDTYUPDx holds the new duty-cycle value until the end of the update period of synchronous
channels (when UPRCNT is equal to UPR in “PWM Sync Channels Update Period Register”
(PWM_SCUP)) and the end of the current PWM period, then updates the value for the next period.
Note: If the update registers PWM_CDTYUPDx, PWM_CPRDUPDx and PWM_DTUPDx are written several times
between two updates, only the last written value is taken into account.
Figure 38-17.Synchronized Period, Duty-Cycle and Dead-Times Update
PWM_CPRDUPDx Value
PWM_CPRDx PWM_CDTYx
- If Asynchronous Channel
-> End of PWM period
- If Synchronous Channel
-> End of PWM period and UPDULOCK = 1
Users Writing
PWM_DTUPDx Value
Users Writing
PWM_DTx
- If Asynchronous Channel
-> End of PWM period
- If Synchronous Channel
-IfUPDM=0
-> End of PWM period and UPDULOCK = 1
-IfUPDM=1or2
-> End of PWM period and end of Update Period
PWM_CDTYUPDx Value
Users Writing
876
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.6.5.4Changing the Synchronous Channels Update Period
It is possible to change the update period of synchronous channels while they are enabled. (See “Method 2: Manual write
of duty-cycle values and automatic trigger of the update” on page 867 and “Method 3: Automatic write of duty-cycle
values and automatic trigger of the update” on page 868.)
To prevent an unexpected update of the synchronous channels registers, the user must use the “PWM Sync Channels
Update Period Update Register” (PWM_SCUPUPD) to change the update period of synchronous channels while they
are still enabled. This register holds the new value until the end of the update period of synchronous channels (when
UPRCNT is equal to UPR in “PWM Sync Channels Update Period Register” (PWM_SCUP)) and the end of the current
PWM period, then updates the value for the next period.
Note: If the update register PWM_SCUPUPD is written several times between two updates, only the last written value
is taken into account.
Note: Changing the update period does make sense only if there is one or more synchronous channels and if the
update method 1 or 2 is selected (UPDM = 1 or 2 in “PWM Sync Channels Mode Register” ).
Figure 38-18.Synchronized Update of Update Period Value of Synchronous Channels
End of PWM period and
end of Update Period
of Synchronous Channels
PWM_SCUPUPD Value
Users Writing
PWM_SCUP
877
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.6.5.5Changing the Comparison Value and the Comparison Configuration
It is possible to change the comparison values and the comparison configurations while the channel 0 is enabled (see
Section 38.6.3 “PWM Comparison Units”).
To prevent unexpected comparison match, the user must use the “PWM Comparison x Value Update Register” and the
“PWM Comparison x Mode Update Register” (PWM_CMPVUPDx and PWM_CMPMUPDx) to change respectively the
comparison values and the comparison configurations while the channel 0 is still enabled. These registers hold the new
values until the end of the comparison update period (when CUPRCNT is equal to CUPR in “PWM Comparison x Mode
Register” (PWM_CMPMx) and the end of the current PWM period, then update the values for the next period.
CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be followed by a write of the
register PWM_CMPMUPDx.
Note: If the update registers PWM_CMPVUPDx and PWM_CMPMUPDx are written several times between two
updates, only the last written value are taken into account.
Figure 38-19.Synchronized Update of Comparison Values and Configurations
38.6.5.6Interrupts
Depending on the interrupt mask in the PWM_IMR1 and PWM_IMR2 registers, an interrupt can be generated at the end
of the corresponding channel period (CHIDx in the PWM_ISR1 register), after a fault event (FCHIDx in the PWM_ISR1
register), after a comparison match (CMPMx in the PWM_ISR2 register), after a comparison update (CMPUx in the
PWM_ISR2 register) or according to the transfer mode of the synchronous channels (WRDY, ENDTX, TXBUFE and
UNRE in the PWM_ISR2 register).
If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a read operation in the
PWM_ISR1 register occurs.
If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt remains active until a read
operation in the PWM_ISR2 register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER1 and PWM_IER2 registers. A channel
interrupt is disabled by setting the corresponding bit in the PWM_IDR1 and PWM_IDR2 registers.
PWM_CMPVUPDx Value
Comparison Value
for comparison x
Users Writing
PWM_CMPVx
End of channel0 PWM period and
end of Comparison Update Period
PWM_CMPMUPDx Value
Comparison configuration
for comparison x
PWM_CMPMx
Users Writing
End of channel0 PWM period and
end of Comparison Update Period and
and PWM_CMPMx written
878
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.6.5.7Write Protect Registers
To prevent any single software error that may corrupt PWM behavior, the registers listed below can be write-protected by
writing the field WPCMD in the “PWM Write Protect Control Register” on page 911 (PWM_WPCR). They are divided into
6 groups:
Register group 0:
“PWM Clock Register” on page 882
Register group 1:
“PWM Disable Register” on page 884
Register group 2:
“PWM Sync Channels Mode Register” on page 890
“PWM Channel Mode Register” on page 918
“PWM Stepper Motor Mode Register” on page 910
Register group 3:
“PWM Channel Period Register” on page 922
“PWM Channel Period Update Register” on page 923
Register group 4:
“PWM Channel Dead Time Register” on page 925
“PWM Channel Dead Time Update Register” on page 926
Register group 5:
“PWM Fault Mode Register” on page 904
“PWM Fault Protection Value Register” on page 907
There are two types of Write Protect:
Write Protect SW, which can be enabled or disabled.
Write Protect HW, which can just be enabled, only a hardware reset of the PWM controller can disable it.
Both types of Write Protect can be applied independently to a particular register group by means of the WPCMD and
WPRG fields in PWM_WPCR register. If at least one Write Protect is active, the register group is write-protected. The
field WPCMD allows to perform the following actions depending on its value:
0 = Disabling the Write Protect SW of the register groups of which the bit WPRG is at 1.
1 = Enabling the Write Protect SW of the register groups of which the bit WPRG is at 1.
2 = Enabling the Write Protect HW of the register groups of which the bit WPRG is at 1.
At any time, the user can determine which Write Protect is active in which register group by the fields WPSWS and
WPHWS in the “PWM Write Protect Status Register” on page 913 (PWM_WPSR).
If a write access in a write-protected register is detected, then the WPVS flag in the PWM_WPSR register is set and the
field WPVSRC indicates in which register the write access has been attempted, through its address offset without the two
LSBs.
The WPVS and PWM_WPSR fields are automatically reset after reading the PWM_WPSR register.
879
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7 Pulse Width Modulation Controller (PWM) Controller User Interface
Table 38-6. Register Mapping
Offset Register Name Access Reset
0x00 PWM Clock Register PWM_CLK Read-write 0x0
0x04 PWM Enable Register PWM_ENA Write-only –
0x08 PWM Disable Register PWM_DIS Write-only –
0x0C PWM Status Register PWM_SR Read-only 0x0
0x10 PWM Interrupt Enable Register 1 PWM_IER1 Write-only –
0x14 PWM Interrupt Disable Register 1 PWM_IDR1 Write-only –
0x18 PWM Interrupt Mask Register 1 PWM_IMR1 Read-only 0x0
0x1C PWM Interrupt Status Register 1 PWM_ISR1 Read-only 0x0
0x20 PWM Sync Channels Mode Register PWM_SCM Read-write 0x0
0x24 Reserved – – –
0x28 PWM Sync Channels Update Control Register PWM_SCUC Read-write 0x0
0x2C PWM Sync Channels Update Period Register PWM_SCUP Read-write 0x0
0x30 PWM Sync Channels Update Period Update Register PWM_SCUPUPD Write-only 0x0
0x34 PWM Interrupt Enable Register 2 PWM_IER2 Write-only –
0x38 PWM Interrupt Disable Register 2 PWM_IDR2 Write-only –
0x3C PWM Interrupt Mask Register 2 PWM_IMR2 Read-only 0x0
0x40 PWM Interrupt Status Register 2 PWM_ISR2 Read-only 0x0
0x44 PWM Output Override Value Register PWM_OOV Read-write 0x0
0x48 PWM Output Selection Register PWM_OS Read-write 0x0
0x4C PWM Output Selection Set Register PWM_OSS Write-only –
0x50 PWM Output Selection Clear Register PWM_OSC Write-only –
0x54 PWM Output Selection Set Update Register PWM_OSSUPD Write-only –
0x58 PWM Output Selection Clear Update Register PWM_OSCUPD Write-only –
0x5C PWM Fault Mode Register PWM_FMR Read-write 0x0
0x60 PWM Fault Status Register PWM_FSR Read-only 0x0
0x64 PWM Fault Clear Register PWM_FCR Write-only –
0x68 PWM Fault Protection Value Register PWM_FPV Read-write 0x0
0x6C PWM Fault Protection Enable Register PWM_FPE Read-write 0x0
0x70-0x78 Reserved – – –
0x7C PWM Event Line 0 Mode Register PWM_ELMR0 Read-write 0x0
0x80 PWM Event Line 1 Mode Register PWM_ELMR1 Read-write 0x0
0x84-0x9C Reserved – – –
0xA0 - 0xAC Reserved – – –
0xB0 PWM Stepper Motor Mode Register PWM_SMMR Read-write 0x0
0xB4-0xBC Reserved – – –
880
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
0xC0-E0 Reserved – – –
0xE4 PWM Write Protect Control Register PWM_WPCR Write-only –
0xE8 PWM Write Protect Status Register PWM_WPSR Read-only 0x0
0xEC - 0xFC Reserved – – –
0x100 - 0x128 Reserved for PDC registers – – –
0x12C Reserved – – –
0x130 PWM Comparison 0 Value Register PWM_CMPV0 Read-write 0x0
0x134 PWM Comparison 0 Value Update Register PWM_CMPVUPD0 Write-only –
0x138 PWM Comparison 0 Mode Register PWM_CMPM0 Read-write 0x0
0x13C PWM Comparison 0 Mode Update Register PWM_CMPMUPD0 Write-only –
0x140 PWM Comparison 1 Value Register PWM_CMPV1 Read-write 0x0
0x144 PWM Comparison 1 Value Update Register PWM_CMPVUPD1 Write-only –
0x148 PWM Comparison 1 Mode Register PWM_CMPM1 Read-write 0x0
0x14C PWM Comparison 1 Mode Update Register PWM_CMPMUPD1 Write-only –
0x150 PWM Comparison 2 Value Register PWM_CMPV2 Read-write 0x0
0x154 PWM Comparison 2 Value Update Register PWM_CMPVUPD2 Write-only –
0x158 PWM Comparison 2 Mode Register PWM_CMPM2 Read-write 0x0
0x15C PWM Comparison 2 Mode Update Register PWM_CMPMUPD2 Write-only –
0x160 PWM Comparison 3 Value Register PWM_CMPV3 Read-write 0x0
0x164 PWM Comparison 3 Value Update Register PWM_CMPVUPD3 Write-only –
0x168 PWM Comparison 3 Mode Register PWM_CMPM3 Read-write 0x0
0x16C PWM Comparison 3 Mode Update Register PWM_CMPMUPD3 Write-only –
0x170 PWM Comparison 4 Value Register PWM_CMPV4 Read-write 0x0
0x174 PWM Comparison 4 Value Update Register PWM_CMPVUPD4 Write-only –
0x178 PWM Comparison 4 Mode Register PWM_CMPM4 Read-write 0x0
0x17C PWM Comparison 4 Mode Update Register PWM_CMPMUPD4 Write-only –
0x180 PWM Comparison 5 Value Register PWM_CMPV5 Read-write 0x0
0x184 PWM Comparison 5 Value Update Register PWM_CMPVUPD5 Write-only –
0x188 PWM Comparison 5 Mode Register PWM_CMPM5 Read-write 0x0
0x18C PWM Comparison 5 Mode Update Register PWM_CMPMUPD5 Write-only –
0x190 PWM Comparison 6 Value Register PWM_CMPV6 Read-write 0x0
0x194 PWM Comparison 6 Value Update Register PWM_CMPVUPD6 Write-only –
0x198 PWM Comparison 6 Mode Register PWM_CMPM6 Read-write 0x0
0x19C PWM Comparison 6 Mode Update Register PWM_CMPMUPD6 Write-only –
0x1A0 PWM Comparison 7 Value Register PWM_CMPV7 Read-write 0x0
0x1A4 PWM Comparison 7 Value Update Register PWM_CMPVUPD7 Write-only –
0x1A8 PWM Comparison 7 Mode Register PWM_CMPM7 Read-write 0x0
Table 38-6. Register Mapping (Continued)
Offset Register Name Access Reset
881
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Notes: 1. Some registers are indexed with “ch_num” index ranging from 0 to 3.
0x1AC PWM Comparison 7 Mode Update Register PWM_CMPMUPD7 Write-only –
0x1B0 - 0x1FC Reserved – – –
0x200 + ch_num *
0x20 + 0x00 PWM Channel Mode Register(1) PWM_CMR Read-write 0x0
0x200 + ch_num *
0x20 + 0x04 PWM Channel Duty Cycle Register(1) PWM_CDTY Read-write 0x0
0x200 + ch_num *
0x20 + 0x08 PWM Channel Duty Cycle Update Register(1) PWM_CDTYUPD Write-only –
0x200 + ch_num *
0x20 + 0x0C PWM Channel Period Register(1) PWM_CPRD Read-write 0x0
0x200 + ch_num *
0x20 + 0x10 PWM Channel Period Update Register(1) PWM_CPRDUPD Write-only –
0x200 + ch_num *
0x20 + 0x14 PWM Channel Counter Register(1) PWM_CCNT Read-only 0x0
0x200 + ch_num *
0x20 + 0x18 PWM Channel Dead Time Register(1) PWM_DT Read-write 0x0
0x200 + ch_num *
0x20 + 0x1C PWM Channel Dead Time Update Register(1) PWM_DTUPD Write-only –
Table 38-6. Register Mapping (Continued)
Offset Register Name Access Reset
882
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.1 PWM Clock Register
Name: PWM_CLK
Address: 0x40020000
Access: Read-write
This register can only be written if the bits WPSWS0 and WPHWS0 are cleared in “PWM Write Protect Status Register” on page
913.
• DIVA, DIVB: CLKA, CLKB Divide Factor
• PREA, PREB: CLKA, CLKB Source Clock Selection
31 30 29 28 27 26 25 24
– – – – PREB
23 22 21 20 19 18 17 16
DIVB
15 14 13 12 11 10 9 8
– – – – PREA
76543210
DIVA
DIVA, DIVB CLKA, CLKB
0 CLKA, CLKB clock is turned off
1 CLKA, CLKB clock is clock selected by PREA, PREB
2-255 CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
PREA, PREB Divider Input Clock
0000MCK
0001MCK/2
0010MCK/4
0011MCK/8
0100MCK/16
0101MCK/32
0110MCK/64
0111MCK/128
1000MCK/256
1001MCK/512
1010MCK/1024
Other Reserved
883
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.2 PWM Enable Register
Name: PWM_ENA
Address: 0x40020004
Access: Write-only
• CHIDx: Channel ID
0 = No effect.
1 = Enable PWM output for channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – CHID3 CHID2 CHID1 CHID0
884
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.3 PWM Disable Register
Name: PWM_DIS
Address: 0x40020008
Access: Write-only
This register can only be written if the bits WPSWS1 and WPHWS1 are cleared in “PWM Write Protect Status Register” on page
913.
• CHIDx: Channel ID
0 = No effect.
1 = Disable PWM output for channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – CHID3 CHID2 CHID1 CHID0
885
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.4 PWM Status Register
Name: PWM_SR
Address: 0x4002000C
Access: Read-only
• CHIDx: Channel ID
0 = PWM output for channel x is disabled.
1 = PWM output for channel x is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – CHID3 CHID2 CHID1 CHID0
886
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.5 PWM Interrupt Enable Register 1
Name: PWM_IER1
Address: 0x40020010
Access: Write-only
• CHIDx: Counter Event on Channel x Interrupt Enable
• FCHIDx: Fault Protection Trigger on Channel x Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – FCHID3 FCHID2 FCHID1 FCHID0
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – CHID3 CHID2 CHID1 CHID0
887
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.6 PWM Interrupt Disable Register 1
Name: PWM_IDR1
Address: 0x40020014
Access: Write-only
• CHIDx: Counter Event on Channel x Interrupt Disable
• FCHIDx: Fault Protection Trigger on Channel x Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – FCHID3 FCHID2 FCHID1 FCHID0
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – CHID3 CHID2 CHID1 CHID0
888
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.7 PWM Interrupt Mask Register 1
Name: PWM_IMR1
Address: 0x40020018
Access: Read-only
• CHIDx: Counter Event on Channel x Interrupt Mask
• FCHIDx: Fault Protection Trigger on Channel x Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – FCHID3 FCHID2 FCHID1 FCHID0
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – CHID3 CHID2 CHID1 CHID0
889
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.8 PWM Interrupt Status Register 1
Name: PWM_ISR1
Address: 0x4002001C
Access: Read-only
• CHIDx: Counter Event on Channel x
0 = No new counter event has occurred since the last read of the PWM_ISR1 register.
1 = At least one counter event has occurred since the last read of the PWM_ISR1 register.
• FCHIDx: Fault Protection Trigger on Channel x
0 = No new trigger of the fault protection since the last read of the PWM_ISR1 register.
1 = At least one trigger of the fault protection since the last read of the PWM_ISR1 register.
Note: Reading PWM_ISR1 automatically clears CHIDx and FCHIDx flags.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – FCHID3 FCHID2 FCHID1 FCHID0
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – CHID3 CHID2 CHID1 CHID0
890
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.9 PWM Sync Channels Mode Register
Name: PWM_SCM
Address: 0x40020020
Access: Read-write
This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in
“PWM Write Protect Status Register” on page 913
.
• SYNCx: Synchronous Channel x
0 = Channel x is not a synchronous channel.
1 = Channel x is a synchronous channel.
• UPDM: Synchronous Channels Update Mode
Notes: 1. The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in “PWM Sync Channels
Update Control Register” is set.
2. The update occurs when the Update Period is elapsed.
• PTRM: PDC Transfer Request Mode
• PTRCS: PDC Transfer Request Comparison Selection
Selection of the comparison used to set the flag WRDY and the corresponding PDC transfer request.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
PTRCS PTRM – – UPDM
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – SYNC3 SYNC2 SYNC1 SYNC0
Value Name Description
0 MODE0 Manual write of double buffer registers and manual update of synchronous channels(1)
1 MODE1 Manual write of double buffer registers and automatic update of synchronous channels(2)
2 MODE2 Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous
channels(2)
3 – Reserved
UPDM PTRM WRDY Flag and PDC Transfer Request
0x
The WRDY flag in “PWM Interrupt Status Register 2” on page 897 and the PDC transfer request
are never set to 1.
1x
The WRDY flag in “PWM Interrupt Status Register 2” on page 897 is set to 1 as soon as the
update period is elapsed, the PDC transfer request is never set to 1.
20The WRDY flag in “PWM Interrupt Status Register 2” on page 897 and the PDC transfer request
are set to 1 as soon as the update period is elapsed.
1The WRDY flag in “PWM Interrupt Status Register 2” on page 897 and the PDC transfer request
are set to 1 as soon as the selected comparison matches.
891
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.10 PWM Sync Channels Update Control Register
Name: PWM_SCUC
Address: 0x40020028
Access: Read-write
• UPDULOCK: Synchronous Channels Update Unlock
0 = No effect
1 = If the UPDM field is set to “0” in “PWM Sync Channels Mode Register” on page 890, writing the UPDULOCK bit to “1” triggers
the update of the period value, the duty-cycle and the dead-time values of synchronous channels at the beginning of the next
PWM period. If the field UPDM is set to “1” or “2”, writing the UPDULOCK bit to “1” triggers only the update of the period value and
of the dead-time values of synchronous channels.
This bit is automatically reset when the update is done.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––UPDULOCK
892
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.11 PWM Sync Channels Update Period Register
Name: PWM_SCUP
Address: 0x4002002C
Access: Read-write
• UPR: Update Period
Defines the time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or
UPDM = 2 in “PWM Sync Channels Mode Register” on page 890). This time is equal to UPR+1 periods of the synchronous
channels.
• UPRCNT: Update Period Counter
Reports the value of the Update Period Counter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
UPRCNT UPR
893
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.12 PWM Sync Channels Update Period Update Register
Name: PWM_SCUPUPD
Address: 0x40020030
Access: Write-only
This register acts as a double buffer for the UPR value. This prevents an unexpected automatic trigger of the update of synchro-
nous channels.
• UPRUPD: Update Period Update
Defines the wanted time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM
= 1 or UPDM = 2 in “PWM Sync Channels Mode Register” on page 890). This time is equal to UPR+1 periods of the synchronous
channels.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – UPRUPD
894
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.13 PWM Interrupt Enable Register 2
Name: PWM_IER2
Address: 0x40020034
Access: Write-only
• WRDY: Write Ready for Synchronous Channels Update Interrupt Enable
• ENDTX: PDC End of TX Buffer Interrupt Enable
• TXBUFE: PDC TX Buffer Empty Interrupt Enable
• UNRE: Synchronous Channels Update Underrun Error Interrupt Enable
• CMPMx: Comparison x Match Interrupt Enable
• CMPUx: Comparison x Update Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0
15 14 13 12 11 10 9 8
CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0
76543210
– – – – UNRE TXBUFE ENDTX WRDY
895
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.14 PWM Interrupt Disable Register 2
Name: PWM_IDR2
Address: 0x40020038
Access: Write-only
• WRDY: Write Ready for Synchronous Channels Update Interrupt Disable
• ENDTX: PDC End of TX Buffer Interrupt Disable
• TXBUFE: PDC TX Buffer Empty Interrupt Disable
• UNRE: Synchronous Channels Update Underrun Error Interrupt Disable
• CMPMx: Comparison x Match Interrupt Disable
• CMPUx: Comparison x Update Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0
15 14 13 12 11 10 9 8
CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0
76543210
– – – – UNRE TXBUFE ENDTX WRDY
896
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.15 PWM Interrupt Mask Register 2
Name: PWM_IMR2
Address: 0x4002003C
Access: Read-only
• WRDY: Write Ready for Synchronous Channels Update Interrupt Mask
• ENDTX: PDC End of TX Buffer Interrupt Mask
• TXBUFE: PDC TX Buffer Empty Interrupt Mask
• UNRE: Synchronous Channels Update Underrun Error Interrupt Mask
• CMPMx: Comparison x Match Interrupt Mask
• CMPUx: Comparison x Update Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0
15 14 13 12 11 10 9 8
CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0
76543210
– – – – UNRE TXBUFE ENDTX WRDY
897
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.16 PWM Interrupt Status Register 2
Name: PWM_ISR2
Address: 0x40020040
Access: Read-only
• WRDY: Write Ready for Synchronous Channels Update
0 = New duty-cycle and dead-time values for the synchronous channels cannot be written.
1 = New duty-cycle and dead-time values for the synchronous channels can be written.
• ENDTX: PDC End of TX Buffer
0 = The Transmit Counter register has not reached 0 since the last write of the PDC.
1 = The Transmit Counter register has reached 0 since the last write of the PDC.
• TXBUFE: PDC TX Buffer Empty
0 = PWM_TCR or PWM_TCNR has a value other than 0.
1 = Both PWM_TCR and PWM_TCNR have a value other than 0.
• UNRE: Synchronous Channels Update Underrun Error
0 = No Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register.
1 = At least one Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register.
• CMPMx: Comparison x Match
0 = The comparison x has not matched since the last read of the PWM_ISR2 register.
1 = The comparison x has matched at least one time since the last read of the PWM_ISR2 register.
• CMPUx: Comparison x Update
0 = The comparison x has not been updated since the last read of the PWM_ISR2 register.
1 = The comparison x has been updated at least one time since the last read of the PWM_ISR2 register.
Note: Reading PWM_ISR2 automatically clears flags WRDY, UNRE and CMPSx.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CMPU7 CMPU6 CMPU5 CMPU4 CMPU3 CMPU2 CMPU1 CMPU0
15 14 13 12 11 10 9 8
CMPM7 CMPM6 CMPM5 CMPM4 CMPM3 CMPM2 CMPM1 CMPM0
76543210
– – – – UNRE TXBUFE ENDTX WRDY
898
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.17 PWM Output Override Value Register
Name: PWM_OOV
Address: 0x40020044
Access: Read-write
• OOVHx: Output Override Value for PWMH output of the channel x
0 = Override value is 0 for PWMH output of channel x.
1 = Override value is 1 for PWMH output of channel x.
• OOVLx: Output Override Value for PWML output of the channel x
0 = Override value is 0 for PWML output of channel x.
1 = Override value is 1 for PWML output of channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – OOVL3 OOVL2 OOVL1 OOVL0
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – OOVH3 OOVH2 OOVH1 OOVH0
899
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.18 PWM Output Selection Register
Name: PWM_OS
Address: 0x40020048
Access: Read-write
• OSHx: Output Selection for PWMH output of the channel x
0 = Dead-time generator output DTOHx selected as PWMH output of channel x.
1 = Output override value OOVHx selected as PWMH output of channel x.
• OSLx: Output Selection for PWML output of the channel x
0 = Dead-time generator output DTOLx selected as PWML output of channel x.
1 = Output override value OOVLx selected as PWML output of channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – OSL3 OSL2 OSL1 OSL0
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – OSH3 OSH2 OSH1 OSH0
900
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.19 PWM Output Selection Set Register
Name: PWM_OSS
Address: 0x4002004C
Access: Write-only
• OSSHx: Output Selection Set for PWMH output of the channel x
0 = No effect.
1 = Output override value OOVHx selected as PWMH output of channel x.
• OSSLx: Output Selection Set for PWML output of the channel x
0 = No effect.
1 = Output override value OOVLx selected as PWML output of channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – OSSL3 OSSL2 OSSL1 OSSL0
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – OSSH3 OSSH2 OSSH1 OSSH0
901
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.20 PWM Output Selection Clear Register
Name: PWM_OSC
Address: 0x40020050
Access: Write-only
• OSCHx: Output Selection Clear for PWMH output of the channel x
0 = No effect.
1 = Dead-time generator output DTOHx selected as PWMH output of channel x.
• OSCLx: Output Selection Clear for PWML output of the channel x
0 = No effect.
1 = Dead-time generator output DTOLx selected as PWML output of channel x.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – OSCL3 OSCL2 OSCL1 OSCL0
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – OSCH3 OSCH2 OSCH1 OSCH0
902
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.21 PWM Output Selection Set Update Register
Name: PWM_OSSUPD
Address: 0x40020054
Access: Write-only
• OSSUPHx: Output Selection Set for PWMH output of the channel x
0 = No effect.
1 = Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period.
• OSSUPLx: Output Selection Set for PWML output of the channel x
0 = No effect.
1 = Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – OSSUPL3 OSSUPL2 OSSUPL1 OSSUPL0
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – OSSUPH3 OSSUPH2 OSSUPH1 OSSUPH0
903
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.22 PWM Output Selection Clear Update Register
Name: PWM_OSCUPD
Address: 0x40020058
Access: Write-only
• OSCUPHx: Output Selection Clear for PWMH output of the channel x
0 = No effect.
1 = Dead-time generator output DTOHx selected as PWMH output of channel x at the beginning of the next channel x PWM
period.
• OSCUPLx: Output Selection Clear for PWML output of the channel x
0 = No effect.
1 = Dead-time generator output DTOLx selected as PWML output of channel x at the beginning of the next channel x PWM
period.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – OSCUPL3 OSCUPL2 OSCUPL1 OSCUPL0
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – OSCUPH3 OSCUPH2 OSCUPH1 OSCUPH0
904
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.23 PWM Fault Mode Register
Name: PWM_FMR
Address: 0x4002005C
Access: Read-write
This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page
913.
• FPOL: Fault Polarity (fault input bit varies from 0 to 5)
For each field bit y (fault input number):
0 = The fault y becomes active when the fault input y is at 0.
1 = The fault y becomes active when the fault input y is at 1.
• FMOD: Fault Activation Mode (fault input bit varies from 0 to 5)
For each field bit y (fault input number):
0 = The fault y is active until the Fault condition is removed at the peripheral(1) level.
1 = The fault y stays active until the Fault condition is removed at the peripheral(1) le vel AND until it i s cleared in the “PWM
Fault Clear Register” .
Note: 1. The Peripheral generating the fault.
• FFIL: Fault Filtering (fault input bit varies from 0 to 5)
For each field bit y (fault input number):
0 = The fault input y is not filtered.
1 = The fault input y is filtered.
CAUTION: To prevent an unexpected activation of the status flag FSy in the “PWM Fault Status Register” on page 905, the bit
FMODy can be set to “1” only if the FPOLy bit has been previously configured to its final value.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
FFIL
15 14 13 12 11 10 9 8
FMOD
76543210
FPOL
905
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.24 PWM Fault Status Register
Name: PWM_FSR
Address: 0x40020060
Access: Read-only
• FIV: Fault Input Value (fault input bit varies from 0 to 5)
For each field bit y (fault input number):
0 = The current sampled value of the fault input y is 0 (after filtering if enabled).
1 = The current sampled value of the fault input y is 1 (after filtering if enabled).
• FS: Fault Status (fault input bit varies from 0 to 5)
For each field bit y (fault input number):
0 = The fault y is not currently active.
1 = The fault y is currently active.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
FS
76543210
FIV
906
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.25 PWM Fault Clear Register
Name: PWM_FCR
Address: 0x40020064
Access: Write-only
• FCLR: Fault Clear (fault input bit varies from 0 to 5)
For each field bit y (fault input number):
0 = No effect.
1 = If bit y of FM OD field is set t o 1 and if the fault i nput y is not at t he level def ined by the bit y o f FPOL field, th e fault y is
cleared and becomes inactive (FMOD and FPOL fields belong to “PWM Fault Mode Register” on page 904), else writing this
bit to 1 has no effect.
31 30 29 28 27 26 25 24
–
23 22 21 20 19 18 17 16
–
15 14 13 12 11 10 9 8
–
76543210
FCLR
907
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.26 PWM Fault Protection Value Register
Name: PWM_FPV
Address: 0x40020068
Access: Read-write
This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page
913.
• FPVHx: Fault Protection Value for PWMH output on channel x
0 = PWMH output of channel x is forced to 0 when fault occurs.
1 = PWMH output of channel x is forced to 1 when fault occurs.
• FPVLx: Fault Protection Value for PWML output on channel x
0 = PWML output of channel x is forced to 0 when fault occurs.
1 = PWML output of channel x is forced to 1 when fault occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – FPVL3 FPVL2 FPVL1 FPVL0
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – FPVH3 FPVH2 FPVH1 FPVH0
908
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.27 PWM Fault Protection Enable Register
Name: PWM_FPE
Address: 0x4002006C
Access: Read-write
This register can only be written if the bits WPSWS5 and WPHWS5 are cleared in “PWM Write Protect Status Register” on page
913.
Only the first 6 bits (number of fault input pins) of fields FPE0, FPE1, FPE2 and FPE3 are significant.
• FPEx: Fault Protection Enable for channel x (fault input bit varies from 0 to 5)
For each field bit y (fault input number):
0 = Fault y is not used for the Fault Protection of channel x.
1 = Fault y is used for the Fault Protection of channel x.
CAUTION: To prevent an unexpected activation of the Fault Protection, the bit y of FPEx field can be set to “1” only if the corre-
sponding FPOL bit has been previously configured to its final value in “PWM Fault Mode Register” on page 904.
31 30 29 28 27 26 25 24
FPE3
23 22 21 20 19 18 17 16
FPE2
15 14 13 12 11 10 9 8
FPE1
76543210
FPE0
909
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.28 PWM Event Line x Register
Name: PWM_ELMRx
Address: 0x4002007C
Access: Read-write
• CSELy: Comparison y Selection
0 = A pulse is not generated on the event line x when the comparison y matches.
1 = A pulse is generated on the event line x when the comparison y match.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
CSEL7 CSEL6 CSEL5 CSEL4 CSEL3 CSEL2 CSEL1 CSEL0
910
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.29 PWM Stepper Motor Mode Register
Name: PWM_SMMR
Address: 0x400200B0
Access: Read-write
• GCENx: Gray Count ENable
0 = Disable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1]
1 = enable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1.
• DOWNx: DOWN Count
0 = Up counter.
1 = Down counter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – – – DOWN1 DOWN0
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – – – GCEN1 GCEN0
911
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.30 PWM Write Protect Control Register
Name: PWM_WPCR
Address: 0x400200E4
Access: Write-only
• WPCMD: Write Protect Command
This command is performed only if the WPKEY value is correct.
0 = Disable the Write Protect SW of the register groups of which the bit WPRGx is at 1.
1 = Enable the Write Protect SW of the register groups of which the bit WPRGx is at 1.
2 = Enable the Write Protect HW of the register groups of which the bit WPRGx is at 1.
Moreover, to meet security requirements, in this mode of operation, the PIO lines associated with PWM can not be con-
figured through the PIO interface, not even by the PIO controller.
3 = No effect.
Note: Only a hardware reset of the PWM controller can disable the Write Protect HW.
• WPRGx: Write Protect Register Group x
0 = The WPCMD command has no effect on the register group x.
1 = The WPCMD command is applied to the register group x.
• WPKEY: Write Protect Key
Should be written at value 0x50574D (“PWM” in ASCII). Writing any other value in this field aborts the write operation of the
WPCMD field. Always reads as 0.
List of register groups:
• Register group 0:
–“PWM Clock Register” on page 882
• Register group 1:
–“PWM Disable Register” on page 884
• Register group 2:
–“PWM Sync Channels Mode Register” on page 890
–“PWM Channel Mode Register” on page 918
–“PWM Stepper Motor Mode Register” on page 910
• Register group 3:
–“PWM Channel Period Register” on page 922
–“PWM Channel Period Update Register” on page 923
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
WPRG5 WPRG4 WPRG3 WPRG2 WPRG1 WPRG0 WPCMD
913
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.31 PWM Write Protect Status Register
Name: PWM_WPSR
Address: 0x400200E8
Access: Read-only
• WPSWSx: Write Protect SW Status
0 = The Write Protect SW x of the register group x is disabled.
1 = The Write Protect SW x of the register group x is enabled.
• WPHWSx: Write Protect HW Status
0 = The Write Protect HW x of the register group x is disabled.
1 = The Write Protect HW x of the register group x is enabled.
• WPVS: Write Protect Violation Status
0 = No Write Protect violation has occurred since the last read of the PWM_WPSR register.
1 = At least one Write Protect violation has occurred since the last read of the PWM_WPSR register. If this violation is an unau-
thorized attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset) in which a write access has been
attempted.
Note: The two LSBs of the address offset of the write-protected register are not reported
Note: Reading PWM_WPSR automatically clears WPVS and WPVSRC fields.
31 30 29 28 27 26 25 24
WPVSRC
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
– – WPHWS5 WPHWS4 WPHWS3 WPHWS2 WPHWS1 WPHWS0
76543210
WPVS – WPSWS5 WPSWS4 WPSWS3 WPSWS2 WPSWS1 WPSWS0
914
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.32 PWM Comparison x Value Register
Name: PWM_CMPVx
Address: 0x40020130 [0], 0x40020140 [1], 0x40020150 [2], 0x40020160 [3], 0x40020170 [4], 0x40020180 [5],
0x40020190 [6], 0x400201A0 [7]
Access: Read-write
Only the first 16 bits (channel counter size) of field CV are significant.
• CV: Comparison x Value
Define the comparison x value to be compared with the counter of the channel 0.
• CVM: Comparison x Value Mode
0 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
incrementing.
1 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
decrementing.
Note: This bit is useless if the counter of the channel 0 is left aligned (CALG = 0 in “PWM Channel Mode Register” on page
918)
31 30 29 28 27 26 25 24
–––––––CVM
23 22 21 20 19 18 17 16
CV
15 14 13 12 11 10 9 8
CV
76543210
CV
915
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.33 PWM Comparison x Value Update Register
Name: PWM_CMPVUPDx
Address: 0x40020134 [0], 0x40020144 [1], 0x40020154 [2], 0x40020164 [3], 0x40020174 [4], 0x40020184 [5],
0x40020194 [6], 0x400201A4 [7]
Access: Write-only
This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match.
Only the first 16 bits (channel counter size) of field CVUPD are significant.
• CVUPD: Comparison x Value Update
Define the comparison x value to be compared with the counter of the channel 0.
• CVMUPD: Comparison x Value Mode Update
0 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
incrementing.
1 = The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is
decrementing.
Note: This bit is useless if the counter of the channel 0 is left aligned (CALG = 0 in “PWM Channel Mode Register” on page
918)
CAUTION: to be taken into account, the write of the register PWM_CMPVUPDx must be followed by a write of the register
PWM_CMPMUPDx.
31 30 29 28 27 26 25 24
–––––––CVMUPD
23 22 21 20 19 18 17 16
CVUPD
15 14 13 12 11 10 9 8
CVUPD
76543210
CVUPD
916
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.34 PWM Comparison x Mode Register
Name: PWM_CMPMx
Address: 0x40020138 [0], 0x40020148 [1], 0x40020158 [2], 0x40020168 [3], 0x40020178 [4], 0x40020188 [5],
0x40020198 [6], 0x400201A8 [7]
Access: Read-write
• CEN: Comparison x Enable
0 = The comparison x is disabled and can not match.
1 = The comparison x is enabled and can match.
• CTR: Comparison x Trigger
The comparison x is performed when the value of the comparison x period counter (CPRCNT) reaches the value defined by CTR.
• CPR: Comparison x Period
CPR defines the maximum value of the comparison x period counter (CPRCNT). The comparison x value is performed periodi-
cally once every CPR+1 periods of the channel 0 counter.
• CPRCNT: Comparison x Period Counter
Reports the value of the comparison x period counter.
Note: The field CPRCNT is read-only
• CUPR: Comparison x Update Period
Defines the time between each update of the comparison x mode and the comparison x value. This time is equal to CUPR+1 peri-
ods of the channel 0 counter.
• CUPRCNT: Comparison x Update Period Counter
Reports the value of the comparison x update period counter.
Note: The field CUPRCNT is read-only
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CUPRCNT CUPR
15 14 13 12 11 10 9 8
CPRCNT CPR
76543210
CTR – – – CEN
917
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.35 PWM Comparison x Mode Update Register
Name: PWM_CMPMUPDx
Address: 0x4002013C [0], 0x4002014C [1], 0x4002015C [2], 0x4002016C [3], 0x4002017C [4], 0x4002018C [5],
0x4002019C [6], 0x400201AC [7]
Access: Write-only
This register acts as a double buffer for the CEN, CTR, CPR and CUPR values. This prevents an unexpected comparison x
match.
• CENUPD: Comparison x Enable Update
0 = The comparison x is disabled and can not match.
1 = The comparison x is enabled and can match.
• CTRUPD: Comparison x Trigger Update
The comparison x is performed when the value of the comparison x period counter (CPRCNT) reaches the value defined by CTR.
• CPRUPD: Comparison x Period Update
CPR defines the maximum value of the comparison x period counter (CPRCNT). The comparison x value is performed periodi-
cally once every CPR+1 periods of the channel 0 counter.
• CUPRUPD: Comparison x Update Period Update
Defines the time between each update of the comparison x mode and the comparison x value. This time is equal to CUPR+1 peri-
ods of the channel 0 counter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – CUPRUPD
15 14 13 12 11 10 9 8
– – – – CPRUPD
76543210
CTRUPD – – – CENUPD
918
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.36 PWM Channel Mode Register
Name: PWM_CMRx [x=0..3]
Address: 0x40020200 [0], 0x40020220 [1], 0x40020240 [2], 0x40020260 [3]
Access: Read-write
This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in “PWM Write Protect Status Register” on page
913.
• CPRE: Channel Pre-scaler
• CALG: Channel Alignment
0 = The period is left aligned.
1 = The period is center aligned.
• CPOL: Channel Polarity
0 = The OCx output waveform (output from the comparator) starts at a low level.
1 = The OCx output waveform (output from the comparator) starts at a high level.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – – – – DTLI DTHI DTE
15 14 13 12 11 10 9 8
– – – – – CES CPOL CALG
76543210
– – – – CPRE
Value Name Description
0b0000 MCK Master clock
0b0001 MCK_DIV_2 Master clock/2
0b0010 MCK_DIV_4 Master clock/4
0b0011 MCK_DIV_8 Master clock/8
0b0100 MCK_DIV_16 Master clock/16
0b0101 MCK_DIV_32 Master clock/32
0b0110 MCK_DIV_64 Master clock/64
0b0111 MCK_DIV_128 Master clock/128
0b1000 MCK_DIV_256 Master clock/256
0b1001 MCK_DIV_512 Master clock/512
0b1010 MCK_DIV_1024 Master clock/1024
0b1011 CLKA Clock A
0b1100 CLKB Clock B
919
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• CES: Counter Event Selection
The bit CES defines when the channel counter event occurs when the period is center aligned (flag CHIDx in the “PWM Interrupt
Status Register 1” on page 889).
CALG = 0 (Left Alignment):
0/1 = The channel counter event occurs at the end of the PWM period.
CALG=1(Center Alignment):
0 = The channel counter event occurs at the end of the PWM period.
1 = The channel counter event occurs at the end of the PWM period and at half the PWM period.
• DTE: Dead-Time Generator Enable
0 = The dead-time generator is disabled.
1 = The dead-time generator is enabled.
• DTHI: Dead-Time PWMHx Output Inverted
0 = The dead-time PWMHx output is not inverted.
1 = The dead-time PWMHx output is inverted.
• DTLI: Dead-Time PWMLx Output Inverted
0 = The dead-time PWMLx output is not inverted.
1 = The dead-time PWMLx output is inverted.
920
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.37 PWM Channel Duty Cycle Register
Name: PWM_CDTYx [x=0..3]
Address: 0x40020204 [0], 0x40020224 [1], 0x40020244 [2], 0x40020264 [3]
Access: Read-write
Only the first 16 bits (channel counter size) are significant.
• CDTY: Channel Duty-Cycle
Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CDTY
15 14 13 12 11 10 9 8
CDTY
76543210
CDTY
921
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.38 PWM Channel Duty Cycle Update Register
Name: PWM_CDTYUPDx [x=0..3]
Address: 0x40020208 [0], 0x40020228 [1], 0x40020248 [2], 0x40020268 [3]
Access: Write-only.
This register acts as a double buffer for the CDTY value. This prevents an unexpected waveform when modifying the waveform
duty-cycle.
Only the first 16 bits (channel counter size) are significant.
• CDTYUPD: Channel Duty-Cycle Update
Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CDTYUPD
15 14 13 12 11 10 9 8
CDTYUPD
76543210
CDTYUPD
922
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.39 PWM Channel Period Register
Name: PWM_CPRDx [x=0..3]
Address: 0x4002020C [0], 0x4002022C [1], 0x4002024C [2], 0x4002026C [3]
Access: Read-write
This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in “PWM Write Protect Status Register” on page
913.
Only the first 16 bits (channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
64, 128, 256, 512, or 1024). The resulting period formula will be:
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
64, 128, 256, 512, or 1024). The resulting period formula will be:
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CPRD
15 14 13 12 11 10 9 8
CPRD
76543210
CPRD
X CPRD×()
MCK
--------------------------------
CRPD DIVA×()
MCK
------------------------------------------ CRPD DIVB×()
MCK
------------------------------------------
2X CPRD××()
MCK
------------------------------------------
2CPRD DIVA××()
MCK
----------------------------------------------------2CPRD×DIVB×()
MCK
----------------------------------------------------
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38.7.40 PWM Channel Period Update Register
Name: PWM_CPRDUPDx [x=0..3]
Address: 0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3]
Access: Write-only
This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in “PWM Write Protect Status Register” on page
913.
This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the waveform
period.
Only the first 16 bits (channel counter size) are significant.
• CPRDUPD: Channel Period Update
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
64, 128, 256, 512, or 1024). The resulting period formula will be:
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
64, 128, 256, 512, or 1024). The resulting period formula will be:
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CPRDUPD
15 14 13 12 11 10 9 8
CPRDUPD
76543210
CPRDUPD
X CPRDUPD×()
MCK
----------------------------------------------
CRPDUPD DIVA×()
MCK
--------------------------------------------------------CRPDUPD DIVB×()
MCK
--------------------------------------------------------
2X CPRDUPD××()
MCK
-------------------------------------------------------
2CPRDUPD DIVA××()
MCK
----------------------------------------------------------------- 2CPRDUPD×DIVB×()
MCK
-----------------------------------------------------------------
924
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38.7.41 PWM Channel Counter Register
Name: PWM_CCNTx [x=0..3]
Address: 0x40020214 [0], 0x40020234 [1], 0x40020254 [2], 0x40020274 [3]
Access: Read-only
Only the first 16 bits (channel counter size) are significant.
• CNT: Channel Counter Register
Channel counter value. This register is reset when:
• the channel is enabled (writing CHIDx in the PWM_ENA register).
• the channel counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
CNT
15 14 13 12 11 10 9 8
CNT
76543210
CNT
925
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38.7.42 PWM Channel Dead Time Register
Name: PWM_DTx [x=0..3]
Address: 0x40020218 [0], 0x40020238 [1], 0x40020258 [2], 0x40020278 [3]
Access: Read-write
This register can only be written if the bits WPSWS4 and WPHWS4 are cleared in “PWM Write Protect Status Register” on page
913.
Only the first 12 bits (dead-time counter size) of fields DTH and DTL are significant.
• DTH: Dead-Time Value for PWMHx Output
Defines the dead-time value for PWMHx output. This value must be defined between 0 and CPRD-CDTY (PWM_CPRx and
PWM_CDTYx).
• DTL: Dead-Time Value for PWMLx Output
Defines the dead-time value for PWMLx output. This value must be defined between 0 and CDTY (PWM_CDTYx).
31 30 29 28 27 26 25 24
DTL
23 22 21 20 19 18 17 16
DTL
15 14 13 12 11 10 9 8
DTH
76543210
DTH
926
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38.7.43 PWM Channel Dead Time Update Register
Name: PWM_DTUPDx [x=0..3]
Address: 0x4002021C [0], 0x4002023C [1], 0x4002025C [2], 0x4002027C [3]
Access: Write-only
This register can only be written if the bits WPSWS4 and WPHWS4 are cleared in “PWM Write Protect Status Register” on page
913.
This register acts as a double buffer for the DTH and DTL values. This prevents an unexpected waveform when modifying the
dead-time values.
Only the first 12 bits (dead-time counter size) of fields DTHUPD and DTLUPD are significant.
• DTHUPD: Dead-Time Value Update for PWMHx Output
Defines the dead-time value for PWMHx output. This value must be defined between 0 and CPRD-CDTY (PWM_CPRx and
PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period.
• DTLUPD: Dead-Time Value Update for PWMLx Output
Defines the dead-time value for PWMLx output. This value must be defined between 0 and CDTY (PWM_CDTYx). This value is
applied only at the beginning of the next channel x PWM period.
31 30 29 28 27 26 25 24
DTLUPD
23 22 21 20 19 18 17 16
DTLUPD
15 14 13 12 11 10 9 8
DTHUPD
76543210
DTHUPD
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39. USB Device Port (UDP)
39.1 Description
The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification.
Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a
dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the
processor, while the other is read or written by the USB device peripheral. This feature is mandatory for isochronous
endpoints. Thus the device maintains the maximum bandwidth (1M bytes/s) by working with endpoints with two banks of
DPR.
Note: 1. The Dual-Bank function provides two banks for an endpoint. This feature is used for ping-pong mode.
Suspend and resume are automatically detected by the USB device, which notifies the processor by raising an interrupt.
Depending on the product, an external signal can be used to send a wake up to the USB host controller.
39.2 Embedded Characteristics
USB V2.0 full-speed compliant,12 Mbits per second.
Embedded USB V2.0 full-speed transceiver
Embedded 2688-byte dual-port RAM for endpoints
Eight endpoints
Endpoint 0: 64bytes
Endpoint 1 and 2: 64 bytes ping-pong
Endpoint 3: 64 bytes
Endpoint 4 and 5: 512 bytes ping-pong
Endpoint 6 and 7: 64 bytes ping-pong
Ping-pong Mode (two memory banks) for Isochronous and bulk endpoints
Suspend/resume logic
Integrated Pull-up on DDP
Pull-down resistor on DDM and DDP when disabled
Table 39-1. USB Endpoint Description
Endpoint Number Mnemonic Dual-Bank(1) Max. Endpoint Size Endpoint Type
0 EP0 No 64 Control/Bulk/Interrupt
1 EP1 Yes 64 Bulk/Iso/Interrupt
2 EP2 Yes 64 Bulk/Iso/Interrupt
3 EP3 No 64 Control/Bulk/Interrupt
4 EP4 Yes 512 Bulk/Iso/Interrupt
5 EP5 Yes 512 Bulk/Iso/Interrupt
6 EP6 Yes 64 Bulk/Iso/Interrupt
7 EP7 Yes 64 Bulk/Iso/Interrupt
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39.3 Block Diagram
Figure 39-1. Block Diagram
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit
values to APB registers.
The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48 MHz
clock (UDPCK) used by the 12 MHz domain.
A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).
The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode. The host is then
notified that the device asks for a resume. This optional feature must also be negotiated with the host during the
enumeration.
39.3.1 Signal Description
Atmel Bridge
12 MHz
Suspend/Resume Logic
W
r
a
p
p
e
r
W
r
a
p
p
e
r
U
s
e
r
I
n
t
e
r
f
a
c
e
Serial
Interface
Engine
SIE
MCK
Master Clock
Domain
Dual
Port
RAM
FIFO
UDPCK
Recovered 12 MHz
Domain
udp_int
USB Device
Embedded
USB
Transceiver
DDP
DDM
APB
to
MCU
Bus txoen
eopn
txd
rxdm
rxd
rxdp
Table 39-2. Signal Names
Signal Name Description Type
UDPCK 48 MHz clock input
MCK Master clock input
udp_int Interrupt line connected to the Interrupt Controller input
DDP USB D+ line I/O
DDM USB D- line I/O
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39.4 Product Dependencies
For further details on the USB Device hardware implementation, see the specific Product Properties document.
The USB physical transceiver is integrated into the product. The bidirectional differential signals DDP and DDM are
available from the product boundary.
One I/O line may be used by the application to check that VBUS is still available from the host. Self-powered devices
may use this entry to be notified that the host has been powered off. In this case, the pull-up on DP must be disabled in
order to prevent feeding current to the host. The application should disconnect the transceiver, then remove the pull-up.
39.4.1 I/O Lines
The USB pins are shared with PIO lines. By default, the USB function is activated, and pins DDP and DDM are used for
USB. To configure DDP or DDM as PIOs, the user needs to configure the system I/O configuration register
(CCFG_SYSIO) in the MATRIX.
39.4.2 Power Management
The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL with an accuracy of ±
0.25%.
Thus, the USB device receives two clocks from the Power Management Controller (PMC): the master clock, MCK, used
to drive the peripheral user interface, and the UDPCK, used to interface with the bus USB signals (recovered 12 MHz
domain).
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any
read/write operations to the UDP registers including the UDP_TXVC register.
39.4.3 Interrupt
The USB device interface has an interrupt line connected to the Interrupt Controller.
Handling the USB device interrupt requires programming the Interrupt Controller before configuring the UDP.
Table 39-3. Peripheral IDs
Instance ID
UDP 34
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39.5 Typical Connection
Figure 39-2. Board Schematic to Interface Device Peripheral
39.5.1 USB Device Transceiver
The USB device transceiver is embedded in the product. A few discrete components are required as follows:
the application detects all device states as defined in chapter 9 of the USB specification;
VBUS monitoring
to reduce power consumption the host is disconnected
for line termination.
39.5.2 VBUS Monitoring
VBUS monitoring is required to detect host connection. VBUS monitoring is done using a standard PIO with internal pull-
up disabled. When the host is switched off, it should be considered as a disconnect, the pull-up must be disabled in order
to prevent powering the host through the pull-up resistor.
When the host is disconnected and the transceiver is enabled, then DDP and DD M are floating. This may lead to over
consumption. A solution is to enable the integrated pull-down by disabling the transceiver (TXVDIS = 1) and then remove
the pull-up (PUON = 0).
A termination serial resistor must be connected to DDP and DDM. The resistor value is defined in the electrical
specification of the product (REXT).
REXT
REXT
DDM
DDP
PIO 27 K
47 K
Type B
Connector
12
34
5V Bus Monitoring
931
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39.6 Functional Description
39.6.1 USB V2.0 Full-speed Introduction
The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is
offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host
communicates with a USB device through a set of communication flows.
Figure 39-3. Example of USB V2.0 Full-speed Communication Control
The Control Transfer endpoint EP0 is always used when a USB device is first configured (USB v. 2.0 specifications).
39.6.1.1USB V2.0 Full-speed Transfer Types
A communication flow is carried over one of four transfer types defined by the USB device.
39.6.1.2USB Bus Transactions
Each transfer results in one or more transactions over the USB bus. There are three kinds of transactions flowing across
the bus in packets:
1. Setup Transaction
2. Data IN Transaction
3. Data OUT Transaction
EP0
USB Host V2.0
Software Client 1 Software Client 2
Data Flow: Bulk Out Transfer
Data Flow: Bulk In Transfer
Data Flow: Control Transfer
Data Flow: Control Transfer
EP1
EP2
USB Device 2.0
Block 1
USB Device 2.0
Block 2
EP5
EP4
EP0
Data Flow: Isochronous In Transfer
Data Flow: Isochronous Out Transfer
USB Device endpoint configuration requires that
in the first instance Control Transfer must be EP0.
Table 39-4. USB Communication Flow
Transfer Direction Bandwidth Supported Endpoint Size Error Detection Retrying
Control Bidirectional Not guaranteed 8, 16, 32, 64 Yes Automatic
Isochronous Unidirectional Guaranteed 512 Yes No
Interrupt Unidirectional Not guaranteed ≤ 64 Yes Yes
Bulk Unidirectional Not guaranteed 8, 16, 32, 64 Yes Yes
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39.6.1.3USB Transfer Event Definitions
As indicated below, transfers are sequential events carried out on the USB bus.
Notes: 1. Control transfer must use endpoints with no ping-pong attributes.
2. Isochronous transfers must use endpoints with ping-pong attributes.
3. Control transfers can be aborted using a stall handshake.
A status transaction is a special type of host-to-device transaction used only in a control transfer. The control transfer
must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the
USB device sends or receives a status transaction.
Table 39-5. USB Transfer Events
Control Transfers(1) (3)
Setup transaction > Data IN transactions > Status
OUT transaction
Setup transaction > Data OUT transactions > Status
IN transaction
Setup transaction > Status IN transaction
Interrupt IN Transfer
(device toward host)
Data IN transaction > Data IN transaction
Interrupt OUT Transfer
(host toward device)
Data OUT transaction > Data OUT transaction
Isochronous IN Transfer(2)
(device toward host)
Data IN transaction > Data IN transaction
Isochronous OUT Transfer(2)
(host toward device)
Data OUT transaction > Data OUT transaction
Bulk IN Transfer
(device toward host)
Data IN transaction > Data IN transaction
Bulk OUT Transfer
(host toward device)
Data OUT transaction > Data OUT transaction
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Figure 39-4. Control Read and Write Sequences
Notes: 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device
using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the
protocol layer.
2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data).
39.6.2 Handling Transactions with USB V2.0 Device Peripheral
39.6.2.1Setup Transaction
Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed
using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the
firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device
and may require more arguments. The arguments are sent to the device by a Data OUT transaction which follows the
setup transaction. These requests may also return data. The data is carried out to the host by the next Data IN
transaction which follows the setup transaction. A status transaction ends the control transfer.
When a setup transfer is received by the USB endpoint:
The USB device automatically acknowledges the setup packet
RXSETUP is set in the UDP_CSRx register
An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the
microcontroller if interrupts are enabled for this endpoint.
Thus, firmware must detect the RXSETUP polling the UDP_CSRx or catching an interrupt, read the setup packet in the
FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the FIFO.
Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the FIFO.
Control Read Setup TX Data OUT TX Data OUT TX
Data Stage
Control Write
Setup Stage
Setup Stage
Setup TX
Setup TX
No Data
Control
Data IN TX Data IN TX
Status Stage
Status Stage
Status IN TX
Status OUTTX
Status IN TX
Data Stage
Setup Stage Status Stage
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Figure 39-5. Setup Transaction Followed by a Data OUT Transaction
39.6.2.2Data IN Transaction
Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from
the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong
attributes.
Using Endpoints Without Ping-pong Attributes
To perform a Data IN transaction using a non ping-pong endpoint:
1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_CSRx reg-
ister (TXPKTRDY must be cleared).
2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in
the endpoint’s UDP_FDRx register,
3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_CSRx
register.
4. The application is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the
endpoint’s UDP_CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while
TXCOMP is set.
5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO, writing zero or more byte
values in the endpoint’s UDP_FDRx register,
6. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s
UDP_CSRx register.
7. The application clears the TXCOMP in the endpoint’s UDP_CSRx.
After the last packet has been sent, the application must clear TXCOMP once this has been set.
TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is
pending while TXCOMP is set.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN proto-
col layer.
RX_Data_BKO
(UDP_CSRx)
ACK
PID
Data OUT
Data OUT
PID
NAK
PID
ACK
PID
Data Setup
Setup
PID
USB
Bus Packets
RXSETUP Flag
Set by USB Device Cleared by Firmware Set by USB
Device Peripheral
FIFO (DPR)
Content Data Setup Data
XX XX OUT
Interrupt Pending
Setup Received Setup Handled by Firmware Data Out Received
Data OUT
Data OUT
PID
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Figure 39-6. Data IN Transfer for Non Ping-pong Endpoint
Using Endpoints With Ping-pong Attribute
The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This also allows handling the
maximum bandwidth defined in the USB specification during bulk transfer. To be able to guarantee a constant or the
maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being
sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other
one is locked by the USB device.
Figure 39-7. Bank Swapping Data IN Transfer for Ping-pong Endpoints
USB Bus Packets Data IN 2
Data IN NAK
ACK
Data IN 1
FIFO (DPR)
Content Data IN 2Load In ProgressData IN 1
Cleared by Firmware
DPR access by the firmware
Payload in FIFO
TXCOMP Flag
(UDP_CSRx)
TXPKTRDY Flag
(UDP_CSRx)
PID
Data IN Data IN
PIDPID PIDPID ACK
PID
Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus
Interrupt
Pending
Interrupt Pending
Set by the firmware Set by the firmware
Cleared by
Firmware
Cleared by Hw
Cleared by Hw
DPR access by the hardware
USB Device USB Bus
Read
Write
Read and Write at the Same Time
1st Data Payload
2nd Data Payload
3rd Data Payload
3rd Data Payload
2nd Data Payload
1st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
Microcontroller
Endpoint 1
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 1
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When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions:
1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the end-
point’s UDP_CSRx register.
2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values
in the endpoint’s UDP_FDRx register.
3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPK-
TRDY in the endpoint’s UDP_CSRx register.
4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the
FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_FDRx register.
5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the end-
point’s UDP_CSRx register is set. An interrupt is pending while TXCOMP is being set.
6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared
the second Bank to be sent, raising TXPKTRDY in the endpoint’s UDP_CSRx register.
7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent.
Figure 39-8. Data IN Transfer for Ping-pong Endpoint
Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for
TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long, some
Data IN packets may be NACKed, reducing the bandwidth.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
Data INData IN
Read by USB Device
Read by USB Device
Bank 1
Bank 0
FIFO (DPR)
TXCOMP Flag
(UDP_CSRx) Interrupt Cleared by Firmware
Set by USB
Device
TXPKTRDY Flag
(UDP_MCSRx)
ACK
PID Data IN
PID ACK
PID
Set by Firmware,
Data Payload Written in FIFO Bank 1
Cleared by USB Device,
Data Payload Fully Transmitted
Data IN
PID
USB Bus
Packets
Set by USB Device
Set by Firmware,
Data Payload Written in FIFO Bank 0
Written by
FIFO (DPR) Microcontroller
Written by
Microcontroller
Written by
Microcontroller
Microcontroller
Load Data IN Bank 0 Microcontroller Load Data IN Bank 1
USB Device Send Bank 0 Microcontroller Load Data IN Bank 0
USB Device Send Bank 1
Interrupt Pending
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39.6.2.3Data OUT Transaction
Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data
from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-
pong attributes.
Data OUT Transaction Without Ping-pong Attributes
To perform a Data OUT transaction, using a non ping-pong endpoint:
1. The host generates a Data OUT packet.
2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by
the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by
the USB device and an ACK is automatically carried out to the host.
3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the end-
point’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set.
4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s
UDP_CSRx register.
5. The microcontroller carries out data received from the endpoint’s memory to its memory. Data received is available
by reading the endpoint’s UDP_FDRx register.
6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the end-
point’s UDP_CSRx register.
7. A new Data OUT packet can be accepted by the USB device.
Figure 39-9. Data OUT Transfer for Non Ping-pong Endpoints
An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB device, the FIFO and
microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would
accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO.
Using Endpoints With Ping-pong Attributes
During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a
constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current data
payload is received by the USB device. Thus two banks of memory are used. While one is available for the
microcontroller, the other one is locked by the USB device.
ACK
PID
Data OUTNAK PIDPIDPIDPIDPID Data OUT2ACKData OUT Data OUT 1
USB Bus
Packets
RX_DATA_BK0
Set by USB Device Cleared by Firmware,
Data Payload Written in FIFO
FIFO (DPR)
Content Written by USB Device Microcontroller Read
Data OUT 1 Data OUT 1 Data OUT 2
Host Resends the Next Data Payload
Microcontroller Transfers Data
Host Sends Data Payload
Data OUT2 Data OUT2
Host Sends the Next Data Payload
Written by USB Device
(UDP_CSRx) Interrupt Pending
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Figure 39-10.Bank Swapping in Data OUT Transfers for Ping-pong Endpoints
When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions:
1. The host generates a Data OUT packet.
2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0.
3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT
packet. It is accepted by the device and copied to FIFO Bank 1.
4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the end-
point’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set.
5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s
UDP_CSRx register.
6. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data
received is made available by reading the endpoint’s UDP_FDRx register.
7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0
in the endpoint’s UDP_CSRx register.
8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0.
9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in
the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set.
10. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data
received is available by reading the endpoint’s UDP_FDRx register.
11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the end-
point’s UDP_CSRx register.
12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0.
USB Device USB Bus
Read
Write
Write and Read at the Same Time
1st Data Payload
2nd Data Payload
3rd Data Payload
3rd Data Payload
2nd Data Payload
1st Data Payload
Data IN Packet
Data IN Packet
Data IN Packet
Microcontroller
Endpoint 1
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 1
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Figure 39-11.Data OUT Transfer for Ping-pong Endpoint
Note: An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set.
Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first.
Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1.
This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host.
Once the application comes back to the USB driver, the two flags are set
.
39.6.2.4Stall Handshake
A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to
Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.)
A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the
Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.)
To abort the current request, a protocol stall is used, but uniquely with control transfer.
The following procedure generates a stall packet:
1. The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint’s register.
2. The host receives the stall packet.
3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint
interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt.
When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts
due to STALLSENT being set.
Data OUT PID
ACK Data OUT 3
Data OUT
Data OUT 2
Data OUT
Data OUT 1
PID
Data OUT 3Data OUT 1Data OUT1
Data OUT 2 Data OUT 2
PID PID PID
ACK
Cleared by Firmware
USB Bus
Packets
RX_DATA_BK0 Flag
RX_DATA_BK1 Flag
Set by USB Device,
Data Payload Written
in FIFO Endpoint Bank 1
FIFO (DPR)
Bank 0
Bank 1
Write by USB Device Write In Progress
Read By Microcontroller
Read By Microcontroller
Set by USB Device,
Data Payload Written
in FIFO Endpoint Bank 0
Host Sends First Data Payload Microcontroller Reads Data 1 in Bank 0,
Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1,
Host Sends Third Data Payload
Cleared by Firmware
Write by USB Device
FIFO (DPR)
(UDP_CSRx)
(UDP_CSRx)
Interrupt Pending
Interrupt Pending
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Figure 39-12.Stall Handshake (Data IN Transfer)
Figure 39-13.Stall Handshake (Data OUT Transfer)
39.6.2.5Transmit Data Cancellation
Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure to cancel transmission
data held in these banks is described below.
To see the organization of dual-bank availability refer to Table 39-1 ”USB Endpoint Description”.
Endpoints Without Dual-Banks
There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance,
TXPKTRDY is not set.
TXPKTRDY is not set:
Reset the endpoint to clear the FIFO (pointers). (See, Section 39.7.9 ”UDP Reset Endpoint Register”.)
TXPKTRDY has already been set:
Clear TXPKTRDY so that no packet is ready to be sent
Reset the endpoint to clear the FIFO (pointers). (See, Section 39.7.9 ”UDP Reset Endpoint Register”.)
Endpoints With Dual-Banks
There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance,
TXPKTRDY is not set.
TXPKTRDY is not set:
Reset the endpoint to clear the FIFO (pointers). (See, Section 39.7.9 ”UDP Reset Endpoint Register”.)
TXPKTRDY has already been set:
Clear TXPKTRDY and read it back until actually read at 0.
Data IN Stall PIDPID
USB Bus
Packets
Cleared by Firmware
Set by Firmware
FORCESTALL
STALLSENT Set by
USB Device
Cleared by Firmware
Interrupt Pending
Data OUT PID Stall PID
Data OUT
USB Bus
Packets
Cleared by Firmware
Set by Firmware
FORCESTALL
STALLSENT
Set by USB Device
Interrupt Pending
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Set TXPKTRDY and read it back until actually read at 1.
Clear TXPKTRDY so that no packet is ready to be sent.
Reset the endpoint to clear the FIFO (pointers). (See, Section 39.7.9 ”UDP Reset Endpoint Register”.)
39.6.3 Controlling Device States
A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0.
Figure 39-14.USB Device State Diagram
Movement from one state to another depends on the USB bus state or on standard requests sent through control
transactions via the default endpoint (endpoint 0).
After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the
USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not
consume more than 500 μA on the USB bus.
While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may
send a wake up request to the host, e.g., waking up a PC by moving a USB mouse.
The wake up feature is not mandatory for all devices and must be negotiated with the host.
Attached
Suspended
Suspended
Suspended
Suspended
Hub Reset
or
Deconfigured
Hub
Configured
Bus Inactive
Bus Activity
Bus Inactive
Bus Activity
Bus Inactive
Bus Activity
Bus Inactive
Bus Activity
Reset
Reset
Address
Assigned
Device
Deconfigured Device
Configured
Powered
Default
Address
Configured
Power
Interruption
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39.6.3.1Not Powered State
Self powered devices can detect 5V VBUS using a PIO as described in the typical connection section. When the device
is not connected to a host, device power consumption can be reduced by disabling MCK for the UDP, disabling UDPCK
and disabling the transceiver. DDP and DDM lines are pulled down by 330 KΩ resistors.
39.6.3.2Entering Attached State
To enable integrated pull-up, the PUON bit in the UDP_TXVC register must be set.
Warning: To write to the UD P_TXVC r egister, MCK cl ock must b e enabled on the UD P. This is d one in the P ower
Management Controller.
After pull-up connection, the device enters the powered state. In this state, the UDPCK and MCK must be enabled in the
Power Management Controller. The transceiver can remain disabled.
39.6.3.3From Powered State to Default State
After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmaskable flag ENDBUSRES is
set in the register UDP_ISR and an interrupt is triggered.
Once the ENDBUSRES interrupt has been triggered, the device enters Default State. In this state, the UDP software
must:
Enable the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the
interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer.
Configure the interrupt mask register which has been reset by the USB reset detection
Enable the transceiver clearing the TXVDIS flag in the UDP_TXVC register.
In this state UDPCK and MCK must be enabled.
Warning: Each time an ENDBUSRES interrupt is triggered, the Interrupt Mask Register and UDP_CSR registers have
been reset.
39.6.3.4From Default State to Address State
After a set address standard device request, the USB host peripheral enters the address state.
Warning: Before the device enters in address state, it must achieve the Status IN transaction of the control transfer, i.e.,
the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared.
To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STAT register, sets its new
address, and sets the FEN bit in the UDP_FADDR register.
39.6.3.5From Address State to Configured State
Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints
corresponding to the current configuration. This is done by setting the EPEDS and EPTYPE fields in the UDP_CSRx
registers and, optionally, enabling corresponding interrupts in the UDP_IER register.
39.6.3.6Entering in Suspend State
When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This
triggers an interrupt if the corresponding bit is set in the UDP_IMR register.This flag is cleared by writing to the UDP_ICR
register. Then the device enters Suspend Mode.
In this state bus powered devices must drain less than 500uA from the 5V VBUS. As an example, the microcontroller
switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices
on the board.
The USB device peripheral clocks can be switched off. Resume event is asynchronously detected. MCK and UDPCK
can be switched off in the Power Management controller and the USB transceiver can be disabled by setting the TXVDIS
field in the UDP_TXVC register.
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Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral.
Switching off MCK for the UDP peripheral must be one of the last operations after writing to the UDP_TXVC and
acknowledging the RXSUSP.
39.6.3.7Receiving a Host Resume
In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled
(however the pull-up shall not be removed).
Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may generate an interrupt if the
corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake up the core, enable PLL and main
oscillators and configure clocks.
Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. MCK
for the UDP must be enabled before clearing the WAKEUP bit in the UDP_ICR register and clearing TXVDIS in the
UDP_TXVC register.
39.6.3.8Sending a Device Remote Wake-up
In Suspend state it is possible to wake up the host sending an external resume.
The device must wait at least 5 ms after being entered in suspend before sending an external resume.
The device has 10 ms from the moment it starts to drain current and it forces a K state to resume the host.
The device must force a K state from 1 to 15 ms to resume the host
Before sending a K state to the host, MCK, UDPCK and the transceiver must be enabled. Then to enable the remote
wake-up feature, the RMWUPE bit in the UDP_GLB_STAT register must be enabled. To force the K state on the line, a
transition of the ESR bit from 0 to 1 has to be done in the UDP_GLB_STAT register. This transition must be
accomplished by first writing a 0 in the ESR bit and then writing a 1.
The K state is automatically generated and released according to the USB 2.0 specification.
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39.7 USB Device Port (UDP) User Interface
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write opera-
tions to the UDP registers, including the UDP_TXVC register.
Notes: 1. Reset values are not defined for UDP_ISR.
2. See Warning above the ”Register Mapping” on this page.
Table 39-6. Register Mapping
Offset Register Name Access Reset
0x000 Frame Number Register UDP_FRM_NUM Read-only 0x0000_0000
0x004 Global State Register UDP_GLB_STAT Read-write 0x0000_0010
0x008 Function Address Register UDP_FADDR Read-write 0x0000_0100
0x00C Reserved – – –
0x010 Interrupt Enable Register UDP_IER Write-only
0x014 Interrupt Disable Register UDP_IDR Write-only
0x018 Interrupt Mask Register UDP_IMR Read-only 0x0000_1200
0x01C Interrupt Status Register UDP_ISR Read-only –(1)
0x020 Interrupt Clear Register UDP_ICR Write-only
0x024 Reserved – – –
0x028 Reset Endpoint Register UDP_RST_EP Read-write 0x0000_0000
0x02C Reserved – – –
0x030 Endpoint Control and Status Register 0 UDP_CSR0 Read-write 0x0000_0000
... ... ... ... ...
0x030 + 0x4 * 7 Endpoint Control and Status Register 7 UDP_CSR7 Read-write 0x0000_0000
0x050 Endpoint FIFO Data Register 0 UDP_FDR0 Read-write 0x0000_0000
... ... ... ... ...
0x050 + 0x4 * 7 Endpoint FIFO Data Register 7 UDP_FDR7 Read-write 0x0000_0000
0x070 Reserved – – –
0x074 Transceiver Control Register UDP_TXVC(2) Read-write 0x0000_0100
0x078 - 0xFC Reserved – – –
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39.7.1 UDP Frame Number Register
Name: UDP_FRM_NUM
Address: 0x40034000
Access: Read-only
• FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats
This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame.
Value Updated at the SOF_EOP (Start of Frame End of Packet).
• FRM_ERR: Frame Error
This bit is set at SOF_EOP when the SOF packet is received containing an error.
This bit is reset upon receipt of SOF_PID.
• FRM_OK: Frame OK
This bit is set at SOF_EOP when the SOF packet is received without any error.
This bit is reset upon receipt of SOF_PID (Packet Identification).
In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP.
Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L.
31 30 29 28 27 26 25 24
--- --- --- --- --- --- --- ---
23 22 21 20 19 18 17 16
– – – – – – FRM_OK FRM_ERR
15 14 13 12 11 10 9 8
– – – – – FRM_NUM
76543210
FRM_NUM
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39.7.2 UDP Global State Register
Name: UDP_GLB_STAT
Address: 0x40034004
Access: Read-write
This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0.
• FADDEN: Function Address Enable
Read:
0 = Device is not in address state.
1 = Device is in address state.
Write:
0 = No effect, only a reset can bring back a device to the default state.
1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the UDP_FADDR register must
have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FADDEN. Refer
to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details.
• CONFG: Configured
Read:
0 = Device is not in configured state.
1 = Device is in configured state.
Write:
0 = Sets device in a non configured state
1 = Sets device in configured state.
The device is set in configured state when it is in address state and receives a successful Set Configuration request. Refer to
Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details.
• ESR: Enable Send Resume
0 = Mandatory value prior to starting any Remote Wake Up procedure.
1 = Starts the Remote Wake Up procedure if this bit value was 0 and if RMWUPE is enabled.
• RMWUPE: Remote Wake Up Enable
0 = The Remote Wake Up feature of the device is disabled.
1 = The Remote Wake Up feature of the device is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – RMWUPE RSMINPR ESR CONFG FADDEN
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39.7.3 UDP Function Address Register
Name: UDP_FADDR
Address: 0x40034008
Access: Read-write
• FADD[6:0]: Function Address Value
The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and
has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more
information. After power up or reset, the function address value is set to 0.
• FEN: Function Enable
Read:
0 = Function endpoint disabled.
1 = Function endpoint enabled.
Write:
0 = Disables function endpoint.
1 = Default value.
The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this
bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and
to the host.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––– FEN
76543210
– FADD
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39.7.4 UDP Interrupt Enable Register
Name: UDP_IER
Address: 0x40034010
Access: Write-only
• EP0INT: Enable Endpoint 0 Interrupt
• EP1INT: Enable Endpoint 1 Interrupt
• EP2INT: Enable Endpoint 2Interrupt
• EP3INT: Enable Endpoint 3 Interrupt
• EP4INT: Enable Endpoint 4 Interrupt
• EP5INT: Enable Endpoint 5 Interrupt
• EP6INT: Enable Endpoint 6 Interrupt
• EP7INT: Enable Endpoint 7 Interrupt
0 = No effect.
1 = Enables corresponding Endpoint Interrupt.
• RXSUSP: Enable UDP Suspend Interrupt
0 = No effect.
1 = Enables UDP Suspend Interrupt.
• RXRSM: Enable UDP Resume Interrupt
0 = No effect.
1 = Enables UDP Resume Interrupt.
• SOFINT: Enable Start Of Frame Interrupt
0 = No effect.
1 = Enables Start Of Frame Interrupt.
• WAKEUP: Enable UDP bus Wake-up Interrupt
0 = No effect.
1 = Enables USB bus Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP – SOFINT EXTRSM RXRSM RXSUSP
76543210
EP7INT EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
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39.7.5 UDP Interrupt Disable Register
Name: UDP_IDR
Address: 0x40034014
Access: Write-only
• EP0INT: Disable Endpoint 0 Interrupt
• EP1INT: Disable Endpoint 1 Interrupt
• EP2INT: Disable Endpoint 2 Interrupt
• EP3INT: Disable Endpoint 3 Interrupt
• EP4INT: Disable Endpoint 4 Interrupt
• EP5INT: Disable Endpoint 5 Interrupt
• EP6INT: Disable Endpoint 6 Interrupt
• EP7INT: Disable Endpoint 7 Interrupt
0 = No effect.
1 = Disables corresponding Endpoint Interrupt.
• RXSUSP: Disable UDP Suspend Interrupt
0 = No effect.
1 = Disables UDP Suspend Interrupt.
• RXRSM: Disable UDP Resume Interrupt
0 = No effect.
1 = Disables UDP Resume Interrupt.
• SOFINT: Disable Start Of Frame Interrupt
0 = No effect.
1 = Disables Start Of Frame Interrupt
• WAKEUP: Disable USB Bus Interrupt
0 = No effect.
1 = Disables USB Bus Wake-up Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP – SOFINT EXTRSM RXRSM RXSUSP
76543210
EP7INT EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
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39.7.6 UDP Interrupt Mask Register
Name: UDP_IMR
Address: 0x40034018
Access: Read-only
• EP0INT: Mask Endpoint 0 Interrupt
• EP1INT: Mask Endpoint 1 Interrupt
• EP2INT: Mask Endpoint 2 Interrupt
• EP3INT: Mask Endpoint 3 Interrupt
• EP4INT: Mask Endpoint 4 Interrupt
• EP5INT: Mask Endpoint 5 Interrupt
• EP6INT: Mask Endpoint 6 Interrupt
• EP7INT: Mask Endpoint 7 Interrupt
0 = Corresponding Endpoint Interrupt is disabled.
1 = Corresponding Endpoint Interrupt is enabled.
• RXSUSP: Mask UDP Suspend Interrupt
0 = UDP Suspend Interrupt is disabled.
1 = UDP Suspend Interrupt is enabled.
• RXRSM: Mask UDP Resume Interrupt.
0 = UDP Resume Interrupt is disabled.
1 = UDP Resume Interrupt is enabled.
• SOFINT: Mask Start Of Frame Interrupt
0 = Start of Frame Interrupt is disabled.
1 = Start of Frame Interrupt is enabled.
• BIT12: UDP_IMR Bit 12
Bit 12 of UDP_IMR cannot be masked and is always read at 1.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP BIT12 SOFINT EXTRSM RXRSM RXSUSP
76543210
EP7INT EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
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• WAKEUP: USB Bus WAKEUP Interrupt
0 = USB Bus Wake-up Interrupt is disabled.
1 = USB Bus Wake-up Interrupt is enabled.
Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB
HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the
register UDP_IMR is enabled.
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39.7.7 UDP Interrupt Status Register
Name: UDP_ISR
Address: 0x4003401C
Access: Read-only
• EP0INT: Endpoint 0 Interrupt Status
• EP1INT: Endpoint 1 Interrupt Status
• EP2INT: Endpoint 2 Interrupt Status
• EP3INT: Endpoint 3 Interrupt Status
• EP4INT: Endpoint 4 Interrupt Status
• EP5INT: Endpoint 5 Interrupt Status
• EP6INT: Endpoint 6 Interrupt Status
• EP7INT: Endpoint 7Interrupt Status
0 = No Endpoint0 Interrupt pending.
1 = Endpoint0 Interrupt has been raised.
Several signals can generate this interrupt. The reason can be found by reading UDP_CSR0:
RXSETUP set to 1
RX_DATA_BK0 set to 1
RX_DATA_BK1 set to 1
TXCOMP set to 1
STALLSENT set to 1
EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_CSR0 bit.
• RXSUSP: UDP Suspend Interrupt Status
0 = No UDP Suspend Interrupt pending.
1 = UDP Suspend Interrupt has been raised.
The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP ENDBUSRES SOFINT EXTRSM RXRSM RXSUSP
76543210
EP7INT EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT
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• RXRSM: UDP Resume Interrupt Status
0 = No UDP Resume Interrupt pending.
1 =UDP Resume Interrupt has been raised.
The USB device sets this bit when a UDP resume signal is detected at its port.
After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR register.
• SOFINT: Start of Frame Interrupt Status
0 = No Start of Frame Interrupt pending.
1 = Start of Frame Interrupt has been raised.
This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using
isochronous endpoints.
• ENDBUSRES: End of BUS Reset Interrupt Status
0 = No End of Bus Reset Interrupt pending.
1 = End of Bus Reset Interrupt has been raised.
This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requests on the endpoint 0.
The host starts the enumeration, then performs the configuration.
• WAKEUP: UDP Resume Interrupt Status
0 = No Wake-up Interrupt pending.
1 = A Wake-up Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear.
After reset the state of this bit is undefined, the application must clear this bit by setting the WAKEUP flag in the UDP_ICR
register.
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39.7.8 UDP Interrupt Clear Register
Name: UDP_ICR
Address: 0x40034020
Access: Write-only
• RXSUSP: Clear UDP Suspend Interrupt
0 = No effect.
1 = Clears UDP Suspend Interrupt.
• RXRSM: Clear UDP Resume Interrupt
0 = No effect.
1 = Clears UDP Resume Interrupt.
• SOFINT: Clear Start Of Frame Interrupt
0 = No effect.
1 = Clears Start Of Frame Interrupt.
• ENDBUSRES: Clear End of Bus Reset Interrupt
0 = No effect.
1 = Clears End of Bus Reset Interrupt.
• WAKEUP: Clear Wake-up Interrupt
0 = No effect.
1 = Clears Wake-up Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – WAKEUP ENDBUSRES SOFINT EXTRSM RXRSM RXSUSP
76543210
––––––––
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39.7.9 UDP Reset Endpoint Register
Name: UDP_RST_EP
Address: 0x40034028
Access: Read-write
• EP0: Reset Endpoint 0
• EP1: Reset Endpoint 1
• EP2: Reset Endpoint 2
• EP3: Reset Endpoint 3
• EP4: Reset Endpoint 4
• EP5: Reset Endpoint 5
• EP6: Reset Endpoint 6
• EP7: Reset Endpoint 7
This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also
resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter 5.8.5 in the
USB Serial Bus Specification, Rev.2.0.
Warning: This flag must be cleared at the end of the reset. It does not clear UDP_CSRx flags.
0 = No reset.
1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_CSRx register.
Resetting the endpoint is a two-step operation:
1. Set the corresponding EPx field.
2. Clear the corresponding EPx field.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0
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39.7.10 UDP Endpoint Control and Status Register (Control, Bulk Interrupt Endpoints)
Name: UDP_CSRx [x = 0..7]
Address: 0x40034030
Access: Read-write
WARNING: Due to synchronization between MCK and UDPCK, the software application must wait for the end of the write opera-
tion before executing another write by polling the bits which must be set/cleared.
#if defined ( __ICCARM__ )
#define nop() (__no_operation())
#elif defined ( __GNUC__ )
#define nop() __asm__ __volatile__ ( "nop" )
#endif
/// Bitmap for all status bits in CSR that are not effected by a value 1.
#define REG_NO_EFFECT_1_ALL AT91C_UDP_RX_DATA_BK0\
| AT91C_UDP_RX_DATA_BK1\
| AT91C_UDP_STALLSENT\
| AT91C_UDP_RXSETUP\
| AT91C_UDP_TXCOMP
/// Sets the specified bit(s) in the UDP_CSR register.
/// \param endpoint The endpoint number of the CSR to process.
/// \param flags The bitmap to set to 1.
#define SET_CSR(endpoint, flags) \
{\
volatile unsigned int reg; \
reg = AT91C_BASE_UDP->UDP_CSR[endpoint] ; \
reg |= REG_NO_EFFECT_1_ALL; \
reg |= (flags); \
AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \
for( nop_count=0; nop_count<15; nop_count++ ) {\
nop();\
}\
}
31 30 29 28 27 26 25 24
– – – – – RXBYTECNT
23 22 21 20 19 18 17 16
RXBYTECNT
15 14 13 12 11 10 9 8
EPEDS – – – DTGLE EPTYPE
76543210
DIR RX_DATA_BK1 FORCESTALL TXPKTRDY STALLSENT RXSETUP RX_DATA_
BK0 TXCOMP
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/// Clears the specified bit(s) in the UDP_CSR register.
/// \param endpoint The endpoint number of the CSR to process.
/// \param flags The bitmap to clear to 0.
#define CLEAR_CSR(endpoint, flags) \
{\
volatile unsigned int reg; \
reg = AT91C_BASE_UDP->UDP_CSR[endpoint]; \
reg |= REG_NO_EFFECT_1_ALL; \
reg &= ~(flags); \
AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \
for( nop_count=0; nop_count<15; nop_count++ ) {\
nop();\
}\
}
In a preemptive environment, set or clear the flag and wait for a time of 1 UDPCK clock cycle and
1peripheral clock cycle. However, RX_DATA_BK0, TXPKTRDY, RX_DATA_BK1 require wait times of 3 UDPCK
clock cycles and 5 peripheral clock cycles before accessing DPR.
• TXCOMP: Generates an IN Packet with Data Previously Written in the DPR
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware):
0 = Clear the flag, clear the interrupt.
1 = No effect.
Read (Set by the USB peripheral):
0 = Data IN transaction has not been acknowledged by the Host.
1 = Data IN transaction is achieved, acknowledged by the Host.
After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has
acknowledged the transaction.
• RX_DATA_BK0: Receive Data Bank 0
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware):
0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0.
1 = To leave the read value unchanged.
Read (Set by the USB peripheral):
0 = No data packet has been received in the FIFO's Bank 0.
1 = A data packet has been received, it has been stored in the FIFO's Bank 0.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the
microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through
the UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clear-
ing RX_DATA_BK0.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing
DPR.
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• RXSETUP: Received Setup
This flag generates an interrupt while it is set to one.
Read:
0 = No setup packet available.
1 = A setup data packet has been sent by the host and is available in the FIFO.
Write:
0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO.
1 = No effect.
This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully
received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_FDRx register
to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware.
Ensuing Data OUT transaction is not accepted while RXSETUP is set.
• STALLSENT: Stall Sent
This flag generates an interrupt while it is set to one.
This ends a STALL handshake.
Read:
0 = The host has not acknowledged a STALL.
1 = Host has acknowledged the stall.
Write:
0 = Resets the STALLSENT flag, clears the interrupt.
1 = No effect.
This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains.
Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL
handshake.
• TXPKTRDY: Transmit Packet Ready
This flag is cleared by the USB device.
This flag is set by the USB device firmware.
Read:
0 = There is no data to send.
1 = The data is waiting to be sent upon reception of token IN.
Write:
0 = Can be used in the procedure to cancel transmission data. (See, Section 39.6.2.5 “Transmit Data Cancellation” on page 940)
1 = A new data payload has been written in the FIFO by the firmware and is ready to be sent.
This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the
FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx register. Once the data pay-
load has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can
start. TXCOMP is set once the data payload has been received by the host.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing
DPR.
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• FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints)
Read:
0 = Normal state.
1 = Stall state.
Write:
0 = Return to normal state.
1 = Send STALL to the host.
Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL
handshake.
Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request.
Bulk and interrupt endpoints: This bit notifies the host that the endpoint is halted.
The host acknowledges the STALL, device firmware is notified by the STALLSENT flag.
• RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware):
0 = Notifies USB device that data have been read in the FIFO’s Bank 1.
1 = To leave the read value unchanged.
Read (Set by the USB peripheral):
0 = No data packet has been received in the FIFO's Bank 1.
1 = A data packet has been received, it has been stored in FIFO's Bank 1.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to micro-
controller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through
UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing
RX_DATA_BK1.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing
DPR.
• DIR: Transfer Direction (only available for control endpoints)
Read-write
0 = Allows Data OUT transactions in the control data stage.
1 = Enables Data IN transactions in the control data stage.
Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage.
This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the
setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary
to check this bit to reverse direction for the status stage.
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• EPTYPE[2:0]: Endpoint Type
Read-Write
• DTGLE: Data Toggle
Read-only
0 = Identifies DATA0 packet.
1 = Identifies DATA1 packet.
Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions.
• EPEDS: Endpoint Enable Disable
Read:
0 = Endpoint disabled.
1 = Endpoint enabled.
Write:
0 = Disables endpoint.
1 = Enables endpoint.
Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints.
Note: After reset, all endpoints are configured as control endpoints (zero).
• RXBYTECNT[10:0]: Number of Bytes Available in the FIFO
Read-only
When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The
microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx register.
Value Name Description
000 CTRL Control
001 ISO_OUT Isochronous OUT
101 ISO_IN Isochronous IN
010 BULK_OUT Bulk OUT
110 BULK_IN Bulk IN
011 INT_OUT Interrupt OUT
111 INT_IN Interrupt IN
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39.7.11 UDP Endpoint Control and Status Register (Isochronous Endpoints)
Name: UDP_CSRx [x = 0..7] (ISOENDPT)
Address: 0x40034030
Access: Read-write
• TXCOMP: Generates an IN Packet with Data Previously Written in the DPR
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware):
0 = Clear the flag, clear the interrupt.
1 = No effect.
Read (Set by the USB peripheral):
0 = Data IN transaction has not been acknowledged by the Host.
1 = Data IN transaction is achieved, acknowledged by the Host.
After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has
acknowledged the transaction.
• RX_DATA_BK0: Receive Data Bank 0
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware):
0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0.
1 = To leave the read value unchanged.
Read (Set by the USB peripheral):
0 = No data packet has been received in the FIFO's Bank 0.
1 = A data packet has been received, it has been stored in the FIFO's Bank 0.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the
microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through
the UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clear-
ing RX_DATA_BK0.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing
DPR.
31 30 29 28 27 26 25 24
– – – – – RXBYTECNT
23 22 21 20 19 18 17 16
RXBYTECNT
15 14 13 12 11 10 9 8
EPEDS – – – DTGLE EPTYPE
76543210
DIR RX_DATA_BK1 FORCESTALL TXPKTRDY ISOERROR RXSETUP RX_DATA_
BK0 TXCOMP
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• RXSETUP: Received Setup
This flag generates an interrupt while it is set to one.
Read:
0 = No setup packet available.
1 = A setup data packet has been sent by the host and is available in the FIFO.
Write:
0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO.
1 = No effect.
This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully
received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_FDRx register
to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware.
Ensuing Data OUT transaction is not accepted while RXSETUP is set.
• ISOERROR: A CRC error has been detected in an isochronous transfer
This flag generates an interrupt while it is set to one.
Read:
0 = No error in the previous isochronous transfer.
1 = CRC error has been detected, data available in the FIFO are corrupted.
Write:
0 = Resets the ISOERROR flag, clears the interrupt.
1 = No effect.
• TXPKTRDY: Transmit Packet Ready
This flag is cleared by the USB device.
This flag is set by the USB device firmware.
Read:
0 = There is no data to send.
1 = The data is waiting to be sent upon reception of token IN.
Write:
0 = Can be used in the procedure to cancel transmission data. (See, Section 39.6.2.5 “Transmit Data Cancellation” on page 940)
1 = A new data payload has been written in the FIFO by the firmware and is ready to be sent.
This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the
FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx register. Once the data pay-
load has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can
start. TXCOMP is set once the data payload has been received by the host.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing
DPR.
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• FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints)
Read:
0 = Normal state.
1 = Stall state.
Write:
0 = Return to normal state.
1 = Send STALL to the host.
Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL
handshake.
Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request.
Bulk and interrupt endpoints: This bit notifies the host that the endpoint is halted.
The host acknowledges the STALL, device firmware is notified by the STALLSENT flag.
• RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes)
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware):
0 = Notifies USB device that data have been read in the FIFO’s Bank 1.
1 = To leave the read value unchanged.
Read (Set by the USB peripheral):
0 = No data packet has been received in the FIFO's Bank 1.
1 = A data packet has been received, it has been stored in FIFO's Bank 1.
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to micro-
controller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through
UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing
RX_DATA_BK1.
After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing
DPR.
• DIR: Transfer Direction (only available for control endpoints)
Read-write
0 = Allows Data OUT transactions in the control data stage.
1 = Enables Data IN transactions in the control data stage.
Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage.
This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the
setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary
to check this bit to reverse direction for the status stage.
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• EPTYPE[2:0]: Endpoint Type
Read-Write
• DTGLE: Data Toggle
Read-only
0 = Identifies DATA0 packet.
1 = Identifies DATA1 packet.
Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions.
• EPEDS: Endpoint Enable Disable
Read:
0 = Endpoint disabled.
1 = Endpoint enabled.
Write:
0 = Disables endpoint.
1 = Enables endpoint.
Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints.
Note: After reset, all endpoints are configured as control endpoints (zero).
• RXBYTECNT[10:0]: Number of Bytes Available in the FIFO
Read-only
When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The
microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx register.
Value Name Description
000 CTRL Control
001 ISO_OUT Isochronous OUT
101 ISO_IN Isochronous IN
010 BULK_OUT Bulk OUT
110 BULK_IN Bulk IN
011 INT_OUT Interrupt OUT
111 INT_IN Interrupt IN
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39.7.12 UDP FIFO Data Register
Name: UDP_FDRx [x = 0..7]
Address: 0x40034050
Access: Read-write
• FIFO_DATA[7:0]: FIFO Data Value
The microcontroller can push or pop values in the FIFO through this register.
RXBYTECNT in the corresponding UDP_CSRx register is the number of bytes to be read from the FIFO (sent by the host).
The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more
than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more
information.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
FIFO_DATA
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39.7.13 UDP Transceiver Control Register
Name: UDP_TXVC
Address: 0x40034074
Access: Read-write
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write opera-
tions to the UDP registers including the UDP_TXVC register.
• TXVDIS: Transceiver Disable
When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can be
done by setting TXVDIS field.
To enable the transceiver, TXVDIS must be cleared.
• PUON: Pull-up On
0: The 1.5KΩ integrated pull-up on DDP is disconnected.
1: The 1.5 KΩ integrated pull-up on DDP is connected.
NOTE: If the USB pull-up is not connected on DDP, the user should not write in any UDP register other than the UDP_TXVC reg-
ister. This is because if DDP and DDM are floating at 0, or pulled down, then SE0 is received by the device with the consequence
of a USB Reset.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––
PUON TXVDIS
76543210
––––––––
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40. Analog Comparator Controller (ACC)
40.1 Description
The Analog Comparator Controller (ACC) configures the Analog Comparator and generates an interrupt according to the
user settings. The analog comparator embeds 8 to 1 multiplexers on both inputs.
The Analog Comparator compares two voltages and the result of this comparison gives a compare output. The user can
select a high-speed or low-power option. Additionally, the hysteresis level, edge detection and polarity are configurable.
The ACC can also generate a compare event which can be used by the PWM.
Refer to Figure 40-1 on page 967 for detailed schematics.
40.2 Embedded Characteristics
8 User Analog Inputs Selectable for Comparison
4 Voltage References Selectable for Comparison: Temperature Sensor, ADVREF, DAC0 and DAC1
Interrupt Generation
Compare Event Fault Generation for PWM
40.3 Block Diagram
Figure 40-1. Analog Comparator Controller Block Diagram
Mux
AD7
AD0
Mux
TS
AD3
ADVREF
DAC0
DAC1
AD0
+
-
inp
inn
Analog Comparator
isel
oncomp
hyst
bias
AND
AND MCK
Synchro
+
Edge
Detect
ACC_MR, ACC_ACR
Change Detect
+Mask Timer
INVSELMINUSSELPLUS ACEN EDGETYP SCO
CE
MASK
SELFS
SCO
MCK
HYSTISEL
Interrupt Controller
FE
User Interface
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40.4 Pin Name List
40.5 Product Dependencies
40.5.1 I/O Lines
The analog input pins (AD0-AD7 and DAC0-1) are multiplexed with PIO lines. In this case, the assignment of the ACC
inputs is automatically done as soon as the corresponding input is enabled by writing the ACC Mode register
(SELMINUS and SELPLUS).
40.5.2 Power Management
The ACC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the Analog Comparator Controller clock.
Note that the voltage regulator needs to be activated to use the Analog Comparator.
40.5.3 Interrupt
The ACC has an interrupt line connected to the Interrupt Controller (IC). Handling the ACC interrupt requires
programming the Interrupt Controller before configuring the ACC.
40.5.4 Fault Output
The ACC has the FAULT output connected to the FAULT input of PWM. Please refer to chapter Section 40.6.5 ”Fault
Mode” and implementation of the PWM in the product.
Table 40-1. ACC Pin List
Pin Name Description Type
AD0..AD7 Analog Inputs Input
TS On-Chip Temperature Sensor Input
ADVREF ADC Voltage Reference. Input
DAC0, DAC1 On-Chip DAC Outputs Input
FAULT Drives internal fault input of PWM Output
Table 40-2. Peripheral IDs
Instance ID
ACC 33
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40.6 Functional Description
40.6.1 ACC Description
The Analog Comparator Controller mainly controls the analog comparator settings. There is also post processing of the
analog comparator output.
The output of the analog comparator is masked for the time the output may be invalid. This situation is encountered as
soon as the analog comparator settings are modified.
A comparison flag is triggered by an event on the output of the analog comparator and an interrupt can be generated
accordingly. The event on the analog comparator output can be selected among falling edge, rising edge or any edge.
The registers for programming are listed in Table 40-3 on page 970.
40.6.2 Analog Settings
The user can select the input hysteresis and configure high-speed or low-speed options.
shortest propagation delay/highest current consumption
longest propagation delay/lowest current consumption
40.6.3 Write Protection System
In order to provide security to the Analog Comparator Controller, a write protection system has been implemented.
The write protection mode prevents writing ACC Mode Register and ACC Analog Control Register. When this mode is
enabled and one of the protected registers is written, the register write request is canceled.
Due to the nature of the write protection feature, enabling and disabling the write protection mode requires a security
code. Thus when enabling or disabling the write protection mode, the WPKEY field of the ACC_WPMR register must be
filled with the “ACC” ASCII code (corresponding to 0x414343), otherwise the register write will be canceled.
40.6.4 Automatic Output Masking Period
As soon as the analog comparator settings change, the output is invalid for a duration depending on ISEL current.
A masking period is automatically triggered as soon as a write access is performed on ACC_MR or ACC_ACR registers
(whatever the register data content).
When ISEL = 0, the mask period is 8*tMCK, else 128*tMCK.
The masking period is reported by reading a negative value (bit 31 set) on ACC_ISR register
40.6.5 Fault Mode
The FAULT output can be used to propagate a comparison match and act immediately via combinatorial logic by using
the FAULT output which is directly connected to the FAULT input of the PWM.
The source of the FAULT output can be configured to be either a combinational value derived from the analog
comparator output or the MCK resynchronized value (Refer to Figure 40-1 ”Analog Comparator Controller Block
Diagram”).
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40.7 Analog Comparator Controller (ACC) User Interface
Table 40-3. Register Mapping
Offset Register Name Access Reset
0x00 Control Register ACC_CR Write-only
0x04 Mode Register ACC_MR Read-write 0
0x08-0x20 Reserved
0x24 Interrupt Enable Register ACC_IER Write-only
0x28 Interrupt Disable Register ACC_IDR Write-only
0x2C Interrupt Mask Register ACC_IMR Read-only 0
0x30 Interrupt Status Register ACC_ISR Read-only 0
0x34-0x90 Reserved
0x94 Analog Control Register ACC_ACR Read-write 0
0x98-0xE0 Reserved
0xE4 Write Protect Mode Register ACC_WPMR Read-write 0
0xE8 Write Protect Status Register ACC_WPSR Read-only 0
0xEC-0xF8 Reserved
0xFC Reserved – – –
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40.7.1 ACC Control Register
Name: ACC_CR
Address: 0x40040000
Access: Write-only
• SWRST: SoftWare ReSeT
0 = No effect.
1 = Resets the module.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SWRST
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40.7.2 ACC Mode Register
Name: ACC_MR
Address: 0x40040004
Access: Read-write
This register can only be written if the WPEN bit is cleared in the ACC Write Protect Mode Register.
• SELMINUS: SELection for MINUS comparator input
0..7 = Selects the input to apply on analog comparator SELMINUS comparison input.
• SELPLUS: SELection for PLUS comparator input
0..7 = selects the input to apply on analog comparator SELPLUS comparison input.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– FE SELFS INV – EDGETYP ACEN
76543210
– SELPLUS – SELMINUS
Value Name Description
0 TS Select TS
1 ADVREF Select ADVREF
2 DAC0 Select DAC0
3 DAC1 Select DAC1
4 AD0 Select AD0
5 AD1 Select AD1
6 AD2 Select AD2
7 AD3 Select AD3
Value Name Description
0 AD0 Select AD0
1 AD1 Select AD1
2 AD2 Select AD2
3 AD3 Select AD3
4 AD4 Select AD4
5 AD5 Select AD5
6 AD6 Select AD6
7 AD7 Select AD7
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• ACEN: Analog Comparator ENable
0 (DIS) = Analog Comparator Disabled.
1 (EN) = Analog Comparator Enabled.
• EDGETYP: EDGE TYPe
• INV: INVert comparator output
0 (DIS) = Analog Comparator output is directly processed.
1 (EN) = Analog Comparator output is inverted prior to being processed.
• SELFS: SELection of Fault Source
0 (CF) = The CF flag is used to drive the FAULT output.
1 (OUTPUT) = The output of the Analog Comparator flag is used to drive the FAULT output.
• FE: Fault Enable
0 (DIS) = The FAULT output is tied to 0.
1 (EN) = The FAULT output is driven by the signal defined by SELFS.
Value Name Description
0RISING only rising edge of comparator output
1FALLING falling edge of comparator output
2ANY any edge of comparator output
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40.7.3 ACC Interrupt Enable Register
Name: ACC_IER
Address: 0x40040024
Access: Write-only
• CE: Comparison Edge
0 = No effect.
1 = Enables the interruption when the selected edge (defined by EDGETYP) occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––CE
975
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40.7.4 ACC Interrupt Disable Register
Name: ACC_IDR
Address: 0x40040028
Access: Write-only
• CE: Comparison Edge
0 = No effect.
1 = Disables the interruption when the selected edge (defined by EDGETYP) occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––CE
976
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40.7.5 ACC Interrupt Mask Register
Name: ACC_IMR
Address: 0x4004002C
Access: Read-only
• CE: Comparison Edge
0 = The interruption is disabled.
1 = The interruption is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––CE
977
SAM4S [DATASHEET]
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40.7.6 ACC Interrupt Status Register
Name: ACC_ISR
Address: 0x40040030
Access: Read-only
• CE: Comparison Edge
0 = No edge occurred (defined by EDGETYP) on analog comparator output since the last read of ACC_ISR register.
1 = A selected edge (defined by EDGETYP) on analog comparator output occurred since the last read of ACC_ISR register.
• SCO: Synchronized Comparator Output
Returns an image of Analog Comparator Output after being pre-processed (refer to Figure 40-1 on page 967).
If INV = 0
SCO=0ifinn>inp
SCO=1ifinp>inn
If INV = 1
SCO=1ifinn>inp
SCO=0ifinp>inn
• MASK:
0 = The CE flag is valid.
1 = The CE flag and SCO value are invalid.
31 30 29 28 27 26 25 24
MASK – – –––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––SCOCE
978
SAM4S [DATASHEET]
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40.7.7 ACC Analog Control Register
Name: ACC_ACR
Address: 0x40040094
Access: Read-write
This register can only be written if the WPEN bit is cleared in ACC Write Protect Mode Register.
• ISEL: Current SELection
Refer to the product Electrical Characteristics.
0 (LOPW) = Low power option.
1 (HISP) = High speed option.
• HYST: HYSTeresis selection
0 to 3: Refer to the product Electrical Characteristics.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – – HYST ISEL
979
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40.7.8 ACC Write Protect Mode Register
Name: ACC_WPMR
Address: 0x400400E4
Access: Read-write
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x414343 (“ACC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x414343 (“ACC” in ASCII).
Protects the registers:
•“ACC Mode Register” on page 972
•“ACC Analog Control Register” on page 978
• WPKEY: Write Protect KEY
This security code is needed to set/reset the WPROT bit value (see Section 40.6.3 ”Write Protection System” for details).
Must be filled with “ACC” ASCII code.
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
980
SAM4S [DATASHEET]
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40.7.9 ACC Write Protect Status Register
Name: ACC_WPSR
Address: 0x400400E8
Access: Read-only
• WPROTERR: Write PROTection ERRor
0 = No Write Protect Violation has occurred since the last read of the ACC_WPSR register.
1 = A Write Protect Violation (WPEN = 1) has occurred since the last read of the ACC_WPSR register.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––WPROTERR
981
SAM4S [DATASHEET]
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41. Analog-to-Digital Converter (ADC)
41.1 Description
The ADC is based on a 12-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to the Block
Diagram: Figure 41-1. It also integrates a 16-to-1 analog multiplexer, making possible the analog-to-digital conversions
of 16 analog lines. The conversions extend from 0V to the voltage carried on pin ADVREF. The ADC supports an 10-bit
or 12-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a
channel-dedicated register.
Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are
configurable.
The comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a given
range or outside the range, thresholds and ranges being fully configurable.
The ADC Controller internal fault output is directly connected to PWM Fault input. This input can be asserted by means of
comparison circuitry in order to immediately put the PWM outputs in a safe state (pure combinational path).
The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC channel. These features
reduce both power consumption and processor intervention.
This ADC has a selectable single-ended or fully differential input and benefits from a 2-bit programmable gain.
A digital error correction circuit based on the multi-bit redundant signed digit (RSD) algorithm is employed in order to
reduce INL and DNL errors.
Finally, the user can configure ADC timings, such as Startup Time and Tracking Time.
41.2 Embedded Characteristics
up to 16 Channels, 12-bit ADC
10/12-bit resolution
up to 1 MSample/s
Programmable conversion sequence conversion on each channel
Integrated temperature sensor
Automatic calibration mode
Single ended/differential conversion
Programmable gain: 1, 2, 4
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41.3 Block Diagram
Figure 41-1. Analog-to-Digital Converter Block Diagram
Note: DMA is sometimes referenced as PDC (Peripheral DMA Controller).
41.4 Signal Description
Note: 1. AD15 is not an actual pin but is connected to a temperature sensor.
41.5 Product Dependencies
41.5.1 Power Management
The ADC Controller is not continuously clocked. The programmer must first enable the ADC Controller MCK in the Power
Management Controller (PMC) before using the ADC Controller. However, if the application does not require ADC
operations, the ADC Controller clock can be stopped when not needed and restarted when necessary. Configuring the
ADC Controller does not require the ADC Controller clock to be enabled.
41.5.2 Interrupt Sources
The ADC i nterru pt line is c onnecte d on one of th e intern al source s of the Int errupt C ontroll er. Usin g the ADC in terrupt
requires the interrupt controller to be programmed first.
ADTRG
ADVREF
GND
Trigger
Selection
Timer
Counter
Channels
AD0
AD1
ADn
Analog
Inputs
ADC Interrupt
ADC 12-Bit Controller
ADC cell
Control
Logic
User
Interface
Interrupt
Controller
Peripheral Bridge
APB
PDC
AHB
IN+
IN- S/H
OFFSET PGA
PIO
Cyclic Pipeline
12-bit Analog-to-Digital
Converter
CHx
Table 41-1. ADC Pin Description
Pin Name Description
ADVREF Reference voltage
AD0-AD15(1) Analog input channels
ADTRG External trigger
Table 41-2. Peripheral IDs
Instance ID
ADC 29
983
SAM4S [DATASHEET]
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41.5.3 Analog Inputs
The analog input pins can be multiplexed with PIO lines. In this case, the assignment of the ADC input is automatically
done as soon as the corresponding channel is enabled by writing the register ADC_CHER. By default, after reset, the
PIO line is configured as input with its pull-up enabled and the ADC input is connected to the GND.
41.5.4 Temperature Sensor
The temperature sensor is internally connected to channel 15 of the ADC.
The temperature sensor provides an output voltage VT that is proportional to the absolute temperature (PTAT). To
activate the temperature sensor, TSON bit (ADC_ACR) needs to be set. After being set, the startup time of the
temperature sensor must be achieved prior to initiating any measure.
41.5.5 I/O Lines
The pin ADTRG may be shared with other peripheral functions through the PIO Controller. In this case, the PIO
Controller should be set accordingly to assign the pin ADTRG to the ADC function.
41.5.6 Timer Triggers
Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all of the
timer counters may be unconnected.
41.5.7 PWM Event Line
PWM Event Lines may or may not be used as hardware triggers depending on user requirements.
Table 41-3. I/O Lines
Instance Signal I/O Line Peripheral
ADC ADTRG PA8 B
ADC AD0 PA17 X1
ADC AD1 PA18 X1
ADC AD2/WKUP9 PA19 X1
ADC AD3/WKUP10 PA20 X1
ADC AD4/RTCOUT0 PB0 X1
ADC AD5/RTCOUT1 PB1 X1
ADC AD6/WKUP12 PB2 X1
ADC AD7 PB3 X1
ADC AD8 PA21 X1
ADC AD9 PA22 X1
ADC AD10 PC13 X1
ADC AD11 PC15 X1
ADC AD12 PC12 X1
ADC AD13 PC29 X1
ADC AD14 PC30 X1
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41.5.8 Fault Output
The ADC Controller has the FAULT output connected to the FAULT input of PWM. Please refer to Section 41.6.13
”Fault Output” and implementation of the PWM in the product.
41.5.9 Conversion Performances
For performance and electrical characteristics of the ADC, see the product DC Characteristics section.
41.6 Functional Description
41.6.1 Analog-to-digital Conversion
The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 12-bit digital data requires
Tracking Clock cycles as defined in the field TRACKTIM of the “ADC Mode Register” on page 996. The ADC Clock
frequency is selected in the PRESCAL field of the Mode Register (ADC_MR). The tracking phase starts during the
conversion of the previous channel. If the tracking time is longer than the conversion time, the tracking phase is extended
to the end of the previous conversion.
The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/512, if PRESCAL is set to 255 (0xFF). PRESCAL
must be programmed in order to provide an ADC clock frequency according to the parameters given in the product
Electrical Characteristics section.
Figure 41-2. Sequence of ADC conversions when Tracking time > Conversion time
ADCClock
LCDR
ADC_ON
Trigger event (Hard or Soft)
ADC_SEL
DRDY
ADC_Start
CH0 CH1
CH0
CH2
CH1
Transfer Period Transfer PeriodStart Up
Time
(and tracking of CH0)
Conversion
of CH0 Conversion
of CH1
Tracking of CH1 Tracking of CH2
Commands
from controller
to analog cell
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Figure 41-3. Sequence of ADC conversions when Tracking time < Conversion time
41.6.2 Conversion Reference
The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between
these voltages convert to values based on a linear conversion.
41.6.3 Conversion Resolution
The ADC supports 10-bit or 12-bit resolutions. The 10-bit selection is performed by setting the LOWRES bit in the ADC
Mode Register (ADC_MR). By default, after a reset, the resolution is the highest and the DATA field in the data registers
is fully used. By setting the LOWR ES bit, the ADC switches to the lowest resolution and the conversion results can be
read in the lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding
ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0.
Moreover, when a PDC channel is connected to the ADC, 12-bit or 10-bit resolution sets the request size to 16 bits.
41.6.4 Conversion Results
When a conversion is completed, the resulting 12-bit digital value is stored in the Channel Data Register (ADC_CDRx) of
the current channel and in the ADC Last Converted Data Register (ADC_LCDR). By setting the TAG option in the
ADC_EMR, the ADC_LCDR presents the channel number associated to the last converted data in the CHNB field.
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC
channel, DRDY rising triggers a data request. In any case, either EOC and DRDY can trigger an interrupt.
Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit.
ADCClock
LCDR
ADC_ON
Trigger event (Hard or Soft)
ADC_SEL
DRDY
ADC_Start
CH0 CH1
CH0
CH2
CH1
CH3
CH2
Transfer Period Transfer Period Transfer PeriodStart Up
Time
&
Tracking
of CH0
Conversion
of CH0
&
Tracking
of CH1
Conversion
of CH1
&
Tracking
of CH2
Conversion
of CH2
&
Tracking
of CH3
Read the
ADC_LCDR
Commands
from controller
to analog cell
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Figure 41-4. EOCx and DRDY Flag Behavior
If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVREx) flag is
set in the Overrun Status Register (ADC_OVER).
Likewise, new data converted when DRDY is high sets the GOVRE bit (General Overrun Error) in ADC_SR.
The OVREx flag is automatically cleared when ADC_OVER is read, and GOVRE flag is automatically cleared when
ADC_SR is read.
Read the ADC_CDRx
EOCx
DRDY
Read the ADC_LCDR
CHx
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
Write the ADC_CR
with START = 1
Write the ADC_CR
with START = 1
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Figure 41-5. GOVRE and OVREx Flag Behavior
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a
conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable.
EOC0
GOVRE
CH0
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
Trigger event
EOC1
CH1
(ADC_CHSR)
(ADC_SR)
OVRE0
(ADC_OVER)
Undefined Data Data A Data B
ADC_LCDR
Undefined Data Data A
ADC_CDR0
Undefined Data Data B
ADC_CDR1
Data C
Data C
Conversion C
Conversion A
DRDY
(ADC_SR)
Read ADC_CDR1
Read ADC_CDR0
Conversion B
Read ADC_OVER
Read ADC_SR
OVRE1
(ADC_OVER)
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41.6.5 Conversion Triggers
Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is
provided by writing the Control Register (ADC_CR) with the START bit at 1.
The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, PWM Event line, or the external
trigger input of the ADC (ADTRG). The hardware trigger is selected with the TRGSEL field in the Mode Register
(ADC_MR). The selected hardware trigger is enabled with the TRGEN bit in the “ADC Mode Register”.
The minimum time between 2 consecutive trigger events must be strictly greater than the duration time of the longest
conversion sequence according to configuration of registers ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2.
If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of the
selected signal. Due to asynchronous handling, the delay may vary in a range of 2 MCK clock periods to 1 ADC clock
period.
If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform
Mode.
Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic
automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable
(ADC_CHER) and Channel Disable (ADC_CHDR) Registers permit the analog channels to be enabled or disabled
independently.
If the ADC is used with a PDC, only the transfers of converted data from enabled channels are performed and the
resulting data buffers should be interpreted accordingly.
41.6.6 Sleep Mode and Conversion Sequencer
The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for
conversions. Sleep Mode is selected by setting the SLEEP bit in the Mode Register ADC_MR.
The Sleep mode is automatically managed by a conversion sequencer, which can automatically process the conversions
of all channels at lowest power consumption.
This mode can be used when the minimum period of time between 2 successive trigger events is greater than the startup
period of Analog-Digital converter (See the product ADC Characteristics section).
When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up time,
the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete,
the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into account.
A fast wake-up mode is available in the ADC Mode Register (ADC_MR) as a compromise between power saving
strategy and responsiveness. Setting the FWUP bit to ‘1’ enables the fast wake-up mode. In fast wake-up mode the ADC
cell is not fully deactivated while no conversion is requested, thereby providing less power saving but faster wake-up.
The conversion sequencer allows automatic processing with minimum processor intervention and optimized power
consumption. Conversion sequences can be performed periodically using a Timer/Counter output or the PWM event line.
The periodic acquisition of several samples can be processed automatically without any intervention of the processor
thanks to the PDC.
The sequence can be customized by programming the Sequence Channel Registers, ADC_SEQR1 and ADC_SEQR2
and setting to 1 the USEQ bit of the Mode Register (ADC_MR). The user can choose a sp ecific order of channels and
can program up to 16 conversions by sequence. The user is totally free to create a personal sequence, by writing
channel numbers in ADC_SEQR1 and ADC_SEQR2. Not only can channel numbers be written in any sequence,
channel numbers can be repeated several times. Only enabled sequence bitfields are converted, consequently to
program a 15-conversion sequence, the user can simply put a disable in ADC_CHSR[15], thus disabling the 16THCH
field of ADC_SEQR2.
trigger
start delay
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If all ADC channels (i.e. 16) are used on an application board, there is no restriction of usage of the user sequence. But
as soon as some ADC channels are not enabled for conversion but rather used as pure digital inputs, the respective
indexes of these channels cannot be used in the user sequence fields (ADC_SEQR1, ADC_SEQR2 bitfields). For
example, if channel 4 is disabled (ADC_CSR[4] = 0), ADC_SEQR1, ADC_SEQR2 register bitfields USCH1 up to
USCH16 must not contain the value 4. Thus the length of the user sequence may be limited by this behavior.
As an example, if only 4 channels over 16 (CH0 up to CH3) are selected for ADC conversions, the user sequence length
cannot exceed 4 channels. Each trigger event may launch up to 4 successive conversions of any combination of
channels 0 up to 3 but no more (i.e. in this case the sequence CH0, CH0, CH1, CH1, CH1 is impossible).
A sequence that repeats several times the same channel requires more enabled channels than channels actually used
for conversion. For example, a sequence like CH0, CH0, CH1, CH1 requires 4 enabled channels (4 free channels on
application boards) whereas only CH0, CH1 are really converted.
Note: The reference voltage pins always remain connected in normal mode as in sleep mode.
41.6.7 Comparison Window
The ADC Controller features automatic comparison functions. It compares converted values to a low threshold or a high
threshold or both, according to the CMPMODE function chosen in the Extended Mode Register (ADC_EMR). The
comparison can be done on all channels or only on the channel specified in CMPSEL field of ADC_EMR. To compare all
channels the CMP_ALL parameter of ADC_EMR should be set.
The flag can be read on the COMPE bit of the Interrupt Status Register (ADC_ISR) and can trigger an interrupt.
The High Threshold and the Low Threshold can be read/write in the Comparison Window Register (ADC_CWR).
If the comparison window is to be used with LOWRES bit in ADC_MR set to 1, the thresholds do not need to be adjusted
as adjustment will be done internally. Whether or not the LOWRES bit is set, thresholds must always be configured in
consideration of the maximum ADC resolution.
41.6.8 Differential Inputs
The ADC can be used either as a single ended ADC (DIFF bit equal to 0) or as a fully differential ADC (DIFF bit equal to
1) as shown in Figure 41-6. By default, after a reset, the ADC is in single ended mode.
If ANACH is set in ADC_MR the ADC can apply a different mode on each channel. Otherwise the parameters of CH0 are
applied to all channels.
The same inputs are used in single ended or differential mode.
In single ended mode, inputs are managed by a 16:1 channels analog multiplexer. In the fully differential mode, inputs
are managed by an 8:1 channels analog multiplexer. See Table 41-4 and Table 41-5.
Table 41-4. Input Pins and Channel Number in Single Ended Mode
Input Pins Channel Number
AD0 CH0
AD1 CH1
AD2 CH2
AD3 CH3
AD4 CH4
AD5 CH5
AD6 CH6
AD7 CH7
AD8 CH8
AD9 CH9
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41.6.9 Input Gain and Offset
The ADC has a built in Programmable Gain Amplifier (PGA) and Programmable Offset.
The Programmable Gain Amplifier can be set to gains of 1/2, 1, 2 and 4. The Programmable Gain Amplifier can be used
either for single ended applications or for fully differential applications.
If ANACH is set in ADC_MR the ADC can apply different gain and offset on each channel. Otherwise the parameters of
CH0 are applied to all channels.
The gain is configurable through the GAIN bit of the Channel Gain Register (ADC_CGR) as shown in Table 41-6.
To allow full range, analog offset of the ADC can be configured by the OFFSET bit of the Channel Offset Register
(ADC_COR). The Offset is only available in Single Ended Mode.
AD10 CH10
AD11 CH11
AD12 CH12
AD13 CH13
AD14 CH14
AD15 CH15
Table 41-5. Input Pins and Channel Number In Differential Mode
Input Pins Channel Number
AD0-AD1 CH0
AD2-AD3 CH2
AD4-AD5 CH4
AD6-AD7 CH6
AD8-AD9 CH8
AD10-AD11 CH10
AD12-AD13 CH12
AD14-AD15 CH14
Table 41-4. Input Pins and Channel Number in Single Ended Mode (Continued)
Input Pins Channel Number
Table 41-6. Gain of the Sample and Hold Unit: GAIN Bits and DIFF Bit.
GAIN<0:1> GAIN (DIFF = 0) GAIN (DIFF = 1)
00 1 0.5
01 1 1
10 2 2
11 4 2
Table 41-7. Offset of the Sample and Hold Unit: OFFSET DIFF and Gain (G)
OFFSET Bit OFFSET (DIFF = 0) OFFSET (DIFF = 1)
00 0
1 (G-1)Vrefin/2
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Figure 41-6. Analog Full Scale Ranges in Single Ended/Differential Applications Versus Gain and Offset
41.6.10 ADC Timings
Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register,
ADC_MR.
A minimal Tracking Time is necessary for the ADC to guarantee the best converted final value between two channel
selections. This time has to be programmed through the TRACKTIM bit field in the Mode Register, ADC_MR.
VIN+
gain=0.5
gain=1
gain=2
gain=4
single ended
se0fd1=0 fully dif f er ent ial
se0fd1=1
same as
gain=1
same as
gain=2
0
vrefin
(½)vrefin
vrefin
0
(¾)vrefin
(¼)vrefin
(½)vrefin
vrefin
0
(5/8)vrefin
(3/8)vrefin
(½)vrefin
offset=0offset=1
offset=0offset=1
(¼)vrefin
vrefin
0
(5/8)vrefin
(3/8)vrefin
(½)vrefin
(¼)vrefin
(¾)vrefin
(1/8)vrefin
(00)
(01)
(10)
(11)
VIN+
VIN+
VIN+
VIN+
VIN+
VIN+
VIN-
VIN+
VIN-
VIN+
VIN-
VIN+
VIN-
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When the gain, offset or differential input parameters of the analog cell change between two channels, the analog cell
may need a specific settling time before starting the tracking phase. In that case, the controller automatically waits during
the settling time defined in the “ADC Mode Register”. Obviously, if the ANACH option is not set, this time is unused.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to
program a precise value in the TRACKTIM field. See the product ADC Characteristics section.
41.6.11 Automatic Calibration
The ADC features an automatic calibration (AUTOCALIB) mode for gain errors (calibration).
The automatic calibration sequence can be started at any time writing to '1' the AUTOCAL bit of the ADC Control
Register. The automatic calibration sequence requires a software reset command (SWRST in the ADC_CR register)
prior to write AUTOCAL bit. The end of calibration sequence is given by the EOCAL bit in the interrupt status register
(ADC_ISR), and an interrupt is generated if EOCAL interrupt has been enabled (ADC_IER register).
The calibration sequence will perform an automatic calibration on all enabled channels. The channels required for
conversion do not need to be all enabled during the calibration process if they are programmed with the same gain. Only
channels with different gain settings need to be enabled. The gain settings of all enabled channels must be set before
starting the AUTOCALIB sequence. If the gain settings (ADC_CGR and ADC_COR registers) for a given channel are
changed, the AUTOCALIB sequence must then be started again.
The calibration data (on one or more enabled channels) is stored in the internal ADC memory.
Then, when a new conversion is started (on one or more enabled channels), the converted value (in ADC_LCDR or
ADC_CDRx registers) is a calibrated value.
Autocalibration is for settings, not for channels. Therefore, if a specific combination of gain has been already calibrated,
and a new channel with the same settings is enabled after the initial calibration, there is no need to restart a calibration. If
different enabled channels have different gain settings, the corresponding channels must be enabled before starting the
calibration.
If a software reset is performed (SWRST bit in ADC_CR) or after power up (or wake-up from Backup mode), the
calibration data in the ADC memory is lost.
Changing the ADC running mode (in ADC_CR register) does not affect the calibration data.
Changing the ADC reference voltage (ADVREF pin) requires a new calibration sequence.
For calibration time, gain error after calibration, refer to the 12-bit ADC electrical characteristics section of the product.
41.6.12 Buffer Structure
The PDC read channel is triggered each time a new data is stored in ADC_LCDR register. The same structure of data is
repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of operation
(ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2) the structure differs. Each data read to PDC buffer, carried on a
half-word (16-bit), consists of last converted data right aligned and when TAG is set in ADC _EMR register, the 4 most
significant bits are carrying the channel number thus allowing an easier post-processing in the PDC buffer or better
checking the PDC buffer integrity.
41.6.13 Fault Output
The ADC Controller internal fault output is directly connected to PWM fault input. Fault output may be asserted according
to the configuration of ADC_EMR (Extended Mode Register) and ADC_CWR (Compare Window Register) and
converted values. When the Compare occurs, the ADC fault output generates a pulse of one Master Clock Cycle to the
PWM fault input. This fault line can be enabled or disabled within PWM. Should it be activated and asserted by the ADC
Controller, the PWM outputs are immediately placed in a safe state (pure combinational path). Note that the ADC fault
output connected to the PWM is not the COMPE bit. Thus the Fault Mode (FMOD) within the PWM configuration must be
FMOD = 1.
993
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.6.14 Write Protected Registers
To prevent any single software error that may corrupt ADC behavior, certain address spaces can be write-protected by
setting the WPEN bit in the “ADC Write Protect Mode Register” (ADC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Protect Status Register
(ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset by reading the ADC Write Protect Status Register (ADC_WPSR).
The protected registers are:
“ADC Mode Register” on page 996
“ADC Channel Sequence 1 Register” on page 999
“ADC Channel Sequence 2 Register” on page 1000
“ADC Channel Enable Register” on page 1001
“ADC Channel Disable Register” on page 1002
“ADC Extended Mode Register” on page 1009
“ADC Compare Window Register” on page 1010
“ADC Channel Gain Register” on page 1011
“ADC Channel Offset Register” on page 1012
994
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7 Analog-to-Digital Converter (ADC) User Interface
Any offset not listed in Table 41-8 must be considered as “reserved”.
Notes: 1. If an offset is not listed in the table it must be considered as “reserved”.
Table 41-8. Register Mapping
Offset Register Name Access Reset
0x00 Control Register ADC_CR Write-only –
0x04 Mode Register ADC_MR Read-write 0x00000000
0x08 Channel Sequence Register 1 ADC_SEQR1 Read-write 0x00000000
0x0C Channel Sequence Register 2 ADC_SEQR2 Read-write 0x00000000
0x10 Channel Enable Register ADC_CHER Write-only –
0x14 Channel Disable Register ADC_CHDR Write-only –
0x18 Channel Status Register ADC_CHSR Read-only 0x00000000
0x1C Reserved – – –
0x20 Last Converted Data Register ADC_LCDR Read-only 0x00000000
0x24 Interrupt Enable Register ADC_IER Write-only –
0x28 Interrupt Disable Register ADC_IDR Write-only –
0x2C Interrupt Mask Register ADC_IMR Read-only 0x00000000
0x30 Interrupt Status Register ADC_ISR Read-only 0x00000000
0x3C Overrun Status Register ADC_OVER Read-only 0x00000000
0x40 Extended Mode Register ADC_EMR Read-write 0x00000000
0x44 Compare Window Register ADC_CWR Read-write 0x00000000
0x48 Channel Gain Register ADC_CGR Read-write 0x00000000
0x4C Channel Offset Register ADC_COR Read-write 0x00000000
0x50 Channel Data Register 0 ADC_CDR0 Read-only 0x00000000
0x54 Channel Data Register 1 ADC_CDR1 Read-only 0x00000000
... ... ... ... ...
0x8C Channel Data Register 15 ADC_CDR15 Read-only 0x00000000
0x90 - 0x90 Reserved – – –
0x94 Analog Control Register ADC_ACR Read-write 0x00000100
0x98 - 0xAC Reserved – – –
0xC4 - 0xE0 Reserved – – –
0xE4 Write Protect Mode Register ADC_WPMR Read-write 0x00000000
0xE8 Write Protect Status Register ADC_WPSR Read-only 0x00000000
0xEC - 0xF8 Reserved – – –
0xFC Reserved – – –
0x100 - 0x124 Reserved for PDC Registers –––
995
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.1 ADC Control Register
Name: ADC_CR
Address: 0x40038000
Access: Write-only
• SWRST: Software Reset
0 = No effect.
1 = Resets the ADC simulating a hardware reset.
• START: Start Conversion
0 = No effect.
1 = Begins analog-to-digital conversion.
• AUTOCAL: Automatic Calibration of ADC
0 = No effect.
1 = Launch an automatic calibration of the ADC cell on next sequence.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – AUTOCAL – START SWRST
996
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.2 ADC Mode Register
Name: ADC_MR
Address: 0x40038004
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
• TRGEN: Trigger Enable
• TRGSEL: Trigger Selection
• LOWRES: Resolution
31 30 29 28 27 26 25 24
USEQ – TRANSFER TRACKTIM
23 22 21 20 19 18 17 16
ANACH – SETTLING STARTUP
15 14 13 12 11 10 9 8
PRESCAL
76543210
FREERUN FWUP SLEEP LOWRES TRGSEL TRGEN
Value Name Description
0 DIS Hardware triggers are disabled. Starting a conversion is only possible by software.
1 EN Hardware trigger selected by TRGSEL field is enabled.
Value Name Description
0 ADC_TRIG0 External trigger
1 ADC_TRIG1 TIO Output of the Timer Counter Channel 0
2 ADC_TRIG2 TIO Output of the Timer Counter Channel 1
3 ADC_TRIG3 TIO Output of the Timer Counter Channel 2
4 ADC_TRIG4 PWM Event Line 0
5 ADC_TRIG5 PWM Event Line 1
6 ADC_TRIG6 Reserved
7 – Reserved
Value Name Description
0 BITS_12 12-bit resolution
1 BITS_10 10-bit resolution
997
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• SLEEP: Sleep Mode
• FWUP: Fast Wake Up
• FREERUN: Free Run Mode
• PRESCAL: Prescaler Rate Selection
ADCClock = MCK/((PRESCAL+1)*2)
• STARTUP: Start Up Time
Value Name Description
0 NORMAL Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions
1 SLEEP Sleep Mode: The wake-up time can be modified by programming FWUP bit
Value Name Description
0 OFF If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions
1ON
If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and
ADC Core is OFF
Value Name Description
0 OFF Normal Mode
1 ON Free Run Mode: Never wait for any trigger.
Value Name Description
0 SUT0 0 periods of ADCClock
1 SUT8 8 periods of ADCClock
2 SUT16 16 periods of ADCClock
3 SUT24 24 periods of ADCClock
4 SUT64 64 periods of ADCClock
5 SUT80 80 periods of ADCClock
6 SUT96 96 periods of ADCClock
7 SUT112 112 periods of ADCClock
8 SUT512 512 periods of ADCClock
9 SUT576 576 periods of ADCClock
10 SUT640 640 periods of ADCClock
11 SUT704 704 periods of ADCClock
12 SUT768 768 periods of ADCClock
13 SUT832 832 periods of ADCClock
14 SUT896 896 periods of ADCClock
15 SUT960 960 periods of ADCClock
998
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• SETTLING: Analog Settling Time
• ANACH: Analog Change
• TRACKTIM: Tracking Time
Tracking Time = (TRACKTIM + 1) * ADCClock periods.
• TRANSFER: Transfer Period
This field must be programmed with value 2.
• USEQ: Use Sequence Enable
Value Name Description
0 AST3 3 periods of ADCClock
1 AST5 5 periods of ADCClock
2 AST9 9 periods of ADCClock
3 AST17 17 periods of ADCClock
Value Name Description
0 NONE No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels
1 ALLOWED Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers
Value Name Description
0 NUM_ORDER Normal Mode: The controller converts channels in a simple numeric order depending only on the
channel index.
1 REG_ORDER User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2
registers and can be used to convert several times the same channel.
999
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.3 ADC Channel Sequence 1 Register
Name: ADC_SEQR1
Address: 0x40038008
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
• USCHx: User Sequence Number x
The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in this field. The
allowed range is 0 up to 7. So it is only possible to use the sequencer from CH0 to CH7.
This register activates only if ADC_MR(USEQ) field is set to ‘1’.
Any USCHx field is taken into account only if ADC_CHSR(CHx) register field reads logical ‘1’ else any value written in USCHx
does not add the corresponding channel in the conversion sequence.
When configuring consecutive fields with the same value, the associated channel is sampled as many time as the number of con-
secutive values, this part of the conversion sequence being triggered by a unique event.
Configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. This
can be done consecutively, or not, according to user needs.
31 30 29 28 27 26 25 24
– USCH8 – USCH7
23 22 21 20 19 18 17 16
– USCH6 – USCH5
15 14 13 12 11 10 9 8
– USCH4 – USCH3
76543210
– USCH2 – USCH1
1000
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.4 ADC Channel Sequence 2 Register
Name: ADC_SEQR2
Address: 0x4003800C
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
• USCHx: User Sequence Number x
The sequence number x (USCHx) can be programmed by the Channel number CHy where y is the value written in this field. The
allowed range is 0 up to 7. So it is only possible to use the sequencer from CH0 to CH7.
This register activates only if ADC_MR(USEQ) field is set to ‘1’.
Any USCHx field is taken into account only if ADC_CHSR(CHx) register field reads logical ‘1’ else any value written in USCHx
does not add the corresponding channel in the conversion sequence.
When configuring consecutive fields with the same value, the associated channel is sampled as many time as the number of con-
secutive values, this part of the conversion sequence being triggered by a unique event.
Configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. This
can be done consecutively, or not, according to user needs.
31 30 29 28 27 26 25 24
– USCH16 – USCH15
23 22 21 20 19 18 17 16
– USCH14 – USCH13
15 14 13 12 11 10 9 8
– USCH12 – USCH11
76543210
– USCH10 – USCH9
1001
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.5 ADC Channel Enable Register
Name: ADC_CHER
Address: 0x40038010
Access: Write-only
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
• CHx: Channel x Enable
0 = No effect.
1 = Enables the corresponding channel.
Note: if USEQ = 1 in ADC_MR register, CHx corresponds to the xth channel of the sequence described in ADC_SEQR1 and
ADC_SEQR2.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
1002
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.6 ADC Channel Disable Register
Name: ADC_CHDR
Address: 0x40038014
Access: Write-only
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
• CHx: Channel x Disable
0 = No effect.
1 = Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its
associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
1003
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.7 ADC Channel Status Register
Name: ADC_CHSR
Address: 0x40038018
Access: Read-only
• CHx: Channel x Status
0 = Corresponding channel is disabled.
1 = Corresponding channel is enabled.
41.7.8 ADC Last Converted Data Register
Name: ADC_LCDR
Address: 0x40038020
Access: Read-only
• LDATA: Last Data Converted
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is
completed.
• CHNB: Channel Number
Indicates the last converted channel when the TAG option is set to 1 in the ADC_EMR register. If the TAG option is not set, CHNB
= 0.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CHNB LDATA
76543210
LDATA
1004
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.9 ADC Interrupt Enable Register
Name: ADC_IER
Address: 0x40038024
Access: Write-only
• EOCx: End of Conversion Interrupt Enable x
• EOCAL: End of Calibration Sequence
• DRDY: Data Ready Interrupt Enable
• GOVRE: General Overrun Error Interrupt Enable
• COMPE: Comparison Event Interrupt Enable
• ENDRX: End of Receive Buffer Interrupt Enable
• RXBUFF: Receive Buffer Full Interrupt Enable
0 = No effect.
1 = Enables the corresponding interrupt.
31 30 29 28 27 26 25 24
– – – RXBUFF ENDRX COMPE GOVRE DRDY
23 22 21 20 19 18 17 16
EOCAL – – –––––
15 14 13 12 11 10 9 8
EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
1005
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.10 ADC Interrupt Disable Register
Name: ADC_IDR
Address: 0x40038028
Access: Write-only
• EOCx: End of Conversion Interrupt Disable x
• EOCAL: End of Calibration Sequence
• DRDY: Data Ready Interrupt Disable
• GOVRE: General Overrun Error Interrupt Disable
• COMPE: Comparison Event Interrupt Disable
• ENDRX: End of Receive Buffer Interrupt Disable
• RXBUFF: Receive Buffer Full Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
31 30 29 28 27 26 25 24
– – – RXBUFF ENDRX COMPE GOVRE DRDY
23 22 21 20 19 18 17 16
EOCAL – – –––––
15 14 13 12 11 10 9 8
EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
1006
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.11 ADC Interrupt Mask Register
Name: ADC_IMR
Address: 0x4003802C
Access: Read-only
• EOCx: End of Conversion Interrupt Mask x
• EOCAL: End of Calibration Sequence
• DRDY: Data Ready Interrupt Mask
• GOVRE: General Overrun Error Interrupt Mask
• COMPE: Comparison Event Interrupt Mask
• ENDRX: End of Receive Buffer Interrupt Mask
• RXBUFF: Receive Buffer Full Interrupt Mask
0 = The corresponding interrupt is disabled.
1 = The corresponding interrupt is enabled.
31 30 29 28 27 26 25 24
– – – RXBUFF ENDRX COMPE GOVRE DRDY
23 22 21 20 19 18 17 16
EOCAL – – –––––
15 14 13 12 11 10 9 8
EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
1007
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.12 ADC Interrupt Status Register
Name: ADC_ISR
Address: 0x40038030
Access: Read-only
• EOCx: End of Conversion x
0 = Corresponding analog channel is disabled, or the conversion is not finished. This flag is cleared when reading the correspond-
ing ADC_CDRx registers.
1 = Corresponding analog channel is enabled and conversion is complete.
• EOCAL: End of Calibration Sequence
0 = Calibration sequence is on going, or no calibration sequence has been requested.
1 = Calibration sequence is complete.
• DRDY: Data Ready
0 = No data has been converted since the last read of ADC_LCDR.
1 = At least one data has been converted and is available in ADC_LCDR.
• GOVRE: General Overrun Error
0 = No General Overrun Error occurred since the last read of ADC_ISR.
1 = At least one General Overrun Error has occurred since the last read of ADC_ISR.
• COMPE: Comparison Error
0 = No Comparison Error since the last read of ADC_ISR.
1 = At least one Comparison Error (defined in the ADC_EMR and ADC_CWR registers) has occurred since the last read of
ADC_ISR.
• ENDRX: End of RX Buffer
0 = The Receive Counter Register has not reached 0 since the last write in ADC_RCR or ADC_RNCR.
1 = The Receive Counter Register has reached 0 since the last write in ADC_RCR or ADC_RNCR.
• RXBUFF: RX Buffer Full
0 = ADC_RCR or ADC_RNCR have a value other than 0.
1 = Both ADC_RCR and ADC_RNCR have a value of 0.
31 30 29 28 27 26 25 24
– – – RXBUFF ENDRX COMPE GOVRE DRDY
23 22 21 20 19 18 17 16
EOCAL – – –––––
15 14 13 12 11 10 9 8
EOC15 EOC14 EOC13 EOC12 EOC11 EOC10 EOC9 EOC8
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
1008
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.13 ADC Overrun Status Register
Name: ADC_OVER
Address: 0x4003803C
Access: Read-only
• OVREx: Overrun Error x
0 = No overrun error on the corresponding channel since the last read of ADC_OVER.
1 = There has been an overrun error on the corresponding channel since the last read of ADC_OVER.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
OVRE15 OVRE14 OVRE13 OVRE12 OVRE11 OVRE10 OVRE9 OVRE8
76543210
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
1009
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.14 ADC Extended Mode Register
Name: ADC_EMR
Address: 0x40038040
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
• CMPMODE: Comparison Mode
• CMPSEL: Comparison Selected Channel
If CMPALL = 0: CMPSEL indicates which channel has to be compared.
If CMPALL = 1: No effect.
• CMPALL: Compare All Channels
0 = Only channel indicated in CMPSEL field is compared.
1 = All channels are compared.
• TAG: TAG of the ADC_LDCR register
0 = set CHNB to zero in ADC_LDCR.
1 = append the channel number to the conversion result in ADC_LDCR register.
31 30 29 28 27 26 25 24
–––––––TAG
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – – – CMPALL –
76543210
CMPSEL – – CMPMODE
Value Name Description
0 LOW Generates an event when the converted data is lower than the low threshold of the window.
1 HIGH Generates an event when the converted data is higher than the high threshold of the window.
2 IN Generates an event when the converted data is in the comparison window.
3 OUT Generates an event when the converted data is out of the comparison window.
1010
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.15 ADC Compare Window Register
Name: ADC_CWR
Address: 0x40038044
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
• LOWTHRES: Low Threshold
Low threshold associated to compare settings of the ADC_EMR register.
If LOWRES is set in ADC_MR, only the 12 LSB of LOWTHRES must be programmed. The 2 LSB will be automatically discarded
to match the value carried on ADC_CDR (10-bit).
• HIGHTHRES: High Threshold
High threshold associated to compare settings of the ADC_EMR register.
If LOWRES is set in ADC_MR, only the 12 LSB of HIGHTHRES must be programmed. The 2 LSB will be automatically discarded
to match the value carried on ADC_CDR (10-bit).
31 30 29 28 27 26 25 24
– – – – HIGHTHRES
23 22 21 20 19 18 17 16
HIGHTHRES
15 14 13 12 11 10 9 8
– – – – LOWTHRES
76543210
LOWTHRES
1011
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.16 ADC Channel Gain Register
Name: ADC_CGR
Address: 0x40038048
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
• GAINx: Gain for channel x
Gain applied on input of analog-to-digital converter.
The DIFFx mentioned in this table is described in the following register, ADC_COR.
31 30 29 28 27 26 25 24
GAIN15 GAIN14 GAIN13 GAIN12
23 22 21 20 19 18 17 16
GAIN11 GAIN10 GAIN9 GAIN8
15 14 13 12 11 10 9 8
GAIN7 GAIN6 GAIN5 GAIN4
76543210
GAIN3 GAIN2 GAIN1 GAIN0
GAINx Gain applied when DIFFx = 0 Gain applied when DIFFx = 1
001 0.5
011 1
102 2
114 2
1012
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.17 ADC Channel Offset Register
Name: ADC_COR
Address: 0x4003804C
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
• OFFx: Offset for channel x
0 = No Offset.
1 = center the analog signal on Vrefin/2 before the gain scaling. The Offset applied is: (G-1)Vrefin/2
where G is the gain applied (see description of ADC_CGR register).
• DIFFx: Differential inputs for channel x
0 = Single Ended Mode.
1 = Fully Differential Mode.
31 30 29 28 27 26 25 24
DIFF15 DIFF14 DIFF13 DIFF12 DIFF11 DIFF10 DIFF9 DIFF8
23 22 21 20 19 18 17 16
DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0
15 14 13 12 11 10 9 8
OFF15 OFF14 OFF13 OFF12 OFF11 OFF10 OFF9 OFF8
76543210
OFF7 OFF6 OFF5 OFF4 OFF3 OFF2 OFF1 OFF0
1013
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.18 ADC Channel Data Register
Name: ADC_CDRx [x=0..15]
Address: 0x40038050
Access: Read-write
• DATA: Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is
completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––– DATA
76543210
DATA
1014
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.19 ADC Analog Control Register
Name: ADC_ACR
Address: 0x40038094
Access: Read-write
This register can only be written if the WPEN bit is cleared in “ADC Write Protect Mode Register” on page 1015.
• TSON: Temperature Sensor On
0 = temperature sensor is off.
1 = temperature sensor is on.
• IBCTL: ADC Bias Current Control
Allows to adapt performance versus power consumption (See the product electrical characteristics for further details).
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – – – IBCTL
76543210
– – – TSON ––––
1015
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.20 ADC Write Protect Mode Register
Name: ADC_WPMR
Address: 0x400380E4
Access: Read-write
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x414443 (“ADC” in ASCII).
Protects the registers:
“ADC Mode Register” on page 996
“ADC Channel Sequence 1 Register” on page 999
“ADC Channel Sequence 2 Register” on page 1000
“ADC Channel Enable Register” on page 1001
“ADC Channel Disable Register” on page 1002
“ADC Extended Mode Register” on page 1009
“ADC Compare Window Register” on page 1010
“ADC Channel Gain Register” on page 1011
“ADC Channel Offset Register” on page 1012
“ADC Analog Control Register” on page 1014
• WPKEY: Write Protect KEY
Should be written at value 0x414443 (“ADC” in ASCII). Writing any other value in this field aborts the write operation of the WPEN
bit. Always reads as 0.
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
1016
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.7.21 ADC Write Protect Status Register
Name: ADC_WPSR
Address: 0x400380E8
Access: Read-only
• WPVS: Write Protect Violation Status
0 = No Write Protect Violation has occurred since the last read of the ADC_WPSR register.
1 = A Write Protect Violation has occurred since the last read of the ADC_WPSR register. If this violation is an unauthorized
attempt to write a protected register, the associated violation is reported into field WPVSRC.
• WPVSRC: Write Protect Violation Source
When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has
been attempted.
Reading ADC_WPSR automatically clears all fields.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
76543210
–––––––WPVS
1017
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42. Digital-to-Analog Converter Controller (DACC)
42.1 Description
The Digital-to-Analog Converter Controller (DACC) offers up to 2 analog outputs, making it possible for the digital-to-
analog conversion to drive up to 2 independent analog lines.
The DACC supports 12-bit resolution. Data to be converted are sent in a common register for all channels. External
triggers or free running mode are configurable.
The DACC integrates a Sleep Mode and connects with a PDC channel. These features reduce both power consumption
and processor intervention.
The user can configure DACC timings, such as Startup Time and Refresh Period.
42.2 Embedded characteristics
Up to Two Independent Analog Outputs
12-bit Resolution
Individual Enable and Disable of Each Analog Channel
Hardware Trigger
External Trigger Pins
PDC Support
Possibility of DACC Timings and Current Configuration
Sleep Mode
Automatic Wake-up on Trigger and Back-to-Sleep Mode after Conversions of all Enabled Channels
Internal FIFO
1018
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.3 Block Diagram
Figure 42-1. Digital-to-Analog Converter Controller Block Diagram
42.4 Signal Description
DAC0 DAC1
AHB
Analog Cell
DAC Controller
Control
Logic Interrupt
Controller
PDC
Peripheral Bridge
APB
User
Interface
Sample & Hold
Sample & Hold
Trigger
Selection
DATRG
DAC Core
Table 42-1. DACC Pin Description
Pin Name Description
DAC0 - DAC1 Analog output channels
DATRG External triggers
1019
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.5 Product Dependencies
42.5.1 Power Management
The programmer must first enable the DAC Controller Clock in the Power Management Controller (PMC) before
using the DACC.
The DACC becomes active as soon as a conversion is requested and at least one channel is enabled. The DACC is
automatically deactivated when no channels are enabled.
For power saving options see Section 42.6.6 ”Sleep Mode”.
42.5.2 Interrupt Sources
The DACC interrupt line is connected on one of the internal sources of the interrupt controller. Using the DACC interrupt
requires the interrupt controller to be programmed first.
42.5.3 Conversion Performances
For performance and electrical characteristics of the DACC, see the product DC Characteristics section.
Table 42-2. Peripheral IDs
Instance ID
DACC 30
1020
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.6 Functional Description
42.6.1 Digital-to-Analog Conversion
The DACC uses the master clock (MCK) divided by two to perform conversions. This clock is named DACC Clock.
Once a conversion starts the DACC takes 25 clock periods to provide the analog result on the selected analog
output.
42.6.2 Conversion Results
When a conversion is completed, the resulting analog value is available at th e selected DACC channel output and the
EOC bit in the DACC Interrupt Status Register, is set.
Reading the DACC_ISR register clears the EOC bit.
42.6.3 Conversion Triggers
In free running mode, conversion starts as soon as at least one channel is enabled and data is written in the DACC
Conversion Data Register, t hen 25 DACC Clock periods later, the converted data is available at the corresponding
analog output as stated above.
In external trigger mode, the conversion waits for a rising edge on the selected trigger to begin.
Warning: Disabling the external trigger mode automatically sets the DACC in free running mode.
42.6.4 Conversion FIFO
A 4 half-word FIFO is used to handle the data to be converted.
As long as the TXRDY flag in the DACC Interrupt Status Register is active the DAC Controller is ready to accept
conversion requests by writing data into DACC Conversion Data Register. Data which cannot be converted immediately
are stored in the DACC FIFO.
When the FIFO is full or the DACC is not ready to accept conversion requests, the TXRDY flag is inactive.
The WORD field of the DACC Mode Register allows the user to switch between half-word and word transfer for writing
into the FIFO.
In half-word transfer mode only the 16 LSB of DACC_CDR data are taken into account, DACC_CDR[15:0] is stored into
the FIFO.
DACC_CDR[11:0] field is used as data and the DACC_CDR[15:12] bits are used for channel selection if the TAG field is
set in DACC_MR register.
In word transfer mode each time the DACC_CDR register is written 2 data i tems are stored in the FI FO. The first data
item sampled for conversion is DACC_CDR[15:0] and the second DACC_CDR[31:16].
Fields DACC_CDR[15:12] and DACC_CDR[31:28] are used for channel selection if the TAG field is set in DACC_MR
register.
Warning: Writing in the DACC_CDR register while TXRDY flag is inactive will corrupt FIFO data.
42.6.5 Channel Selection
There are two means by which to select the channel to perform data conversion.
By default, to select the channel where to convert the data, is to use the USER_SEL field of the DACC Mode
Register. Data requests will merely be converted to the channel selected with the USER_SEL field.
A more flexible option to select the channel for the data to be converted to is to use the tag mode, setting the TAG
field of the DACC Mode Register to 1. In this mode the 2 bits, DACC_CDR[13:12] which are otherwise unused, are
employed to select the channel in the same way as with the USER_SEL field. Finally, if the WORD field is set, the
2 bits, DACC_CDR[13:12] are used for channel selection of the first data and the 2 bits, DACC_CDR[29:28] for
channel selection of the second data.
1021
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.6.6 Sleep Mode
The DACC Sleep Mode maximizes power saving by automatically deactivating the DACC when it is not being used for
conversions.
When a start conversion request occurs, the DACC is automatically activated. As the analog cell requires a start-up time,
the logic waits during this time and starts the conversion on the selected channel. When all conversion requests are
complete, the DACC is deactivated until the next request for conversion.
A fast wake-up mode is available in the DACC Mode Register as a compromise between power saving strategy and
responsiveness. Setting the FASTW bit to 1 enables the fast wake-up mode. In fast wake-up mode the DACC is not fully
deactivated while no conversion is requested, thereby providing less power saving but faster wake-up (4 times faster).
42.6.7 DACC Timings
The DACC startup time must be defined by the user in the STARTUP field of the DACC Mode Register.
This startup time differs depending of the use of the fast wake-up mode along with sleep mode, in this case the user must
set the STARTUP time corresponding to the fast wake up and not the standard startup time.
A max speed mode is available by setting the MAXS bit to 1 in the DACC_MR register. Using this mode, the DAC
Controller no longer waits to sample the end of cycle signal coming from the DACC block to start the next conversion and
uses an internal counter instead. This mode gains 2 DACC Clock periods between each consecutive conversion.
Warning: Using this mode, the EOC interrupt of the DACC_IER register should not be used as it is 2 DACC Clock
periods late.
After 20 µs the analog voltage resulting from the converted data will start decreasing, therefore it is necessary to refresh
the channel on a regular basis to prevent this voltage loss. This is the purpose of the REFRESH field in the DACC Mode
Register where the user will define the period for the analog channels to be refreshed.
Warning: A REFRESH PERIOD field set to 0 will disable the refresh function of the DACC channels.
Figure 42-2. Conversion Sequence
MCK
Write USER_SEL
field
Selected Channel
Write DACC_CDR
DAC Channel 0
Output
DAC Channel 1
Output
EOC
Read DACC_ISR
Select Channel 0
Channel 0 Channel 1
Data 0 Data 1 Data 2
Data 0 Data 1
Data 2
Select Channel 1
None
TXRDY CDR FIFO not full
1022
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.6.8 Write Protection Registers
In order to provide security to the DACC, a write protection system has been implemented.
The write protection mode prevents the writing of certain registers. When this mode is enabled and one of the protected
registers is written, an error is generated in the DACC Write Protect Status Register and the register write request is
canceled. When a write protection error occurs, the WPROTERR flag is set and the address of the corresponding
canceled register write is available in the WPROTADRR field of the DACC Write Protect Status Register.
Due to the nature of the write protection feature, enabling and disabling the write protection mode requires the use of a
security code. Thus when enabling or disabling the write protection mode the WPKEY field of the DACC Write Protect
Mode Register must be filled with the “DAC” ASCII code (corresponding to 0x444143) otherwise the register write is
canceled.
The protected registers are:
DACC Mode Register
DACC Channel Enable Register
DACC Channel Disable Register
DACC Analog Current Register
1023
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7 Digital-to-Analog Converter (DACC) User Interface
Table 42-3. Register Mapping
Offset Register Name Access Reset
0x00 Control Register DACC_CR Write-only –
0x04 Mode Register DACC_MR Read-write 0x00000000
0x08 Reserved – – –
0x0C Reserved – – –
0x10 Channel Enable Register DACC_CHER Write-only –
0x14 Channel Disable Register DACC_CHDR Write-only –
0x18 Channel Status Register DACC_CHSR Read-only 0x00000000
0x1C Reserved – – –
0x20 Conversion Data Register DACC_CDR Write-only 0x00000000
0x24 Interrupt Enable Register DACC_IER Write-only –
0x28 Interrupt Disable Register DACC_IDR Write-only –
0x2C Interrupt Mask Register DACC_IMR Read-only 0x00000000
0x30 Interrupt Status Register DACC_ISR Read-only 0x00000000
0x94 Analog Current Register DACC_ACR Read-write 0x00000000
0xE4 Write Protect Mode register DACC_WPMR Read-write 0x00000000
0xE8 Write Protect Status register DACC_WPSR Read-only 0x00000000
... ... ... ... ...
0xEC - 0xFC Reserved – – –
1024
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.1 DACC Control Register
Name: DACC_CR
Address: 0x4003C000
Access: Write-only
• SWRST: Software Reset
0 = No effect.
1 = Resets the DACC simulating a hardware reset.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SWRST
1025
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.2 DACC Mode Register
Name: DACC_MR
Address: 0x4003C004
Access: Read-write
This register can only be written if the WPEN bit is cleared in DACC Write Protect Mode Register.
• TRGEN: Trigger Enable
• TRGSEL: Trigger Selection
• WORD: Word Transfer
31 30 29 28 27 26 25 24
– – STARTUP
23 22 21 20 19 18 17 16
– – MAXS TAG – – USER_SEL
15 14 13 12 11 10 9 8
REFRESH
76543210
– FASTWKUP SLEEP WORD TRGSEL TRGEN
Value Name Description
0 DIS External trigger mode disabled. DACC in free running mode.
1 EN External trigger mode enabled.
TRGSEL Selected TRGSEL
000External trigger
001TIO Output of the Timer Counter Channel 0
010TIO Output of the Timer Counter Channel 1
011TIO Output of the Timer Counter Channel 2
100PWM Event Line 0
101PWM Event Line 1
110Reserved
111Reserved
Value Name Description
0 HALF Half-Word transfer
1 WORD Word Transfer
1026
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• SLEEP: Sleep Mode
0 = Normal Mode: The DAC Core and reference voltage circuitry are kept ON between conversions.
After reset, the DAC is in normal mode but with the voltage reference and the DAC core off. For the first conversion, a startup time
must be defined in the STARTUP field. Note that in this mode, STARTUP time is only required once, at start up.
1 = Sleep Mode: The DAC Core and reference voltage circuitry are OFF between conversions.
• FASTWKUP: Fast Wake up Mode
0 = Normal Sleep Mode: The sleep mode is defined by the SLEEP bit.
1 = Fast Wake Up Sleep Mode: The voltage reference is ON between conversions and DAC Core is OFF.
• REFRESH: Refresh Period
Refresh Period = 1024*REFRESH/DACC Clock
• USER_SEL: User Channel Selection
• TAG: Tag Selection Mode
• MAXS: Max Speed Mode
SLEEP Selected Mode
0 Normal Mode
1 Sleep Mode
FASTWKUP Selected Mode
0 Normal Sleep Mode
1 Fast Wake up Sleep Mode
Value Name Description
0 CHANNEL0 Channel 0
1 CHANNEL1 Channel 1
Value Name Description
0 DIS Tag selection mode disabled. Using USER_SEL to select
the channel for the conversion.
1 EN Tag selection mode enabled
Value Name Description
0 NORMAL Normal Mode
1 MAXIMUM Max Speed Mode enabled
1027
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
• STARTUP: Startup Time Selection
Note: Refer to the product DAC electrical characteristics section for Startup Time value.
Value Name Description Value Name Description
0 0 0 periods of DACClock 32 2048 2048 periods of DACClock
1 8 8 periods of DACClock 33 2112 2112 periods of DACClock
2 16 16 periods of DACClock 34 2176 2176 periods of DACClock
3 24 24 periods of DACClock 35 2240 2240 periods of DACClock
4 64 64 periods of DACClock 36 2304 2304 periods of DACClock
5 80 80 periods of DACClock 37 2368 2368 periods of DACClock
6 96 96 periods of DACClock 38 2432 2432 periods of DACClock
7 112 112 periods of DACClock 39 2496 2496 periods of DACClock
8 512 512 periods of DACClock 40 2560 2560 periods of DACClock
9 576 576 periods of DACClock 41 2624 2624 periods of DACClock
10 640 640 periods of DACClock 42 2688 2688 periods of DACClock
11 704 704 periods of DACClock 43 2752 2752 periods of DACClock
12 768 768 periods of DACClock 44 2816 2816 periods of DACClock
13 832 832 periods of DACClock 45 2880 2880 periods of DACClock
14 896 896 periods of DACClock 46 2944 2944 periods of DACClock
15 960 960 periods of DACClock 47 3008 3008 periods of DACClock
16 1024 1024 periods of DACClock 48 3072 3072 periods of DACClock
17 1088 1088 periods of DACClock 49 3136 3136 periods of DACClock
18 1152 1152 periods of DACClock 50 3200 3200 periods of DACClock
19 1216 1216 periods of DACClock 51 3264 3264 periods of DACClock
20 1280 1280 periods of DACClock 52 3328 3328 periods of DACClock
21 1344 1344 periods of DACClock 53 3392 3392 periods of DACClock
22 1408 1408 periods of DACClock 54 3456 3456 periods of DACClock
23 1472 1472 periods of DACClock 55 3520 3520 periods of DACClock
24 1536 1536 periods of DACClock 56 3584 3584 periods of DACClock
25 1600 1600 periods of DACClock 57 3648 3648 periods of DACClock
26 1664 1664 periods of DACClock 58 3712 3712 periods of DACClock
27 1728 1728 periods of DACClock 59 3776 3776 periods of DACClock
28 1792 1792 periods of DACClock 60 3840 3840 periods of DACClock
29 1856 1856 periods of DACClock 61 3904 3904 periods of DACClock
30 1920 1920 periods of DACClock 62 3968 3968 periods of DACClock
31 1984 1984 periods of DACClock 63 4032 4032 periods of DACClock
1028
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.3 DACC Channel Enable Register
Name: DACC_CHER
Address: 0x4003C010
Access: Write-only
This register can only be written if the WPEN bit is cleared in DACC Write Protect Mode Register.
• CHx: Channel x Enable
0 = No effect.
1 = Enables the corresponding channel.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––CH1CH0
1029
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.4 DACC Channel Disable Register
Name: DACC_CHDR
Address: 0x4003C014
Access: Write-only
This register can only be written if the WPEN bit is cleared in DACC Write Protect Mode Register.
• CHx: Channel x Disable
0 = No effect.
1 = Disables the corresponding channel.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then re-enabled during a conversion, its
associated analog value and its corresponding EOC flags in DACC_ISR are unpredictable.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––CH1CH0
1030
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.5 DACC Channel Status Register
Name: DACC_CHSR
Address: 0x4003C018
Access: Read-only
• CHx: Channel x Status
0 = Corresponding channel is disabled.
1 = Corresponding channel is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––CH1CH0
1031
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.6 DACC Conversion Data Register
Name: DACC_CDR
Address: 0x4003C020
Access: Write-only
• DATA: Data to Convert
When the WORD bit in DACC_MR register is cleared, only DATA[15:0] is used else DATA[31:0] is used to write 2 data to be
converted.
31 30 29 28 27 26 25 24
DATA
23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8
DATA
76543210
DATA
1032
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.7 DACC Interrupt Enable Register
Name: DACC_IER
Address: 0x4003C024
Access: Write-only
• TXRDY: Transmit Ready Interrupt Enable
• EOC: End of Conversion Interrupt Enable
• ENDTX: End of Transmit Buffer Interrupt Enable
• TXBUFE: Transmit Buffer Empty Interrupt Enable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – TXBUFE ENDTX EOC TXRDY
1033
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.8 DACC Interrupt Disable Register
Name: DACC_IDR
Address: 0x4003C028
Access: Write-only
• TXRDY: Transmit Ready Interrupt Disable.
• EOC: End of Conversion Interrupt Disable
• ENDTX: End of Transmit Buffer Interrupt Disable
• TXBUFE: Transmit Buffer Empty Interrupt Disable
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – TXBUFE ENDTX EOC TXRDY
1034
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.9 DACC Interrupt Mask Register
Name: DACC_IMR
Address: 0x4003C02C
Access: Read-only
• TXRDY: Transmit Ready Interrupt Mask
• EOC: End of Conversion Interrupt Mask
• ENDTX: End of Transmit Buffer Interrupt Mask
• TXBUFE: Transmit Buffer Empty Interrupt Mask
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – TXBUFE ENDTX EOC TXRDY
1035
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.10 DACC Interrupt Status Register
Name: DACC_ISR
Address: 0x4003C030
Access: Read-only
• TXRDY: Transmit Ready Interrupt Flag
0 = DACC is not ready to accept new conversion requests.
1 = DACC is ready to accept new conversion requests.
• EOC: End of Conversion Interrupt Flag
0 = no conversion has been performed since the last DACC_ISR read.
1 = at least one conversion has been performed since the last DACC_ISR read.
• ENDTX: End of DMA Interrupt Flag
0 = the Transmit Counter Register has not reached 0 since the last write in DACC_TCR or DACC_TNCR.
1 = the Transmit Counter Register has reached 0 since the last write in DACC _TCR or DACC_TNCR
• TXBUFE: Transmit Buffer Empty
0 = the Transmit Counter Register has not reached 0 since the last write in DACC_TCR or DACC_TNCR.
1 = the Transmit Counter Register has reached 0 since the last write in DACC _TCR or DACC_TNCR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
– – – – TXBUFE ENDTX EOC TXRDY
1036
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.11 DACC Analog Current Register
Name: DACC_ACR
Address: 0x4003C094
Access: Read-write
This register can only be written if the WPEN bit is cleared in DACC Write Protect Mode Register.
• IBCTLCHx: Analog Output Current Control
Allows to adapt the slew rate of the analog output. (See the product electrical characteristics for further details.)
• IBCTLDACCORE: Bias Current Control for DAC Core
Allows to adapt performance versus power consumption. (See the product electrical characteristics for further details.)
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
– – – – – – IBCTLDACCORE
76543210
– – – – IBCTLCH1 IBCTLCH0
1037
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.12 DACC Write Protect Mode Register
Name: DACC_WPMR
Address: 0x4003C0E4
Access: Read-write
• WPEN: Write Protect Enable
0 = Disables the Write Protect if WPKEY corresponds to 0x444143 (“DAC” in ASCII).
1 = Enables the Write Protect if WPKEY corresponds to 0x444143 (“DAC” in ASCII).
The protected registers are:
DACC Mode Register
DACC Channel Enable Register
DACC Channel Disable Register
DACC Analog Current Register
• WPKEY: Write Protect KEY
This security code is needed to set/reset the WPROT bit value (see Section 42.6.8 ”Write Protection Registers” for details).
Must be filled with “DAC” ASCII code.
31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
76543210
–––––––WPEN
1038
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.7.13 DACC Write Protect Status Register
Name: DACC_WPSR
Address: 0x4003C0E8
Access: Read-only
• WPROTADDR: Write protection error address
Indicates the address of the register write request which generated the error.
• WPROTERR: Write protection error
Indicates a write protection error.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
WPROTADDR
76543210
–––––––WPROTERR
1039
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43. SAM4S Electrical Characteristics
43.1 Absolute Maximum Ratings
Table 43-1. Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or other conditions beyond those indi-
cated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature..............................-60°C to + 150°C
Voltage on Input Pins
with Respect to Ground..............................-0.3V to + 4.0V
Maximum Operating Voltage
(VDDCORE)...............................................................1.32V
Maximum Operating Voltage
(VDDIO)........................................................................4.0V
Total DC Output Current on all I/O lines
100-lead LQFP............................................................150 mA
100-ball TFBGA..........................................................150 mA
100-ball VFBGA..........................................................150 mA
64-lead LQFP..............................................................100 mA
64-lead QFN...............................................................100 mA
1040
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.2 DC Characteristics
The following characteristics are applicable to the operating temperature range: T= -40°C to 105°C, unless other-
wise specified.
Table 43-2. DC Characteristics
Symbol Parameter Conditions Min Typ Max Units
VDDCORE DC Supply Core 1.08 1.2 1.32 V
VVDDIO DC Supply I/Os (2) (3) 1.62 3.3 3.6 V
VVDDPLL PLL A, PLLB and Main
Oscillator Supply 1.08 — 1.32 V
VIL Input Low-level Voltage PA0–PA31, PB0–PB14, PC0–PC31
NRST -0.3 — [0.8V:0.3
x VVDDIO] V
VIH Input High-level Voltage PA0–PA31, PB0–PB14, PC0–PC31
NRST MIN[2.0V:0.7
x VVDDIO ] —VVDDIO
+0.3V V
VOH Output High-level
Voltage
PA0–PA31, PB0–PB9, PB12–PB14, PC0–PC31
V
VDDIO
-0.4V
——
V
VDDIO [3.0V–3.6V]
PB10–PB11
V
VDDIO
-0.15V
——
VOL Output Low-level
Voltage
PA0–PA31, PB0–PB9, PB12–PB14, PC0–PC31 —
V
——
VDDIO [3.0V–3.6V]
PB10–PB11 — — 0.15
VHys Hysteresis Voltage PA0–PA31, PB0–PB9, PB12–PB14, PC0–PC31
(Hysteresis mode enabled) 150 — — mV
IOIOH (or ISOURCE)
VDDIO [1.65V–3.6V] ; VOH = VVDDIO - 0.4
- PA14 (SPCK), PA29 (MCCK) pins
- PA[12–13], PA[26–28], PA[30–31] pins
- PA [0–3]
- Other pins(1)
VDDIO [3.0V–3.6V]
- PB[10–11]
——
-4
-4
-2
-2
-30
mA
VDDIO [1.65V–3.6V] ; VOH = VVDDIO - 0.4
- NRST ——-2
IOIOL (or ISINK)
VDDIO [1.65V–3.6V] ;VOL = 0.4V
- PA14 (SPCK), PA29 (MCCK) pins
- PA[12–13], PA[26–28], PA[30–31] pins
- PA [0–3]
- Other pins(1)
VDDIO [3.0V–3.6V]
- PB[10–11]
——
4
4
2
2
30
mA
VDDIO [1.65V–3.6V] ;VOL = 0.4V
- NRST ——2
IIL Input Low Pull_up OFF -1 — 1 μA
Pull_up ON 10 — 50
1041
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Note: 1. PA[4–11], PA[15–25], PB[0–9], PB[12–14], PC[0–31]
2. At power-up VDDIO needs to reach 0.6V before VDDIN reaches 1.0V
3. VDDIO voltage needs to be equal or below to (VDDIN voltage +0.5V)
4. The Flash programming characteristics are applicable at operating temperature range: TA = -40°C to 85°C.
IIH Input High Pull-down OFF -1 — 1 μA
Pull-down ON 10 — 50
RPULLUP Pull-up Resistor PA0–PA31, PB0–PB14, PC0–PC31
NRST 70 100 130 kΩ
RPULLDO
WN Pull-down Resistor PA0–PA31, PB0–PB14, PC0–PC31
NRST 70 100 130 kΩ
RODT On-die Series
Termination Resistor PA4–PA31, PB0–PB9, PB12–PB14, PC0–PC31
PA0-PA3 —36
18 Ω
ICC Flash Active Current on
VDDCORE
Random 144-bit Read @ 25°C :
Maximum read frequency onto VDDCORE =
1.2V, VDDIO =3.3V —1625
mA
Random 72-bit Read @ 25°C:
Maximum read frequency onto VDDCORE =
1.2V, VDDIO =3.3V —1018
Program (4)onto VDDCORE = 1.2V, VDDIO =
3.3V @ 25°C —35
ICC33 Flash Active Current on
VDDIO
Random 144-bit read:
Maximum read frequency onto VDDCORE =
1.2V, VDDIO =3.3V @ 25°C —316
mA
Random 72-bit read:
Maximum read frequency onto VDDCORE =
1.2V, VDDIO =3.3V @ 25°C —35
Program(4) onto VDDCORE = 1.2V, VDDIO =
3.3V @ 25°C —1015
Table 43-2. DC Characteristics (Continued)
Symbol Parameter Conditions Min Typ Max Units
1042
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Notes: 1. A 4.7μF or higher ceramic capacitor must be connected between VDDIN and the closest GND pin of the device.
This large decoupling capacitor is mandatory to reduce startup current, improving transient response and noise
rejection.
2. To ensure stability, an external 2.2μF output capacitor, CDOUT must be connected between the VDDOUT and the
closest GND pin of the device. The ESR (Equivalent Series Resistance) of the capacitor must be in the range 0.1 to
10 ohms.
Solid tantalum, and multilayer ceramic capacitors are all suitable as output capacitor.
A 100nF bypass capacitor between VDDOUT and the closest GND pin of the device helps decreasing output noise
and improves the load transient response.
3. Defined as the current needed to charge external bypass/decoupling capacitor network.
4. At power-up VDDIO needs to reach 0.6V before VDDIN reaches 1.0V
5. VDDIO voltage needs to be equal or below to (VDDIN voltage + 0.5V)
Table 43-3. 1.2V Voltage Regulator Characteristics
Symbol Parameter Conditions Min Typ Max Units
VVDDIN DC Input Voltage Range (4) (5) 1.6 3.3 3.6 V
VVDDOUT DC Output Voltage Normal Mode
Standby Mode —1.2
0—V
VACCURACY Output Voltage Accuracy ILoad = 0.8 mA to 80 mA(after trimming) -3 3 %
ILOAD
ILOAD-
START
Maximum DC Output
Current
Maximum Peak Current
during Startup
VVDDIN > 1.8V
VVDDIN ≤ 1.8V ——80
40 mA
See Note(3). — — 400 mA
DDROPOUT Dropout Voltage VVDDIN = 1.6V, ILoad = Max — 400 — mV
VLINE
VLINE-TR
Line Regulation
Transient Line Regulation
VVDDIN from 2.7V to 3.6V; ILoad MAX
V
VDDIN
from 2.7V to 3.6V; tr = tf = 5µs; I
Load
Max
—10
50
30
150 mV
VLOAD
VLOAD-TR
Load Regulation
Transient Load Regulation
VVDDIN ≥1.8V;
ILoad = 10% to 90% MAX
VVDDIN ≥1.8V;
ILoad = 10% to 90% MAX
tr=tf=5µs
—
20
50
40
150
mV
IQQuiescent Current
Normal Mode;
@ ILoad = 0 mA
@ ILoad = 80 mA
Standby Mode
—5
500 1
μA
CDIN Input Decoupling Capacitor Cf. External Capacitor Requirements (1) — 4.7 μF
CDOUT Output Decoupling
Capacitor
Cf. External Capacitor Requirements (2)
ESR
1.85
0.1
2.2 5.9
10
μF
Ohm
TON Turn-on Time CDOUT= 2.2μF, VVDDOUT reaches 1.2V (+/- 3%) — 300 — μs
TOFF Turn-off Time CDOUT= 2.2μF——40ms
1043
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Note: 1. The product is guaranteed to be functional at VTH-
Figure 43-1. Core Brownout Output Waveform
Table 43-4. Core Power Supply Brownout Detector Characteristics
Symbol Parameter Conditions Min Typ Max Units
VTH- Supply Falling Threshold(1) 0.98 1.0 1.04 V
VHYST Hysteresis — — 110 mV
VTH+ Supply Rising Threshold 0.8 1.0 1.08 V
IDDON
IDDOFF
Current Consumption on
VDDCORE
Brownout Detector enabled
Brownout Detector disabled ——24
2
µA
uA
IDD33ON
IDD33OFF
Current Consumption on
VDDIO
Brownout Detector enabled
Brownout Detector disabled ——24
2
µA
uA
Td- VTH- Detection Propagation
Time VDDCORE = VTH+ to (VTH- - 100mV) — 200 300 ns
TSTART Startup Time From disabled state to enabled state — — 300 µs
t
VDDCORE
Vth-
Vth+
BOD OUTPUT
t
td+td-
Table 43-5. VDDIO Supply Monitor
Symbol Parameter Conditions Min Typ Max Units
VTH Supply Monitor Threshold 16 selectable steps 1.6 — 3.4 V
TACCURACY Threshold Level Accuracy [-40/+105°C]-2.5 — +2.5 %
VHYST Hysteresis — 20 30 mV
IDDON
IDDOFF Current Consumption Enabled
Disabled —23
0.02 40
2µA
TSTART Startup Time From disabled state to enabled state — — 300 µs
1044
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 43-2. VDDIO Supply Monitor
Table 43-6. Threshold Selection
Digital Code Threshold Min (V) Threshold Typ (V) Threshold Max (V)
0000 1.56 1.6 1.64
0001 1.68 1.72 1.76
0010 1.79 1.84 1.89
0011 1.91 1.96 2.01
0100 2.03 2.08 2.13
0101 2.15 2.2 2.23
0110 2.26 2.32 2.38
0111 2.38 2.44 2.50
1000 2.50 2.56 2.62
1001 2.61 2.68 2.75
1010 2.73 2.8 2.87
1011 2.85 2.92 2.99
1100 2.96 3.04 3.12
1101 3.08 3.16 3.24
1110 3.20 3.28 3.36
1111 3.32 3.4 3.49
Vth
Vhyst
VDDIO
Reset
Vth +
1045
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 43-3. Zero-Power-on Reset Characteristics
Table 43-7. Zero-Power-on Reset Characteristics
Symbol Parameter Conditions Min Typ Max Units
Vth+ Threshold Voltage Rising At startup 1.45 1.53 1.59 V
Vth- Threshold Voltage Falling 1.35 1.45 1.55 V
Tres Reset Time-out Period 100 340 580 μs
Vth-
Vth+
VDDIO
Reset
1046
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.3 Power Consumption
Power consumption of the device according to the different Low Power mode capabilities (backup, wait, sleep) and
active mode.
Power consumption on power supply in different modes: backup, wait, sleep and active.
Power consumption by peripheral: calculated as the difference in current measurement after having enabled then
disabled the corresponding clock.
All power consumption values are based on characterization. Power consumption values are not covered by test
limits in production.
43.3.1 Backup Mode Current Consumption
The backup mode configuration and measurements are defined as follows.
Figure 43-4. Measurement Setup
43.3.1.1Configuration A: Embedded Slow Clock RC Oscillator Enabled
Supply Monitor on VDDIO is disabled
RTT used
BOD disabled
One WKUPx enabled
Current measurement on AMP1 (see Figure 43-4)
43.3.1.2Configuration B: 32768kHz Crystal Oscillator Enabled
Supply Monitor on VDDIO is disabled
RTT used
BOD disabled
One WKUPx enabled
Current measurement on AMP1 (see Figure 43-4)
VDDIO
VDDOUT
VDDCORE
VDDIN Voltage
Regulator
VDDPLL
3.3V
AMP1
Table 43-8. Power Consumption for Backup Mode (SAM4S16/S8 rev A)
Backup
Total Consumption Typical value
@25°CMaximum Value
@85°CMaximum Value
@105°C Unit
Conditions (AMP1)
Configuration A (AMP1)
Configuration B (AMP1)
Configuration A (AMP1)
Configuration A
VDDIO = 3.6V
VDDIO = 3.3V
VDDIO = 3.0V
VDDIO = 2.5V
VDDIO = 1.8V
2.7
2.0
1.8
1.5
1
2.5
1.8
1.7
1.4
0.9
14.0
13.0
12.0
10.5
8.8
24.3
NA
NA
NA
NA
µA
1047
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.3.2 Sleep and Wait Mode Current Consumption
The wait mode and sleep mode configuration and measurements are defined below.
Figure 43-5. Measurement Setup for Sleep Mode
43.3.2.1Sleep Mode
Core clock off
VDDIO=VDDIN=3.3V
Master clock (MCK) running at various frequencies with PLLA or the fast RC oscillator
Fast start-up through WKUP0–15 pins
Current measurement as shown in Figure 43-5
All peripheral clocks deactivated
Temperature = 25°C
Table 43-10 shows the current consumption in typical conditions.
Table 43-9. Power Consumption for Backup Mode (SAM4SD32/SD16/SA16 rev A)
Backup
Total Consumption Typical value
@25°CMaximum Value
@85°CMaximum Value
@105°C Unit
Conditions (AMP1)
Configuration A (AMP1)
Configuration B (AMP1)
Configuration A (AMP1)
Configuration A Unit
VDDIO = 3.6V
VDDIO = 3.3V
VDDIO = 3.0V
VDDIO = 2.5V
VDDIO = 1.8V
2.1
1.8
1.7
1.3
0.9
2.0
1.8
1.6
1.3
0.9
15.2
14.6
13.4
11.8
10.8
25.9
NA
NA
NA
NA
µA
VDDIO
VDDOUT
VDDCORE
VDDIN Voltage
Regulator
VDDPLL
3.3V
AMP1
AMP2
1048
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 43-6.
SAM4S16/S8
Current Consumption in Sleep Mode (AMP1) versus Master Clock Ranges (Condition from
Table 43-10)
Table 43-10. SAM4S16/S8 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with PLLA
Sleep Mode
Consumption Typical value
@25°C
Core Clock/MCK (MHz) VDDCORE Consumption
(AMP1) Total Consumption
(AMP2) Unit
120 8.1 9.6 mA
100 7.1 8.1 mA
84 6.0 6.8 mA
64 4.7 5.2 mA
48 3.5 3.9 mA
32 2.4 2.6 mA
24 1.8 2.0 mA
1049
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Table 43-11.
SAM4S16/S8 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with Fast RC
Sleep Mode
Consumption Typical value
@25°C
Core Clock/MCK (MHz) VDDCORE Consumption
(AMP1) Total Consumption
(AMP2) Unit
12 1.1 1.5 mA
8 0.7 1.2 mA
4 0.4 0.7 mA
2 0.3 0.7 mA
1 0.2 0.5 mA
0.5 0.2 0.4 mA
1050
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 43-7.
SAM4SD32/SD16/SA16 Typical
Current Consumption in Sleep Mode (AMP1) versus Master Clock Ranges
(Condition from Table 43-12)
Table 43-12. SAM4SD32/SD16/SA16 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with
PLLA
Sleep Mode
Consumption Typical value
@25°C
Core Clock/MCK (MHz) VDDCORE Consumption
(AMP1) Total Consumption
(AMP2) Unit
120 8.4 10.6 mA
100 7.1 8.9 mA
84 6.0 7.5 mA
64 4.6 5.8 mA
48 3.5 4.4 mA
32 2.4 3.1 mA
24 1.8 2.4 mA
1051
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.3.2.2Wait Mode
Figure 43-8. Measurement Setup for Wait Mode
VDDIO = VDDIN = 3.6V
Core clock and master clock stopped
Current measurement as shown in the above figure
BOD disabled
All peripheral clocks deactivated
Table 43-14 gives current consumption in typical conditions.
Table 43-13.
SAM4SD32/SD16/SA16 Typical Sleep Mode Current Consumption versus Master Clock (MCK) Variation with
FAST RC
Sleep Mode
Consumption Typical value
@25°C
Core Clock/MCK (MHz) VDDCORE Consumption
(AMP1) Total Consumption
(AMP2) Unit
12 1.1 1.8 mA
8 0.8 1.2 mA
4 0.4 0.7 mA
2 0.3 0.7 mA
1 0.2 0.5 mA
0.5 0.2 0.5 mA
VDDIO
VDDOUT
VDDCORE
VDDIN Voltage
Regulator
VDDPLL
3.3V
AMP1
AMP2
1052
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.3.3 Active Mode Power Consumption
The active mode configuration and measurements are defined as follows:
VDDIO = VDDIN = 3.3V
VDDCORE = 1.2V (internal voltage regulator used)
TA = 25°C
Application running from Flash memory with128-bit access mode
All peripheral clocks are deactivated.
Master Clock (MCK) running at various frequencies with PLLA or the fast RC oscillator.
Current measurement on AMP1 (VDDCORE) and total current on AMP2
Table 43-14. SAM4S16/S8 Typical Current Consumption in Wait Mode
Wait Mode
Consumption Typical value
@25°C
Maximum
Value
@85°C
Maximum
Value
@105°C
Conditions
VDDOUT
Consumption
(AMP1)
Total
Consumption
(AMP2)
Total
Consumption
(AMP2)
Total
Consumption
(AMP2 Unit
See Figure 43-8 on page 1051
There is no activity on the I/Os of the
device. With the Flash in standby mode 20.5 32.7 484 929 μA
See Figure 43-8 on page 1051
There is no activity on the I/Os of the
device. With the Flash in deep power
down mode
20.5 27.8 479 918 μA
Table 43-15. SAM4SD32/SD16/SA16 Typical Current Consumption in Wait Mode
Wait Mode
Consumption Typical value
@25°C
Maximum
Value
@85°C
Maximum
Value
@105°C
Conditions
VDDOUT
Consumption
(AMP1)
Total
Consumption
(AMP2)
Total
Consumption
(AMP2
Total
Consumption
(AMP2 Unit
See Figure 43-8 on page 1051
There is no activity on the I/Os of the
device. With the Flash in standby mode NA 42.1 772 1200 μA
See Figure 43-8 on page 1051
There is no activity on the I/Os of the
device. With the Flash in deep power
down mode
NA 35.3 760 1110 μA
1053
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 43-9. Active Mode Measurement Setup
Tables below give Active Mode current consumption in typical conditions.
VDDCORE at 1.2V
Temperature = 25°C
43.3.3.1SAM4S16/S8 Active Power Consumption
Note: 1. Flash Wait State (FWS) in EEFC_FMR adjusted versus core frequency
VDDIO
VDDOUT
VDDCORE
VDDIN Voltage
Regulator
VDDPLL
3.3V
AMP1
AMP2
Table 43-16. SAM4S16/S8 Active Power Consumption with VDDCORE @ 1.2V Running from Flash Memory or SRAM
Core Clock (MHz)
CoreMark
Unit128-bit Flash access(1) 64-bit Flash access(1) SRAM
AMP1 AMP2 AMP1 AMP2
mA
120 24.9 28.8 18 21.4 19.6
100 21.9 25.4 16.3 19.5 16.5
84 18.5 21.4 13.8 16.6 13.9
64 15.0 17.6 11.4 13.9 10.7
48 11.9 14.3 9.6 11.8 8
32 8.1 9.9 7.4 9.3 5.4
24 6.0 7.7 5.8 7.5 4.1
12 3.4 6.1 3.2 6.0 2
8 2.3 4.5 2.2 4.5 1.2
4 1.2 2.6 1.2 2.9 1.2
2 0.7 1.9 0.7 2.0 0.7
1 0.4 1.3 0.4 1.6 NA
0.5 0.3 1.1 0.3 1.3 NA
1054
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 43-10.
SAM4S16/S8
Current Consumption in Active Mode (AMP1) versus Master Clock Ranges
1055
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.3.3.2SAM4SD32/SD16/SA16 Active Power Consumption
Notes: 1. Flash Wait State (FWS) in EEFC_FMR adjusted versus core frequency
Figure 43-11.
SAM4SD32/SD16/SA16
Current Consumption in Active Mode (AMP1) versus Master Clock Ranges
Table 43-17. SAM4SD32/SA16/SD16 Active Power Consumption with VDDCORE @ 1.2V running from Flash Memory
(IDDCORE- AMP1) or SRAM
Core Clock (MHz)
CoreMark
Unit
Cache Enable (CE) Cache Disable (CD)
SRAM
128-bit Flash
access(1) 64-bit Flash
access(1) 128-bit Flash
access(1) 64-bit Flash
access(1)
120 20.7 20.7 24.8 18.1 19.9
mA
100 17.5 17.4 21.6 16.5 16.8
84 14.7 14.7 18.3 13.9 14.2
64 11.3 11.3 14.4 11.5 10.9
48 8.5 8.5 11.3 9.4 8.3
32 5.7 5.7 8.0 7.1 5.6
24 4.3 4.3 6.3 5.9 4.2
12 2.5 2.5 3.5 3.3 1.9
8 1.7 1.7 2.4 2.3 1.7
4 0.9 0.9 1.2 1.2 0.7
2 0.5 0.5 0.7 0.7 0.5
1 0.4 0.4 0.5 0.5 0.4
0.5 0.3 0.3 0.3 0.3 0.3
1056
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.3.4 Peripheral Power Consumption in Active Mode
Note: 1. VDDIO = 3.3V, TA = 25°C
Table 43-18. Typical Power Consumption on VDDCORE(1)
Peripheral Consumption
VDDCORE 1.08V Consumption
VDDCORE 1.2V Consumption
VDDCORE 1.32V Unit
PIO Controller A (PIOA) 4.2 4.7 5.3
μA/MHz
PIO Controller B (PIOB) 1.2 1.4 1.5
PIO Controller C (PIOC) 2.6 3.0 3.2
UART 3.8 4.2 4.6
USART 5.6 6.2 7.0
PWM 10.2 11.5 12.5
TWI 4.0 4.4 5.0
SPI 4.2 4.7 5.1
Timer Counter (TCx) 4.2 4.7 5.2
ADC 2.9 3.3 3.6
DACC 2.7 3.1 3.4
ACC 0.4 0.5 0.6
HSMCI 5.5 6.1 6.8
CRCCU 0.2 0.3 0.3
SMC 1.9 2.1 2.3
SSC 4.9 5.4 6.2
UDP 4.7 5.2 5.8
1057
SAM4S [DATASHEET]
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43.4 Oscillator Characteristics
43.4.1 32 kHz RC Oscillator Characteristics
43.4.2 4/8/12 MHz RC Oscillators Characteristics
Notes: 1. Frequency range can be configured in the Supply Controller registers
2. Not trimmed from factory
3. After trimming from factory
The 4/8/12 MHz Fast RC oscillator is calibrated in production. This calibration can be read through the Get CALIB bit command
(refer to the EEFC section) and the frequency can be trimmed by software through the PMC.
Table 43-19. 32 kHz RC Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
RC Oscillator Frequency 20 32 44 kHz
Frequency Supply Dependency -3 3 %/V
Frequency Temperature Dependency Over temperature range (-40°C/
+105°C) versus 25°C -7 — 7 %
Duty Duty Cycle 45 50 55 %
TON Startup Time — — 100 μs
IDDON Current Consumption
After startup time
Temp. range = -40°C to +125°C
Typical consumption at 2.2V
supply and Temp = 25°C
— 540 860 nA
Table 43-20. 4/8/12 MHz RC Oscillators Characteristics
Symbol Parameter Conditions Min Typ Max Unit
FRange RC Oscillator Frequency Range (1) 4 12 MHz
ACC44 MHz Total Accuracy -40°C<Temp<+105°C
4 MHz output selected (1)(2) — — ±30 %
ACC88 MHz Total Accuracy
-40°C<Temp<+105°C
8 MHz output selected (1)(2) — — ±30 %
-40°C<Temp<+105°C
8 MHz output selected (1)(3) —— ±5
ACC12 12 MHz Total Accuracy
-40°C<Temp<+105°C
12 MHz output selected (1)(2) — — ±30 %
-40°C<Temp<+105°C
12MHz output selected (1)(3) —— ±5
Frequency Deviation versus
Trimming Code 8 MHz
12 MHz —47
64 — kHz/trimming code
Duty Duty Cycle 45 50 55 %
TON Startup Time — — 10 μs
IDDON Active Current Consumption(2) 4 MHz
8 MHz
12 MHz —50
65
82
75
95
118
μA
1058
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.4.3 32.768 kHz Crystal Oscillator Characteristics
Note: 1. RS is the series resistor.
CLEXT = 2x(CCRYSTAL – Cpara – CPCB).
Where CPCB is the capacitance of the printed circuit board (PCB) track layout from the crystal to the SAM4 pin.
43.4.4 32.768 kHz Crystal Characteristics
Table 43-21. 32.768 kHz Crystal Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Freq Operating Frequency Normal mode with crystal 32.768 kHz
Supply Ripple Voltage (on VDDIO) Rms value, 10 kHz to 10 MHz 30 mV
Duty Cycle 40 50 60 %
Startup Time
Rs < 50 KΩ
Rs < 100 KΩ
(1)
Ccrystal = 12.5 pF
Ccrystal = 6 pF
Ccrystal = 12.5 pF
Ccrystal = 6 pF
——
900
300
1200
500
ms
Iddon Current Consumption
Rs < 50 KΩ
Rs < 100 KΩ
(1)
Ccrystal = 12.5 pF
Ccrystal = 6 pF
Ccrystal = 12.5 pF
Ccrystal = 6 pF
—
550
380
820
530
1150
980
1600
1350
nA
PON Drive Level — — 0.1 μW
RfInternal Resistor Between XIN32 and XOUT32 — 10 MΩ
CLEXT Maximum External Capacitor
on XIN32 and XOUT32 — — 20 pF
Cpara Internal Parasitic Capacitance 0.6 0.7 0.8 pF
XIN32 XOUT32
CLEXT
CLEXT
SAM4
Table 43-22. Crystal Characteristics
Symbol Parameter Conditions Min Typ Max Unit
ESR Equivalent Series Resistor (RS) Crystal @ 32.768 kHz — 50 100 KΩ
CMMotional Capacitance Crystal @ 32.768 kHz 0.6 — 3 fF
CSHUNT Shunt Capacitance Crystal @ 32.768 kHz 0.6 — 2 pF
1059
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.4.5 3 to 20 MHz Crystal Oscillator Characteristics
Notes: 1. RS is the series resistor
2. Rs = 100–200 Ohms; Cs = 2.0–2.5 pF; Cm = 2–1.5 fF(typ, worst case) using 1 KΩ serial resistor on XOUT.
3. Rs = 50–100 Ohms; Cs = 2.0–2.5 pF; Cm = 4–3 fF(typ, worst case).
4. Rs = 25–50 Ohms; Cs = 2.5–3.0 pF; Cm = 7–5 fF (typ, worst case).
5. Rs = 20–50 Ohms; Cs = 3.2–4.0 pF; Cm = 10–8 fF(typ, worst case).
CLEXT = 2 x (CCRYSTAL – CL – CPCB).
Where CPCB is the capacitance of the printed circuit board (PCB) track layout from the crystal to the SAM4 pin.
Table 43-23. 3 to 20 MHz Crystal Oscillator Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Freq Operating Frequency Normal mode with crystal 3 16 20 MHz
Supply Ripple Voltage (on VDDPLL) Rms value, 10 kHz to 10 MHz — — 30 mV
Duty Cycle 40 50 60 %
TON Startup Time
3 MHz, CSHUNT = 3 pF
8 MHz, CSHUNT = 7 pF
16 MHz, CSHUNT = 7 pF with Cm = 8 fF
16 MHz, CSHUNT = 7 pF with Cm = 1.6 fF
20 MHz, CSHUNT = 7 pF
——
14.5
4
1.4
2.5
1
ms
IDD_ON Current Consumption
(on VDDIO)
3 MHz(2)
8 MHz(3)
16 MHz(4)
20 MHz(5)
—
230
300
390
450
350
400
470
560
μA
PON Drive Level 3 MHz
8 MHz
16 MHz, 20 MHz —— 15
30
50
μW
RfInternal Resistor Between XIN and XOUT — 0.5 — MΩ
CLEXT Maximum External Capacitor
on XIN and XOUT — — 17 pF
CLInternal Equivalent Load Capacitance Integrated load capacitance
(XIN and XOUT in series) 7.5 9.5 10.5 pF
XIN XOUT
C
LEXT
C
L
C
LEXT
C
Crystal
SAM4
R = 1K if Crystal Frequency
is lower than 8 MHz
1060
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.4.6 3 to 20 MHz Crystal Characteristics
43.4.7 3 to 20 MHz XIN Clock Input Characteristics in Bypass Mode
Note: 1. These characteristics apply only when the 3–20 MHz XTAL Oscillator is in bypass mode.
Table 43-24. Crystal Characteristics
Symbol Parameter Conditions Min Typ Max Unit
ESR Equivalent Series Resistor (Rs)
Fundamental @ 3 MHz
Fundamental @ 8 MHz
Fundamental @ 12 MHz
Fundamental @ 16 MHz
Fundamental @ 20 MHz
——
200
100
80
80
50
Ω
CMMotional Capacitance — — 8 fF
CSHUNT Shunt Capacitance — — 7 pF
Table 43-25. XIN Clock Electrical Characteristics (In Bypass Mode)
Symbol Parameter Conditions Min Typ Max Units
1/(tCPXIN) XIN Clock Frequency (1) — — 50 MHz
tCPXIN XIN Clock Period (1) 20 — — ns
tCHXIN XIN Clock High Half-period (1) 8——ns
tCLXIN XIN Clock Low Half-period (1) 8——ns
tCLCH Rise Time (1) 2.2 — — ns
tCHCL Fall Time (1) 2.2 — — ns
VXIN_IL VXIN Input Low-level Voltage (1) -0.3 — [0.8V:0.3
x VVDDIO] V
VXIN_IH VXIN Input High-level Voltage (1) [2.0V:0.7
x VVDDIO ] —VVDDIO
+0.3V V
tCPXIN
tCPXIN
tCPXIN tCHXIN
tCLCH tCHCL
VXIN_IL
VXIN_IH
1061
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.4.8 Crystal Oscillator Design Considerations Information
43.4.8.1Choosing a Crystal
When choosing a crystal for the 32768 Hz Slow Clock Oscillator or for the 3–20 MHz Oscillator, several parameters must
be taken into account. Important parameters between crystal and SAM4S specifications are as follows:
Load Capacitance
Ccrystal is the equivalent capacitor value the oscillator must “show” to the crystal in order to oscillate at the
target frequency. The crystal must be chosen according to the internal load capacitance (CL) of the on-chip
oscillator. Any mismatch in the load capacitance will result in a frequency drift.
Drive Level
Crystal drive level ≥ Oscillator drive level. Having a crystal drive level number lower than the oscillator
specification may damage the crystal.
Equivalent Series Resistor (ESR)
Crystal ESR ≤ Oscillator ESR Max. Having a crystal with ESR value higher than the oscillator may cause the
oscillator to not start.
Shunt Capacitance
Max. crystal Shunt Capacitance ≤ Oscillator Shunt Capacitance (CSHUNT). Having a crystal with ESR value
higher than the oscillator may cause the oscillator to not start.
43.4.8.2Printed Circuit Board (PCB)
SAM4S oscillators are low-power oscillators requiring particular attention when designing PCB systems.
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43.5 PLLA, PLLB Characteristics
Table 43-26. Supply Voltage Phase Lock Loop Characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDPLL
Supply Voltage Range 1.08 1.2 1.32 V
Allowable Voltage Ripple RMS Value 10 kHz to 10 MHz
RMS Value > 10 MHz ——20
10 mV
Table 43-27. PLLA and PLLB Characteristics
Symbol Parameter Conditions Min Typ Max Unit
FIN Input Frequency 3 — 32 MHz
FOUT Output Frequency 80 — 240 MHz
IPLL Current Consumption
Active mode @ 80 MHz @1.2V
Active mode @ 96 MHz @1.2V
Active mode @ 160 MHz @1.2V
Active Mode @240 MHz @1.2V
—
0.94
1.2
2.1
3.34
1.2
1.5
2.5
4
mA
TSTART Settling Time — 60 150 μS
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43.6 USB Transceiver Characteristics
43.6.1 Typical Connection
For details on a typical connection, refer to the section on the USB Device Port.
43.6.2 Electrical Parameters
Table 43-28. Electrical Parameters
Symbol Parameter Conditions Min Typ Max Unit
Input Levels
VIL Low Level — — 0.8 V
VIH High Level 2.0 — — V
VDI Differential Input Sensitivity |(D+) - (D-)| 0.2 — — V
VCM Differential Input Common Mode
Range 0.8 — 2.5 V
CIN Transceiver Capacitance Capacitance to ground on each line — 9.18 pF
I Hi-Z State Data Line Leakage 0V < VIN < 3.3V -10 — +10 μA
REXT Recommended External USB
Series Resistor In series with each USB pin with ± 5 % — 27 — Ω
Output Levels
VOL Low Level Output Measured with RL of 1.425 kΩtied to
3.6V 0.0 — 0.3 V
VOH High Level Output Measured with RL of 14.25 kΩtied to
GND 2.8 — 3.6 V
VCRS Output Signal Crossover Voltage Measurement conditions described in
Figure 43-12 “USB Data Signal Rise
and Fall Times” 1.3 — 2.0 V
Consumption
IVDDIO Current Consumption Transceiver enabled in input mode
DDP = 1 and DDM = 0 — 105 200 μA
IVDDCORE Current Consumption — 80 150 μA
Pull-up Resistor
RPUI Bus Pull-up Resistor on
Upstream Port (idle bus) 0.900 — 1.575 kΩ
RPUA
Bus Pull-up Resistor on
Upstream Port (upstream port
receiving) 1.425 — 3.090 kΩ
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43.6.3 Switching Characteristics
Figure 43-12.USB Data Signal Rise and Fall Times
Table 43-29. In Full Speed
Symbol Parameter Conditions Min Typ Max Unit
tFR Transition Rise Time CLOAD = 50 pF 4 — 20 ns
tFE Transition Fall Time CLOAD = 50 pF 4 — 20 ns
tFRFM Rise/Fall Time Matching 90 — 111.11 %
10% 10%
90%
VCRS
tRtF
Differential
Data Lines
Rise Time Fall Time
Fosc = 6MHz/750kHz REXT=27 ohms
Cload
Buffer
(b)
(a)
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43.7 12-Bit ADC Characteristics
Note: Use IBCTL = 00 for Sampling Frequency below 500 kHz and IBCTL = 01 between 500 kHz and 1 MHz.
Table 43-30. Analog Power Supply Characteristics
Symbol Parameter Conditions Min Typ Max Units
VVDDIN
ADC Analog Supply 12-bit or 10-bit resolution 2.4 3.0 3.6 V
ADC Analog Supply 10-bit resolution 2.0 — 3.6 V
Max. Voltage Ripple rms value, 10 kHz to 20 MHz — — 20 mV
IVDDIN Current Consumption
Sleep Mode (Clock OFF)
Fast Wake-up Mode (Standby CLK = 20
MHz, IBCTL = 01)
Normal Mode (IBCTL = 01)
—
2
2.4
4.3
4
3.5
6
μA
mA
mA
Table 43-31. Channel Conversion Time and ADC Clock
Symbol Parameter Conditions Min Typ Max Units
fADC ADC Clock Frequency 1 — 20 MHz
tCP_ADC ADC Clock Period 50 — 1000 ns
fSSampling Frequency — 1 MHz
tSTART-UP ADC Startup Time
From OFF mode to normal mode:
- Voltage Reference OFF
- Analog Circuitry OFF
From standby mode to normal mode:
- Voltage Reference ON
- Analog Circuitry OFF
20
4
30
8
40
12
μs
tTRACKTIM Track and Hold Time See Section 43.7.1.1 “Track and Hold
Time versus Source Output
Impedance” for more details 160 — — ns
tCONV Conversion Time — 20 tCP_ADC
tcal Calibration Time — — 306 tCP_ADC
tSETTLE Settling Time Settlling time to change offset and gain 200 — — ns
Table 43-32. External Voltage Reference Input
Parameter Conditions Min Typ Max Units
ADVREF Input Voltage Range, 12-bit 2.4V < VVDDIN < 3.6V 2.4 — VDDIN V
ADVREF Input Voltage Range, 10-bit 2.0V < VVDDIN < 3.6V 2.0 — VDDIN V
ADVREF Input DC Impedance 6 8 10 kΩ
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43.7.1 Static Performance Characteristics
In the following tables, the LSB is relative to analog scale:
Single Ended (ex: ADVREF =3.0V),
Gain = 1, LSB = (3.0V / 4096) = 732 μV
Gain = 2, LSB = (1.5V / 4096) = 366 μV
Gain = 4, LSB = (750 mV / 4096) = 183 μV
Differential (ex: ADVREF =3.0V),
Gain = 0.5, LSB = (6.0V / 4096) = 1465 μV
Gain = 1, LSB = (3.0V / 4096) = 732 μV
Gain = 2, LSB = (1.5V / 4096) = 366 μV
Table 43-33. INL, DNL, 12-bit Mode, VDDIN 2.4V to 3.6V Supply Voltage Conditions
Parameter Conditions Min Typ Max Units
Resolution — 12 — bit
Integral Non-linearity (INL) Differential mode or single mode,
gain = xx -4 +/-1 4 LSB
Differential Non-linearity (DNL) Differential mode or single mode,
gain = xx -2 +/-0.5 2 LSB
Table 43-34. Gain and Error Offset, 12-bit Mode, VDDIN 2.4V to 3.6V Supply Voltage Conditions
Parameter Conditions Min Typ Max Units
Offset Error
Differential Mode,
Gain = xx -24 +/-8 24
LSB
Single Ended
Gain = 1 -16 +/-5 16
Single Ended
Gain = 2 -26 +/-8 26
Single Ended
Gain = 4 -39 +/-13 39
Gain Error, Uncalibrated Any gain and offset values -45 — 45
Gain Error, after Calibration
Single Ended or Differential Mode,
Gain ≤ 1 -12 — 12
Single Ended or Differential Mode,
Gain = 2 -22 — 22
Single Ended or Differential Mode
Gain = 4 -28 — 28
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Note: 1. Single Ended or Differential Mode, any gain values.
Note: 1. ADC Clock (FADC) = 20 MHz, Fs = 1 MHz, Fin = 127 kHz, IBCTL = 01, FFT using 1024 points or more, Frequency
band = [1 kHz, 500 kHz] – Nyquist conditions fulfilled.
Note: 1. ADC Clock (FADC )= 20 MHz, Fs = 1MHz, Fin = 127 kHz, IBCTL = 01, FFT using 1024 points or more, frequency band
= [1kHz, 500kHz] – Nyquist conditions fulfilled.
Table 43-35. Static Performance Characteristics – 10-bit Mode (1)
Parameter Conditions Min Typ Max Units
Resolution — 10 — bit
Integral Non-linearity (INL) — ±0.5 ±1 LSB
Differential Non-linearity (DNL) No missing code — ±0.5 ±1 LSB
Offset Error -10 — 10 LSB
Gain Error -7 — 7 LSB
Table 43-36. Dynamic Performance Characteristics in Single Ended and 12-bit Mode (1)
Parameter Conditions Min Typ Max Units
Signal to Noise Ratio - SNR 56 64 72 dB
Total Harmonic Distortion - THD -84 -74 -66 dB
Signal to Noise and Distortion - SINAD 55 62 71 dB
Effective Number of Bits ENOB 9 10.5 12 bit
Table 43-37. Dynamic Performance Characteristics in Differential and 12-bit Mode(1)
Parameter Conditions Min Typ Max Units
Signal to Noise Ratio - SNR 60 70 74 dB
Total Harmonic Distortion - THD -90 -80 -72 dB
Signal to Noise and Distortion - SINAD 60 68 73 dB
Effective Number of Bits ENOB 9.5 11 12 bit
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43.7.1.1Track and Hold Time versus Source Output Impedance
The following figure shows a simplified acquisition path.
Figure 43-13.Simplified Acquisition Path
During the tracking phase, the ADC needs to track the input signal during the tracking time shown below:
10-bit mode: tTRACK = 0.042 x Zsource + 160
12-bit mode: tTRACK = 0.054 x Zsource + 205
with tTRACK expressed in ns and ZSOURCE expressed in Ohms.
Two cases must be considered:
1. The calculated tracking time (tTRACK) is lower than 15 tCP_ADC.
Set TRANSFER = 1 and TRACTIM = 0.
In this case, the allowed Zsource can be computed versus the ADC frequency with the hypothesis of:
tTRACK = 15 × tCP_ADC:
Where tCP_ADC = 1/fADC.
Table 43-38. Zsource Versus ADC Frequency
fADC = ADC Clock (MHz) ZSOURCE (kOhms) for 12 bits ZSOURCE (kOhms) for 10 bits
20.00 10 14
16.00 14 19
10.67 22 30
8.00 31 41
6.40 40 52
5.33 48 63
4.57 57 74
4.00 66 85
3.56 74 97
3.20 83 108
2.91 92 119
2.67 100 130
2.46 109 141
2.29 118 152
2.13 126 164
2.00 135 175
1.00 274 353
Sample & HoldMux.
Zsource Ron
Csample
ADC
Input 12-bit
ADC
Core
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2. The calculated tracking time (tTRACK) is higher than 15 tCP_ADC.
Set TRANSFER = 1 and TRACTIM = 0.
In this case, a timer will trigger the ADC in order to set the correct sampling rate according to the track time.
The maximum possible sampling frequency will be defined by tTRACK in nanoseconds, computed by the previous formula
but with minus 15 × tCP_ADC and plus TRANSFER time.
10-bit mode: 1/fS = tTRACK - 15 × tCP_ADC + 5 tCP_ADC
12-bit mode: 1/fS = tTRACK - 15 × tCP_ADC + 5 tCP_ADC
Note: Csample and Ron are taken into account in the formulas.
Note: 1. Input voltage range can be up to VDDIN without destruction or over-consumption.
If VDDIO < VADVREF max input voltage is VDDIO.
Table 43-39. Analog Inputs
Parameter Min Typ Max Units
Input Voltage Range 0 — VADVREF
Input Leakage Current — — ±0.5 μA
Input Capacitance — — 8 pF
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43.8 12-Bit DAC Characteristics
External voltage reference for DAC is ADVREF. See the ADC voltage reference characteristics Table 43-32 on page
1065.
Note: DAC Clock (FDAC) = 5 MHz, Fs = 200kHz, IBCTL = 01.
Table 43-40. Analog Power Supply Characteristics
Symbol Parameter Conditions Min Typ Max Units
VVDDIN
Analog
Supply 2.4 3.0 3.6 V
Max. Voltage
Ripple rms value, 10 kHz to 20 MHz — — 20 mV
IVDDIN Current
Consumption
Sleep Mode( Clock OFF)
Fast Wake Up (Stanby Mode, clock ON)
Normal Mode with 1 output ON (IBCTLDACCORE = 01,
IBCTLCHx =10)
Normal Mode with 2 outputs ON (IBCTLDACCORE =01,
IBCTLCHx =10)
—2
4.3
5
3
3
5.6
6.5
μA
mA
mA
mA
Table 43-41. Channel Conversion Time and DAC Clock
Symbol Parameter Conditions Min Typ Max Units
FDAC Clock Frequency 1 — 50 MHz
TCP_DAC Clock Period — — 20 ns
FSSampling Frequency — — 2 MHz
TSTART-UP Startup Time
From Sleep Mode to Normal Mode:
- Voltage reference OFF
- DAC core OFF
From Fast Wake Up to Normal Mode:
- Voltage reference ON
- DAC core OFF
20
2.5
30
3.75
40
5
μs
TCONV Conversion Time — — 25 TCP_DAC
Table 43-42. Static Performance Characteristics
Parameter Conditions Min Typ Max Units
Resolution — 12 — bit
Integral Non-linearity (INL) 2.4V < VVDDIN <2.7V
2.7V < VVDDIN <3.6V
-6
-2 ±1
+6
+2 LSB
Differential Non-linearity (DNL) 2.4V < VVDDIN <2.7V
2.7V < VVDDIN <3.6V -2.5 ±1 +2.5 LSB
Offset Error -32 ±8 32 LSB
Gain Error -32 ±2 32 LSB
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Note: DAC Clock (FDAC) = 50 MHz, Fs = 2 MHz, Fin = 241 kHz, IBCTL = 01, FFT using 1024 points or more, Frequency
band = [10 kHz,1MHz] – Nyquist conditions fulfilled.
Table 43-43. Dynamic Performance Characteristics
Parameter Conditions Min Typ Max Units
Signal to Noise Ratio - SNR 2.4V < VVDDIN < 2.7V
2.7V < VVDDIN < 3.6V
50
62
62
70
70
74 dB
Total Harmonic Distortion - THD 2.4V < VVDDIN < 2.7V
2.7V < VVDDIN < 3.6V
-78
-80
-64
-74
-60
-72 dB
Signal to Noise and Distortion - SINAD 2.4V < VVDDIN < 2.7V
2.7V < VVDDIN < 3.6V
50
62
60
68
70
73 dB
Effective Number of Bits ENOB 2.4V < VVDDIN < 2.7V
2.7V < VVDDIN < 3.6V
8
10
10
11
12
12 bits
Table 43-44. Analog Outputs
Parameter Conditions Min Typ Max Units
Voltage Range (1/6) x
VADVREF —(5/6) x
VADVREF V
Slew Rate
Channel output current versus slew rate (IBCTL
for DAC0 or DAC1, noted IBCTLCHx)
RLOAD = 10 kΩ, 0 pF < CLOAD< 50 pF
IBCTLCHx = 00
IBCTLCHx = 01
IBCTLCHx = 10
IBCTLCHx = 11
—2.7
5.3
8
10.7
—V/μs
Output Channel Current
Consumption
No resistive load
IBCTLCHx = 00
IBCTLCHx = 01
IBCTLCHx = 10
IBCTLCHx = 11
—0.23
0.45
0.67
0.89
—mA
Settling Time RLOAD = 10 kΩ, 0 pF < CLOAD< 50 pF — — 0.5 μs
RLOAD Output load resistor 10 — — kΩ
CLOAD Output load capacitor — 30 50 pF
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43.9 Analog Comparator Characteristics
43.10 Temperature Sensor
The temperature sensor is connected to channel 15 of the ADC.
The temperature sensor provides an output voltage (VT) that is proportional to absolute temperature (PTAT). The VT
output voltage linearly varies with a temperature slope dVT/dT = 4.7 mV/°C.
The VT voltage equals 1.44V at 27°C, with a ±60 mV accuracy. The VT slope versus temperature dVT/dT = 4.7 mV/°C
only shows a ±7% slight variation over process, mismatch and supply voltage.
The user needs to calibrate it (offset calibration) at ambient temperature in order to get rid of the VT spread at ambient
temperature (±15%).
Note: 1. The value of TS only (the value do not take into account the ADC offset/gain/errors)
2. The temperature accuracy is taking account of the ADC offset error, gain error in single ended mode with Gain=1.
.
Table 43-45. Analog Comparator Characteristics
Parameter Conditions Min Typ Max Units
Voltage Range The analog comparator is supplied by
VDDIN 1.62 3.3 3.6 V
Input Voltage Range GND + 0.2 — VDDIN - 0.2 V
Input Offset Voltage — — 20 mV
Current Consumption On VDDIN
Low Power Option (ISEL = 0)
High Speed Option (ISEL = 1) —— 25
170
μA
Hysteresis HYST = 0x01 or 0x10
HYST = 0x11 —15
30 50
90 mV
Settling Time Given for overdrive > 100 mV
Low Power Option
High Speed Option —— 1
0.1
μs
Table 43-46. Temperature Sensor Characteristics
Symbol Parameter Conditions Min Typ Max Units
VTOutput Voltage T° = 27° C(1) 1.44 — V
ΔVTOutput Voltage Accuracy T° = 27° C (1) -60 — +60 mV
dVT/dT Temperature Sensitivity (Slope
Voltage versus Temperature (1) — 4.7 — mV/°C
Slope Accuracy Over temperature range [-40°C /
+105°C](1) -7 — +7 %
Temperature Accuracy(2)
After offset calibration
over temperature range [-40°C / +105°C] -6 — +6 °C
After offset calibration
over temperature range [0°C / +80°C] -5 — +5 °C
TSTART-UP Startup Time After TSON = 1 (1) —510μs
IVDDCORE Current Consumption (1) 50 70 80 μA
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43.11 AC Characteristics
43.11.1 Master Clock Characteristics
43.11.2 I/O Characteristics
Criteria used to define the maximum frequency of the I/Os:
Output duty cycle (40%-60%)
Minimum output swing: 100 mV to VDDIO - 100 mV
Minimum output swing: 100 mV to VDDIO - 100 mV
Addition of rising and falling time inferior to 75% of the period
Notes: 1. Pin Group 1 = PA14, PA29
2. Pin Group 2 = PA[4–11], PA[15–25], PA[30–31], PB[0–9], PB[12–14], PC[0–31]
3. Pin Group 3 = PA[12–13], PA[26–28], PA[30–31]
Table 43-47. Master Clock Waveform Parameters
Symbol Parameter Conditions Min Max Units
1/(tCPMCK) Master Clock Frequency VDDCORE @ 1.20V — 120 MHz
1/(tCPMCK) Master Clock Frequency VDDCORE @ 1.08V — 100 MHz
Table 43-48. I/O Characteristics
Symbol Parameter Conditions Min Max Units
FreqMax1 Pin Group 1 (1) Maximum Output Frequency 10 pF VDDIO = 1.62V — 70 MHz
30 pF VDDIO = 1.62V — 45
PulseminH1Pin Group 1 (1) High Level Pulse Width 10 pF VDDIO = 1.62V — ns
—
30 pF VDDIO = 1.62V 11 —
PulseminL1Pin Group 1 (1) Low Level Pulse Width 10 pF VDDIO = 1.62V 7.2 — ns
30 pF VDDIO = 1.62V 11 —
FreqMax2 Pin Group 2 (2)Maximum Output Frequency 10 pF VDDIO = 1.62V — 46 MHz
25 pF VDDIO = 1.62V — 23
PulseminH2Pin Group 2 (2) High Level Pulse Width 10 pF VDDIO = 1.62V 11 — ns
25 pF VDDIO = 1.62V 21.8 —
PulseminL2Pin Group 2 (2) Low Level Pulse Width 10 pF VDDIO = 1.62V 11 — ns
25 pF VDDIO = 1.62V 21.8 —
FreqMax3 Pin Group3(3) Maximum Output Frequency 10 pF VDDIO = 1.62V — 70 MHz
25 pF VDDIO = 1.62V — 35
PulseminH3Pin Group 3 (3) High Level Pulse Width 10 pF VDDIO = 1.62V 7.2 — ns
25 pF VDDIO = 1.62V 14.2 —
PulseminL3Pin Group 3 (3) Low Level Pulse Width 10 pF VDDIO = 1.62V 7.2 — ns
25 pF VDDIO = 1.62V 14.2 —
FreqMax4 Pin Group 4(4)Maximum Output Frequency 10 pF VDDIO = 1.62V — 58 MHz
25 pF VDDIO = 1.62V — 29
PulseminH4Pin Group 4(4) High Level Pulse Width 10 pF VDDIO = 1.62V 8.6 — ns
25 pF VDDIO = 1.62V 17.2 —
PulseminL4Pin Group 4(4) Low Level Pulse Width 10 pF VDDIO = 1.62V 8.6 — ns
25 pF VDDIO = 1.62V 17.2 —
FreqMax5 Pin Group 5(5)Maximum Output Frequency 25 pF VDDIO = 1.62V — 25 MHz
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4. Pin Group 4 = PA[0–3]
5. Pin Group 5 = PB[10–11]
43.11.3 SPI Characteristics
Figure 43-14.SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)
Figure 43-15.SPI Master Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)
Figure 43-16.SPI Slave Mode with (CPOL= 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)
SPCK
MISO
MOSI
SPI2
SPI0SPI1
SPCK
MISO
MOSI
SPI5
SPI3SPI4
SPCK
MISO
MOSI
SPI
6
SPI
7
SPI
8
NPCSS
SPI
12
SPI
13
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Figure 43-17.SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL = NCPHA = 1)
43.11.3.1Maximum SPI Frequency
The following formulas give maximum SPI frequency in master read and write modes and in slave read and write modes.
Master Write Mode
The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI2 (or SPI5)
timing. Since it gives a maximum frequency above the maximum pad speed (see Section 43.11.2 “I/O Characteris-
tics”), the max SPI frequency is the one from the pad.
Master Read Mode
Tvalid is the slave time response to output data after detecting an SPCK edge. For Atmel SPI DataFlash
(AT45DB642D), Tvalid (or Tv) is 12 ns Max.
In the formula above, FSPCKMax = 33.0 MHz @ VDDIO = 3.3V.
Slave Read Mode
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by setup and hold timings
SPI7/SPI8 (or SPI10/SPI11). Since this gives a frequency well above the pad limit, the limit in slave read mode is
given by SPCK pad.
Slave Write Mode
For 3.3V I/O domain and SPI6, FSPCKMax = 25 MHz. Tsetup is the setup time from the master before sampling data.
SPCK
MISO
MOSI
SPI9
SPI10 SPI11
NPCS0
SPI14
SPI15
fSPCKMax 1
SPI0orSPI3
()Tvalid
+
----------------------------------------------------------
=
fSPCKMax 1
2xS(PI6max orSPI9max
()Tsetup)+
------------------------------------------------------------------------------------------
=
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43.11.3.2SPI Timings
Notes: 1. 3.3V domain: VVDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF.
2. 1.8V domain: VVDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF.
Note that in SPI Master Mode the SAM4S does not sample the data (MISO) on the opposite edge where data clocks out (MOSI)
but the same edge is used. This is shown in Figure 43-14 and Figure 43-15.
43.11.4 HSMCI Timings
The High-speed MultiMedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the
SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1.
Table 43-49. SPI Timings
Symbol Parameter Conditions Min Max Units
SPI0MISO Setup Time before SPCK Rises (Master) 3.3V domain(1) 11.3 — ns
1.8V domain(2) 13.3 — ns
SPI1MISO Hold Time after SPCK Rises (Master) 3.3V domain(1) 0—ns
1.8V domain(2) 0—ns
SPI2SPCK Rising to MOSI Delay (Master) 3.3V domain(1) -2.0 1.9 ns
1.8V domain(2) -1.9 1.0 ns
SPI3MISO Setup Time before SPCK Falls (Master) 3.3V domain(1) 16.2 — ns
1.8V domain(2) 18.4 — ns
SPI4MISO Hold Time after SPCK Falls (Master) 3.3V domain(1) 0—ns
1.8V domain(2) 0—ns
SPI5SPCK Falling to MOSI Delay (Master) 3.3V domain(1) -7 -3.6 ns
1.8V domain(2) -6.7 -4.2 ns
SPI6SPCK Falling to MISO Delay (Slave) 3.3V domain(1) 3.4 11.1 ns
1.8V domain(2) 4.1 13.1 ns
SPI7MOSI Setup Time before SPCK Rises (Slave) 3.3V domain(1) 0—ns
1.8V domain(2) 0—ns
SPI8MOSI Hold Time after SPCK Rises (Slave) 3.3V domain(1) 1.3 — ns
1.8V domain(2) 0.9 — ns
SPI9SPCK Rising to MISO Delay (Slave) 3.3V domain(1) 3.6 11.5 ns
1.8V domain(2) 4.1 12.9 ns
SPI10 MOSI Setup Time before SPCK Falls (Slave) 3.3V domain(1) 0—ns
1.8V domain(2) 0—ns
SPI11 MOSI Hold Time after SPCK Falls (Slave) 3.3V domain(1) 0.8 — ns
1.8V domain(2) 0.9 — ns
SPI12 NPCS Setup to SPCK Rising (Slave) 3.3V domain(1) 3.3 — ns
1.8V domain(2) 3.5 — ns
SPI13 NPCS Hold after SPCK Falling (Slave) 3.3V domain(1) 0—ns
1.8V domain(2) 0—ns
SPI14 NPCS Setup to SPCK Falling (Slave) 3.3V domain(1) 4—ns
1.8V domain(2) 3.6 — ns
SPI15 NPCS Hold after SPCK Falling (Slave) 3.3V domain(1) 0—ns
1.8V domain(2) 0—ns
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43.11.5 SSC Timings
Timings are given in the following domain:
1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF
3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 30 pF
Figure 43-18.SSC Transmitter, TK and TF as Output
Figure 43-19.SSC Transmitter, TK as Input and TF as Output
Figure 43-20.SSC Transmitter, TK as Output and TF as Input
TK (CKI =1)
TF/TD
SSC0
TK (CKI =0)
TK (CKI =1)
TF/TD
SSC1
TK (CKI =0)
TK (CKI=1)
TF
SSC2SSC3
TK (CKI=0)
TD
SSC4
1078
SAM4S [DATASHEET]
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Figure 43-21.SSC Transmitter, TK and TF as Input
Figure 43-22.SSC Receiver RK and RF as Input
Figure 43-23.SSC Receiver, RK as Input and RF as Output
TK (CKI=0)
TF
SSC5SSC6
TK (CKI=1)
TD
SSC7
RK (CKI=1)
RF/RD
SSC8SSC9
RK (CKI=0)
RK (CKI=0)
RD
SSC8SSC9
RK (CKI=1)
RF
SSC10
1079
SAM4S [DATASHEET]
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Figure 43-24.SSC Receiver, RK and RF as Output
Figure 43-25.SSC Receiver, RK as Output and RF as Input
RK (CKI=0)
RD
SSC11 SSC12
RK (CKI=1)
RF
SSC13
RK (CKI=1)
RF/RD
SSC11 SSC12
RK (CKI=0)
Table 43-50. SSC Timings
Symbol Parameter Condition Min Max Units
Transmitter
SSC0TK Edge to TF/TD (TK Output, TF Output) 1.8V domain(3)
3.3V domain(4) -3
-2.6 5.4
5.0 ns
SSC1TK Edge to TF/TD (TK Input, TF Output) 1.8V domain(3)
3.3V domain(4) 4.5
3.8 16.3
13.3 ns
SSC2TF Setup Time before TK Edge (TK Output) 1.8V domain(3)
3.3V domain(4) 14.8
12.0 —ns
SSC3TF Hold Time after TK Edge (TK Output) 1.8V domain(3)
3.3V domain(4) 0—ns
SSC4(1) TK Edge to TF/TD (TK Output, TF Input) 1.8V domain(3)
3.3V domain(4) 2.6(+2*tCPMCK)(1)(4)
2.3(+2*tCPMCK)(1)(4) 5.4(+2*tCPMCK)(1)(4)
5.0(+2*tCPMCK)(1)(4) ns
SSC5TF Setup Time before TK Edge (TK Input) 1.8V domain(3)
3.3V domain(4) 0—ns
SSC6TF Hold Time after TK edge (TK Input) 1.8V domain(3)
3.3V domain(4) tCPMCK —ns
1080
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Notes: 1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive Start Delay) and START = 4, or
5 or 7(Receive Start Selection), two periods of the MCK must be added to timings.
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the
TK (or RK) edge and the signal change. The Max access timing is the time between the TK edge and the signal stabi-
lization. Figure 43-26 illustrates Min and Max accesses for SSC0. The same applies for SSC1, SSC4, and SSC7,
SSC10 and SSC13.
3. 1.8V domain: VVDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF.
4. 3.3V domain: VVDDIO from 2.85V to 3.6V, maximum external capacitor = 30 pF.
Figure 43-26.Min and Max Access Time of Output Signals
SSC7(1) TK Edge to TF/TD (TK Input, TF Input) 1.8V domain(3)
3.3V domain(4) 4.5(+3*tCPMCK)(1)(4)
3.8(+3*tCPMCK)(1)(4) 16.3(+3*tCPMCK)(1)(4)
13.3(+3*tCPMCK)(1)(4) ns
Receiver
SSC8RF/RD Setup Time before RK Edge (RK Input) 1.8V domain(3)
3.3V domain(4) 0—ns
SSC9RF/RD Hold Time after RK Edge (RK Input) 1.8V domain(3)
3.3V domain(4) tCPMCK —ns
SSC10 RK Edge to RF (RK Input) 1.8V domain(3)
3.3V domain(4) 4.7
416.1
12.8 ns
SSC11 RF/RD Setup Time before RK Edge (RK Output) 1.8V domain(3)
3.3V domain(4) 15.8 - tCPMCK
12.5- tCPMCK —ns
SSC12 RF/RD Hold Time after RK Edge (RK Output) 1.8V domain(3)
3.3V domain(4) tCPMCK - 4.3
tCPMCK - 3.6 —ns
SSC13 RK Edge to RF (RK Output) 1.8V domain(3)
3.3V domain(4) -3
-2.6 4.3
3.8 ns
Table 43-50. SSC Timings (Continued)
Symbol Parameter Condition Min Max Units
TK (CKI =0)
TF/TD
SSC0min
TK (CKI =1)
SSC0max
1081
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43.11.6 SMC Timings
Timings are given in the following domain:
1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 30 pF
3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 50 pF.
Timings are given assuming a capacitance load on data, control and address pads:
In the following tables tCPMCK is MCK period. Timing extraction
43.11.6.1Read Timings
Table 43-51. SMC Read Signals - NRD Controlled (READ_MODE = 1)
Symbol Parameter Min Max Units
VDDIO Supply 1.8V(2) 3.3V(3) 1.8V(2) 3.3V(3)
NO HOLD Settings (NRD Hold = 0)
SMC1Data Setup before NRD High 19.9 17.9 — — ns
SMC2Data Hold after NRD High 0 0 — — ns
HOLD Settings (NRD Hold ≠ 0)
SMC3Data Setup before NRD High 16.0 14.0 ——ns
SMC4Data Hold after NRD High 00——ns
HOLD or NO HOLD Settings (NRD Hold ≠ 0, NRD Hold = 0)
SMC5 A0 - A22 Valid before NRD High (NRD setup +
NRD pulse) *
tCPMCK -6.5
(NRD setup +
NRD pulse)*
tCPMCK - 6.3 ——ns
SMC6NCS Low before NRD High
(NRD setup +
NRD pulse -
NCS rd setup)
* tCPMCK - 4.5
(NRD setup +
NRD pulse -
NCS rd setup)
* tCPMCK - 5.1
——ns
SMC7NRD Pulse Width NRD pulse *
tCPMCK - 7.2 NRD pulse *
tCPMCK - 6.2 ——ns
Table 43-52. SMC Read Signals - NCS Controlled (READ_MODE = 0)
Symbol Parameter Min Max Units
VDDIO Supply 1.8V(2) 3.3V(3) 1.8V(2) 3.3V(3)
NO HOLD Settings (NCS rd Hold = 0)
SMC8Data Setup before NCS High 20.7 18.4 — — ns
SMC9Data Hold after NCS High 0 0 — — ns
HOLD Settings (NCS rd Hold ≠ 0)
SMC10 Data Setup before NCS High 16.8 14.5 — — ns
SMC11 Data Hold after NCS High 0 0 — — ns
HOLD or NO HOLD Settings (NCS rd Hold ≠ 0, NCS rd Hold = 0)
1082
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43.11.6.2Write Timings
SMC12 A0 - A22 Valid before NCS High (NCS rd setup +
NCS rd pulse)*
tCPMCK - 6.5
(NCS rd setup +
NCS rd pulse)*
tCPMCK - 6.3 ——ns
SMC13 NRD Low before NCS High
(NCS rd setup +
NCS rd pulse -
NRD setup)*
tCPMCK - 5.6
(NCS rd setup +
NCS rd pulse - NRD
setup)* tCPMCK- 5.4 ——ns
SMC14 NCS Pulse Width NCS rd pulse
length * tCPMCK -7.7 NCS rd pulse length
* tCPMCK - 6.7 ——ns
Table 43-52. SMC Read Signals - NCS Controlled (READ_MODE = 0) (Continued)
Table 43-53. SMC Write Signals - NWE Controlled (WRITE_MODE = 1)
Symbol Parameter Min Max
Units1.8V(2) 3.3V(3) 1.8V(2) 3.3V(3)
HOLD or NO HOLD Settings (NWE hold ≠ 0, NWE hold = 0)
SMC15 Data Out Valid before NWE High NWE pulse * tCPMCK
-6.9 NWE pulse *
tCPMCK - 6.7 ——ns
SMC16 NWE Pulse Width NWE pulse * tCPMCK
- 7.3 NWE pulse *
tCPMCK - 6.3 ——ns
SMC17 A0 - A22 Valid before NWE Low NWE setup * tCPMCK
- 7.2 NWE setup *
tCPMCK - 7.0 ——ns
SMC18 NCS Low before NWE High (NWE setup - NCS
rd setup + NWE
pulse) * tCPMCK -7.1
(NWE setup -
NCS rd setup +
NWE pulse) *
tCPMCK - 6.8
——ns
HOLD Settings (NWE hold ≠ 0)
SMC19
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2 - A25
Change
NWE hold * tCPMCK -
8.8 NWE hold * tCPMCK
- 6.9 ——ns
SMC20 NWE High to NCS Inactive(1) (NWE hold - NCS
wr hold)* tCPMCK -
5.2
(NWE hold - NCS
wr hold)* tCPMCK -
5.0 ——ns
NO HOLD Settings (NWE hold = 0)
SMC21
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2 - A25,
NCS change(1) 3.0 2.8 — — ns
1083
SAM4S [DATASHEET]
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Notes: 1. Hold length = total cycle duration - setup duration - pulse duration. “Hold length” is for “NCS wr hold length” or “NWE
hold length”.
2. 1.8V domain: VDDIO from 1.65 V to 1.95V, maximum external capacitor = 30pF
3. 3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 50pF
Figure 43-27.SMC Timings - NCS Controlled Read and Write
Table 43-54. SMC Write NCS Controlled (WRITE_MODE = 0)
Symbol Parameter Min Max
Units1.8V(2) 3.3V(3) 1.8V(2) 3.3V(3)
SMC22 Data Out Valid before NCS High NCS wr pulse *
tCPMCK - 6.3 NCS wr pulse *
tCPMCK - 6.2 ——ns
SMC23 NCS Pulse Width NCS wr pulse *
tCPMCK - 7.7 NCS wr pulse *
tCPMCK - 6.7 ——ns
SMC24 A0 - A22 Valid before NCS Low NCS wr setup *
tCPMCK - 6.5 NCS wr setup *
tCPMCK - 6.3 ——ns
SMC25 NWE Low before NCS High
(NCS wr setup -
NWE setup +
NCS pulse)*
tCPMCK - 5.1
(NCS wr setup -
NWE setup +
NCS pulse)*
tCPMCK - 4.9
——ns
SMC26 NCS High to Data Out, A0 - A25,
Change NCS wr hold *
tCPMCK - 10.2 NCS wr hold *
tCPMCK - 8.4 ——ns
SMC27 NCS High to NWE Inactive (NCS wr hold -
NWE hold)*
tCPMCK - 7.4
(NCS wr hold -
NWE hold)*
tCPMCK - 7.1 ——ns
NRD
NCS
DATA
NWE
NCS Controlled READ
with NO HOLD NCS Controlled READ
with HOLD NCS Controlled WRITE
SMC22 SMC26
SMC10 SMC11
SMC12
SMC9
SMC8
SMC14 SMC14 SMC23
SMC27
SMC26
A0 - A23
SMC24
SMC25
SMC12
SMC13 SMC13
1084
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Figure 43-28.SMC Timings - NRD Controlled Read and NWE Controlled Write
NRD
NCS
DATA
NWE
A0-A23
NRD Controlled READ
with NO HOLD NWE Controlled WRITE
with NO HOLD NRD Controlled READ
with HOLD NWE Controlled WRITE
with HOLD
SMC1 SMC2 SMC15
SMC21
SMC3 SMC4 SMC15 SMC19
SMC20
SMC7
SMC21
SMC16
SMC7
SMC16
SMC19
SMC21
SMC17
SMC18
SMC5 SMC5
SMC6 SMC6
SMC17
SMC18
1085
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11100E–ATARM–24-Jul-13
43.11.7 USART in SPI Mode Timings
Timings are given in the following domain:
1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF
3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF
Figure 43-29.USART SPI Master Mode
Figure 43-30.USART SPI Slave Mode: (Mode 1 or 2)
NSS
SPI0
MSB LSB
SPI1
CPOL=1
CPOL=0
MISO
MOSI
SCK
SPI5
SPI2
SPI3
SPI4
SPI4
• the MOSI line is driven by the output pin TXD
• the MISO line drives the input pin RXD
• the SCK line is driven by the output pin SCK
• the NSS line is driven by the output pin RTS
SCK
MISO
MOSI
SPI6
SPI7SPI8
NSS
SPI12 SPI13
• the MOSI line drives the input pin RXD
• the MISO line is driven by the output pin TXD
• the SCK line drives the input pin SCK
• the NSS line drives the input pin CTS
1086
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 43-31.USART SPI Slave Mode: (Mode 0 or 3)
SCK
MISO
MOSI
SPI9
SPI10 SPI11
NSS
SPI14
SPI15
1087
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.11.7.1USART SPI TImings
Notes: 1. 1.8V domain: VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF
2. 3.3V domain: VDDIO from 2.85V to 3.6V, maximum external capacitor = 40 pF
Table 43-55. USART SPI Timings
Symbol Parameter Conditions Min Max Units
Master Mode
SPI0SCK Period 1.8v domain
3.3v domain MCK/6 — ns
SPI1Input Data Setup Time 1.8v domain
3.3v domain 0.5 * MCK + 0.8
0.5 * MCK + 1.0 —ns
SPI2Input Data Hold Time 1.8v domain
3.3v domain 1.5 * MCK + 0.3
1.5 * MCK + 0.1 —ns
SPI3Chip Select Active to Serial Clock 1.8v domain
3.3v domain 1.5 * SPCK - 1.5
1.5 * SPCK - 2.1 —ns
SPI4Output Data Setup Time 1.8v domain
3.3v domain - 7.9
- 7.2 9.9
10.7 ns
SPI5Serial Clock to Chip Select Inactive 1.8v domain
3.3v domain 1 * SPCK - 4.1
1 * SPCK - 4.8 —ns
Slave Mode
SPI6SCK Falling to MISO 1.8V domain
3.3V domain 4.7
417.3
15.2 ns
SPI7MOSI Setup Time before SCK Rises 1.8V domain
3.3V domain 2 * MCK + 0.7
2 * MCK —ns
SPI8MOSI Hold Time after SCK Rises 1.8v domain
3.3v domain 0
0.1 —ns
SPI9SCK Rising to MISO 1.8v domain
3.3v domain 4.7
4.1 17.1
15.5 ns
SPI10 MOSI Setup Time before SCK Falls 1.8v domain
3.3v domain 2 * MCK + 0.7
2 * MCK + 0.6 —ns
SPI11 MOSI Hold Time after SCK Falls 1.8v domain
3.3v domain 0.2
0.1 —ns
SPI12 NPCS0 Setup to SCK Rising 1.8v domain
3.3v domain 2,5 * MCK + 0.5
2,5 * MCK —ns
SPI13 NPCS0 Hold after SCK Falling 1.8v domain
3.3v domain 1,5 * MCK + 0.2
1,5 * MCK —ns
SPI14 NPCS0 Setup to SCK Falling 1.8v domain
3.3v domain 2,5 * MCK + 0.5
2,5 * MCK + 0.3 —ns
SPI15 NPCS0 Hold after SCK Rising 1.8v domain
3.3v domain 1,5 * MCK
1,5 * MCK —ns
1088
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
43.11.8 Two-wire Serial Interface Characteristics
Table 43-56 describes the requirements for devices connected to the Two-wire Serial Bus. For timing symbols refer to Figure 43-
32.
Notes: 1. Required only for fTWCK > 100 kHz.
2. CB = capacitance of one bus line in pF. Per I2C Standard, Cb Max = 400 pF
3. The TWCK low period is defined as follows:
4. The TWCK high period is defined as follows:
5. tCP_MCK = MCK bus period.
Table 43-56. Two-wire Serial Bus Requirements
Symbol Parameter Condition Min Max Units
VIL Input Low-voltage -0.3 0.3 VVDDIO V
VIH Input High-voltage 0.7xVVDDIO VCC + 0.3 V
VHYS Hysteresis of Schmitt Trigger Inputs 0.150 — V
VOL Output Low-voltage 3 mA sink current - 0.4 V
tRRise Time for both TWD and TWCK 20 + 0.1Cb(1)(2) 300 ns
tOF Output Fall Time from VIHmin to VILmax 10 pF < Cb < 400 pF
Figure 43-32 20 + 0.1Cb(1)(2) 250 ns
Ci(1) Capacitance for each I/O Pin — 10 pF
fTWCK TWCK Clock Frequency 0 400 kHz
Rp Value of Pull-up Resistor
fTWCK ≤ 100 kHz
fTWCK > 100 kHz
tLOW Low Period of the TWCK Clock fTWCK ≤ 100 kHz (3) —µs
fTWCK > 100 kHz (3) —µs
tHIGH High Period of the TWCK Clock fTWCK ≤ 100 kHz (4) —µs
fTWCK > 100 kHz (4) —µs
tHD;STA Hold Time (repeated) START Condition fTWCK ≤ 100 kHz tHIGH —µs
fTWCK > 100 kHz tHIGH —µs
tSU;STA Set-up Time for a Repeated START Condition fTWCK ≤ 100 kHz tHIGH —µs
fTWCK > 100 kHz tHIGH —µs
tHD;DAT Data Hold Time fTWCK ≤ 100 kHz 0 3 x TCP_MCK(5) µs
fTWCK > 100 kHz 0 3 x TCP_MCK(5) µs
tSU;DAT Data Setup Time fTWCK ≤ 100 kHz tLOW - 3 x
tCP_MCK(5) —ns
fTWCK > 100 kHz tLOW - 3 x
tCP_MCK(5) —ns
tSU;STO Setup Time for STOP Condition fTWCK ≤ 100 kHz tHIGH —µs
fTWCK > 100 kHz tHIGH —µs
tHD;STA Hold Time (Repeated) START Condition fTWCK ≤ 100 kHz tHIGH —µs
fTWCK > 100 kHz tHIGH —µs
VVDDIO 0,4
V
–
3mA
------------------------------------
--
1000ns
Cb
------------------- Ω
VVDDIO 0,4V–
3mA
-------------------------------------- 300ns
Cb
----------------Ω
Tlow CLDIV(2CKDIV
×()4)+TMCK
×=
Thigh CHDIV(2CKDIV
×()4)+TMCK
×=
1089
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 43-32.Two-wire Serial Bus Timing
43.11.9 Embedded Flash Characteristics
The maximum operating frequency given in Table 43-57 is limited by the embedded Flash access time when the processor is
fetching code out of it. Table 43-57 gives the device maximum operating frequency depending on the field FWS of the MC_FMR
register. This field defines the number of wait states required to access the embedded Flash memory.
The embedded Flash is fully tested during production test. The Flash contents are not set to a known state prior to shipment.
Therefore, the Flash contents should be erased prior to programming an application.
Note: 1. Only the read operation is characterized between -40 and +105°C.
The others are characterized between -40 and +85°C.
Table 43-57. Embedded Flash Wait State
FWS Read Operations
Maximum Operating Frequency (MHz)
@105°C
VDDCORE Set at
1.08V and VDDIO
1.62V to 3.6V
VDDCORE Set at
1.08V and VDDIO
2.7V to 3.6V
VDDCORE Set at
1.2V and VDDIO
1.62V to 3.6V
VDDCORE Set at
1.2V and VDDIO
2.7V to 3.6V
0 1 cycle 16 20 17 17
1 2 cycles 33 40 34 34
2 3 cycles 50 60 52 52
3 4 cycles 67 80 69 69
4 5 cycles 84 100 87 87
5 6 cycles 100 — 104 104
tSU;STA
tLOW
tHIGH
tLOW
tof
tHD;STA tHD;DAT tSU;DAT tSU;STO
tBUF
TWCK
TWD
tr
Table 43-58. AC Flash Characteristics(1)
Parameter Conditions Min Typ Max Units
Program Cycle Time
Erase Page Mode — 10 50 ms
Erase Block Mode (by 4 Kbyte) — 50 200 ms
Erase Sector Mode — 400 950 ms
Full Chip Erase 1 MByte
512 KByte —9
5.5 18
11 s
Data Retention Not Powered or Powered — 20 — years
Endurance Write/Erase cycles per page, block or
sector @ 85°C 10k — — cycles
1090
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
44. SAM4S Mechanical Characteristics
Figure 44-1. 100-lead LQFP Package Mechanical Drawing
This package respects the recommendations of the NEMI User Group.
Table 44-1. Device and LQFP Package Maximum Weight
SAM4S 800 mg
Table 44-2. Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification e3
Table 44-3. LQFP Package Characteristics
Moisture Sensitivity Level 3
Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information.
1091
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 44-2. 100-ball TFBGA Package Drawing
This package respects the recommendations of the NEMI User Group.
Table 44-4. TFBGA Package Reference - Soldering Information (Substrate Level)
Ball Land Diameter 450 μm
Soldering Mask Opening 350 μm
Table 44-5. Device and 100-ball TFBGA Package Maximum Weight
SAM4S 141 mg
Table 44-6. 100-ball TFBGA Package Characteristics
Moisture Sensitivity Level 3
100-ball TFBGA Package Reference
JEDEC Drawing Reference MO-275-DDAC-1
JESD97 Classification e8
1092
SAM4S [DATASHEET]
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Figure 44-3. 100-ball VFBGA Package Drawing
Table 44-7. VFBGA Package Dimensions
Symbol Common Dimensions (mm)
Package: VFBGA
Body Size: X E 7.000 ± 0.100
Y D 7.000 ± 0.100
Ball Pitch: X eE 0.650
Y eD 0.650
Total Thickness: A 1.000 max
Mold Thickness: M 0.450 ref.
Substrate Thickness: S 0.210 ref.
Ball Diameter: 0.300
1093
SAM4S [DATASHEET]
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This package respects the recommendations of the NEMI User Group.
Stand Off: A1 0.160 ~ 0.260
Ball Width: b 0.270 ~ 0.370
Package Edge Tolerance: aaa 0.100
Mold Flatness: bbb 0.100
Coplanarity: ddd 0.080
Ball Offset (Package): eee 0.150
Ball Offset (Ball): fff 0.080
Ball Count: n 100
Edge Ball Center to Center: X E1 5.850
Y D1 5.850
Corner Ball Center to Package Edge: X I 0.575
Y J 0.575
Table 44-8. VFBGA Package Reference - Soldering Information (Substrate Level)
Ball Land Diameter 0.27 mm
Soldering Mask Opening 275 μm
Table 44-9. Device and 100-ball VFBGA Package Maximum Weight
SAM4S 75 mg
Table 44-10. 100-ball VFBGA Package Characteristics
Moisture Sensitivity Level 3
Table 44-11. 100-ball VFBGA Package Reference
JEDEC Drawing Reference MO-275-BBE-1
JESD97 Classification e8
Table 44-7. VFBGA Package Dimensions (Continued)
Symbol Common Dimensions (mm)
1094
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 44-4. 64-lead LQFP Package Drawing
1095
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
This package respects the recommendations of the NEMI User Group.
Table 44-12. 64-lead LQFP Package Dimensions (in mm)
Symbol
Millimeter Inch
Min Nom Max Min Nom Max
A – – 1.60 – – 0.063
A1 0.05 – 0.15 0.002 – 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
D 12.00 BSC 0.472 BSC
D1 10.00 BSC 0.383 BSC
E 12.00 BSC 0.472 BSC
E1 10.00 BSC 0.383 BSC
R2 0.08 – 0.20 0.003 – 0.008
R1 0.08 – – 0.003 – –
q 0° 3.5° 7° 0° 3.5° 7°
θ10° – – 0° – –
θ211° 12° 13° 11° 12° 13°
θ311° 12° 13° 11° 12° 13°
c 0.09 – 0.20 0.004 – 0.008
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 REF 0.039 REF
S 0.20 – – 0.008 – –
b 0.17 0.20 0.27 0.007 0.008 0.011
e 0.50 BSC. 0.020 BSC.
D2 7.50 0.285
E2 7.50 0.285
Tolerances of Form and Position
aaa 0.20 0.008
bbb 0.20 0.008
ccc 0.08 0.003
ddd 0.08 0.003
Table 44-13. Device and LQFP Package Maximum Weight
SAM4S 750 mg
Table 44-14. LQFP Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification e3
Table 44-15. LQFP and QFN Package Characteristics
Moisture Sensitivity Level 3
1096
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 44-5. 64-lead QFN Package Drawing
This package respects the recommendations of the NEMI User Group.
Table 44-16. Device and QFN Package Maximum Weight (Preliminary)
SAM4S 280 mg
Table 44-17. QFN Package Reference
JEDEC Drawing Reference MO-220
JESD97 Classification e3
Table 44-18. QFN Package Characteristics
Moisture Sensitivity Level 3
1097
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 44-6. 64-ball WLCSP Package Mechanical Drawing
Table 44-19. 64-ball WLCSP Package Dimensions (in mm)
SYMBOL COMMON DIMENSIONS
MIN. NOM. MAX.
Total Thickness A 0.455 0.494 0.533
Stand Off A1 0.17 - 0.23
Wafer Thickness A2 0.254 +/- 0.025
Body Size D 4.424 BSC
E 3.420 BSC
Ball Diameter (Size) 0.25
Ball/Bump Width b 0.23 0.26 0.29
Ball/Bump Pitch eD 0.4
eE 0.4
Ball/Bump Count n 64
1098
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 44-7. UBM Pad Installation
This package respects the recommendations of the NEMI User Group.
Edge Ball Center to Center D1 2.8 BSC
E1 2.8 BSC
Package Edge Tolerance aaa 0.03
Coplanarity (Whole Wafer) ccc 0.075
Ball/Bump Offset (Package) ddd 0.05
Ball/Bump Offset (Ball) eee 0.015
Table 44-20. WLCSP Package Reference - Soldering Information (Substrate Level)
UBM Pad (Under Bump Metallurgy) (E) 200 μm
PBO2 Opening (j) 240 μm
Table 44-21. Device and 64-ball WLCSP Package Maximum Weight
SAM4S TBD mg
Table 44-22. 64-ball WLCSP Package Characteristics
Moisture Sensitivity Level 1
Table 44-23. 64-ball WLCSP Package Reference
JEDEC Drawing Reference Not JEDEC
JESD97 Classification e1
Table 44-19. 64-ball WLCSP Package Dimensions (in mm)
SYMBOL COMMON DIMENSIONS
MIN. NOM. MAX.
1099
SAM4S [DATASHEET]
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44.1 Soldering Profile
Table 44-24 gives the recommended soldering profile from J-STD-020C.
Note: The package is certified to be backward compatible with Pb/Sn soldering profile.
A maximum of three reflow passes is allowed per component.
44.2 Packaging Resources
Land Pattern Definition.
Refer to the following IPC Standards:
IPC-7351A and IPC-782 (Generic Requirements for Surface Mount Design and Land Pattern Standards)
http://landpatterns.ipc.org/default.asp
Atmel Green and RoHS Policy and Package Material Declaration Data Sheet http://www.atmel.com/green/
Table 44-24. Soldering Profile
Profile Feature Green Package
Average Ramp-up Rate (217°C to Peak) 3°C/sec. max.
Preheat Temperature 175°C ± 25°C 180 sec. max.
Temperature Maintained Above 217°C 60 sec. to 150 sec.
Time within 5°C of Actual Peak Temperature 20 sec. to 40 sec.
Peak Temperature Range 260°C
Ramp-down Rate 6°C/sec. max.
Time 25°C to Peak Temperature 8 min. max.
1100
SAM4S [DATASHEET]
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1101
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
45. Ordering Information
Table 45-1. Ordering Codes for SAM4S Devices
Ordering Code MRL Flash
(Kbytes) SRAM
(Kbytes) Package Conditioning Package
Type Temperature
Operating Range
ATSAM4SD32CA-CU A 2*1024 160 TFBGA100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SD32CA-CUR A 2*1024 160 TFBGA100 Reel Green
ATSAM4SD32CA-CFU A 2*1024 160 VFBGA100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SD32CA-CFUR A 2*1024 160 VFBGA100 Reel Green
ATSAM4SD32CA-AU A 2*1024 160 LQFP100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SD32CA-AUR A 2*1024 160 LQFP100 Reel Green
ATSAM4SD32CA-AN A 2*1024 160 LQFP100 Tray Green Industrial
(-40°C to +105°C)
ATSAM4SD32CA-ANR A 2*1024 160 LQFP100 Reel Green
ATSAM4SD32BA-MU A 2*1024 160 QFN64 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SD32BA-MUR A 2*1024 160 QFN64 Reel Green
ATSAM4SD32BA-AU A 2*1024 160 LQFP64 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SD32BA-AUR A 2*1024 160 LQFP64 Reel Green
ATSAM4SD32BA-AN A 2*1024 160 LQFP64 Tray Green Industrial
(-40°C to +105°C)
ATSAM4SD32BA-ANR A 2*1024 160 LQFP64 Reel Green
ATSAM4SD16CA-CU A 2*512 160 TFBGA100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SD16CA-CUR A 2*512 160 TFBGA100 Reel Green
ATSAM4SD16CA-CFU A 2*512 160 VFBGA100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SD16CA-CFUR A 2*512 160 VFBGA100 Reel Green
ATSAM4SD16CA-AU A 2*512 160 LQFP100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SD16CA-AUR A 2*512 160 LQFP100 Reel Green
ATSAM4SD16CA-AN A 2*512 160 LQFP100 Tray Green Industrial
(-40°C to +105°C)
ATSAM4SD16CA-ANR A 2*512 160 LQFP100 Reel Green
ATSAM4SD16BA-MU A 2*512 160 QFN64 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SD16BA-MUR A 2*512 160 QFN64 Reel Green
ATSAM4SD16BA-AU A 2*512 160 LQFP64 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SD16BA-AUR A 2*512 160 LQFP64 Reel Green
ATSAM4SD16BA-AN A 2*512 160 LQFP64 Tray Green Industrial
(-40°C to +105°C)
ATSAM4SD16BA-ANR A 2*512 160 LQFP64 Reel Green
ATSAM4SA16CA-CU A 1024 160 TFBGA100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SA16CA-CUR A 1024 160 TFBGA100 Reel Green
ATSAM4SA16CA-CFU A 1024 160 VFBGA100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SA16CA-CFUR A 1024 160 VFBGA100 Reel Green
ATSAM4SA16CA-AU A 1024 160 LQFP100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SA16CA-AUR A 1024 160 LQFP100 Reel Green
1102
SAM4S [DATASHEET]
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ATSAM4SA16CA-AN A 1024 160 LQFP100 Tray Green Industrial
(-40°C to +105°C)
ATSAM4SA16CA-ANR A 1024 160 LQFP100 Reel Green
ATSAM4SA16BA-MU A 1024 160 QFN64 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SA16BA-MUR A 1024 160 QFN64 Reel Green
ATSAM4SA16BA-AU A 1024 160 LQFP64 Tray Green Industrial
(-40°C to +85°C)
ATSAM4SA16BA-AUR A 1024 160 LQFP64 Reel Green
ATSAM4SA16BA-AN A 1024 160 LQFP64 Tray Green Industrial
(-40°C to +105°C)
ATSAM4SA16BA-ANR A 1024 160 LQFP64 Reel Green
ATSAM4S16CA-CU A 1024 128 TFBGA100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4S16CA-CUR A 1024 128 TFBGA100 Reel Green
ATSAM4S16CA-CFU A 1024 128 VFBGA100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4S16CA-CFUR A 1024 128 VFBGA100 Reel Green
ATSAM4S16CA-AU A 1024 128 LQFP100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4S16CA-AUR A 1024 128 LQFP100 Reel Green
ATSAM4S16CA-CFN A 1024 128 VFBGA100 Tray Green Industrial
(-40°C to +105°C)
ATSAM4S16CA-CFNR A 1024 128 VFBGA100 Reel Green
ATSAM4S16CA-AN A 1024 128 LQFP100 Tray Green Industrial
(-40°C to +105°C)
ATSAM4S16CA-ANR A 1024 128 LQFP100 Reel Green
ATSAM4S16BA-MU A 1024 128 QFN64 Tray Green Industrial
(-40°C to +85°C)
ATSAM4S16BA-MUR A 1024 128 QFN64 Reel Green
ATSAM4S16BA-AU A 1024 128 LQFP64 Tray Green Industrial
(-40°C to +85°C)
ATSAM4S16BA-AUR A 1024 128 LQFP64 Reel Green
ATSAM4S16BA-UUR A 1024 128 WLCSP64 Reel Green Industrial
(-40°C to +85°C)
ATSAM4S16BA-AN A 1024 128 LQFP64 Tray Green Industrial
(-40°C to +105°C)
ATSAM4S16BA-ANR A 1024 128 LQFP64 Reel Green
ATSAM4S8CA-CU A 512 128 TFBGA100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4S8CA-CUR A 512 128 TFBGA100 Reel Green
ATSAM4S8CA-CFU A 512 128 VFBGA100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4S8CA-CFUR A 512 128 VFBGA100 Reel Green
ATSAM4S8CA-AU A 512 128 LQFP100 Tray Green Industrial
(-40°C to +85°C)
ATSAM4S8CA-AUR A 512 128 LQFP100 Reel Green
ATSAM4S8CA-CFN A 512 128 VFBGA100 Tray Green Industrial
(-40°C to +105°C)
ATSAM4S8CA-CFNR A 512 128 VFBGA100 Reel Green
ATSAM4S8CA-AN A 512 128 LQFP100 Tray Green Industrial
(-40°C to +105°C)
ATSAM4S8CA-ANR A 512 128 LQFP100 Reel Green
Table 45-1. Ordering Codes for SAM4S Devices
Ordering Code MRL Flash
(Kbytes) SRAM
(Kbytes) Package Conditioning Package
Type Temperature
Operating Range
1103
SAM4S [DATASHEET]
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ATSAM4S8BA-MU A 512 128 QFN64 Tray Green Industrial
(-40°C to +85°C)
ATSAM4S8BA-MUR A 512 128 QFN64 Reel Green
ATSAM4S8BA-AU A 512 128 LQFP64 Tray Green Industrial
(-40°C to +85°C)
ATSAM4S8BA-AUR A 512 128 LQFP64 Reel Green
ATSAM4S8BA-UUR A 512 128 WLCSP64 Reel Green Industrial
(-40°C to +85°C)
ATSAM4S8BA-AN A 512 128 LQFP64 Tray Green Industrial
(-40°C to +105°C)
ATSAM4S8BA-ANR A 512 128 LQFP64 Reel Green
Table 45-1. Ordering Codes for SAM4S Devices
Ordering Code MRL Flash
(Kbytes) SRAM
(Kbytes) Package Conditioning Package
Type Temperature
Operating Range
1104
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
1105
SAM4S [DATASHEET]
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46. Errata on SAM4S Devices
46.1 Marking
All devices are marked with the Atmel logo and the ordering code.
Additional marking is as follows:
where
“YY”: manufactory year
“WW”: manufactory week
“V”: revision
“XXXXXXXXX”: lot number
46.2 Errata SAM4SD32/SD16/SA16/S16/S8 Rev A Parts
It applies to:
SAM4SD32C (rev A) 0x29A7_0EE0
SAM4SD32B (rev A) 0x2997_0EE0
SAM4SD16C (rev A) 0x29A7_0CE0
SAM4SD16B(rev A) 0x2997_0CE0
SAM4SA16C (rev A) 0x28A7_0CE0
SAM4SA16B (rev A) 0x2897_0CE0
SAM4S16C (rev A) 0x28AC_0CE0
SAM4S16B (rev A) 0x289C_0CE0
SAM4S8C (rev A) 0x28AC_0AE0
SAM4S8B (rev A) 0x289C_0AE0
46.2.1 Flash Controller
46.2.1.1EFC: Flash Buffer not Cleared
The Write Buffer in the embedded Flash is not cleared after trying to write to a locked region. Therefore, the data that was
previously loaded into the Write Buffer would remain in the buffer while the next page write command (e.g. WP) is being
executed.
Problem Fix/Workaround
Do not do partial programming (Fill completely the Write Buffer). Note that this problem occurs only if the software tries to
write into a locked region.
46.2.1.2EFC: Code Loop Optimization Cannot Be Disabled
The EFC does not work after the buffer for loop optimization is disabled, in Flash Mode Register (EEFC_FMR) CLOE = 0.
Problem Fix/Workaround
The CLOE bit must be kept at 1.
YYWW V
XXXXXXXXX
1106
SAM4S [DATASHEET]
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46.2.2 Flash
46.2.2.1Flash: Read Error after a GPNVM or Lock Bit Writing
The sequence below leads to a bad read value.
Fail sequence is:
Read Flash @ address XXX
Programming Flash: Write GPNVM or Lock Bit instructions
Read Flash @ address XXX
Problem Fix/Workaround
A dummy read at another address needs to be included in the sequence.
Sequence is:
Read Flash @ address XXX
Programming Flash: Write GPNVM or Lock Bit instructions
Read Flash @ address YYY (dummy read)
Read Flash @ address XXX
46.2.3 Watchdog
46.2.3.1Watchdog Not Stopped in Wait Mode
When the Watchdog is enabled and the bit WAITMODE = 1 is used to enter wait mode, the watchdog is not halted. If the
time spent in Wait Mode is longer than the Watchdog time-out, the device will be reset if Watchdog reset is enabled.
Problem Fix/Workaround
When entering wait mode, the Wait For Event (WFE) instruction of the processor Cortex-M4 must be used with the
SLEEPDEEP of the System Control Register (SCB_SCR) of the Cortex-M = 0.
46.2.4 Brownout Detector
46.2.4.1Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected
In active mode or in wait mode, if the Brownout Detector is disabled (SUPC_MR: BODDIS=1) and power is lost on
VDDCORE while VDDIO is powered, the device might not be properly reset and may behave unpredictably.
Problem Fix/Workaround
When the Brownout Detector is disabled in active or in wait mode, VDDCORE always needs to be powered.
1107
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Revision History
In the tables that follow, the most recent version of the document appears first.
“rfo” indicates changes requested during document review and approval loop.
Doc. Rev.
11100E Comments Change
Request
Ref.
Introduction
Added WLCSP64 package in Section 1. “Features”, Table 1-1, “Configuration Summary”, added Figure 4-6 and
Table 4-5, “64-ball WLCSP Pinout”.
Updated Section 5.5 “Low-power Modes”. Added information on WFE.
Added 2nd paragraph in Section 6.1 “General Purpose I/O Lines”.
8620
9073
8992
RTC
Added new bullet “Safety/security features” in Section 16.2 “Embedded Characteristics”.
Last sentence added in Section 16.5.3 “Alarm”.
Added note in Section 16.5.3 “Alarm”, Section 16.6.5 “RTC Time Alarm Register” and Section 16.6.6 “RTC
Calendar Alarm Register”.
Replaced values for temperature range with a generic term in Section 16.5.7 “RTC Accurate Clock Calibration”.
Block diagram centered for readability in Section 16.3 “Block Diagram”.
8544
8900
9027
9033
rfo
PMC
Section 28.1.4.2 “Slow Clock Crystal Oscillator”, replaced “...in MOSCSEL bit of CKGR_MOR,...” with “...in
XTALSEL bit of SUPC_CR,...” in the last phrase of the 3d paragraph.
Section 28.1.4.2 “Slow Clock Crystal Oscillator”, added references on the OSCSEL bit of PMC_SR in the 3d
paragraph.
Register names in Clock Generator: Replaced “PLL_MCKR” with “PMC_MCKR” and “PLL_SR” with “PMC_SR”
in Section 28.1.5.5 “Software Sequence to Detect the Presence of Fast Crystal”
In Section 28.1.6.1 “Divider and Phase Lock Loop Programming”, 3rd bullet, replaced PMC_IER with PMC_SR.
Deleted previous 4th bullet (was useless sentence “Disable and then enable the PLL...”).
In Figure 28-3 and Section 28.1.5.3 “3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator” paragraph 5,
replaced MOSCXTCNT with MOSCXTST.
Added code example in step 1. of Section 28.2.13 “Programming Sequence”.
Corrected reset value of CKGR_MOR register in Table 28-3, “Register Mapping”.
Corrected value of PLLA(B)COUNT field description in Section 28.2.16.9 “PMC Clock Generator PLLA
Register” and Section 28.2.16.10 “PMC Clock Generator PLLB Register”.
Added a note in Section 28.2.16.8 “PMC Clock Generator Main Clock Frequency Register” and reworked a
paragraph in Section 28.1.5.2 “Fast RC Oscillator Clock Frequency Adjustment”
9069
rfo
8970
8963
8447
8564
8853
Electrical Characteristics
Changed 85°C temperatures with 105°C in the whole chapter. Added read/write characteristics temperature
information on Flash in Note (4), Table 43-2, “DC Characteristics” and Note (1), Table 43-58, “AC Flash
Characteristics(1)”. Modified Section 43.3.1 “Backup Mode Current Consumption” and Table 43-8 to Table 43-
17 with up-to-date current consumption values.
Updated Section 43.3.2.1 “Sleep Mode”.
Added Section 43.3.3.1 “SAM4S16/S8 Active Power Consumption”.
In Section 43.3.4 “Peripheral Power Consumption in Active Mode”, updated Table 43-18, “Typical Power
Consumption on VDDCORE(1)”
rfo
rfo
rfo
rfo
1108
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Mechanical Characteristics
Added Figure 44-6 and associated package dimensions and soldering tables for WLCSP64 package.
Soldering tables updated in Section 44. “SAM4S Mechanical Characteristics”.8620
rfo
Ordering Information
New ordering codes (105 °C, reel conditioning, WLCSP package) added in Table 45-1, “Ordering Codes for
SAM4S Devices”.8620, rfo
Errata
Added Section 46.2.3.1 “Watchdog Not Stopped in Wait Mode” and Section 46.2.4.1 “Unpredictable Behavior if
BOD is Disabled, VDDCORE is Lost and VDDIO is Connected”.9075
Backpage
ARMConnected® logo and corresponding text deleted. rfo
Doc. Rev.
11100E Comments Change
Request
Ref.
1109
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Doc. Rev.
11100D Comments Change
Request
Ref.
Introduction
Deleted sleep mode for fast start-up in Section 5.7 “Fast Start-up”.
Added 32 kHz trimming features in Section 1. “Features”.
Notes added in Section 8.1.3.1 “Flash Overview”, below Figure 8-3.
8763
rfo
Electrical Characteristics
In Table 43-26, added 2 lines describing CPARASTANDBY and RPARASTANDBY parameters.
In Table 43-62, Endurance line, deleted “Write/erase... @ 25°C” and 100k value.
In Table 43-62, added Write Page Mode values.
8614
8850
8860
Errata
Deleted former Chapter 45 “SAM4S Series Errata” (was only a cross-reference to Engineering Samples
Erratas), added a new detailed Section 46. “Errata on SAM4S Devices”.8645
Backpage
ARMPowered® logo replaced with ARMConnected® logo, corresponding text updated. rfo
1110
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Doc. Rev.
11100C Comments Change
Request
Ref.
Introduction
In Section 2. “Block Diagram”, USB linked to Peripheral Bridge instead of AHB Bus Matrix in Figure 2-1, Figure
2-2, Figure 2-3 and Figure 2-4.
Reference to the LPM bit removed in the whole datasheet.
Flash rails mentioned in Section 5.1 “Power Supplies”.
Section 9. “Real Time Event Management” created.
WKUP[15:0] pins added on each block diagram in Section 2. “Block Diagram” and in Table 3-1, “Signal
Description List”.
All diagrams updated with Real Time Events in Section 2. “Block Diagram”.
JTAG and PA7 pins details added in Section 6.2.1 “Serial Wire JTAG Debug Port (SWJ-DP) Pins”.
8386
8392
8406
8439
8459
8484
8547
CORTEX
Section 12.8.3 “Nested Vectored Interrupt Controller (NVIC) User Interface”, offset information for NVIC register
mapping updated in Table 12-31, “Nested Vectored Interrupt Controller (NVIC) Register Mapping”.
Section 12.9.1 “System Control Block (SCB) User Interface”, deleted lines with MMFSR, BFSR, UFSR and
updated the note in Table 12-32, “System Control Block (SCB) Register Mapping”.
Table 12-34, “System Timer (SYST) Register Mapping”: table name updated (SysTick changed to SYST).
Harmonized instructions code fonts in Section 12.6 “Cortex-M4 Instruction Set”. Fixed various typos.
8211
8343
RTT
RTC 1Hz calibrated clock feature added in Section 15.1 “Description”, Section 15.4 “Functional Description”
and in RTT_MR register, see Section 15.5.1 “Real-time Timer Mode Register”.
RTC
New bullet “Safety/security features” added in Section 16.2 “Embedded Characteristics”. 8544
WDT
Note added in Section 17.5.3 “Watchdog Timer Status Register”. 8128
SUPC
Offsets updated and SYSC_WPMR in Table 18-1, “System Controller Registers”. Section 18.5.9 “System
Controller Write Protect Mode Register” added.
Force Wake Up Pin removed from Section 18.2 “Embedded Characteristics”.
In Section 18.4.3 “Voltage Regulator Control/Backup Low Power Mode”, removed informations related to WFE
and WFI, deleted reference to 1.8V for voltage regulator.
Figure 18-1 Block Diagram updated.
8253
8263
8363, 8407
8515
EEFC
In Section 20.5.2 “EEFC Flash Command Register”, table added in FCMD bitfield, details added in table in
FARG bitfield.
Note concerning bit number limitation added in Section 20.4.3.5 “GPNVM Bit”.
8352
8390
1111
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
CMCC
Updated access condition from Write-only to Read-only in Section 22.5.4 “Cache Controller Status Register”
and Section 22.5.10 “Cache Controller Monitor Status Register”. Index bitfield size increased from 4 to 5 bits in
Section 22.5.6 “Cache Controller Maintenance Register 1”, bitfield description completed.
“0xXX - 0xFC” offset replaced with “0x38 - 0xFC” in the last row in Table 22-1, “Register Mapping”. In Figure
22-1, replaced “Cortex MPPB” with “APB Interface” in Block Diagram.
8373
rfo
CRCCU
TRWIDTH bitfield description table completed in Section 23.6.2 “Transfer Control Register”.
Updated Section 23.1 “Description” and Section 23.5.2 “CRC Calculation Unit Operation”.8303
rfo
PDC
Offset data for Register Mapping updated in Table 27-2, “Register Mapping”.
“ABP bridge” changed to “APB bridge” in Section 27.1 “Description”.7976
rfo
PMC
Section 28.1.5.5 “Software Sequence to Detect the Presence of Fast Crystal” added.
Updated CKGR_MOR register reset value to 0x0000_0008 in Section 28.2.16 “Power Management Controller
(PMC) User Interface”.
8371
8448
CHIPID
Section 29.3.1 “Chip ID Register”, in ARCH bitfield description table, rows sharing SAM3/SAM4 names
reconfigured with standalone rows for each name.
Section 29.3.1 “Chip ID Register”, in ARCH bitfield description table, various devices added or removed.
Section 29.3.1 “Chip ID Register”, in SRAMSIZ bitfield description table, replaced 1K/1Kbyte with
192K/192Kbyte for value1.
In Section 29.2 “Embedded Characteristics”, updated Table 29-1, “ATSAM4S Chip IDs Registers”.
7730
7977,
8034, 8383
8036
rfo
PIO
DSIZE bit description updated in Section 30.7.49 “PIO Parallel Capture Mode Register”.
Section 30.4.2 “External Interrupt Lines” added. Section 30.4.4 “Interrupt Generation” updated. 7705
rfo
SSC
Removed Table 30-4 in Section 31.7.1.1 “Clock Divider”.
Last line (PDC register) updated in Table 31-5, “Register Mapping”.
Reworked tables and bitfield descriptions in Section 31.9.3 “SSC Receive Clock Mode Register”, Section
31.9.4 “SSC Receive Frame Mode Register”, Section 31.9.5 “SSC Transmit Clock Mode Register”, Section
31.9.6 “SSC Transmit Frame Mode Register”.
7303
7971
8466
SPI
In Section 32.2 “Embedded Characteristics”, added the 2 first bullets, deleted the previous last bullet. 8544
Doc. Rev.
11100C Comments Change
Request
Ref.
1112
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
TWI
NVIC and AIC changed to Interrupt Controller. Section 33.10.4.5 “PDC” removed. “This bit is only used in
Master mode” removed from bitfields ENDRX, ENDTX, RXBUFF, and TXBUFE in Section 33.11.6 “TWI Status
Register”.
Figure 33-23 updated: SVREAD = 1 and first occurrence of RXRDY = 1.
Removed “20” at the end of the 1st paragraph in Section 33.1 “Description”.
Table 33-6, “Register Mapping”, replaced “0x100 - 0x124” with “0x100 - 0x128” and “Reserved for the PDC”
with “Reserved for PDC registers” in the PDC line.
Section 33.8.7 “Using the Peripheral DMA Controller (PDC)” reworked.
7844
7884
7921
7973
rfo
UART
Table 34-3, “Register Mapping”, PDC registers info for register mapping updated. 7967
USART
Section 35.7.1 “Baud Rate Generator”, replaced “or 6” with “or 6 times lower” in the last phrase. rfo
HSMCI
Phrase “not only for Write operations now” removed from NOTBUSY bitfield descriptionI in Section 37.14.12
“HSMCI Status Register”.
replaced BCNT bitfield table with the corresponding description and updated Warning note in BCNT bitfield
description in Section 37.14.7 “HSMCI Block Register”.
In Section 37.6.3 “Interrupt”, replaced references to NVIC/AIC with “interrupt controller”.
8394
8431
rfo
PWM
Typo corrected in line Timer0 in Table 38-4, “Fault Inputs”.
Replaced ‘Main OSC’ with ‘Main OSC (PMC)’ in Table 38-4, “Fault Inputs”.8438
rfo
UDP
Pull-up’ and ‘pull-down’ spelling harmonized in the whole chapter.
Added UDP_CSRx (ISOENDPT) alternate register in Section 39.7.11 “UDP Endpoint Control and Status
Register (Isochronous Endpoints)”.
7867
8414
ADC
Removed “...and EOC bit corresponding to the last converted channel” from the last phrase of the third
paragraph in Section 41.6.4 “Conversion Results”.
TRANSFER value set to 2 in TRANSFER bitfield description in Section 41.7.2 “ADC Mode Register”.
Text amended in Section 41.1 “Description”.
SLEEP and FWUP bitfield description texts in tables updated in Section 41.7.2 “ADC Mode Register”.
8357
8462
rfo
Electrical Characteristics
Whole chapter reworked to add SAM4SD32/SD16/SA16 data, various values added or updated.
Clext values changed in Table 43-24.
Configurations A and B updated in Section 43.3.1 “Backup Mode Current Consumption”.
rfo, 8435
8391
8422
Mechanical Characteristics
QFN64 package drawing and table updated in Figure 44-5. 8529
Doc. Rev.
11100C Comments Change
Request
Ref.
1113
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
.
Doc. Rev.
11100B Comments Change
Request
Ref.
Introduction
48 pins packages (SAM4S16A and SAM4S8A devices) removed.
Write Protected Registers added in “Description” on page 1.
Note related to EWP and EWPL commands added in Section 8.1.3.1 “Flash Overview” on page 31.
References to WFE instructions replaced by relevant bits precise descriptions.
Dual bank and cache memory mentioned in “Description” on page 1 and “Configuration Summary” on page 3.
Flash and SRAM memory sizes updated in “Description” on page 1 and “Configuration Summary” on page 3.
1 μA instead of 3 in “Description” on page 1, Section 5.2 on page 20 and Section 5.5.1 on page 22.
Table titles and sub-section titles updated with new devices.
New block diagram added in Figure 2-4 on page 7.
VFBGA100 package added: Figure 4-3 on page 13 and Table 4-3 on page 16 added.
Reference to CortexM3 deleted and VDDIO value added in Section 5.5.1 “Backup Mode” on page 22.
Entering Wait Mode process updated and current changed from 15 to 32 μA in Section 5.5.2 on page 22.
Added paragraph detailing mode selection with FLPM value in Section 5.5.3 on page 23.
Values added and notes updated in Table 5-1 on page 24.
Third paragraph frequency values updated in Section 6.1 on page 27.
SRAM upper address changed to 0x20400000, and EFC1 added in Figure 7-1 on page 30.
Note added in Section 8.1.3.1 “Flash Overview” on page 31.
New devices features added in Section 8.1.1 “Internal SRAM” on page 31, Section 8.1.3.1 “Flash Overview” on
page 31, Section 8.1.3.4 “Lock Regions” on page 33, Section 8.1.3.5 “Security Bit Feature” on page 34, Section
8.1.3.11 “GPNVM Bits” on page 34.
EEFC replaced by EEFC0 and EEFC1 in Table 11-1 on page 41.
‘Cortex M-4’ changed for ‘Cortex-M4’ in block diagrams: Figure 2-1 on page 4 and Figure 2-2 on page 5.
Section 5.5.4 “Low-power Mode Summary Table”, updated the list of potential wake up sources for Sleep Mode
in Table 5-1 on page 24.
Added references to S16 in the flash size description in Section 8.1.3.1 “Flash Overview”.
Section 2. “Block Diagram”, replaced “Time Counter B” by “Time Counter A” in Figure 2-1 on page 4.
Fixed the section structure for Section 5.5.3 “Sleep Mode”.
8100
8213
8225
8275
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CORTEX
FPU related instructions deleted in Table 12-13 on page 79.
Fonts style corrected for instructions code in the whole chapter.
Updated Figure 12-9 on page 88.
8252
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RSTC
Updated for dual core.
EXTRST field description updated in Section 14.5.1 “Reset Controller Control Register” on page 250.8306
8340
1114
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
RTC
In Section 16.6.2 “RTC Mode Register” on page 268, formulas associated with conditions HIGHPPM = 1 and
HIGHPPM = 0 have been swapped, text has been clarified.
In Section 16.5.7 “RTC Accurate Clock Calibration” on page 264, paragraph describing RTC clock calibration
circuitry correction updated with mention of crystal drift.
7950
7952
SUPC
References to WFE instructions deleted in Section 18.4.3 “Voltage Regulator Control/Backup Low Power
Mode” on page 290.
Supply monitor threshold values modified in Section 18.4.4 “Supply Monitor” on page 291.
SMTH bit table replaced by a cross-reference to Electrical characteristics in Section 18.5.4 “Supply Controller
Supply Monitor Mode Register” on page 299.
Typo in Section 18.5.8 “Supply Controller Status Register” on page 304 is now fixed.
“half” replaced with “first half” in Section 18.5.6 “Supply Controller Wake Up Mode Register” on page 301 and in
Section 18.4.7.2 “Low Power Debouncer Inputs” on page 295.
Figure 18-4 on page 294 modified.
Push-to-Break figure example Figure 18-6 on page 296 added, title of Figure 18-5 on page 295 modified.
“square waveform ..” changed to “duty cycle ..” in Section 18.4.7.2 “Low Power Debouncer Inputs” on page
295.
Switching time of slow crystal oscillator updated in Section 18.4.2 “Slow Clock Generator” on page 290.
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8024
8067
8064, 8082
8082
8226
8266
EEFC
Added GPNVM command line in Section • “FARG: Flash Command Argument” on page 324.
Unique identifier address changed in Section 20.4.3.8 “Unique Identifier” on page 319.
User Signature address changed in Section 20.4.3.9 “User Signature” on page 320.
Changed the System Controller base address from 0x400E0800 to 0x400E0A00 in Section 20.5 “Enhanced
Embedded Flash Controller (EEFC) User Interface” on page 321.
8076
8274
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FFPI
All references, tables, figures related to 48-bit devices cleared in this whole chapter. rfo
CMCC
New chapter.
CRCCU
Typos: CCIT802 corrected to CCITT802, CCIT16 corrected to CCITT16 in Section 23.5.1 “CRC Calculation
Unit description” on page 350 and Section 23.7.10 “CRCCU Mode Register” on page 365. TRC_RC corrected
to TR_CRC in Section 23.7.10 “CRCCU Mode Register” on page 365.
7803
SMC
“turned out” changed to “switched to output mode” in Section 26.8.4 “Write Mode” on page 400.
Removed DBW which is not required for 8-bit only in Section 26.15.4 “SMC MODE Register” on page 426.7925
8307
Doc. Rev.
11100B Comments Change
Request
Ref.
1115
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
PMC
Added a note in Section 28.2.16.7 “PMC Clock Generator Main Oscillator Register” on page 477.
Max MULA/MULB value changed from 2047 to 62 in Section 28.2.16.9 “PMC Clock Generator PLLA Register”
on page 480 and Section 28.2.16.10 “PMC Clock Generator PLLB Register” on page 481.
Step 5 in Section 28.2.13 “Programming Sequence” on page 463: Master Clock option added in CSS field.
Third paragraph added in Section 28.2.12 “Main Crystal Clock Failure Detector” on page 462. WAITMODE bit
added in Section 28.2.16.7 “PMC Clock Generator Main Oscillator Register” on page 477.
7848
8064
8170
8208
CHIPID
Table 29-1 on page 501 modified. rfo
TC
Changed TIOA1 in TIOB1 in Section 36.6.14.1 “Description” on page 775 and Section 36.6.14.4 “Position and
Rotation Measurement” on page 780.8101
PWM
Font size enlarged in Figure 38-14 on page 871.
“CMPS” replaced with “CMPM” in whole document. 7910
8021
ADC
EOCAL pin and description added in Section 41.7.12 “ADC Interrupt Status Register” on page 1007.
PDC register row added in Section 41.7 “Analog-to-Digital Converter (ADC) User Interface” on page 994.
Added comment in Section 41.7.15 “ADC Compare Window Register” on page 1010.
Features added in Section 41.2 “Embedded Characteristics” on page 981.
Comments added, and removed “offset” in Section 41.6.11 “Automatic Calibration” on page 992.
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7969
8045
8088
8133
Electrical Characteristics
Whole chapter updated. In tables, values updated, and missing values added.
Comment for flash erasing added in Section 43.11.9 “Embedded Flash Characteristics” on page 1089.
Updated conditions for VLINE-TR and VLOAD-TR in Table 43-3 on page 1042.
Removed the “ADVREF Current” row from Table 43-30 on page 1059.
Updated the “Offset Error” parameter description in Table 43-32 on page 1061.
Updated the TACCURACY parameter description in Table 43-5 on page 1043.
Updated the temperature sensor description in Section 43.10 “Temperature Sensor” on page 1072 and the
slope accuracy parameter data in Table 43-47 on page 1067.
8085, 8245
8223
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Mechanical Characteristics
48 pins packages (SAM4S16A and SAM4S8A devices) removed.
100-ball VFBGA package drawing added in Figure 44-3 on page 1092.8100
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Ordering Information
Table 45-1 on page 1096 completed with new devices and reordered. rfo
Errata
Removed the Flash Memory section.
Removed the Errata section and added references for two separate errata documents in Section 45. “Ordering
Information” on page 1096.
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Specified the preliminary status of the datasheet. rfo
Doc. Rev.
11100B Comments Change
Request
Ref.
1116
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Doc. Rev.
11100A Comments Change
Request
Ref.
First issue.
i
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4. Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 SAM4SD32/SD16/SA16/S16/S8C Package and Pinout. . . . . . . . . . . . . . . . . 12
4.2 SAM4SD32/SD16/SA16/S16/S8 Package and Pinout . . . . . . . . . . . . . . . . . . 17
5. Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 Typical Powering Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.4 Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.5 Low-power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.6 Wake-up Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.7 Fast Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6. Input/Output Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 General Purpose I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2 System I/O Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3 Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4 NRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.5 ERASE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7. Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.1 Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.2 External Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9. Real Time Event Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.1 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.2 Real Time Event Mapping List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10. System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.1 System Controller and Peripheral Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.2 Power-on-Reset, Brownout and Supply Monitor. . . . . . . . . . . . . . . . . . . . . . . 40
11. Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.1 Peripheral Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11.2 Peripheral Signal Multiplexing on I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12. ARM Cortex-M4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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12.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
12.4 Cortex-M4 Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
12.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.6 Cortex-M4 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.7 Cortex-M4 Core Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.8 Nested Vectored Interrupt Controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . . 175
12.9 System Control Block (SCB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.10 System Timer (SysTick) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
12.11 Memory Protection Unit (MPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
12.12 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
13. Debug and Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
13.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
13.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
13.3 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
13.4 Debug and Test Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
13.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
14. Reset Controller (RSTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
14.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
14.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
14.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
14.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
14.5 Reset Controller (RSTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
15. Real-time Timer (RTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
15.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
15.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
15.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
15.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
15.5 Real-time Timer (RTT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
16. Real-time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
16.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
16.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
16.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
16.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
16.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
16.6 Real-time Clock (RTC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
17. Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
17.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
17.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
17.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
17.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
17.5 Watchdog Timer (WDT) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
18. Supply Controller (SUPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
18.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
18.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
18.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
18.4 Supply Controller Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
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18.5 Supply Controller (SUPC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
19. General Purpose Backup Registers (GPBR) . . . . . . . . . . . . . . . . . 307
19.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
19.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
19.3 General Purpose Backup Registers (GPBR) User Interface. . . . . . . . . . . . . 307
20. Enhanced Embedded Flash Controller (EEFC) . . . . . . . . . . . . . . . 309
20.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
20.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
20.3 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
20.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
20.5 Enhanced Embedded Flash Controller (EEFC) User Interface. . . . . . . . . . . 321
21. Fast Flash Programming Interface (FFPI) . . . . . . . . . . . . . . . . . . . 327
21.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
21.2 Parallel Fast Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
22. Cortex M Cache Controller (CMCC) (ONLY FOR
SAM4SD32/SD16/SA16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
22.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
22.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
22.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
22.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
22.5 Cortex M Cache Controller (CMCC) User Interface . . . . . . . . . . . . . . . . . . . 337
23. Cyclic Redundancy Check Calculation Unit (CRCCU) . . . . . . . . . 349
23.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
23.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
23.3 CRCCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
23.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
23.5 CRCCU Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
23.6 Transfer Control Registers Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . 351
23.7 Cyclic Redundancy Check Calculation Unit (CRCCU) User Interface. . . . . 355
24. SAM4S Boot Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
24.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
24.2 Hardware and Software Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
24.3 Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
24.4 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
24.5 SAM-BA Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
25. Bus Matrix (MATRIX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
25.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
25.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
25.3 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
25.4 Special Bus Granting Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
25.5 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
25.6 System I/O Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
25.7 Write Protect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
25.8 Bus Matrix (MATRIX) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
26. Static Memory Controller (SMC) . . . . . . . . . . . . . . . . . . . . . . . . . . 389
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26.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
26.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
26.3 I/O Lines Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
26.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
26.5 External Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
26.6 Connection to External Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
26.7 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
26.8 Standard Read and Write Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
26.9 Scrambling/Unscrambling Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
26.10 Automatic Wait States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
26.11 Data Float Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
26.12 External Wait. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
26.13 Slow Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
26.14 Asynchronous Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
26.15 Static Memory Controller (SMC) User Interface . . . . . . . . . . . . . . . . . . . . . . 422
27. Peripheral DMA Controller (PDC) . . . . . . . . . . . . . . . . . . . . . . . . . 433
27.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
27.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
27.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
27.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
27.5 Peripheral DMA Controller (PDC) User Interface . . . . . . . . . . . . . . . . . . . . . 438
28. Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . 449
28.1 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
28.2 Power Management Controller (PMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
29. Chip Identifier (CHIPID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
29.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
29.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
29.3 Chip Identifier (CHIPID) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
30. Parallel Input/Output (PIO) Controller . . . . . . . . . . . . . . . . . . . . . . 507
30.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
30.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
30.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
30.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
30.5 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
30.6 I/O Lines Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
30.7 Parallel Input/Output Controller (PIO) User Interface . . . . . . . . . . . . . . . . . . 522
31. Synchronous Serial Controller (SSC) . . . . . . . . . . . . . . . . . . . . . . 559
31.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
31.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
31.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
31.4 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
31.5 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
31.6 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
31.7 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
31.8 SSC Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
31.9 Synchronous Serial Controller (SSC) User Interface . . . . . . . . . . . . . . . . . . 573
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11100E–ATARM–24-Jul-13
32. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . 597
32.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
32.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
32.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
32.4 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
32.5 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
32.6 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
32.7 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
32.8 Serial Peripheral Interface (SPI) User Interface . . . . . . . . . . . . . . . . . . . . . . 613
33. Two-wire Interface (TWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
33.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
33.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
33.3 List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
33.4 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
33.5 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
33.6 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
33.7 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
33.8 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
33.9 Multi-master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
33.10 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
33.11 Two-wire Interface (TWI) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
34. Universal Asynchronous Receiver Transmitter (UART) . . . . . . . . . 671
34.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
34.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
34.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
34.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
34.5 UART Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
34.6 Universal Asynchronous Receiver Transmitter (UART) User Interface . . . . 678
35. Universal Synchronous Asynchronous Receiver Transmitter
(USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
35.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
35.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
35.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
35.4 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
35.5 I/O Lines Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
35.6 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
35.7 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
35.8 Universal Synchronous Asynchronous Receiver Transmitter (USART)
User Interface 724
36. Timer Counter (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
36.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
36.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
36.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
36.4 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
36.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
36.6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
36.7 Timer Counter (TC) User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
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11100E–ATARM–24-Jul-13
37. High Speed MultiMedia Card Interface (HSMCI) . . . . . . . . . . . . . . 809
37.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
37.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
37.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
37.4 Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
37.5 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
37.6 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
37.7 Bus Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
37.8 High Speed MultiMedia Card Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
37.9 SD/SDIO Card Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
37.10 CE-ATA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
37.11 HSMCI Boot Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
37.12 HSMCI Transfer Done Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
37.13 Write Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
37.14 High Speed MultiMedia Card Interface (HSMCI) User Interface. . . . . . . . . . 826
38. Pulse Width Modulation Controller (PWM) . . . . . . . . . . . . . . . . . . 853
38.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
38.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
38.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
38.4 I/O Lines Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
38.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
38.6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
38.7 Pulse Width Modulation Controller (PWM) Controller User Interface . . . . . . 879
39. USB Device Port (UDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
39.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
39.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
39.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
39.4 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
39.5 Typical Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
39.6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
39.7 USB Device Port (UDP) User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
40. Analog Comparator Controller (ACC) . . . . . . . . . . . . . . . . . . . . . . 967
40.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
40.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
40.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
40.4 Pin Name List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
40.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
40.6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
40.7 Analog Comparator Controller (ACC) User Interface . . . . . . . . . . . . . . . . . . 970
41. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . 981
41.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
41.2 Embedded Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
41.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
41.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
41.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
41.6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
41.7 Analog-to-Digital Converter (ADC) User Interface . . . . . . . . . . . . . . . . . . . . 994
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SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42. Digital-to-Analog Converter Controller (DACC) . . . . . . . . . . . . . . 1017
42.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
42.2 Embedded characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
42.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
42.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
42.5 Product Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
42.6 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
42.7 Digital-to-Analog Converter (DACC) User Interface . . . . . . . . . . . . . . . . . . 1023
43. SAM4S Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 1039
43.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
43.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
43.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046
43.4 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
43.5 PLLA, PLLB Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
43.6 USB Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
43.7 12-Bit ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
43.8 12-Bit DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
43.9 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
43.10 Temperature Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
43.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
44. SAM4S Mechanical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 1090
44.1 Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
44.2 Packaging Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
45. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101
46. Errata on SAM4S Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
46.1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
46.2 Errata SAM4SD32/SD16/SA16/S16/S8 Rev A Parts . . . . . . . . . . . . . . . . . 1105
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i
viii
SAM4S [DATASHEET]
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