FS6217-01 Dual PLL Clock Generator IC AMERICAN MICROSYSTEMS, INC. February 2001 1.0 Features 2.0 * High-performance functional superset of PLL1700 device * 27MHz crystal reference * May be used with external clock reference source * Generated audio system clocks SCKO1 : 33.8688MHz (fixed) SCKO2 : 256 x Fs SCKO3 : 384 x Fs SCKO4 : 768 x Fs * Zero ppm synthesis error on all output clocks * Low cycle-to-cycle and cumulative clock jitter * Multiple sampling frequencies: Fs = 32, 44.1, 48, 64, 88.2, and 96KHz (@ 256x, 384x, and 768x Fs) Fs = 128, 176.4, and 192KHz (@ 256x and 384x Fs) * 3.3V logic interface * Dual power supplies: +5v and +3.3v (contact factory for +3.3 volt only version) Description The FS6217-01 is a CMOS clock generator IC designed to minimize cost and component count in digital video/ audio systems. The FS6217-01 can generate four system clocks from a single 27MHz reference frequency. This device eliminates external components and provides the low phase jitter performance needed for highperformance digital-to-analog converters (DAC) and analog-to-digital converters (ADC). The FS6217-01 is ideal for MPEG-2 applications which use a 27MHz master clock such as: DVD players, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes. Figure 1: Pin Configuration * Small package: 20 pin SSOP (5.3mm) * Custom frequency patterns and packages are available. Contact your local AMI Sales Representative for more information. ML/SR0 1 20 MC/FS1 MODE 2 19 MD/FS0 VDD 3 18 RST GND 4 17 SCKO3 XT2 5 16 VDDB XT1 6 15 GNDB GNDP 7 14 SCKO2 VDDP 8 13 SCKO4 SR1 9 12 SCKO1 10 11 MCKON MCKOP FS6217-01 20-pin SSOP (5.3mm) Figure 2: Block Diagram XT1 6 XT2 5 SR1 ISO9001 PLL1 9 ML/SR0 MC/FS1 MD/FS0 MODE 1 20 19 2 RST 18 Shift Register Dividers & Switching Look-Up Table 10 MCKOP 11 MCKON 12 SCKO1 14 SCKO2 17 SCKO3 13 SCKO4 PLL2 Reset Logic FS6217-01 2.23.01 FS6217-01 Dual PLL Clock Generator IC February 2001 Table 1: Pin Descriptions Key: A = Analog Pin; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN TYPE NAME DESCRIPTION 1 DID ML/SR0 2 DID MODE 3 P VDD VDD (for digital logic) 4 P GND Ground (for digital logic) 5 A XT2 Crystal oscillator feedback (must be no connection if using external reference source) - see Note 1 below 6 A XT1 Crystal oscillator drive / External reference input 7 P GNDP Ground (for PLLs) 8 P VDDP VDD (for PLLs) 9 DID SR1 10 DO MCKOP 27MHz clock output 11 DO MCKON 27MHz clock output (inverted phase) 12 DO SCKO1 Fixed 33.8688MHz clock output 13 DO SCKO4 768*Fs clock output (see Table 2 ) 14 DO SCKO2 256*Fs clock output (see Table 2) 15 P GNDB Ground (for output buffers) Latch ("SOFTWARE" mode) / Sample rate select 0 ("HARDWARE" mode) Mode control select. For "SOFTWARE" mode, set MODE=0. For "HARDWARE" mode, set MODE=1 Sample rate select 1 ("HARDWARE" mode), may be left open for backward compatiblity with PLL1700 16 P VDDB Power supply (for output buffers) 17 DO SCKO3 384*Fs clock output (see Table 2) 18 DID RST 19 DID MD/FS0 Data ("SOFTWARE" mode) / Frequency select 0 ("HARDWARE" mode) 20 DID MC/FS1 Clock ("SOFTWARE" mode) / Frequency select 1 ("HARDWARE" mode) Reset (when low, device is held in reset state) NOTE: If compatibility with BB PLL1700 in external reference mode (which requires pin 5 be grounded) is required, contact factory. Table 2: Sampling and Clock Output Frequencies Note: F(XT1) = 27.0000MHz SAMPLING RATE SCKO1 (MHz) SCKO2 (MHz) SCKO3 (MHz) SCKO4 (MHz) MCKO (MHz) 0 48KHz 33.8688 12.2880 (x256) 18.4320 (x384) 36.8640 (x768) 27.0000 1 44.1KHz 33.8688 11.2896 (x256) 16.9344 (x384) 33.8688 (x768) 27.0000 1 0 32KHz 33.8688 8.1920 (x256) 12.2880 (x384) 24.5760 (x768) 27.0000 0 1 1 - - - - - - 0 1 0 0 96KHz 33.8688 24.5760 (x256) 36.8640 (x384) 36.8640 (x384) 27.0000 0 1 0 1 88.2KHz 33.8688 22.5792 (x256) 33.8688 (x384) 33.8688 (x384) 27.0000 0 1 1 0 64KHz 33.8688 16.3840 (x256) 24.5760 (x384) 24.5760 (x384) 27.0000 0 1 1 1 - - - - - - 1 0 0 0 96KHz 33.8688 24.5760 (x256) 36.8640 (x384) 73.7280 (x768) 27.0000 1 0 0 1 88.2KHz 33.8688 22.5792 (x256) 33.8688 (x384) 67.7376 (x768) 27.0000 1 0 1 0 64KHz 33.8688 16.3840 (x256) 24.5760 (x384) 49.1520 (x768) 27.0000 1 0 1 1 - - - - - - 1 1 0 0 192KHz 33.8688 49.1520 (x256) 73.7280 (x384) 73.7280 (x384) 27.0000 1 1 0 1 176.4KHz 33.8688 45.1584 (x256) 67.7376 (x384) 67.7376 (x384) 27.0000 1 1 1 0 128KHz 33.8688 32.7680 (x256) 49.1520 (x384) 49.1520 (x384) 27.0000 1 1 1 1 - - - - - - SR1 SR0 FS1 FS0 0 0 0 0 0 0 0 0 0 2 2.23.01 FS6217-01 AMERICAN MICROSYSTEMS, INC. Dual PLL Clock Generator IC February 2001 3.0 Device Control 3.1 HARDWARE Mode In "HARDWARE" mode, the clock frequencies are selected by the logic levels on the SR1, ML/SR0, MC/FS1, and MD/FS0 pins according to Table 2. "HARDWARE" mode is activated by setting the logic level on the MODE pin to "1" (low). In "HARDWARE" mode all output buffers are always enabled. 3.2 SOFTWARE Mode In "SOFTWARE" mode, the clock frequencies may be selected by an internal data register called the "Mode Register" (see Table 3 and Table 4). Data is loaded into the "Mode Register" by the ML/SR0, MC/FS1, and MD/FS0 pins. Additionally, the output buffers may be individually enabled or disabled by the "Mode Register". Table 3: Mode Register D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 0 CE6 CE5 CE4 CE3 CE2 CE1 SR1 SR0 FS1 FS0 Table 4: Register Mapping On RESET, all bits revert to the "default" state in this table. REGISTER MODE 3.3 BIT NAME DESCRIPTION DEFAULT CE6 MCKON Enable ("1"=Enabled, "0"=Disabled) 1 CE5 MCKOP Enable ("1"=Enabled, "0"=Disabled) 1 CE4 SCKO4 Enable ("1"=Enabled, "0"=Disabled) 1 CE3 SCKO3 Enable ("1"=Enabled, "0"=Disabled) 1 CE2 SCKO2 Enable ("1"=Enabled, "0"=Disabled) 1 CE1 SCKO1 Enable ("1"=Enabled, "0"=Disabled) 1 SR1 Sampling Rate Select Bit 1 0 SR0 Sampling Rate Select Bit 0 0 FS1 Sampling Frequency Select Bit 1 0 FS0 Sampling Frequency Select Bit 0 0 Device RESET Either of two conditions will cause a device RESET to occur. ! Initial application of VDD to the FS6217. ! RST pin logic low level. The RESET is held for 1024 MCKO periods after both of the conditions have been removed. 3 2.23.01 FS6217-01 Dual PLL Clock Generator IC February 2001 Figure 3: Mode Register Signal Timing tMLL tMHH ML (pin 1) tMLS tMCH tMCL tMLH tMLS MC (pin 20) tMCY MD (pin 19) MSB (D15) LSB (D0) tMDS DESCRIPTION tMDH SYMBOL MIN tMCY 100 ns MC Pulse Width LOW tMCL 40 ns MC Pulse Width HIGH tMCH 40 ns MD Hold Time tMDH 40 ns MD Set-up Time tMDS 40 ns ML Pulse Width LOW tMLL 16 MC Clocks (1) ML Pulse Width High tMHH 200 ns tMLH 40 ns tMLS 40 ns MC Pulse Period ML Hold Time (2) ML Set-up Time (3) TYP MAX UNITS NOTES: (1) MC clocks: MC clock period. (2) MC rising edge for LSB to ML rising edge. (3) ML rising edge to next MC rising edge. If the MC clock is stopped after the LSB, any ML rising time is accepted. 4 2.23.01 FS6217-01 AMERICAN MICROSYSTEMS, INC. Dual PLL Clock Generator IC February 2001 4.0 Electrical Specifications Table 5: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER Supply Voltage (VDD, VDDP, VDDB) MIN. MAX. UNITS VSS - 0.5 6.5 V Supply Voltage Difference (VDD-VDDP) - 0.1 + 0.1 V GND Voltage Difference (GND, GNDP, GNDB) - 0.1 + 0.1 V Digital Input Voltage VGND - 0.3 VDD+ 0.3 V Digital Output Voltage VGNDB - 0.3 VDDB+ 0.3 V -10 + 10 mA 300 mW 70 C Input Current (except supply pins) Power Dissipation Operating Temperature Range (non-condensing) Storage Temperature Range (non-condensing) 0 150 C Lead Temperature (soldering, 10s) 260 C Package Temperature (IR reflow, 10s) 235 C 2 kV Input Static Discharge Voltage Protection (MILSTD 883E, Method 3015.7) -65 CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. 5 2.23.01 FS6217-01 Dual PLL Clock Generator IC February 2001 Table 6: Specifications PARAMETER CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS 3 4.75 6.5 pF Crystal Oscillator Internal Load Capacitance CX(INT) Oscillator Transconductance gmOSC Crystal Drive Level 12 mS 500 uW Crystal ESR Digital Inputs 35 Input Logic Level High VIH Input Logic Level Low VIL Input Current High IIH (VIN = VDD) Input Current Low IIL (VIN = 0V) Reference Input 2.0 V 50 0.8 V 200 uA 1 uA XT1 (note: this data is only relevant to the case where XT2 is grounded for external clock reference) Input Logic Level High VIHX Input Logic Level Low VILX Input Current High IIHX (VIN = VDD) Input Current Low IILX (VIN = 0V) Output Buffers SR1, ML/SR0, MC/FS1, MD/FS0 2.0 V 50 0.8 V 100 uA 800 uA MCKOx, SCKOx : F(XT1) = 27MHz, CL = 20pF Output Logic Level High IOH = 4mA Output Logic Level Low IOL = 4mA VDDB-0.4 V +0.4 V Rise Time 20% to 80% VDDB 3 Fall Time 80% to 20% VDDB 3 SCKOx Duty Cycle Measured at +1.4V 45 55 % MCKOx Duty Cycle (using crystal oscillator) Measured at +1.4V 40 60 % Phase-Locked Loops ns SCKOx (all modes) Jitter (Short-term) Jitter (Long-term) ns referred to ideal clock @ 500us delay 100 ps RMS 150 ps RMS PLL Settling Time 10 ms +5.5 VDC +3.6 VDC Power Supply Requirements VDD, VDDP Voltage Range Referred to GND, GNDP +4.5 VDDB Voltage Range Referred to GNDB +2.7 IDD + IDDP Supply Current VDD = VDDP = +5V, using crystal osc. 19 26 mA IDDb Supply Current VDDB = +3.3V, outputs unloaded 7 10 mA 6 2.23.01 FS6217-01 AMERICAN MICROSYSTEMS, INC. Dual PLL Clock Generator IC February 2001 5.0 Package Information Table 7: 20-pin 5.3mm (0.209") SSOP Package Dimensions 20 DIMENSIONS INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.068 0.078 1.73 1.99 A1 0.002 0.008 0.05 0.21 A2 0.066 0.070 1.68 1.78 B 0.010 0.015 0.25 0.38 C 0.005 0.008 0.13 0.20 D 0.278 0.289 7.07 7.33 E e 0.205 0.212 5.20 0.0256 BSC 5.38 E R 1 B e 0.65 BSC H 0.301 0.311 7.65 7.90 L 0.022 0.037 0.55 0.95 0 8 0 8 H AMERIC AN MICRO SYSTEMS, INC . A2 D A1 BASE PLANE A C L SEATING PLANE Table 8: 20-pin SSOP (5.3mm) Package Characteristics PARAMETER Thermal Impedance, Junction to Free-Air SYMBOL JA Lead Inductance, Self L11 Lead Inductance, Mutual L12 Lead Capacitance, Bulk C11 Lead Capacitance, Mutual C12 CONDITIONS/DESCRIPTION Air flow = 0 m/s TYP. UNITS 110 C/W Longest trace 2.260 Shortest trace 0.958 Longest trace to first adjacent trace 0.848 Shortest trace to first adjacent trace 0.408 Longest trace to VSS 0.395 Shortest trace to VSS 0.209 Longest trace to first adjacent trace 0.163 Shortest trace to first adjacent trace 0.057 nH nH pF pF 7 2.23.01 FS6217-01 Dual PLL Clock Generator IC February 2001 6.0 Ordering Information ORDERING CODE DEVICE NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE SHIPPING CONFIGURATION 11825-805 FS6217-01 20-pin (5.3mm) SSOP 0C to 70C (Commercial) Tape and Reel 11825-815 FS6217-01 20-pin (5.3mm) SSOP 0C to 70C (Commercial) Tubes Copyright (c) 1999, 2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com 8 2.23.01