AMERICAN MICROSYSTEMS, INC.
Februar y 2001
2.23.01
FS6217-01
FS6217-01FS6217-01
FS6217-01
Dual PLL Clock Generator IC
Dual PLL Clock Generator ICDual PLL Clock Generator IC
Dual PLL Clock Generator IC
ISO9001
ISO9001ISO9001
ISO9001
1.0 Features
• High-performance functional superset of PLL1700
device
• 27MHz crystal reference
• May be used with external clock reference source
• Generated audio system clocks
SCKO1 : 33.8688MHz (fixed)
SCKO2 : 256 x Fs
SCKO3 : 384 x Fs
SCKO4 : 768 x Fs
• Zero ppm synthesis error on all output clocks
• Low cycle-to-cycle and cumulative clock jitter
• Multiple sampling frequencies:
Fs = 32, 44.1, 48, 64, 88.2, and 96KHz
(@ 256x, 384x, and 768x Fs)
Fs = 128, 176.4, and 192KHz
(@ 256x and 384x Fs)
• 3.3V logic interface
• Dual power supplies: +5v and +3.3v
(contact factory for +3.3 volt only version)
• Small package: 20 pin SSOP (5.3mm)
• Custom frequency patterns and packages are avail-
able. Contact your local AMI Sales Representative for
more information.
2.0 Description
The FS6217-01 is a CMOS clock generator IC designed
to minimize cost and component count in digital video/
audio systems.
The FS6217-01 can generate four system clocks from a
single 27MHz reference frequency.
This devic e elim inates ext ernal c om ponents and pro vides
the low phase jitter performance needed for high-
performance digital-to-analog converters (DAC) and
analog-to-digital converters (ADC).
The FS6217-01 is ideal for MPEG-2 applications which
use a 27MHz master clock such as: DVD players, DVD
add-on cards for multimedia PCs, digital HDTV systems,
and set-top boxes.
Figure 1: Pin Configuration
1
16
2
3
4
5
6
7
8
15
14
13
12
11
ML/SR0
MODE
VDD
GND
XT2
GNDP
VDDP
MCKON
SCKO1
SCKO4
SCKO2
GNDB
VDDB
FS6217-01
9
10
SR1
MCKOP
18
17
SCKO3
RST
20
19
MD/FS0
MC/FS1
XT1
20-pin SSOP (5.3mm)
Figure 2: Block Diagram
XT2
XT1
SCKO3
SCKO4
MCKOP
MCKON
SCKO1
SCKO2
10
Reset
Logic
PLL1
PLL2
Shift
Register
MODE
Dividers
&
Switching
FS6217-01
RST
Look-Up
Table
11
12
14
17
13
6
5
1
20
19
2
18
MD/FS0
MC/FS1
ML/SR0
SR1
9
Februar y 2001
22.23.01
FS6217-01
FS6217-01FS6217-01
FS6217-01
Dual PLL Clock Generator IC
Dual PLL Clock Generator ICDual PLL Clock Generator IC
Dual PLL Clock Generator IC
Table 1: Pin Descriptions
Key: A = Analog Pin; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN TYPE NAME DESCRIPTION
1DI
DML/SR0 Latch (“SOFTWARE” mode) / Sample rate select 0 (“HARDWARE” mode)
2DI
DMODE Mode control select. For “SOFTWARE” mode, set MODE=0. For “HARDWARE” mode, set MODE=1
3 P VDD VDD (for digital logic)
4 P GND Ground (for digital logic)
5 A XT2 Crystal oscillator feedback (must be no connection if using external reference source) – see Note 1 below
6 A XT1 Crystal oscillator drive / External reference input
7 P GNDP Ground (for PLLs)
8 P VDDP VDD (for PLLs)
9DI
DSR1 Sample rate select 1 (“HARDWARE” mode), may be left open for backward compatiblity with PLL1700
10 DO MCKOP 27MHz clock output
11 DO MCKON 27MHz clock output (inverted phase)
12 DO SCKO1 Fixed 33.8688MHz clock output
13 DO SCKO4 768*Fs clock output (see Table 2 )
14 DO SCKO2 256*Fs clock output (see Table 2)
15 P GNDB Ground (for output buffers)
16 P VDDB P ower supply (for output buffe rs)
17 DO SCKO3 384*Fs clock output (see Table 2)
18 DIDRST Reset (when low, device is held in reset state)
19 DIDMD/FS0 Data (“SOFTWARE” mode) / Frequency select 0 (“HARDWARE” mode)
20 DIDMC/FS1 Clock (“SOFTWARE” mode) / Frequency select 1 (“HARDWARE” mode)
NOTE: If compatibility with BB PLL1700 in external reference mode (which requires pin 5 be grounded) is required, contact factory.
Table 2: Sampling and Clock Output Frequencies
Note: F(XT1) = 27.0000M Hz
SR1 SR0 FS1 FS0 SAMPLING
RATE SCKO1 (MHz) SCKO2 (MHz) SCKO3 (MHz) SCKO4 (MHz) MCKO (MHz)
0 0 0 0 48KHz 33.868 8 12.288 0 ( x256) 18.432 0 ( x384) 36.864 0 ( x768) 27.0000
0 0 0 1 44.1KHz 33.868 8 11.289 6 ( x256) 16.934 4 ( x384) 33.868 8 ( x768) 27.0000
0 0 1 0 32KHz 33.8688 8.1920 (x256) 12.288 0 ( x384) 24.576 0 ( x768) 27.0000
0011------
0 1 0 0 96KHz 33.868 8 24.576 0 ( x256) 36.864 0 ( x384) 36.864 0 ( x384) 27.0000
0 1 0 1 88.2KHz 33.868 8 22.579 2 ( x256) 33.868 8 ( x384) 33.868 8 ( x384) 27.0000
0 1 1 0 64KHz 33.868 8 16.384 0 ( x256) 24.576 0 ( x384) 24.576 0 ( x384) 27.0000
0111------
1 0 0 0 96KHz 33.868 8 24.576 0 ( x256) 36.864 0 ( x384) 73.728 0 ( x768) 27.0000
1 0 0 1 88.2KHz 33.868 8 22.579 2 ( x256) 33.868 8 ( x384) 67.737 6 ( x768) 27.0000
1 0 1 0 64KHz 33.868 8 16.384 0 ( x256) 24.576 0 ( x384) 49.152 0 ( x768) 27.0000
1011------
1 1 0 0 192KHz 33.8688 49.1520 ( x256) 73.728 0 ( x384) 73.728 0 ( x384) 27.0000
1 1 0 1 176.4KH z 33.868 8 45.158 4 ( x256) 67.737 6 ( x384) 67.737 6 ( x384) 27.0000
1 1 1 0 128KHz 33.8688 32.7680 ( x256) 49.152 0 ( x384) 49.152 0 ( x384) 27.0000
1111------
AMERICAN MICROSYSTEMS, INC.
Februar y 2001
32.23.01
FS6217-01
FS6217-01FS6217-01
FS6217-01
Dual PLL Clock Generator IC
Dual PLL Clock Generator ICDual PLL Clock Generator IC
Dual PLL Clock Generator IC
3.0 Device Control
3.1 HARDWARE Mode
In “HARDWARE” mode, the clock frequencies are selected by the logic levels on the SR1, ML/SR0, MC/FS1, and
MD/FS0 pins acc ording t o T able 2. “ HARDWARE” mode is activate d b y settin g the log ic leve l o n th e MO DE pin to “1”
(low). In “HARDWARE” mode all output buffers are always enabled.
3.2 SOFTWARE Mode
In “SOFTW ARE” mode, the cloc k frequenc ies m ay be selected by an inter nal data regist er ca lled t he “Mode Regis ter”
(see Table 3 and T able 4). D ata is l oaded into the “Mod e Regis ter ” by the ML/SR0, MC/FS1, and MD/FS0 pins. Ad-
ditionally, the output buffers may be individually enabled or disabled by the “Mode Register”.
Table 3: Mode Register
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
011100CE6CE5CE4CE3CE2CE1SR1SR0FS1FS0
Table 4: Register Mapping
On RESET, all bits revert to the “default” state in this table.
REGISTER BIT NAME DESCRIPTION DEFAULT
CE6 MCKON E nabl e (“1”=Enabled, “0”=Disabled) 1
CE5 MCKOP Enable (“1”=Enabled, “0”=Disabled) 1
CE4 S CK O4 Enable (“1”=Enabled, “0”=Disabled) 1
CE3 S CK O3 Enable (“1”=Enabled, “0”=Disabled) 1
CE2 S CK O2 Enable (“1”=Enabled, “0”=Disabled) 1
CE1 S CK O1 Enable (“1”=Enabled, “0”=Disabled) 1
SR1 Sampling Rate Selec t Bit 1 0
SR0 Sampling Rate Selec t Bit 0 0
FS1 Sampling Frequency Select Bit 1 0
MODE
FS0 Sampling Frequency Select Bit 0 0
3.3 Device RESET
Either of two conditions will cause a device RESET to occur.
! Initial application of VDD to the FS6217.
! RST pin logic low level.
The RESET is held for 1024 MCKO periods after both of the conditions have been removed.
Februar y 2001
42.23.01
FS6217-01
FS6217-01FS6217-01
FS6217-01
Dual PLL Clock Generator IC
Dual PLL Clock Generator ICDual PLL Clock Generator IC
Dual PLL Clock Generator IC
Figure 3: Mode Register Signal Timing
t
MLL
t
MCH
t
MCL
t
MDS
t
MDH
t
MCY
t
MLH
t
MLS
t
MHH
t
MLS
ML (pin 1)
MC (pin 20)
MD (pin 19) MSB
(D15) LSB
(D0)
DESCRIPTION SYMBOL MIN TYP MAX UNITS
MC Pulse Period tMCY 100 ns
MC Pulse Width LOW tMCL 40 ns
MC Pulse Width HIGH tMCH 40 ns
MD Hol d Tim e tMDH 40 ns
MD Set-up Time tMDS 40 ns
ML Pul se Widt h LOW tMLL 16 MC Clocks (1)
ML Pul se Widt h High tMHH 200 ns
ML Hol d Tim e (2) tMLH 40 ns
ML Set-up Time (3) tMLS 40 ns
NOTES:
(1) MC clocks: MC clock peri od.
(2) MC rising edge for LSB to ML rising edge.
(3) ML rising edge to next MC rising edge. If the MC clock is stopped after the LSB, any ML rising
time is accept ed.
AMERICAN MICROSYSTEMS, INC.
Februar y 2001
52.23.01
FS6217-01
FS6217-01FS6217-01
FS6217-01
Dual PLL Clock Generator IC
Dual PLL Clock Generator ICDual PLL Clock Generator IC
Dual PLL Clock Generator IC
4.0 Electrical Specifications
Table 5: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rati ng conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER MIN. MAX. UNITS
Supply Voltage (VDD, VDDP, VDDB) VSS - 0 .5 6.5 V
Supply Voltage Di ff erence (VDD-VDDP) - 0.1 + 0.1 V
GND Voltage Differenc e (GND, GNDP, GNDB) - 0.1 + 0.1 V
Digital Input Voltage VGND - 0.3 VDD+ 0. 3 V
Digital Output Voltage VGNDB - 0.3 VDDB+ 0.3 V
Input Current (except supply pi ns) -10 + 10 mA
Power Dissipati on 300 mW
Operating Temperature Range (non-condensing) 0 70 °C
Storage Temperature Range (non-condensing) -65 150 °C
Lead Temperature (soldering, 10s) 260 °C
Package Temperature (I R reflow, 10s ) 235 ° C
Input Static Disc harge Voltage Protection (MIL-
STD 883E, Method 3015.7) 2kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage result ing in a loss of funct ionalit y or perf ormance m ay
occur if this device is subj ect ed to a high-energy elec trostatic discharge.
Februar y 2001
62.23.01
FS6217-01
FS6217-01FS6217-01
FS6217-01
Dual PLL Clock Generator IC
Dual PLL Clock Generator ICDual PLL Clock Generator IC
Dual PLL Clock Generator IC
Table 6: Specifications
PARAMETER CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS
Crystal Oscillator
Internal Load Capacitance CX(INT) 3 4.75 6.5 pF
Oscillator Transc onductance gmOSC 12 mS
Crystal Drive Level 500 uW
Crystal ESR 35 Ω
Digital Input s SR1, ML/SR 0 , MC/FS1, MD/FS0
Input Logic Level High VIH 2.0 V
Input Logic Level Low VIL 0.8 V
Input Current High IIH (VIN = VDD) 50 200 uA
Input Current Low IIL (VIN = 0V) 1 uA
Reference Input XT1
(note: this dat a is onl y rel ev ant to the case w her e XT2 is grou nd ed fo r exter nal clock reference)
Input Logic Level High VIHX 2.0 V
Input Logic Level Low VILX 0.8 V
Input Current High IIHX (VIN = VDD) 50 100 uA
Input Current Low IILX (V IN = 0V) 800 uA
Output Buffers MCKOx, SCKOx : F(XT1) = 27MHz, CL = 20pF
Output Logic Level High IOH = 4mA VDDB–0.4 V
Output Logic Level Low IOL = 4mA +0.4 V
Rise Time 20% to 80% VDDB 3ns
Fall Time 80% to 20% VDDB 3ns
SCKOx Duty Cycle Measured at +1.4V 45 55 %
MCKOx Duty Cycle
(using crystal oscillator) Measured at +1.4V 40 60 %
Phase-Locked Loops SCKOx (all modes)
Jitter (Short-term) 100 ps RMS
Jitter (Long-term) referred to ideal clock @ 500us delay 150 ps RMS
PLL Settling Time 10 ms
Power Supply Requirements
VDD, VDDP Voltage Range Referred to GND, GNDP +4.5 +5.5 VDC
VDDB Voltage Range Referred to GNDB +2.7 +3.6 VDC
IDD + IDDP Supply Current VDD = VDDP = +5V, using crystal osc. 19 26 mA
IDDb Supply Current VDDB = +3.3V, outputs unloaded 7 10 mA
AMERICAN MICROSYSTEMS, INC.
Februar y 2001
72.23.01
FS6217-01
FS6217-01FS6217-01
FS6217-01
Dual PLL Clock Generator IC
Dual PLL Clock Generator ICDual PLL Clock Generator IC
Dual PLL Clock Generator IC
5.0 Package Information
Table 7: 20-pin 5.3mm (0.209") SSOP Package Dimensions
DIMENSIONS
INCHES MILLIMETERS
MIN. MAX. MIN. MAX.
A 0.068 0.078 1.73 1.99
A1 0.002 0.008 0.05 0.21
A2 0.066 0.070 1.68 1.78
B 0.010 0.015 0.25 0.38
C 0.005 0.008 0.13 0.20
D 0.278 0.289 7.07 7.33
E 0.205 0.212 5.20 5.38
e 0.0256 BSC 0.65 BSC
H 0.301 0.311 7.65 7.90
L 0.022 0.037 0.55 0.95
Θ0808
Be
DA
1
SEATING PLANE
HE
20
1
BASE PLANE
A
2
C
L
θ
A
AME RICAN MICROSYSTE MS, INC.
R
Table 8: 20-pin SSOP (5.3mm) Package Characteristics
PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 m/s 110 °C/W
Longest trace 2.260
Lead Inductanc e, Self L11 Shortest trace 0.958 nH
Longest trace to first adjacent trace 0.848
Lead Inductanc e, Mutual L12 Shortest trace to first adjacent trace 0.408 nH
Longest trace to VSS 0.395
Lead Capacitance, Bulk C11 Shortest trace to VSS 0.209 pF
Longest trace to first adjacent trace 0.163
Lead Capacitance, Mutual C12 Shortest trace to first adjacent trace 0.057 pF
Februar y 2001
82.23.01
FS6217-01
FS6217-01FS6217-01
FS6217-01
Dual PLL Clock Generator IC
Dual PLL Clock Generator ICDual PLL Clock Generator IC
Dual PLL Clock Generator IC
6.0 Ordering Information
ORDERING CODE DEVICE NUMBER PACKAGE TYPE OPERATING
TEMPERATURE RANGE SHIPPING
CONFIGURATION
11825-805 FS6217-01 20-pin (5.3mm) SSOP 0°C to 70°C (Commercial) Tape and Reel
11825-815 FS6217-01 20-pin (5.3mm) SSOP 0°C to 70°C (Commercial) Tubes
Copyright © 1999, 2000 American Microsystems, Inc.
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI
makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom
of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-
serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are
intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-
ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom-
mended without additional processing by AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,
WWW Add ress: http://www.amis.com E-mail: tgp@amis.com
