High CMR, High Speed
Optocouplers
Technical Data HCPL-4504
HCPL-J454
HCPL-0454
HCNW4504
Features
• Short Propagation Delays
for TTL and IPM
Applications
• 15 kV/µs Minimum Common
Mode Transient Immunity at
VCM = 1500 V for TTL/Load
Drive
• High CTR at TA = 25°C
>25% for HCPL-4504/0454
>23% for HCNW4504
>19% for HCPL-J454
• Electrical Specifications for
Common IPM Applications
• TTL Compatible
• Guaranteed Performance
from 0°C to 70°C
• Open Collector Output
• Safety Approval
UL Recognized
- 2500 V rms / 1min. for
HCPL-4504/0454
- 3750 V rms / 1min. for
HCPL-J454
- 5000 V rms / 1min. for
HCPL-4504 Option020 and
HCNW4504
CSA Approved
VDE0884 Approved
-V
IORM = 560 Vpeak for
HCPL-0454 Option060
-V
IORM = 630 Vpeak for
HCPL-4504 Option060
-V
IORM = 891 Vpeak for
HCPL-J454
-V
IORM = 1414 Vpeak for
HCNW4504
Applications
• Inverter Circuits and
Intelligent Power Module
(IPM) interfacing -
High Common Mode Transient
Immunity (> 10 kV/µs for an
IPM load/drive) and (tPLH - tPHL)
Specified (See Power Inverter
Dead Time section)
• Line Receivers -
Short Propagation Delays and
Low Input-Output Capacitance
• High Speed Logic Ground
Isolation - TTL/TTL, TTL/
CMOS, TTL/LSTTL
Functional Diagram
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
A 0.1 µF bypass capacitor between pins 5 and 8 is recommended.
7
1
2
3
45
6
8
NC
ANODE
CATHODE
NC
V
CC
NC
V
O
GND
TRUTH TABLE
LED
ON
OFF
V
O
LOW
HIGH
Description
The HCPL-4504 and HCPL-0454
contain a GaAsP LED while the
HCPL-J454 and HCNW4504
contain an AlGaAs LED. The LED
is optically coupled to an
integrated high gain photo
detector.
The HCPL-4504 series has short
propagation delays and high CTR.
The HCPL-4504 series also has a
guaranteed propagation delay
difference (tPLH-tPHL). These
• Replaces Pulse
Transformers -
Save Board Space and Weight
• Analog Signal Ground
Isolation -
Integrated Photodetector
Provides Improved Linearity
over Phototransistors
2
features make the HCPL-4504
series an excellent solution to IPM
inverter dead time and other
switching problems. The CTR,
propagation delay, and CMR are
specified both for TTL and IPM
conditions which are provided for
ease of application. These single
channel, diode-transistor opto-
couplers are available in 8-Pin
DIP, SO-8, and Widebody
Schematic
Selection Guide
Standard 8-Pin White Mold 8-Pin Widebody
Package Type DIP (300 Mil) DIP (300 Mil) Small Outline SO8 (400 Mil)
Part Number HCPL-4504 HCPL-J454 HCPL-0454 HCNW4504
VDE0884 VIORM = 630 Vpeak VIORM = 891 Vpeak VIORM = 560 Vpeak VIORM = 1414 Vpeak
Approval (Option 060) (Option 060)
Ordering Information
Specify Part number followed by Option Number (if desired)
Example
HCPL-4504 #XXX
020 = UL 5000 Vrms/1minute Option* for HCPL-4504 Only.
060 = VDE0884 Option* for HCPL-4504/0454.
300 = Gull-Wing Lead Option for HCPL-4504/J454, HCNW4504.
500 = Tape and Reel Packaging Option.
Option data sheets available. Contact Agilent sales representative or authorized distributor for information.
*Combination of Option 020 and Option 060 is not available.
package configurations. An
insulating layer between a LED
and an integrated photodetector
provide electrical insulation
between input and output.
Separate connections for the
photodiode bias and output-
transistor collector increase the
speed up to a hundred times that
of a conventional phototransistor
coupler by reducing the base
collector capacitance.
I
F
SHIELD
8
6
5GND
V
CC
2
3
V
O
I
CC
V
F
I
O
ANODE
CATHODE
+
–
3
Package Outline Drawings
HCPL-4504 and HCPL-J454 Outline Drawing
HCPL-4504 and HCPL-J454 Gull Wing Surface Mount Option 300 Outline Drawing
0.635 ± 0.25
(0.025 ± 0.010) 12° NOM.
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.65 ± 0.25
(0.380 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
1.016 (0.040)
1.194 (0.047)
1.194 (0.047)
1.778 (0.070)
9.398 (0.370)
9.906 (0.390)
4.826
(0.190)
TYP.
0.381 (0.015)
0.635 (0.025)
PAD LOCATION (FOR REFERENCE ONLY)
1.080 ± 0.320
(0.043 ± 0.013)
4.19
(0.165)MAX.
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
9.65 ± 0.25
(0.380 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A XXXXZ
YYWW
DATE CODE
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
5678
4321
5° TYP.
OPTION CODE*
UL
RECOGNITION
UR
0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
TYPE NUMBER
* MARKING CODE LETTER FOR OPTION NUMBERS (HCPL-4504 ONLY).
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
4
HCPL-0454 Outline Drawing (8-Pin Small Outline Package)
HCNW4504 Outline Drawing (8-Pin Widebody Package)
XXX
YWW
8765
4321
5.994 ± 0.203
(0.236 ± 0.008)
3.937 ± 0.127
(0.155 ± 0.005)
0.406 ± 0.076
(0.016 ± 0.003) 1.270
(0.050)BSG
5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005) 1.524
(0.060)
45° X 0.432
(0.017)
0.228 ± 0.025
(0.009 ± 0.001)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
0.305
(0.012)MIN.
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
0.203 ± 0.102
(0.008 ± 0.004)
7°
PIN ONE
0 ~ 7°
*
*
5
6
7
8
4
3
2
1
11.15 ± 0.15
(0.442 ± 0.006)
1.78 ± 0.15
(0.070 ± 0.006)
5.10
(0.201)MAX.
1.55
(0.061)
MAX.
2.54 (0.100)
TYP.
DIMENSIONS IN MILLIMETERS (INCHES).
7° TYP. 0.254 + 0.076
- 0.0051
(0.010+ 0.003)
- 0.002)
11.00
(0.433)
9.00 ± 0.15
(0.354 ± 0.006)
MAX.
10.16 (0.400)
TYP.
A
HCNWXXXX
YYWW
DATE CODE
TYPE NUMBER
0.51 (0.021) MIN.
0.40 (0.016)
0.56 (0.022)
3.10 (0.122)
3.90 (0.154)
5
HCNW4504 Gull Wing Surface Mount Option 300 Outline Drawing
Note: Use of nonchlorine activated fluxes is highly recommended.
Solder Reflow Temperature Profile
(HCPL-0454 and Gull Wing Surface Mount Option Parts)
1.00 ± 0.15
(0.039 ± 0.006)
7° NOM.
12.30 ± 0.30
(0.484 ± 0.012)
0.75 ± 0.25
(0.030 ± 0.010)
11.00
(0.433)
5
6
7
8
4
3
2
1
11.15 ± 0.15
(0.442 ± 0.006)
9.00 ± 0.15
(0.354 ± 0.006)
1.3
(0.051)
12.30 ± 0.30
(0.484 ± 0.012)
6.15
(0.242)
TYP.
0.9
(0.035)
PAD LOCATION (FOR REFERENCE ONLY)
1.78 ± 0.15
(0.070 ± 0.006)
4.00
(0.158)MAX.
1.55
(0.061)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.254 + 0.076
- 0.0051
(0.010+ 0.003)
- 0.002)
MAX.
240
∆T = 115°C, 0.3°C/SEC
0
∆T = 100°C, 1.5°C/SEC
∆T = 145°C, 1°C/SEC
TIME – MINUTES
TEMPERATURE – °C
220
200
180
160
140
120
100
80
60
40
20
0
260
123456789101112
6
Regulatory Information
The devices contained in this data sheet have been approved by the following agencies:
Agency/Standard HCPL-4504 HCPL-J454 HCPL-0456 HCNW4504
Underwriters UL1577
Laboratories (UL)
Recognized under UL1577, Component ✔✔✔✔
Recognition Program, Category FPQU2,
File E55361
Canadian Component
Standards Acceptance
Association Notice #5 ✔✔✔✔
(CSA)
File CA88324
Verband DIN VDE 0884
Deutscher (June 1992)
Electrotechniker ✔✔ ✔
(VDE)
Technischer DIN VDE 0884
Uberwachungs- (June 1992)
Verein Rheinland ✔
(TUV) Certificate R9650938
7
Insulation and Safety Related Specifications
Value
Parameter Symbol Units Conditions
HCPL-4504 HCPL-J454 HCPL-0454 HCNW4504
Minimum External L(101) 7.1 7.4 4.9 9.6 mm Measured from input
Air Gap (External terminals to output
Clearance) terminals, shortest
distance through air.
Minimum External L(102) 7.4 8.0 4.8 10.0 mm Measured from input
Tracking (External terminals to output
Creepage) terminals, shortest
distance path along
body.
Minimum Internal 0.08 0.5 0.08 1.0 mm Through insulation
Plastic Gap distance, conductor
(Internal Clearance) to conductor,
usually the direct
distance between the
photoemitter and
photodetector inside
the optocoupler
cavity.
Minimum Internal NA NA NA 4.0 mm Measured from input
Tracking (Internal terminals to output
Creepage) terminals, along
internal cavity.
Tracking Resistance CTI ≥175 ≥175 ≥175 ≥200 Volts DIN IEC 112/VDE
(Comparative 0303 Part 1
Tracking Index)
Isolation Group IIIa IIIa IIIa IIIa Material Group
(DIN VDE 0110,
1/89, Table 1)
All Agilent data sheets report the
creepage and clearance inherent
to the optocoupler component
itself. These dimensions are
needed as a starting point for the
equipment designer when
determining the circuit insulation
requirements.
However, once mounted on a
printed circuit board, minimum
creepage and clearance
requirements must be met as
specified for individual
equipment standards. For
creepage, the shortest distance
path along the surface of a
printed circuit board between the
solder fillets of the input and
output leads must be considered.
There are recommended
techniques such as grooves and
ribs which may be used on a
printed circuit board to achieve
desired creepage and clearances.
Creepage and clearance distances
will also change depending on
factors such as pollution degree
and insulation level.
8
VDE 0884 Insulation Related Characteristics
HCPL-0454 HCPL-4504
Description Symbol OPTION 060 OPTION 060 HCPL-J454 HCNW4504 Unit
Installation classification per
DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤150 V rms I-IV I-IV I-IV I-IV
for rated mains voltage ≤300 V rms I-III I-IV I-IV I-IV
for rated mains voltage ≤450 V rms I-III I-III I-IV
for rated mains voltage ≤600 V rms I-III I-IV
for rated mains voltage ≤1000 V rms I-III
Climatic Classification 55/100/21 55/100/21 55/100/21 55/85/21
Pollution Degree (DIN VDE 0110/1.89) 2 2 2 2
Maximum Working Insulation Voltage VIORM 560 630 891 1414 V peak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production VPR 1050 1181 1670 2652 V peak
Test with tm = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and Sample VPR 840 945 1336 2121 V peak
Test, tm = 60 sec,
Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec) VIOTM 4000 6000 6000 8000 V peak
Safety Limiting Values - Maximum
Values Allowed in the Event of a Failure,
also see Thermal Derating curve
Case Temperature TS150 175 175 150 °C
Input Current IS,INPUT 150 230 400 400 mA
Output Power PS,OUTPUT 600 600 600 700 mW
Insulation Resistance at TS,R
S
≥109≥109≥109≥109Ω
VIO = 500 V
NOTE: These optocouplers are suitable for "safe electrical isolation" only within the safety limit data.
Maintenance of the safety data shall be ensured by means of protective circuits.
NOTE: Insulation Characteristics are per DIN VDE 0884 (June 1992 revision).
NOTE: Surface mount classification is Class A in accordance with CECC 00802.
*Refer to the optocoupler section of the Designer's Catalog, under regulatory information (VDE 0884) for a detailed description of
Method a and Method b partial discharge test profiles.
9
Absolute Maximum Ratings
Parameter Symbol Device Min. Max. Units Note
Storage Temperature TS-55 125 °C
Operating Temperature T
AHCPL-4504 -55 100 °C
HCPL-0454
HCPL-J454
HCNW4504 -55 85
Average Forward Input Current IF(AVG) 25 mA 1
Peak Forward Input Current IF(PEAK) HCPL-4504 50 mA 2
(50% duty cycle, 1 ms pulse width) HCPL-0454
HCPL-J454 40
HCNW4504
Peak Transient Input Current IF(TRANS) HCPL-4504 1 A
(≤1 µs pulse width, 300 pps) HCPL-0454
HCPL-J454 0.1
HCNW4504
Reverse LED Input Voltage (Pin 3-2) VRHCPL-4504 5 V
HCPL-0454
HCPL-J454 3
HCNW4504
Input Power Dissipation PIN HCPL-4504 45 mW 3
HCPL-0454
HCPL-J454 40
HCNW4504
Average Output Current (Pin 6) IO(AVG) 8mA
Peak Output Current IO(PEAK) 16 mA
Supply Voltage (Pin 8-5) VCC -0.5 30 V
Output Voltage (Pin 6-5) VO-0.5 20 V
Output Power Dissipation PO100 mW 4
Lead Solder Temperature TLS HCPL-4504 260 °C
(Through-Hole Parts Only) HCPL-J454
1.6 mm below seating plane, 10 seconds
Up to seating plane, 10 seconds HCNW4504 260
Reflow Temperature Profile TRP HCPL-0454
and
Option 300
See Package Outline
Drawings section
10
Parameter Symbol Device Min. Typ.* Max. Units Test Conditions Fig. Note
Current CTR HCPL-4504 25 32 60 % TA = 25°CV
O
= 0.4 V IF = 16 mA, 1, 2, 5
Transfer Ratio HCPL-0454 21 34 VO = 0.5 V VCC = 4.5 V 4
HCPL-J454 19 37 60 TA = 25°CV
O
= 0.4 V
13 39 VO = 0.5 V
HCNW4504 23 29 60 TA = 25°CV
O
= 0.4 V
19 31 63 VO = 0.5 V
Current CTR HCPL-4504 26 35 65 % TA = 25°CV
O
= 0.4 V IF = 12 mA, 1, 2, 5
Transfer Ratio HCPL-0454 22 37 VO = 0.5 V VCC = 4.5 V 4
HCPL-J454 21 43 65 TA = 25°CV
O
= 0.4 V
16 45 VO = 0.5 V
HCNW4504 25 33 65 TA = 25°CV
O
= 0.4 V
21 35 68 VO = 0.5 V
Logic Low VOL HCPL-4504 0.2 0.4 V TA = 25°CI
O
= 4.0 mA IF = 16 mA,
Output Voltage HCPL-0454 0.5 IO = 3.3 mA VCC = 4.5 V
HCPL-J454 0.2 0.4 TA = 25°CI
O
= 3.6 mA
0.5 IO = 3.0 mA
HCNW4504 0.2 0.4 TA = 25°CI
O
= 3.6 mA
0.5 IO = 3.0 mA
Logic High IOH 0.003 0.5 µAT
A
= 25°CV
O
= VCC = 5.5 V IF = 0 mA 5
Output Current 0.01 1 TA = 25°CV
O
= V
CC = 15 V
50
Logic Low ICCL HCPL-4504 50 200 µAI
F
= 16 mA, VO = Open, VCC = 15 V 12
Supply Current HCPL-0454
HCNW4504
HCPL-J454 70
Logic High ICCH 0.02 1 µAT
A
= 25°CI
F
= 0 mA, VO = Open, 12
Supply Current 2 VCC = 15 V
Input Forward VFHCPL-4504 1.5 1.7 V TA = 25°CI
F
= 16 mA 3
Voltage HCPL-0454 1.8
HCPL-J454 1.45 1.59 1.85 TA = 25°CI
F
= 16 mA
HCNW4504 1.35 1.95
Input Reverse BVRHCPL-4504 5 V IR = 10 µA
Breakdown HCPL-0454
Voltage HCPL-J454 3 IR = 100 µA
HCNW4504
Temperature ∆VFHCPL-4504 -1.6 mV/°CI
F
= 16 mA
Coefficient of ∆TAHCPL-0454
Forward Voltage HCPL-J454 -1.4
HCNW4504
Input CIN HCPL-4504 60 pF f = 1 MHz, VF = 0 V
Capacitance HCPL-0454
HCPL-J454 70
HCNW4504
*All typicals at TA = 25°C.
Electrical Specifications (DC)
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified. See note 12.
11
AC Switching Specifications
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified.
Parameter Symbol Device Min. Typ. Max. Units Test Conditions Fig. Note
Propagation tPHL 0.2 0.3 TA = 25°C Pulse: f = 20 kHz, 6,
Delay Time µs Duty Cycle = 10%, 8, 9 9
to Logic Low 0.2 0.5 IF = 16 mA, VCC = 5.0 V,
at Output RL = 1.9 kΩ, CL = 15 pF,
VTHHL = 1.5 V
tPHL 0.2 0.5 0.7 µsT
A
= 25°C Pulse: f = 10 kHz, 6,
Duty Cycle = 50%, 10-14 10
HCPL- 0.05 1.0 IF = 12 mA, VCC = 15.0 V,
J454 RL = 20 kΩ, CL = 100 pF,
Others 0.1 VTHHL = 1.5 V
Propagation tPLH 0.3 0.5 TA = 25°C Pulse: f = 20 kHz, 6,
Delay Time µs Duty Cycle = 10%, 8, 9 9
to Logic 0.3 0.7 IF = 16 mA, VCC = 5.0 V,
High at RL = 1.9 kΩ, CL = 15 pF,
Output VTHLH = 1.5 V
tPLH 0.3 0.8 1.1 µsT
A
= 25°C Pulse: f = 10 kHz, 6,
Duty Cycle = 50%, 10-14 10
0.2 0.8 1.4 IF = 12 mA, VCC = 15.0 V,
RL = 20 kΩ, CL = 100 pF,
VTHLH = 2.0 V
Propagation tPLH-tPHL -0.4 0.3 0.9 µsT
A
= 25°C Pulse: f = 10 kHz, 6,
Delay Duty Cycle = 50%, 10-14 17
Difference -0.7 0.3 1.3 IF = 12 mA, VCC = 15.0 V,
Between RL = 20 kΩ, CL = 100 pF,
Any 2 Parts VTHHL = 1.5 V, VTHLH = 2.0 V
Common |CMH| 15 30 kV/µsT
A
= 25°CV
CC = 5.0 V, RL = 1.9 kΩ,
Mode VCM =C
L
= 15 pF, IF = 0 mA 7 7, 9
Transient 1500 VP-P
Immunity at |CMH| 15 30 kV/µsV
CC = 15.0 V, RL = 20 kΩ,
Logic High CL = 100 pF, IF = 0 mA 7 8, 10
Level Output
Common |CML| 15 30 kV/µsT
A
= 25°CV
CC = 5.0 V, RL = 1.9 kΩ,
Mode VCM =C
L
= 15 pF, IF = 16 mA 7 7, 9
Transient 1500 VP-P
Immunity at |CML| 15 30 kV/µsV
CC = 15.0 V, RL = 20 kΩ,
Logic Low CL = 100 pF, IF = 12 mA 7 8, 10
Level Output Others 10
|CML| 15 30 kV/µsV
CC = 15.0 V, RL = 20 kΩ, 7 8, 10
CL = 100 pF, IF = 16 mA
*All typicals at TA = 25°C.
HCPL-
J454
12
Package Characteristics
Over recommended temperature (TA = 0°C to 25°C) unless otherwise specified.
Parameter Sym. Device Min. Typ.* Max. Units Test Conditions Fig. Note
Input-Output VISO HCPL-4504 2500 V rms RH ≤50%, 6, 13,
Momentary HCPL-0454 t = 1 min., 16
Withstand TA = 25°C
Voltage†
HCPL-4504 5000 6, 11,
Option 020 15
HCNW4504 5000 6, 15,
16
Input-Output RI-O HCPL-4504 1012 ΩVI-O = 500 Vdc 6
Resistance HCPL-0454
HCPL-J454
HCNW4504 1012 1013 TA = 25°C
1011 TA = 100°C
Capacitance CI-O HCPL-4504 0.6 pF f = 1 MHz 6
(Input-Output) HCPL-0454
HCPL-J454 0.8
HCNW4504 0.5 0.6
*All typicals at T
A = 25°C..
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if
applicable), your equipment level safety specification or Agilent Application Note 1074 entitled “Optocoupler Input-Output Endurance
Voltage.”
HCPL-J454 3750
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 0.5 mA/°C (SO-8).
2. Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.0 mA/°C (SO-8).
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.1 mW/°C (SO-8).
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 2.3 mW/°C (SO-8).
5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current, IO, to the forward LED input current,
IF, times 100.
6. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive)
dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state
(i.e., VO> 2.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the
trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V).
8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is
the maximum tolerable dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a
Logic High state (i.e., VO > 3.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt on
the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a Logic Low state
(i.e., VO< 1.0 V).
9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
10. The RL = 20 kΩ, CL = 100 pF load represents an IPM (Intelligent Power Module) load.
11. See Option 020 data sheet for more information.
12. Use of a 0.1 µF bypass capacitor connected between Pins 5 and 8 is recommended.
13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥3000 V rms for 1 second
(leakage detection current limit, Ii-o ≤5 µA).
14. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V rms for 1 second
(leakage detection current limit, Ii-o ≤ 5 µA).
15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 V rms for 1 second
(leakage detection current limit, Ii-o ≤5 µA).
16. This test is performed before the 100% Production test shown in the VDE 0884 Insulation Related Characteristics Table, if
applicable.
17. The difference between tPLH and tPHL between any two devices (same part number) under the same test condition. (See Power
Inverter Dead Time and Propagation Delay Specifications section.)
6, 14,
16
13
Figure 1. DC and Pulsed Transfer Characteristics.
Figure 2. Current Transfer Ratio vs. Input Current.
Figure 3. Input Current vs. Forward Voltage.
010 20
V
O
– OUTPUT VOLTAGE – V
I
O
– OUTPUT CURRENT – mA
10
5
0
T = 25°C
V = 5.0 V
A
CC
40 mA
35 mA
30 mA
25 mA
20 mA
15 mA
10 mA
I = 5 mA
F
HCPL-4504/0454
I
O
– OUTPUT CURRENT – mA
0
0
V
O
– OUTPUT VOLTAGE – V
2015
25
5
510
20
15
10
T
A
= 25° C
V
CC
= 5.0 V 40 mA
30 mA
35 mA
25 mA
15 mA
20 mA
10 mA
I
F
= 5 mA
HCPL-J454
010 20
V
O
– OUTPUT VOLTAGE – V
I
O
– OUTPUT CURRENT – mA
20
10
0
T = 25°C
V = 5.0 V
A
CC
40 mA
35 mA
30 mA
25 mA
20 mA
15 mA
10 mA
I = 5 mA
F
HCNW4504
2
4
6
8
12
14
16
18
I
F
– INPUT CURRENT – mA
NORMALIZED CURRENT TRANSFER RATIO
1.5
1.0
0.5
0.0 2 4 6 8 10 12 14 16 18
020 22 24 26
I
F
= 16 mA
V
O
= 0.4 V
V
CC
= 5.0 V
T
A
= 25°C
NORMALIZED
HCPL-4504/0454
NORMALIZED CURRENT TRANSFER RATIO
0
0
IF – INPUT CURRENT – mA
2015
2.0
0.5
510
1.5
1.0
25
NORMALIZED
IF = 16 mA
VO = 0.4 V
VCC = 5.0 V
TA = 25° C
HCPL-J454
I
F
– INPUT CURRENT – mA
NORMALIZED CURRENT TRANSFER RATIO
1.6
0.8
0510150 20 25
I
F
= 16 mA
V
O
= 0.4 V
V
CC
= 5.0 V
T
A
= 25°C
NORMALIZED
HCNW4504
0.4
1.2
2.0
V
F
– FORWARD VOLTAGE – VOLTS
100
10
0.1
0.01
1.1 1.2 1.3 1.4
I
F
– FORWARD CURRENT – mA
1.61.5
1.0
0.001
1000
I
F
V
F
+T = 25°C
A
–
HCPL-4504/0454
V
F
– FORWARD VOLTAGE – VOLTS
100
10
0.1
0.01
1.2 1.3 1.4 1.5
I
F
– FORWARD CURRENT – mA
1.71.6
1.0
0.001
1000
I
F
V
F
+
T = 25°C
A
–
HCPL-J454/HCNW4504
14
Figure 6. Switching Test Circuit.
Figure 4. Current Transfer Ratio vs. Temperature.
Figure 5. Logic High Output Current vs. Temperature.
Figure 7. Test Circuit for Transient Immunity and Typical Waveforms.
T
A
– TEMPERATURE – °C
NORMALIZED CURRENT TRANSFER RATIO
1.0
0.8
0.6
1.1
0.7
0.9
-40 -20 020 40 60 80 100 120-60
I
F
= 16 mA
V
O
= 0.4 V
V
CC
= 5.0 V
T
A
= 25°C
NORMALIZED
HCPL-4504/0454
NORMALIZED CURRENT TRANSFER RATIO
-60
0.85
T
A
– TEMPERATURE – °C
10060
1.05
0.9
-20 20
1.0
0.95
NORMALIZED
I
F
= 16 mA
V
O
= 0.4 V
V
CC
= 5.0 V
T
A
= 25° C
80400-40
HCPL-J454
T
A
– TEMPERATURE – °C
NORMALIZED CURRENT TRANSFER RATIO
1.0
0.9
0.85
1.05
0.95
-40 -20 020 40 60 80 100 120-60
I
F
= 16 mA
V
O
= 0.4 V
V
CC
= 5.0 V
T
A
= 25°C
NORMALIZED
HCNW4504
T
A
– TEMPERATURE – °C
I
OH
– LOGIC HIGH OUTPUT CURRENT – nA
10
4
10
3
10
2
10
1
10
0
10
-1
10
-2
-40 -20 0 20 40 60 80 100 120
-60
I
F
= 0 mA
V
O
= V
CC
= 5.0 V
V
O
PULSE
GEN.
Z = 50 Ω
t = 5 ns
O
r
I MONITOR
F
I
F
0.1µF
L
R
C
L
R
M
0
t
PHL
t
PLH
O
V
I
F
OL
V
THHL
V
THLH
V
V
CC
V
CC
1
2
3
4
8
7
6
5
V
O
I
F
0.1µF
L
R
A
B
PULSE GEN.
V
CM
+
V
FF L
C
O
V
OL
V
O
V
0 V 10% 90% 90% 10%
SWITCH AT A: I = 0 mA
F
SWITCH AT B: I = 12 mA, 16 mA
F
CM
V
t
r
t
f
CC
V
V
CC
–
1
2
3
4
8
7
6
5
15
Figure 11. Propagation Delay Time vs. Temperature.
Figure 8. Propagation Delay Time vs. Temperature.
Figure 10. Propagation Delay Time vs.
Load Resistance.
Figure 9. Propagation Delay Time vs.
Load Resistance.
T
A
– TEMPERATURE – °C
t
p
– PROPAGATION DELAY – µs
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10 -40 -20 0 20 40 60 80 100 120
-60
V
CC
= 5.0 V
R
L
= 1.9 kΩ
C
L
= 15 pF
V
THHL
t
PLH
t
PHL
I
F
= 10 mA
I
F
= 16 mA
= V
THLH
= 1.5 V
10% DUTY CYCLE
HCPL-4504/0454
T
A
– TEMPERATURE – °C
t
p
– PROPAGATION DELAY – µs
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10 -40 -20 0 20 40 60 80 100 120
-60
V
CC
= 5.0 V
R
L
= 1.9 kΩ
C
L
= 15 pF
V
THHL
t
PLH
t
PHL
I
F
= 10 mA
I
F
= 16 mA
= V
THLH
= 1.5 V
10% DUTY CYCLE
HCPL-J454/HCNW4504
R
L
– LOAD RESISTANCE – kΩ
t
p
– PROPAGATION DELAY – µs
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0 2 4 6 8 10 12 14 16 18
020
t
PHL
V
CC
= 5.0 V
T
A
= 25° C
C
L
= 15 pF
V = V = 1.5 V
I
F
= 10 mA
I
F
= 16 mA
t
PLH
10% DUTY CYCLE
THHL THLH
R
L
– LOAD RESISTANCE – kΩ
t
p
– PROPAGATION DELAY – µs
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0 2 4 6 8 10 12 14 16 180 20
1.6
1.8
2.0
2.2
2.4
2.6 V
CC
= 5.0 V
T
A
= 25° C
C
L
= 100 pF
V
THHL
= 1.5 V
V
THLH
= 2.0 V
I
F
= 10 mA
I
F
= 16 mA
t
PLH
t
PHL
50% DUTY CYCLE
T
A
– TEMPERATURE – °C
t
p
– PROPAGATION DELAY – µs
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3 -40 -20 0 20 40 60 80 100 120
-60
V
CC
= 15.0 V
R
L
= 20 kΩ
C
L
= 100 pF
V
THHL
= 1.5 V
V
THLH
= 2.0 V t
PLH
t
PHL
I
F
= 10 mA
I
F
= 16 mA
50% DUTY CYCLE
HCPL-4504/0454
T
A
– TEMPERATURE – °C
t
p
– PROPAGATION DELAY – µs
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3 -40 -20 0 20 40 60 80 100 120
-60
V
CC
= 15.0 V
R
L
= 20 kΩ
C
L
= 100 pF
V
THHL
= 1.5 V
V
THLH
= 2.0 V t
PLH
t
PHL
I
F
= 10 mA
I
F
= 16 mA
50% DUTY CYCLE
HCPL-J454/HCNW4504
16
Figure 14. Propagation Delay Time vs.
Supply Voltage.
Figure 13. Propagation Delay Time vs.
Load Capacitance.
Figure 12. Propagation Delay Time vs.
Load Resistance.
R
L
– LOAD RESISTANCE – kΩ
t
p
– PROPAGATION DELAY – µs
1.6
1.4
1.2
1.0
0.6
0.2
0.0 510152025303540450
V
CC
= 15.0 V
T
A
= 25° C
C
L
= 100 pF
V
THHL
= 1.5 V
V
THLH
= 2.0 V
50
t
PLH
t
PHL
1.8
0.4
0.8
I
F
= 10 mA
I
F
= 16 mA
50% DUTY CYCLE
C
L
– LOAD CAPACITANCE – pF
t
p
– PROPAGATION DELAY – µs
2.0
1.5
0.5
0.0
100 200 300 400 500 600 700 800 9000
V
CC
= 15.0 V
T
A
= 25° C
R
L
= 20 kΩ
V
THHL
= 1.5 V
V
THLH
= 2.0 V
1000
t
PLH
t
PHL
2.5
3.0
3.5
1.0
I
F
= 10 mA
I
F
= 16 mA
50% DUTY CYCLE
V
CC
– SUPPLY VOLTAGE – V
tp – PROPAGATION DELAY – µs
0.9
0.8
0.6
0.2 11 12 13 14 15 16 17 18 1910 20
1.0
1.1
1.2
0.7
T
A
= 25° C
R
L
= 20 kΩ
C
L
= 100 pF
V
V
0.5
0.4
0.3
t
PLH
t
PHL
I
F
= 10 mA
I
F
= 16 mA
50% DUTY CYCLE
THHL
= 1.5 V
= 2.0 V
THLH
Figure 15. Thermal Derating Curve, Dependence of Safety Limiting Valve with
Case Temperature per VDE 0884.
OUTPUT POWER – P
S
, INPUT CURRENT – I
S
0
0
T
S
– CASE TEMPERATURE – °C
20050
400
12525 75 100 150
600
800
200
100
300
500
700
HCPL-4504 OPTION 060/HCPL-J454
175
(230)
P
S
(mW)
I
S
(mA) for HCPL-4504
OPTION 060
I
S
(mA) for HCPL-J454
OUTPUT POWER – P
S
, INPUT CURRENT – I
S
0
0
T
S
– CASE TEMPERATURE – °C
175
1000
50
400
12525 75 100 150
600
800
200
100
300
500
700
900
HCPL-0454 OPTION 060/HCNW4504
P
S
(mW) for HCNW4504
I
S
(mA) for HCNW4504
P
S
(mW) for HCPL-0454
OPTION 060
I
S
(mA) for HCPL-0454
OPTION 060
(150)
17
Figure 16. Typical Power Inverter.
Figure 17. LED Delay and Dead Time Diagram.
LED 1
OUT 1
LED 2
OUT 2
t
PLH min
t
PLH max
t
PHL min
t
PHL max
(t
PLH max
–t
PLH min
)
(t
PHL max
–t
PHL min
)
TURN-ON DELAY
MAXIMUM DEAD TIME
(t
PLH max
–t
PLH min
)
Power Inverter Dead
Time and Propagation
Delay Specifications
The HCPL-4504/0454/J454 and
HCNW4504 include a specifica-
tion intended to help designers
minimize “dead time” in their
power inverter designs. The new
“propagation delay difference”
specification (tPLH -t
PHL) is useful
for determining not only how
much optocoupler switching delay
is needed to prevent “shoot-
through” current, but also for
determining the best achievable
worst-case dead time for a given
design.
When inverter power transistors
switch (Q1 and Q2 in Figure 17),
it is essential that they never
conduct at the same time.
Extremely large currents will flow
if there is any overlap in their
conduction during switching
transitions, potentially damaging
the transistors and even the sur-
rounding circuitry. This “shoot-
through” current is eliminated by
delaying the turn-on of one
transistor (Q2) long enough to
ensure that the opposing
transistor (Q1) has completely
turned off. This delay introduces a
small amount of “dead time” at
the output of the inverter during
which both transistors are off
during switching transitions.
Minimizing this dead time is an
important design goal for an
inverter designer.
The amount of turn-on delay
needed depends on the propaga-
tion delay characteristics of the
optocoupler, as well as the
characteristics of the transistor
base/gate drive circuit. Consider-
ing only the delay characteristics
of the optocoupler (the charac-
teristics of the base/gate drive
circuit can be analyzed in the
BASE/GATE
DRIVE CIRCUIT
HCPL-4504/0454/J454
HCNW4504
2
3
8
7
6
5
+HV
Q1
LED 1
OUT 1
BASE/GATE
DRIVE CIRCUIT
2
3
8
7
6
5
–HV
Q2
LED 2
OUT 2
+
+
HCPL-4504/0454/J454
HCNW4504
which is the maximum minus the
minimum data sheet values of
(tPLH-tPHL). The difference
between the maximum and
minimum values depends directly
on the total spread in propagation
delays and sets the limit on how
good the worst-case dead time
can be for a given design.
Therefore, optocouplers with tight
propagation delay specifications
(and not just shorter delays or
lower pulse-width distortion) can
achieve short dead times in power
inverters. The
HCPL-4504/0454/J454 and
HCNW4504 specify a minimum
(tPLH -t
PHL) of -0.7 µs over an
operating temperature range of
0-70°C, resulting in a maximum
dead time of 2.0 µs when the LED
turn-on delay is equal to
(tPLH-tPHL)max, or 1.3 µs.
It is important to maintain
accurate LED turn-on delays
because delays shorter than
(tPLH -t
PHL)max may allow shoot-
through currents, while longer
delays will increase the worst-case
dead time.
same way), it is important to
know the minimum and maximum
turn-on (tPHL) and turnoff (tPLH)
propagation delay specifications,
preferably over the desired
operating temperature range. The
importance of these specifications
is illustrated in Figure 17. The
waveforms labeled “LED1”,
“LED2”, “OUT1”, and “OUT2” are
the input and output voltages of
the optocoupler circuits driving
Q1 and Q2 respectively. Most
inverters are designed such that
the power transistor turns on
when the optocoupler LED turns
on; this ensures that both power
transistors will be off in the event
of a power loss in the control
circuit. Inverters can also be
designed such that the power
transistor turns off when the
optocoupler LED turns on; this
type of design, however, requires
additional fail-safe circuitry to
turn off the power transistor if an
over-current condition is
detected. The timing illustrated in
Figure 17 assumes that the power
transistor turns on when the
optocoupler LED turns on.
The LED signal to turn on Q2
should be delayed enough so that
an optocoupler with the very
fastest turn-on propagation delay
(tPHLmin) will never turn on before
an optocoupler with the very
slowest turn-off propagation delay
(tPLHmax) turns off. To ensure this,
the turn-on of the optocoupler
should be delayed by an amount
no less than (tPLHmax -t
PHLmin),
which also happens to be the
maximum data sheet value for the
propagation delay difference
specification, (tPLH -t
PHL). The
HCPL-4504/0454/J454 and
HCNW4504 specify a maximum
(tPLH -t
PHL) of 1.3 µs over an
operating temperature range
of 0-70°C.
Although (tPLH-tPHL)max tells the
designer how much delay is
needed to prevent shoot-through
current, it is insufficient to tell the
designer how much dead time a
design will have. Assuming that
the optocoupler turn-on delay is
exactly equal to (tPLH - tPHL)max,
the minimum dead time is zero
(i.e., there is zero time between
the turnoff of the very slowest
optocoupler and the turn-on of
the very fastest optocoupler).
Calculating the maximum dead
time is slightly more complicated.
Assuming that the LED turn-on
delay is still exactly equal to
(tPLH -t
PHL)max, it can be seen in
Figure 17 that the maximum dead
time is the sum of the maximum
difference in turn-on delay plus
the maximum difference in turnoff
delay,
[(tPLHmax-tPLHmin)+(tPHLmax-tPHLmin)].
This expression can be
rearranged to obtain
[(tPLHmax-tPHLmin)-(tPHLmin-tPHLmax)],
and further rearranged to obtain
[(tPLH-tPHL)max-(tPLH-tPHL)min],
18
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2001 Agilent Technologies, Inc.
September 6, 2001
Obsoletes 5968-1091E (11/99)
5988-4106EN
