NTE65101
Integrated Circuit
256 x 4–Bit Static Random Access Memory (SRAM)
Description:
The NTE65101 is a CMOS 1024–bit device organized in 256 words by 4 bits in a 22–Lead DIP type
package. This device offers ultra low power and fully static operation with a single 5V supply. Sepa-
rate data inputs and data outputs permit maximum flexibility in bus–oriented systems. Data retention
at a power supply as low as 2V over temperature readily allows design into applications using battery
backup for nonvolatility. The NTE65101 is fully static and does not require clocking in standby mode.
Features:
DOrganized as 256 Bytes of 4–Bits
DStatic Operation
DLow Standby Power
DThree–State Output
DSingle 5V Power Supply
DData Retention to 2V
DTTL Compatible
DMaximum Access Time: 450ns
Absolute Maximum Ratings: (Voltages referenced to VSS Pin8)
Supply Voltage, VCC –0.5 to +7V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage, Vin –0.3 to VCC +0.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature Range, TA–40° to +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range, Tstg –65° to +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application
of any voltage higher than maximum rated voltages to this high impedance circuit.
DC Electrical Characteristics: (VCC = 5V ±5%, TA = 0° to +70°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Input Current Iin Note 3 –5.0 –nA
Input High Voltage VIH 2.2 –VCC V
Input Low Voltage VIL –0.3 –0.65 V
Output High Voltage VOH IOH = –1mA 2.4 – – V
Output Low Voltage VOL IOL = 2mA – – 0.4 V
Output Leakage Current ILO CE1 = 2.2V, VOL = 0V to VCC, Note 3 – – ±1.0 µA
Operating Current ICC1 Vin = VCC, except CE1 ≤ 0.65V,
Outputs open –9.0 22 mA
ICC2 Vin = 2.2V, except CE1 ≤ 0.65V,
Outputs open –13 27 mA
Standby Current ICCL CE2 ≤ 0.2V, Note 3, Note 4 – – 10 µA
Note 2. Typical values are TA = +25°C and nominal voltage.
Note 3. Current through all inputs and outputs included in ICCL measurement.
Note 4. Low current state is for CE2 = 0 only.
Capacitance:
Parameter Symbol Test Conditions Min Typ Max Unit
Input Capacitance Cin Vin = 0V –4.0 8.0 pF
Output Capacitance Cout Vout = 0V –8.0 12.0 pF
Note 2. Typical values are TA = +25°C and nominal voltage.
Low VCC Retention Characteristics: (TA = 0° to +70°C unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
VCC for Data Retention VDR 2.0 – – V
Data Retention Current ICCDR1 CE2 ≤ 0.2V, VDR = 2V –0.14 10 µA
Chip Deselect to Data Retention Time tCDR 0– – ns
Operation Recovery Time tRNote 5 tRC – – ns
Note 2. Typical values are TA = +25°C and nominal voltage.
Note 5. tRC = Read Cycle Time.
AC Operating Conditions and Characteristics: (Full operating voltage and temperature unless
otherwise specified)
AC Test Conditions: Condition Value
Input Pulse Levels +0.65V to 2.2V
Input Rise and Fall Times 20ns
Output Load –1 TTL Gate and CL = 100pF
Timing Measurement Reference Level 1.5V
AC Operating Conditions and Characteristics (Cont’d): (Full operating voltage and temperature
unless otherwise specified)
Read Cycle:
Parameter Symbol Min Max Unit
Read Cycle Time tRC 450 –ns
Access Time tA–450 ns
Read Cycle (Cont’d):
Parameter Symbol Min Max Unit
Address Setup Time tAS 20 –ns
Address Hold Time tAH 0–ns
Chip Enable (CE1) to Output tCO1 –400 ns
Chip Enable (CE2) to Output tCO2 –500 ns
Output Disable to Output tOD –250 ns
Data Output to High Z State tDF 0130 ns
Previous Read Data Valid with Respect to Address Change tOH1 0–ns
Previous Read Data Valid with Respect to Chip Enable tOH2 0–ns
Write Cycle:
Parameter Symbol Min Max Unit
Write Cycle tWC 450 –ns
Write Delay tAW 130 –ns
Chip Enable (CE1) to Write tCW1 350 –ns
Chip Enable (CE2) to Write tCW2 350 –ns
Data Setup tDW 250 –ns
Data Hold tDH 50 –ns
Write Pulse tWP 250 –ns
Write Recovery tWR 50 –ns
Output Disable Setup tDS 130 –ns
Truth Table:
CE1 CE2 OD R/W Din Output Mode
H X X X X High Z Not Selected
X L X X X High Z Not Selected
X X H H X High Z Output Disable
L H H L X High Z Write
L H L L X Din Write
L H L H X Dout Read
CE 1
VCC
Pin Connection Diagram
DO 3
R/W
GND
A5
A0
A1
A6 OD
DI 4
A7
A2 1
2
3
4
A3
5
6
7
22
21
20
19
A4
18
17 CD 2
16
8 15
DO 1 9 14
DI 1 DI 3
10 13
DI 2 11 12 DO 2
DO 4
22 12
111
1.300 (33.0)
1.000 (25.4)
.100 (2.54)
.410
(11.41)
.216
(5.5)
.110 (2.79)
.400
(10.16)
