ispLSI® 1048E
In-System Programmable High Density PLD
1048e_12 1
USE ispLSI 1048EA FOR NEW DESIGNS
Lead-
Free
Package
Options
Available!
Functional Block DiagramFeatures
• HIGH DENSITY PROGRAMMABLE LOGIC
— 8,000 PLD Gates
— 96 I/O Pins, Twelve Dedicated Inputs
— 288 Registers
— High-Speed Global Interconnects
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally and Pin-out Compatible to ispLSI 1048C
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
—fmax = 125 MHz Maximum Operating Frequency
—tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Eraseable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
Output Routing Pool
Output Routing Pool
F7 F6 F5 F4 F3 F2 F1 F0
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
Output Routing Pool
Output Routing Pool
Output Routing Pool
CLK
E7 E6 E5 E4 E3 E2 E1 E0
C0 C1 C2 C3 C4 C5 C6 C7
D7
D6
D5
D4
D3
D2
D1
D0
Output Routing Pool
Logic
Array
DQ
DQ
DQ
DQ
Global Routing Pool (GRP) GLB
0139G1A-isp
Description
The ispLSI 1048E is a High Density Programmable Logic
Device containing 288 Registers, 96 Universal I/O pins,
12 Dedicated Input pins, four Dedicated Clock Input pins,
two dedicated Global OE input pins, and a Global Routing
Pool (GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1048E offers
5V non-volatile in-system programmability of the logic, as
well as the interconnect to provide truly reconfigurable
systems. A functional superset of the ispLSI 1048 archi-
tecture, the ispLSI 1048E device adds two new global
output enable pins and two additional dedicated inputs.
The basic unit of logic on the ispLSI 1048E device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…F7 (see Figure 1). There are a total of 48 GLBs in the
ispLSI 1048E device. Each GLB has 18 inputs, a pro-
grammable AND/OR/Exclusive OR array, and four outputs
which can be configured to be either combinatorial or
registered. Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
of any other GLB on the device.
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Specifications ispLSI 1048E
2
USE ispLSI 1048EA FOR NEW DESIGNS
Functional Block Diagram
Figure 1. ispLSI 1048E Functional Block Diagram
The device also has 96 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional
I/O pin with 3-state control. The signal levels are TTL
compatible voltages and the output drivers can source 4
mA or sink 8 mA. Each output can be programmed
independently for fast or slow output slew rate to mini-
mize overall output switching noise.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. Each ispLSI
1048E device contains six Megablocks.
The GRP has, as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1048E device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (D0). The logic
of this GLB allows the user to create an internal clock
from a combination of internal signals within the device.
Output Routing Pool (ORP)
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool (ORP)
C0 C1 C2 C3 C4 C5 C6 C7
Output Routing Pool (ORP)
F7 F6 F5 F4 F3 F2 F1 F0
Input Bus
Output Routing Pool (ORP)
E7 E6 E5 E4 E3 E2 E1 E0
Input Bus
A0
A1
A2
A3
A4
A5
A6
A7
Output Routing Pool (ORP)
Generic
Logic Blocks
(GLBs)
Megablock
Input Bus
Global
Routing
Pool
(GRP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Clock
Distribution
Network
D7
D6
D5
D4
D3
D2
D1
D0
Output Routing Pool (ORP)
I/O
94
I/O
95
I/O
93
I/O
92
I/O
91
I/O
90
I/O
89
I/O
88
I/O
87
I/O
86
I/O
85
I/O
84
I/O
83
I/O
82
I/O
81
I/O
80
IN
11
I/O
78
I/O
79
I/O
77
I/O
76
I/O
75
I/O
74
I/O
73
I/O
72
I/O
71
I/O
70
I/O
69
I/O
68
I/O
67
I/O
66
I/O
65
I/O
64
IN
9
IN
10
I/O
17
I/O
16
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
SDO/
IN 3
Y
0
Y
1
Y
2
Y
3
I/O
33
I/O
32
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
I/O
43
I/O
44
I/O
45
I/O
46
I/O
47
SCLK/
IN 5
IN
4
IN 7
IN 6
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDI/IN 0
MODE/IN 1
I/O 4
I/O 5
ispEN
RESET
Input Bus Input Bus
lnput Bus
0139F(2)-48B-isp
IN
8
GOE 0
GOE 1
IN 2
Specifications ispLSI 1048E
3
USE ispLSI 1048EA FOR NEW DESIGNS
Absolute Maximum Ratings 1
Supply Voltage Vcc. ................................. -0.5 to +7.0V
Input Voltage Applied........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
Capacitance (TA=25oC, f=1.0 MHz)
Data Retention Specifications
C
SYMBOL
Table 2-0006/1048E
C
PARAMETER
Y0 Clock Capacitance 15
UNITSTYPICAL TEST CONDITIONS
1
2
8
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance
pf
pf
V = 5.0V, V = 2.0V
V = 5.0V, V = 2.0V
CC
CC PIN
PIN
TA = 0°C to + 70°C
TA = -40°C to + 85°C
SYMBOL
Table 2-0005/1048E
VCC
VIH
VIL
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
MIN. MAX. UNITS
4.75
4.5
2.0
0
5.25
5.5
Vcc+1
0.8
V
V
V
V
Commercial
Industrial
Table 2-0008/1048E
PARAMETER
Data Retention
MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles
20
10000
–
–
Years
Cycles
Specifications ispLSI 1048E
4
USE ispLSI 1048EA FOR NEW DESIGNS
Switching Test Conditions
DC Electrical Characteristics
Over Recommended Operating Conditions
Output Load Conditions (see Figure 2)
Figure 2. Test Load
Input Pulse Levels
Table 2-0003/1048E
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
≤ 3 ns 10% to 90%
+ 5V
R1
R2CL*
Device
Output
Test
Point
*CL includes Test Fixture and Probe Capacitance.
0213a
TEST CONDITION R1 R2 CL
A 470Ω390Ω35pF
B∞390Ω35pF
470Ω390Ω35pF
Active High
Active Low
C
470Ω390Ω5pF
∞390Ω5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2-0004a
VOL
SYMBOL
1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using twelve 16-bit counters.
3. Typical values are at V = 5V and T = 25°C.
4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I .
Table 2-0007/1048E
1
VOH
IIH
IIL
IIL-isp
PARAMETER
IIL-PU
IOS
2, 4
ICC
Output Low Voltage
Output High Voltage
Input or I/O High Leakage Current
Input or I/O Low Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I = 8 mA
I = -4 mA
3.5V ≤ V ≤ V
0V ≤ V ≤ V (Max.)
0V ≤ V ≤ V
0V ≤ V ≤ V
V = 5V, V = 0.5V
V = 0.0V, V = 3.0V
f = 1 MHz
OL
OH
IN IL
IN CC
IN
IL
IN IL
CC OUT
CLOCK
IL IH
CONDITION MIN. TYP. MAX. UNITS
3
–
2.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
175
175
0.4
–
10
-10
-150
-150
-200
–
–
V
V
μA
μA
μA
μA
mA
mA
mA
CC A
OUT
CC
CC
Commercial
Industrial
Specifications ispLSI 1048E
5
USE ispLSI 1048EA FOR NEW DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
tpd1
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/1048E
1
4
3
1
tsu2 + tco1
( )
-90
MIN. MAX.
DESCRIPTION#2
PARAMETER
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 ns
tpd2 A 2 Data Propagation Delay, Worst Case Path – ns
fmax (Int.) A 3 Clock Frequency with Internal Feedback 90.9 – MHz
fmax (Ext.) – 4 Clock Frequency with External Feedback – MHz
fmax (Tog.) – 5 Clock Frequency, Max. Toggle – MHz
tsu1 – 6 GLB Reg. Setup Time before Clock,4 PT Bypass – ns
tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – ns
th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass – ns
tsu2 – 9 GLB Reg. Setup Time before Clock – ns
tco2 – 10 GLB Reg. Clock to Output Delay – ns
th2 – 11 GLB Reg. Hold Time after Clock – ns
tr1 A 12 Ext. Reset Pin to Output Delay – ns
trw1 – 13 Ext. Reset Pulse Duration – ns
tptoeen B 14 Input to Output Enable – ns
tptoedis C 15 Input to Output Disable – ns
twh – 18 External Synchronous Clock Pulse Duration, High 4.0 ns
twl – 19 External Synchronous Clock Pulse Duration, Low 4.0 ns
tsu3 – 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) – ns
th3 – 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) – ns
71.0
125.0
6.5
0.0
7.5
0.0
6.5
4.0
0.0
12.5
6.5
7.5
13.5
15.0
15.0
–
–
( )
1
twh + twl
tgoeen B 16 Global OE Output Enable – ns9.0
tgoedis C 17 Global OE Output Disable – ns
-125
MIN. MAX.
– 7.5
–
125.0 –
–
–
–
–
0.0
6.5
–
0.0
–
5.0
–
–
3.0
3.0
3.0 –
0.0 –
91.0
167.0
5.5
4.5
–
–
5.5
–
10.0
–
12.0
12.0
–
–
10.0
– 7.0
– 7.0 9.0
-100
MIN. MAX.
– 10.0
–
100.0 –
–
–
–
–
–
–
–
–
–
–
–
–
4.0
4.0
–
–
71.0
125.0
6.5
0.0
7.5
0.0
6.5
3.5
0.0
12.5
6.5
7.5
13.5
15.0
15.0
–
–
– 9.0
– 9.0
Specifications ispLSI 1048E
6
USE ispLSI 1048EA FOR NEW DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
tpd1
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B/1048E
1
4
3
1
tsu2 + tco1
( )
-50
MIN. MAX.
DESCRIPTION#2
PARAMETER
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 20.0 ns
tpd2 A 2 Data Propagation Delay, Worst Case Path – ns
fmax (Int.) A 3 Clock Frequency with Internal Feedback 50.0 – MHz
fmax (Ext.) – 4 Clock Frequency with External Feedback – MHz
fmax (Tog.) – 5 Clock Frequency, Max. Toggle – MHz
tsu1 – 6 GLB Reg. Setup Time before Clock,4 PT Bypass – ns
tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – ns
th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass – ns
tsu2 – 9 GLB Reg. Setup Time before Clock – ns
tco2 – 10 GLB Reg. Clock to Output Delay – ns
th2 – 11 GLB Reg. Hold Time after Clock – ns
tr1 A 12 Ext. Reset Pin to Output Delay – ns
trw1 – 13 Ext. Reset Pulse Duration – ns
tptoeen B 14 Input to Output Enable – ns
tptoedis C 15 Input to Output Disable – ns
twh – 18 External Synchronous Clock Pulse Duration, High 6.5 ns
twl – 19 External Synchronous Clock Pulse Duration, Low 6.5 ns
tsu3 – 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) – ns
th3 – 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) – ns
42.0
77.0
12.0
0.0
14.5
0.0
13.0
6.5
0.0
24.5
9.5
12.0
20.5
24.0
24.0
–
–
( )
1
twh + twl
tgoeen B 16 Global OE Output Enable – ns16.0
tgoedis C 17 Global OE Output Disable – ns16.0
-70
MIN. MAX.
– 15.0
–
70.0 –
–
–
–
–
–
–
–
–
–
–
–
–
5.0
5.0
–
–
56.0
100.0
9.0
0.0
11.0
0.0
10.0
4.0
0.0
18.5
7.0
9.0
15.0
18.0
18.0
–
–
– 12.0
– 12.0
Specifications ispLSI 1048E
7
USE ispLSI 1048EA FOR NEW DESIGNS
Internal Timing Parameters1
tiobp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/1048E
Inputs
UNITS
-100
MIN.
-90
MIN.MAX. MAX.
DESCRIPTION
#
2
PARAMETER
22 I/O Register Bypass – – 0.5 ns
tiolat 23 I/O Latch Delay – – 2.5 ns
tgrp1 29 GRP Delay, 1 GLB Load – – 2.2 ns
GLB
t1ptxor 36 1 Product Term/XOR Path Delay – – 6.5 ns
t20ptxor 37 20 Product Term/XOR Path Delay – – 6.5 ns
txoradj 38 XOR Adjacent Path Delay – – 7.3 ns
tgbp 39 GLB Register Bypass Delay – – 0.4 ns
tgsu 40 GLB Register Setup Time before Clock – 0.1 – ns
tgh 41 GLB Register Hold Time after Clock – 6.4 – ns
tgco 42 GLB Register Clock to Output Delay – – 2.0 ns
3
tgro 43 GLB Register Reset to Output Delay – – 6.3 ns
tptre 44 GLB Product Term Reset to Register Delay – – 5.0 ns
tptoe 45 GLB Product Term Output Enable to I/O Cell Delay – – 5.7 ns
tptck 46 GLB Product Term Clock Delay 4.0 5.2 ns
ORP
0.3
2.3
GRP
1.9
t4ptbpc 34 4 Product Term Bypass Path Delay (Combinatorial) – – 5.4 ns
4.6
5.8
6.3
1.0
5.3
t4ptbpr 35 4 Product Term Bypass Path Delay (Registered) – – 6.3 ns5.3
0.5
5.3
2.5
6.2
4.5
7.2
3.5 4.7
torp 47 ORP Delay – – 1.0 ns
torpbp 48 ORP Bypass Delay – – 0.0 ns
1.0
0.0
tiosu 24 I/O Register Setup Time before Clock 3.5 4.0 – ns–
tioh 25 I/O Register Hold Time after Clock 0.0 -0.5 – ns–
tioco 26 I/O Register Clock to Out Delay – – 5.0 ns5.0
tior 27 I/O Register Reset to Out Delay – – 5.0 ns5.0
tdin 28 Dedicated Input Delay – – 2.9 ns2.7
tgrp4 30 GRP Delay, 4 GLB Loads – – 2.4 ns
tgrp8 31 GRP Delay, 8 GLB Loads – – 2.7 ns
tgrp16 32 GRP Delay, 16 GLB Loads – – 3.3 ns
tgrp48 33 GRP Delay, 48 GLB Loads – – 5.7 ns
2.4
2.6
3.0
5.4
-125
MIN. MAX.
–
–
–
–
–
–
–
–
–
–
–
–
–
0.3
1.9
1.8
–
3.6
5.0
5.0
0.4
3.9
– 4.0
0.1
4.5
2.3
4.9
3.9
5.4
2.9 4.0
–
–
1.0
0.0
3.0 –
0.0 –
– 4.6
– 4.6
– 2.3
–
–
–
–
2.0
2.3
2.8
4.9
Specifications ispLSI 1048E
8
USE ispLSI 1048EA FOR NEW DESIGNS
Internal Timing Parameters1
tiobp
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036B/1048E
Inputs
UNITS
-70
MIN.
-50
MIN.MAX. MAX.
DESCRIPTION
#
2
PARAMETER
22 I/O Register Bypass – – 0.7 ns
tiolat 23 I/O Latch Delay – – 4.7 ns
tgrp1 29 GRP Delay, 1 GLB Load – – 5.1 ns
GLB
t1ptxor 36 1 Product Term/XOR Path Delay – – 10.5 ns
t20ptxor 37 20 Product Term/XOR Path Delay – – 10.5 ns
txoradj 38 XOR Adjacent Path Delay – – 11.7 ns
tgbp 39 GLB Register Bypass Delay – – 2.2 ns
tgsu 40 GLB Register Setup Time before Clock – 0.0 – ns
tgh 41 GLB Register Hold Time after Clock – 11.5 – ns
tgco 42 GLB Register Clock to Output Delay – – 3.0 ns
3
tgro 43 GLB Register Reset to Output Delay – – 7.3 ns
tptre 44 GLB Product Term Reset to Register Delay – – 7.9 ns
tptoe 45 GLB Product Term Output Enable to I/O Cell Delay – – 10.0 ns
tptck 46 GLB Product Term Clock Delay 6.9 8.3 ns
ORP
0.6
3.6
GRP
3.5
t4ptbpc 34 4 Product Term Bypass Path Delay (Combinatorial) – – 10.7 ns
8.4
8.4
9.4
1.6
8.5
t4ptbpr 35 4 Product Term Bypass Path Delay (Registered) – – 9.2 ns7.4
0.1
8.5
2.0
6.3
6.1
6.8
5.1 6.4
torp 47 ORP Delay – – 2.5 ns
torpbp 48 ORP Bypass Delay – – 0.0 ns
2.0
0.0
tiosu 24 I/O Register Setup Time before Clock 4.1 6.5 – ns–
tioh 25 I/O Register Hold Time after Clock -0.6 -0.7 – ns–
tioco 26 I/O Register Clock to Out Delay – – 7.0 ns6.0
tior 27 I/O Register Reset to Out Delay – – 7.0 ns6.0
tdin 28 Dedicated Input Delay – – 6.1 ns4.3
tgrp4 30 GRP Delay, 4 GLB Loads – – 5.4 ns
tgrp8 31 GRP Delay, 8 GLB Loads – – 5.8 ns
tgrp16 32 GRP Delay, 16 GLB Loads – – 6.6 ns
tgrp48 33 GRP Delay, 48 GLB Loads – – 9.8 ns
3.7
4.1
4.8
7.5
Specifications ispLSI 1048E
9
USE ispLSI 1048EA FOR NEW DESIGNS
Internal Timing Parameters1
tob
1. Internal timing parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Table 2-0037A/1048E
Outputs
UNITS
-100
MIN.
-90
MIN.MAX. MAX.
DESCRIPTION
#
PARAMETER
49 Output Buffer Delay – – 1.7 ns
toen 51 I/O Cell OE to Output Enabled – – 6.4 ns
tgy0 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 2.0 2.8 2.8 ns
Global Reset
2.0
5.1
Clocks
2.0
tgr 59 Global Reset to GLB and I/O Registers – – 4.5 ns4.3
todis 52 I/O Cell OE to Output Disabled – – 6.4 ns5.1
tgy1/2 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.0 2.8 2.8 ns2.0
tgcp 56 Clock Delay, Clock GLB to Global GLB Clock Line 0.8 0.8 1.8 ns1.8
tioy2/3 57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 0.0 0.0 0.5 ns0.0
tiocp 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 0.8 0.8 1.8 ns1.8
tgoe 53 Global OE – – 2.6 ns3.9
tsl 50 Output Slew Limited Delay Adder – – 12.0 ns10.0
-125
MIN. MAX.
–
–
0.9
1.3
4.3
0.9
– 2.8
– 4.3
0.9 0.9
0.8 1.8
0.0 0.0
0.8 1.8
– 2.7
– 10.0
Specifications ispLSI 1048E
10
USE ispLSI 1048EA FOR NEW DESIGNS
Internal Timing Parameters1
tob
1. Internal timing parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
Table 2-0037B/1048E
Outputs
UNITS
-70
MIN.
-50
MIN.MAX. MAX.
DESCRIPTION
#
PARAMETER
49 Output Buffer Delay – – 3.2 ns
toen 51 I/O Cell OE to Output Enabled – – 7.9 ns
tgy0 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 2.8 3.3 3.3 ns
Global Reset
2.2
6.9
Clocks
2.8
tgr 59 Global Reset to GLB and I/O Registers – – 7.5 ns4.5
todis 52 I/O Cell OE to Output Disabled – – 7.9 ns6.9
tgy1/2 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 2.8 3.3 3.3 ns2.8
tgcp 56 Clock Delay, Clock GLB to Global GLB Clock Line 0.8 0.8 1.8 ns1.8
tioy2/3 57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 0.1 0.0 0.7 ns0.6
tiocp 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 0.8 0.8 1.8 ns1.8
tgoe 53 Global OE – – 8.1 ns5.1
tsl 50 Output Slew Limited Delay Adder – – 12.0 ns12.0
Specifications ispLSI 1048E
11
USE ispLSI 1048EA FOR NEW DESIGNS
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
0491
Feedback
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
Input
Register
Clock
Distribution
I/O Pin
(Input)
Y0
Y1,2,3
DQ
GRP4 GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Reg Bypass
I/O CellORPGLBGRPI/O Cell
#23 - 27
#30 #35
#34 Comb 4 PT Bypass
#36 - 38
#55 - 58 #44 - 46
#54
#53
#47
#48
Reset
Ded. In
GOE 0,1
#28
#22
RST
#59
#59
#39
#40 - 43
#51, 52
#49, 50
GRP Loading
Delay
#29, 31-33
Derivations of tsu, th and tco from the Product Term Clock1
=
=
=
=
tsu
2.2 ns
Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) – (tiobp + tgrp4 + tptck(min))
(#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
(0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
=
=
=
=
th Clock (max) + Reg h - Logic
(tiobp + tgrp4 + tptck(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)
=
=
=
=
tco
Clock (max) + Reg co + Output
(tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
(#22 + #30 + #46) + (#42) + (#47 + #49)
(0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
Table 2-0042/1048E
Derivations of tsu, th and tco from the Clock GLB 1
=
=
=
=
tsu
Logic + Reg su - Clock (min)
(tiobp + tgrp4 + t20ptxor) + (tgsu) – (tgy0(min) + tgco + tgcp(min))
(#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
(0.3 + 2.0 + 5.0) + (0.1) – (0.9 + 2.3 + 0.8)
=
=
=
=
th
Clock (max) + Reg h - Logic
(tgy0(max) + tgco + tgcp(max)) + (tgh) – (tiobp + tgrp4 + t20ptxor)
(#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
(0.9 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)
=
=
=
=
tco
Clock (max) + Reg co + Output
(tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
(#54 + #42 + #56) + (#42) + (#47 + #49)
(0.9 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
3.5 ns
10.9 ns
3.4 ns
2.2 ns
9.6 ns
1. Calculations are based upon timing specifications for the ispLSI 1048E-125.
ispLSI 1048E Timing Model
Specifications ispLSI 1048E
12
USE ispLSI 1048EA FOR NEW DESIGNS
Maximum GRP Delay vs. GLB Loads
3
1816 32
GLB Loads
GRP Delay (ns)
2
1
4
5
6
7
4
0127A/1048E
8
48
ispLSI 1048E-50
ispLSI 1048E-70
ispLSI 1048E-90/100
ispLSI 1048E-125
9
10
ICC can be estimated for the ispLSI 1048E using the following equation:
ICC = 20 + (# of PTs * 0.42) + (# of nets * Max. freq * 0.010)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 4 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
0127B/1048E
Notes: Configuration of twelve 16-bit counters,
Typical current at 5V, 25°C
180
220
260
300
340
380
0 20 40 60 80 100 120 140
fmax (MHz)
ICC (mA)
ispLSI 1048E
Power Consumption
Power consumption in the ispLSI 1048E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
Figure 3 shows the relationship between power and
operating speed.
Figure 3. Typical Device Power Consumption vs fmax
Specifications ispLSI 1048E
13
USE ispLSI 1048EA FOR NEW DESIGNS
Pin Description
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
NAME
Table 2 - 0002C-48E
PQFP / TQFP PIN NUMBERS DESCRIPTION
21,
27,
34,
40,
52,
58,
66,
72,
85,
91,
98,
104,
117,
123,
2,
8,
22,
28,
35,
41,
53,
59,
67,
73,
86,
92,
99,
105,
118,
124,
3,
9,
23,
29,
36,
42,
54,
60,
68,
74,
87,
93,
100,
106,
119,
125,
4,
10,
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
24,
30,
37,
43,
55,
61,
69,
75,
88,
94,
101,
107,
120,
126,
5,
11,
25,
31,
38,
44,
56,
62,
70,
76,
89,
95,
102,
108,
121,
127,
6,
12,
83Y1
15Y0
46MODE/IN 1
1
Input - This pin performs two functions. When ispEN is logic low, it
functions as pin to control the operation of the isp state machine. When
ispEN is high, it functions as a dedicated input pin.
Ground (GND)
GND
V
VCC
1. Pins have dual function capability.
CC
26,
32,
39,
45,
57,
63,
71,
77,
90,
96,
103,
109,
122,
128,
7,
13
Global Output Enable input pins.GOE0, GOE1
Dedicated input pins to the device.IN 2, IN 4
64, 114
47, 51
84, 110, 111,IN 6 - IN 11 115, 116, 14
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. When low, the MODE,
SDI, SDO and SCLK controls become active.
18ispEN
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 also is used as one of the two control pins for the ISP state
machine. When ispEN is high, it functions as a dedicated input pin.
20SDI/IN 0
1
50SDO/IN 3
1
Output/Input - This pin performs two functions. When ispEN is logic low,
it functions as an output pin to read serial shift register data. When
ispEN is high, it functions as a dedicated input pin.
78SCLK/IN 5
1
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
19RESET
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
80Y2
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
79Y3
1,
97,
17,
112
33, 49, 65, 81,
16, 48, 82, 113
Specifications ispLSI 1048E
14
USE ispLSI 1048EA FOR NEW DESIGNS
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
IN 11
Y0
VCC
GND
ispEN
RESET
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
GND
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
Y1
VCC
GND
Y2
SCLK/IN 5
1
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
IN 10
IN 9
VCC
IN 8
IN 7
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
1MODE/IN 1
VCC
GND
1SDO/IN 3
IN 4
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
ispLSI 1048E
Top View
I/O 10
1SDI/IN 0
I/O 59
GND
Y3
GND
GND
IN 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
128
127
126
125
124
123
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
9764
96
122
GOE 0
GOE 1
0124-48C
1. Pins have dual function capability.
Pin Configuration
ispLSI 1048E 128-Pin PQFP Pinout Diagram
Specifications ispLSI 1048E
15
USE ispLSI 1048EA FOR NEW DESIGNS
Pin Configuration
ispLSI 1048E 128-Pin TQFP Pinout Diagram
I/O 84
I/O 85
I/O 86
I/O 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
I/O 95
IN 11
Y0
VCC
GND
ispEN
RESET
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
GND
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
IN 6
Y1
VCC
GND
Y2
SCLK/IN 51
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
IN 10
IN 9
VCC
IN 8
IN 7
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
I/O 63
I/O 62
I/O 61
I/O 60
GND
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
1
MODE/IN 1
VCC
GND
1
SDO/IN 3
IN 4
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
I/O 32
I/O 33
I/O 34
I/O 35
ispLSI 1048E
Top View
I/O 10
1SDI/IN 0
I/O 59
GND
Y3
GND
GND
IN 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
128
127
126
125
124
123
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
9764
96
122
GOE 0
GOE 1
1. Pins have dual function capability.
0124-48/TQFP
Specifications ispLSI 1048E
16
USE ispLSI 1048EA FOR NEW DESIGNS
Part Number Description
ispLSI 1048E Ordering Information
50
50
128-Pin PQFP20
20
ispLSI 1048E-50LQ
128-Pin TQFPispLSI 1048E-50LT
Table 2-0041A/1048E
FAMILY fmax (MHz)
90
90
70
ORDERING NUMBER PACKAGE
128-Pin PQFP
128-Pin TQFP
tpd (ns)
10
10
15
ispLSI ispLSI 1048E-90LQ
ispLSI 1048E-90LT
128-Pin PQFPispLSI 1048E-70LQ
70 128-Pin TQFP15 ispLSI 1048E-70LT
125
125
100
128-Pin PQFP
128-Pin TQFP
7.5
7.5
10
ispLSI 1048E-125LQ
ispLSI 1048E-125LT
128-Pin PQFPispLSI 1048E-100LQ
100 128-Pin TQFP10 ispLSI 1048E-100LT
COMMERCIAL
70 128-Pin PQFP15 ispLSI 1048E-70LQI*
50 128-Pin PQFP20 ispLSI 1048E-50LQI*
Table 2-0041B/1048E
FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)
ispLSI
INDUSTRIAL
*Use 1048E-70 for new 1048E-50 designs.
Package Thermal Characteristics
For the ispLSI 1048E-125LT, it is strongly recommended
that the actual Icc be verified to ensure that the maximum
junction temperature (TJ) with power supplied is not
exceeded. Depending on the specific logic design and
clock speed, airflow may be required to satisfy the maxi-
mum allowable junction temperature (TJ) specification.
Please refer to the Thermal Management section of the
Lattice Semiconductor Data Book or CD-ROM for addi-
tional information on calculating TJ.
Conventional Packaging
Grade
Blank = Commercial
I = Industrial
Device Number
1048E XXX X X X
Speed
125 = 125 MHz
f
max
100 = 100 MHz
f
max
90 = 90 MHz
f
max
70 = 70 MHz
f
max
50 = 50 MHz
f
max Power
L = Low
Package
Q = PQFP
T = TQFP
QN = Lead-Free PQFP
TN = Lead-Free TQFP
–
Device Family
ispLSI
Specifications ispLSI 1048E
17
USE ispLSI 1048EA FOR NEW DESIGNS
ispLSI 1048E Ordering Information (Cont.)
Lead-Free Packaging
50
50
Lead-Free 128-Pin PQFP20
20
ispLSI 1048E-50LQN
Lead-Free 128-Pin TQFPispLSI 1048E-50LTN
FAMILY fmax (MHz)
90
90
70
ORDERING NUMBER PACKAGE
Lead-Free 128-Pin PQFP
Lead-Free 128-Pin TQFP
tpd (ns)
10
10
15
ispLSI ispLSI 1048E-90LQN
ispLSI 1048E-90LTN
Lead-Free 128-Pin PQFPispLSI 1048E-70LQN
70 Lead-Free 128-Pin TQFP15 ispLSI 1048E-70LTN
125
125
100
Lead-Free 128-Pin PQFP
Lead-Free 128-Pin TQFP
7.5
7.5
10
ispLSI 1048E-125LQN
ispLSI 1048E-125LTN
Lead-Free 128-Pin PQFPispLSI 1048E-100LQN
100 Lead-Free 128-Pin TQFP10 ispLSI 1048E-100LTN
COMMERCIAL
70
Lead-Free 128-Pin PQFP
15 ispLSI 1048E-70LQNI
FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns)
ispLSI
INDUSTRIAL
Revision History
Date Version
12
11
August 2006
—
Change Summary
Updated for lead-free package options.
Previous Lattice release.
