LT3061 Series
1
3061fb
For more information www.linear.com/LT3061
TYPICAL APPLICATION
FEATURES DESCRIPTION
45V VIN, Micropower, Low
Noise, 100mA LDO
with Active Output Discharge
The LT
®
3061 is a micropower, low dropout (LDO) linear
regulator that operates over a 1.6V to 45V supply range
and is available in a series of fixed output and adjustable
versions. The device supplies 100mA of output current
with a typical dropout voltage of 250mV. A single external
capacitor provides programmable low noise reference
performance and output soft-start functionality. The
LT3061’s quiescent current is merely 45μA and provides
fast transient response with a minimum 3.3μF output ca-
pacitor. In shutdown, quiescent current is less than 3μA
and the reference soft start capacitor is reset.
The LT3061 features an NMOS pull-down that discharges
the output when SHDN or IN is driven low.
Internal protection circuitry includes reverse-battery
protection, reverse-current protection, current limit with
foldback and thermal shutdown.
The LT3061 is available in fixed output voltages of 3.3V
and 5V, and as an adjustable device with an output voltage
range from the 600mV reference up to 19V. The LT3061
is offered in the thermally enhanced 8-lead 2mm × 3mm
DFN and MSOP packages.
3.3V Low Noise Regulator
LT3061-3.3
Active Output Discharge
APPLICATIONS
n Input Voltage Range: 1.6V to 45V
n Output Current: 100mA
n Output Discharge
n Quiescent Current: 45µA
n Dropout Voltage: 250mV
n Low Noise: 30µVRMS (10Hz to 100kHz)
n Adjustable Output (VREF = 600mV)
n Fixed Output Voltages: 3.3V, 5V
n Output Tolerance: ±2% Over Load, Line, and
Temperature
n Single Capacitor Soft-Starts Reference and Lowers
Output Noise
n Shutdown Current: < 3µA
n Reverse Battery Protection
n Current Limit Foldback and Thermal Limit Protection
n 8-Lead 2mm × 3mm DFN and MSOP Packages
n Battery Powered Systems
n Automotive Power Supplies
n Industrial Power Supplies
n Avionic Power Supplies
n Portable Instruments All registered trademarks and trademarks are the property of their respective owners.
3061 TA01
IN
SHDN
OUT
ADJ
GND BYP
LT3061-3.3
VIN
5V
VOUT
3.3V
100mA
1µF 10µF
10nF
10nF
1ms/DIV
0.5V/DIV
1V
3.3V
0V
3061 TA01a
COUT = 10µF
IL = 0
SHDN
LT3061 Series
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3061fb
For more information www.linear.com/LT3061
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
IN Pin Voltage .........................................................±50V
OUT Pin Voltage .............................................. +20V, –1V
Input to Output Differential Voltage (Note 2) ...........±50V
ADJ Pin Voltage ......................................................±50V
SHDN Pin Voltage ...................................................±50V
REF/BYP Pin Voltage .................................... –0.3V to 1V
Output Short-Circuit Duration .......................... Indefinite
(Note 1)
TOP VIEW
GND
SHDN
IN
IN
REF/BYP
ADJ
OUT
OUT
DCB PACKAGE
8-LEAD (2mm × 3mm) PLASTIC DFN
9
GND
3
4
2
1
6
5
7
8
TJMAX = 150°C, θJA = 38°C/W TO 45°C/W, θJC = 3.5°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
REF/BYP
ADJ
OUT
OUT
8
7
6
5
GND
SHDN
IN
IN
TOP VIEW
MS8E PACKAGE
8-LEAD PLASTIC MSOP
9
GND
TJMAX = 150°C, θJA = 29°C/W TO 45°C/W, θJC = 5°C/W TO 10°C/W
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3061EDCB#PBF LT3061EDCB#TRPBF LGNF 8-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LT3061IDCB#PBF LT3061IDCB#TRPBF LGNF 8-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LT3061HDCB#PBF LT3061HDCB#TRPBF LGNF 8-Lead (2mm × 3mm) Plastic DFN –40°C to 150°C
LT3061MPDCB#PBF LT3061MPDCB#TRPBF LGNF 8-Lead (2mm × 3mm) Plastic DFN –55°C to 150°C
LT3061EMS8E#PBF LT3061EMS8E#TRPBF LTGNG 8-Lead Plastic MSOP –40°C to 125°C
LT3061IMS8E#PBF LT3061IMS8E#TRPBF LTGNG 8-Lead Plastic MSOP –40°C to 125°C
LT3061HMS8E-5#PBF LT3061HMS8E#TRPBF LTGNG 8-Lead Plastic MSOP –40°C to 150°C
LT3061MPMS8E#PBF LT3061MPMS8E#TRPBF LTGNG 8-Lead Plastic MSOP –55°C to 150°C
Operating Junction Temperature (Notes 3, 5, 12)
E-, I-Grades ....................................... –40°C to 125°C
MP-Grade .......................................... –55°C to 150°C
H-Grade ............................................. –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS8E Package Only ..........................................300°C
http://www.linear.com/product/LT3061#orderinfo
LT3061 Series
3
3061fb
For more information www.linear.com/LT3061
ORDER INFORMATION
ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Input Voltage (Note 4) ILOAD = 100mA l1.6 2.1 V
Regulated Output Voltage (Note 5) LT3061-3.3: VIN = 3.9, ILOAD = 1mA
LT3061-3.3: 3.9V < VIN < 45V, 1mA < ILOAD < 100mA
LT3061-5: VIN = 5.6, ILOAD = 1mA
LT3061-5: 5.6V < VIN < 45V, 1mA < ILOAD < 100mA
l
l
3.267
3.234
4.950
4.900
3.3
5
3.333
3.366
5.050
5.100
V
V
V
V
ADJ Pin Voltage (Notes 4, 5) VIN = 2.1V, ILOAD = 1mA
2.1V < VIN < 45V, 1mA < ILOAD < 100mA (E-, I-Grades)
2.1V < VIN < 45V, 1mA < ILOAD < 100mA (MP-, H-Grades)
l
l
594
588
585
600
600
600
606
612
612
mV
mV
mV
Line Regulation (Note 4)
ILOAD = 1mA
LT3061-3.3: ΔVIN = 3.9V to 45V (E-, I-Grades)
LT3061-5: ΔVIN = 5.6V to 45V (E-, I-Grades)
l
l
1.6
3.1
22
33
mV
mV
LT3061: ΔVIN = 2.1V to 45V (E-, I-Grades)
LT3061: ΔVIN = 2.1V to 45V (MP-, H-Grades)
l
l
0.5 4
6
mV
mV
Load Regulation (Note 4)
ΔILOAD = 1mA to 100mA
LT3061-3.3: VIN = 3.9V (E-, I-Grades)
LT3061-5: VIN = 5.6V (E-, I-Grades)
l
l
4.4
5.0
25
36
mV
mV
LT3061: VIN = 2.1V (E-, I-Grades)
LT3061: VIN = 2.1V (MP-, H-Grades)
l
l
0.2 4
9
mV
mV
Dropout Voltage
VIN = VOUT(NOMINAL)
(Notes 6, 7)
ILOAD = 1mA
ILOAD = 1mA
l
65 110
180
mV
mV
ILOAD = 10mA
ILOAD = 10mA
l
130 180
270
mV
mV
ILOAD = 50mA
ILOAD = 50mA
l
195 240
350
mV
mV
ILOAD = 100mA
ILOAD = 100mA
l
250 290
430
mV
mV
GND Pin Current
VIN = VOUT(NOMINAL) + 0.6V
(Notes 6, 8)
ILOAD = 0
ILOAD = 1mA
ILOAD = 10mA
ILOAD = 50mA
ILOAD = 100mA
l
l
l
l
l
45
70
225
0.8
2
90
120
500
1.8
4
µA
µA
µA
mA
mA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
http://www.linear.com/product/LT3061#orderinfo
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3061EDCB-3.3#PBF LT3061EDCB-3.3#TRPBF LGZB 8-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LT3061IDCB-3.3#PBF LT3061IDCB-3.3#TRPBF LGZB 8-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LT3061EDCB-5#PBF LT3061EDCB-5#TRPBF LGYZ 8-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LT3061IDCB-5#PBF LT3061IDCB-5#TRPBF LGYZ 8-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C
LT3061EMS8E-3.3#PBF LT3061EMS8E-3.3#TRPBF LTGZJ 8-Lead Plastic MSOP –40°C to 125°C
LT3061IMS8E-3.3#PBF LT3061IMS8E-3.3#TRPBF LTGZJ 8-Lead Plastic MSOP –40°C to 125°C
LT3061EMS8E-5#PBF LT3061EMS8E-5#TRPBF LTGZH 8-Lead Plastic MSOP –40°C to 125°C
LT3061IMS8E-5#PBF LT3061IMS8E-5#TRPBF LTGZH 8-Lead Plastic MSOP –40°C to 125°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult ADI Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
LT3061 Series
4
3061fb
For more information www.linear.com/LT3061
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Absolute maximum input to output differential voltage is not
achievable with all combinations of rated IN pin and OUT pin voltages.
With the IN pin at 50V, the OUT pin may not be pulled below 0V. The total
measured voltage from IN to OUT must not exceed ±50V.
Note 3: The LT3061 is tested and specified under pulse load conditions
such that TJ ≅ TA. The LT3061E regulators are 100% tested at TA = 25°C
and performance is guaranteed from 0°C to 125°C. Performance at
–40°C to 125°C is assured by design, characterization and correlation
with statistical process controls. The LT3061I regulators are guaranteed
over the full –40°C to 125°C operating junction temperature range. The
LT3061MP regulators are 100% tested over the –55°C to 150°C operating
junction temperature. The LT3061H regulators are 100% tested at the
150°C operating junction temperature. High junction temperatures degrade
operating lifetimes. Operating lifetime is derated at junction temperature
greater than 125°C.
Note 4: The LT3061 adjustable version is tested and specified for these
conditions with the ADJ connected to the OUT pin.
Note 5: Maximum junction temperature limits operating conditions. The
regulated output voltage specification does not apply for all possible
combinations of input voltage and output current. Limit the output current
range if operating at the maximum input voltage. Limit the input-to-output
voltage differential if operating at maximum output current. Current limit
foldback limits the maximum output current as a function of input-to-
output voltage. See Current Limit vs VIN – VOUT in the Typical Performance
Characteristics section.
Note 6: To satisfy minimum input voltage requirements, the LT3061
adjustable version is tested and specified for these conditions with an
external resistor divider (bottom 60k, top 230k) for an output voltage of
2.9V. The external resistor divider adds 10µA of DC load on the output.
The external current is not factored into GND pin current.
Note 7: Dropout voltage is the minimum input-to-output voltage
differential needed to maintain regulation at a specified output current. In
dropout, the output voltage equals: (VIN – VDROPOUT).
Note 8: GND pin current is tested with VIN = VOUT(NOMINAL) + 0.6V and a
current source load. GND pin current will increase in dropout. See GND
pin current curves in the Typical Performance Characteristics section. For
fixed voltage options, an internal resistor divider will add 5μA to the GND
pin current. See the GND Pin Current curves in the Typical Performance
Characteristics section.
Note 9: ADJ pin bias current flows out of the ADJ pin.
Note 10: SHDN pin current flows into the SHDN pin.
Note 11: To satisfy requirements for minimum input voltage, current limit
is tested at VIN = VOUT(NOMINAL) + 1V or VIN = 2.1V, whichever is greater.
Note 12: This IC includes thermal limit which protects the device during
momentary overload conditions. Junction temperature exceeds 125°C
(E- and I-Grades) or 150°C (MP- and H-Grades) if thermal limit is active.
Continuous operation above the specified maximum junction temperature
may impair device reliability.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Voltage Noise COUT = 10µF, ILOAD = 100mA, CREF/BYP = 0.01µF
VOUT = 600mV, BW = 10Hz to 100kHz
30 µVRMS
ADJ Pin Bias Current (Notes 4, 9) l15 60 nA
Shutdown Threshold VOUT = Off to On
VOUT = On to Off
l
l
0.3
0.8
0.7
1.5 V
V
SHDN Pin Current (Note 10) VSHDN = 0V
VSHDN = 45V
l
l
1.2
<1
3
µA
µA
Quiescent Current in Shutdown VIN = 45V, VSHDN = 0V 1.25 3 µA
Ripple Rejection
VIN – VOUT = 1.5V (AVG), VRIPPLE = 0.5VP-P,
fRIPPLE = 120Hz, ILOAD = 200mA
LT3061-3.3
LT3061-5
LT3061 (Note 4)
58
55
70
73
70
85
dB
dB
dB
Current Limit VIN = 7V, VOUT = 0
VIN = VOUT(NOMINAL) + 1V (Note 11), ΔVOUT = –5%
l
110
180 mA
mA
Input Reverse Leakage Current VIN = -45V, VOUT = 0 l1 mA
Output Discharge Time (Note 6) VOUT Discharged to 10% of Nominal, COUT = 10μF l0.75 2 ms
Reverse Output Current LT3061-3.3: VOUT = 3.3V, VIN = VSHDN = 2.1V
LT3061-5: VOUT = 5V, VIN = VSHDN = 2.1V
LT3061: VOUT = 3.3V, VIN = VSHDN = 2.1V (Note 4)
7.3
8.4
2.5
15
15
15
µA
µA
µA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
LT3061 Series
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3061fb
For more information www.linear.com/LT3061
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Current
LT3061-5 Output VoltageLT3061-3.3 Output Voltage ADJ Pin Voltage
LT3061-3.3 Quiescent Current LT3061-5 Quiescent Current
Typical Dropout Voltage Guaranteed Dropout Voltage Dropout Voltage
OUTPUT CURRENT (mA)
0
0
DROPOUT VOLTAGE (mV)
350
300
250
200
150
100
50
450
400
10 60 70 80 90 10020 30 40
3061 G01
50
TJ = 125°C
TJ = 25°C
TJ = 150°C
OUTPUT CURRENT (mA)
0
0
DROPOUT VOLTAGE (mV)
350
300
250
200
150
100
50
450
400
10 60 70 80 90 10020 30 40
3061 G02
50
TJ = 25°C
TJ = 150°C
= TEST POINTS
TEMPERATURE (°C)
–75
0
DROPOUT VOLTAGE (mV)
350
300
250
200
150
100
50
450
400
–50 75 100 125 150 175–25 0 25
3061 G03
50
IL = 100mA
IL = 10mA
IL = 1mA
IL = 50mA
TEMPERATURE (°C)
–75
588
ADJ PIN VOLTAGE (mV)
608
606
604
594
596
598
600
602
592
590
612
610
–50 75 100 125 150 175–25 0 25
3061 G04
50
IL = 1mA
TEMPERATURE (°C)
–75
0
QUIESCENT CURRENT (µA)
60
50
40
30
20
10
80
70
–50 75 100 125 150 175–25 0 25
3061 G05
50
VIN = VSHDN = 6V
VOUT = 5V
IL = 5µA
VIN = 6V
ALL OTHER PINS = 0V
TA = 25°C, unless otherwise noted.
I
L
= 1mA
TEMPERATURE (°C)
–75
–50
–25
0
50
100
125
150
175
3.234
3.245
3.256
3.267
3.278
3.289
3.300
3.311
3.322
3.333
3.344
3.355
3.366
OUTPUT VOLTAGE (V)
LT3061 G03a
I
L
= 1mA
TEMPERATURE (°C)
–75
–50
–25
0
50
75
100
125
150
175
4.900
4.920
4.940
4.960
4.980
5.000
5.020
5.040
5.060
5.080
5.100
OUTPUT VOLTAGE (V)
LT3061 G03b
V
SHDN
= V
IN
V
SHDN
= 0V
V
IN
(V)
0
1
2
3
4
5
6
7
8
9
12
0
100
125
150
175
200
225
250
QUIESCENT CURRENT (µA)
3061 G05a
V
SHDN
= V
IN
V
SHDN
= 0V
V
IN
(V)
0
1
2
3
4
5
6
7
8
9
0
100
125
150
175
200
225
250
QUIESCENT CURRENT (µA)
3061 G05b
LT3061 Series
6
3061fb
For more information www.linear.com/LT3061
TYPICAL PERFORMANCE CHARACTERISTICS
SHDN Pin Input Current SHDN Pin Input Current ADJ Pin Bias Current
SHDN PIN VOLTAGE (V)
0
0
SHDN
PIN INPUT CURRENT (µA)
2.5
1.5
1.0
0.5
2.0
3.0
5 25 30 35 40 4510 15
3061 G10
20
TEMPERATURE (°C)
–75
0
SHDN
PIN INPUT CURRENT (µA)
2.5
1.5
1.0
0.5
2.0
3.0
–25–50 75 100 125 150 1750 25
3061 G11
50
SHDN = 45V
TEMPERATURE (°C)
–75
–50
ADJ PIN BIAS CURRENT (nA)
30
10
0
–10
–20
–30
–40
20
50
40
–25–50 75 100 125 150 1750 25
3061 G12
50
TA = 25°C, unless otherwise noted.
GND Pin Current
VOUT = 0.6V GND Pin Current vs ILOAD SHDN Pin Threshold
RL = 600Ω, IL = 1mA
RL = 60Ω, IL = 10mA
RL = 12Ω, IL = 50mA
RL = 6Ω, IL = 100mA
VIN (V)
0
0.00
GND PIN CURRENT (mA)
2.00
1.75
1.50
0.25
0.50
0.75
1.00
1.25
2.50
2.25
21 6 7 8 9 103 4
3061 G07
5
ILOAD (mA)
0
0
GND PIN CURRENT (mA)
3.5
3.0
0.5
1.0
1.5
2
2.5
4.0
2010 60 70 80 90 10030 40
3061 G08
50
VIN = VOUT(NOMINAL) +1V
TEMPERATURE (°C)
–75
0
SHDN PIN THRESHOLD (V)
1.4
1.3
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.9
1.0
1.1
1.2
1.5
–25–50 75 100 125 150 1750 25
3061 G09
50
OFF TO ON
ON TO OFF
Quiescent Current LT3061–3.3 GND Pin Current LT3061–5 GND Pin Current
VIN (V)
0
0
QUIESCENT CURRENT (µA)
100
90
80
30
40
50
60
70
20
10
120
110
5 25 30 35 40 4510 15
3061 G06
20
TJ = 25°C
VOUT = 5V
IL = 10µA
VSHDN = 0V, RL = 0
R
L
= 330Ω, I
L
= 10mA
R
L
= 33Ω, I
L
= 100mA
R
L
= 66Ω, I
L
= 50mA
R
L
= 3.3kΩ, I
L
= 1mA
V
IN
(V)
0
1
2
3
4
5
6
7
8
9
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
GND PIN CURRENT (mA)
3061 G6a
R
L
= 500Ω, I
L
= 10mA
R
L
= 50Ω, I
L
= 100mA
R
L
= 100Ω, I
L
= 50mA
R
L
= 5kΩ, I
L
= 1mA
V
IN
(V)
0
1
2
3
4
5
6
7
8
9
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
GND PIN CURRENT (mA)
3061 G06b
LT3061 Series
7
3061fb
For more information www.linear.com/LT3061
Internal Current Limit Internal Current Limit Output Discharge Time
Output Discharge Time
COUT = 10µF, VIN = VOUT +1V
Output Discharge vs VOUT
CREF/BYP = 0
Input Ripple RejectionReverse Output Current
Output Discharge vs VOUT
CREF/BYP = 0
TYPICAL PERFORMANCE CHARACTERISTICS
Reverse Output Current
INPUT/OUTPUT VOLTAGE DIFFERENTIAL (V)
0
0
CURRENT LIMIT (mA)
200
175
150
25
50
75
100
125
250
225
5 25 30 35 40 4510 15
3061 G13
20
TJ = –55°C
TJ = –40°C
TJ = 25°C
TJ = 125°C
TJ = 150°C
TEMPERATURE (°C)
–75
0
CURRENT LIMIT (mA)
225
200
125
150
75
100
50
25
175
250
–25–50 75 100 125 150 1750 25
3061 G14
50
VIN = 7V
VOUT = 0V
OUTPUT VOLTAGE (V)
0
0
OUTPUT DISCHARGE TIME (ms)
3.5
3.0
1.0
1.5
2.0
2.5
0.5
4.0
2 4 12 14 16 18 206 8
3061 G15
10
COUT = 10µF
VIN = VOUT +1V
OUTPUT DISCHARGE
FOLDBACK STARTS
TEMPERATURE (°C)
–75
0
OUTPUT DISCHARGE TIME (ms)
5
4
1
2
3
7
6
–25–50 75 100 125 150 1750 25
3061 G16
50
OUT = 1.2V
OUT = 3.3V
OUT = 5V
OUT = 12V
OUT = 20V
1ms/DIV
2V/DIV
12V
0V
3061 G17
VIN = VOUT +1V
COUT = 10µF
IFB-DIVIDER = 5µA
12V
10V
8V
6V
5V
2V
3.3V
1.2V
SHDN: 0 TO 1V
1ms/DIV
5V/DIV
20V
20V
15V
12V
0V
3061 G18
VIN = VOUT +1V
COUT = 10µF
IFB-DIVIDER = 5µA
SHDN: 0 TO 1V
VOUT (V)
0
0
OUTPUT CURRENT (µA)
45
40
30
35
20
25
5
10
15
50
2 12 14 16 18 204 6 8
3061 G19
10
VIN = VSHDN = 2.1V
VADJ = VOUT
TEMPERATURE (°C)
–75
0
OUTPUT CURRENT (µA)
130
140
120
60
70
80
90
100
110
40
50
10
20
30
150
–50 75 100 125 150 175–25 0 25
3061 G20
50
VOUT = VADJ = 3.3V
VIN = VSHDN = 2.1V
IADJ
IOUT
VOUT = 0.6V
FREQUENCY (Hz)
10
0
RIPPLE REJECTION (dB)
50
40
10
20
30
90
60
70
80
10k 100k 1M 10M100
3061 G21
1k
VOUT = 5V
COUT = 10µF
ILOAD = 100mA
CREF/BYP = CFF = 0
VIN = VOUT +1.5V +50mVRMS RIPPLE
COUT = 3.3µF
TA = 25°C, unless otherwise noted.
LT3061 Series
8
3061fb
For more information www.linear.com/LT3061
Output Noise Spectral Density
vs CFF, CREF/BYP = 10nF
Output Noise Spectral Density
CREF/BYP = 0, CFF = 0
TYPICAL PERFORMANCE CHARACTERISTICS
Output Noise Spectral Density
vs CREF/BYP, CFF = 0
FREQUENCY (Hz)
10
0.01
OUTPUT NOISE SPECTRAL DENSITY (µV/
√Hz)
1
0.1
10
100 10k 100k
3061 G28
1k
0.6V
1.2V
2.5V
3.3V
5V
COUT = 10µF
IL = 100mA
FREQUENCY (Hz)
10
0.01
OUTPUT NOISE SPECTRAL DENSITY (µV/
√Hz)
1
0.1
10
100 10k 100k
3061 G29
1k
COUT = 10µF
IL = 100mA
VOUT = 5V CREF/BYP = 100pF
CREF/BYP = 10nF
CREF/BYP = 1nF
VOUT = 0.6V
FREQUENCY (Hz)
10
0.01
OUTPUT NOISE SPECTRAL DENSITY (µV/
√Hz)
1
0.1
10
100 10k 100k
3061 G30
1k
CFF = 100pF
CFF = 1nF
CFF = 0
CFF = 10nF
VOUT = 5V
COUT = 10µF
IL = 100mA
TA = 25°C, unless otherwise noted.
Load Regulation
5V Transient Response
CFF = 0, IOUT = 10mA to 100mA
5V Transient Response
CFF = 10nF, IOUT = 10mA to 100mA
∆I
L
= 1mA to 100mA
LT3061, V
OUT
= 0.6V
LT3061–3.3
LT3061–5
TEMPERATURE (°C)
–75
–50
–25
0
100
125
150
175
–50.0
–45.0
–40.0
–35.0
–30.0
–25.0
–20.0
–15.0
–10.0
–5.0
0
5.0
LOAD REGULATION (mV)
3061 G25
100µs/DIV 3061 G26
VIN = 6V
COUT = 10µF
IFB-DIVIDER = 5µA
VOUT
50mV/DIV
IOUT
50mA/DIV
20µs/DIV 3061 G27
VIN = 6V
COUT = 10µF
IFB-DIVIDER = 5µA
VOUT
20mV/DIV
IOUT
50mA/DIV
Minimum Input Voltage
Input Ripple Rejection Input Ripple Rejection
CREF/BYP = 10nF, CFF = 10nF
CREF/BYP = 10nF, CFF = 0
CREF/BYP = CFF = 0
FREQUENCY (Hz)
10
0
RIPPLE REJECTION (dB)
50
40
10
20
30
100
60
70
80
90
10k 100k 1M 10M100
3061 G22
1k
VIN = 6.5V +50mVRMS RIPPLE
ILOAD = 100mA
COUT = 10µF
VOUT = 5V
TEMPERATURE (°C)
–75
0
RIPPLE REJECTION (dB)
60
70
80
90
40
50
10
20
30
100
–50 75 100 125 150 175–25 0 25
3061 G23
50
CREF/BYP = 10nF
CREF/BYP = 0
ILOAD = 100mA
VOUT = 0.6V
VIN = 2.6V +0.5VP-P RIPPLE, f = 120Hz
TEMPERATURE (°C)
–75
0.0
MINIMUM INPUT VOLTAGE (V)
1.4
1.6
1.8
2.0
1.0
1.2
0.2
0.4
0.6
0.8
2.2
–50 75 100 125 150 175–25 0 25
3061 G24
50
ILOAD = 100mA
ILOAD = 50mA
LT3061 Series
9
3061fb
For more information www.linear.com/LT3061
RMS Output Noise
vs Feedforward Capacitor (CFF)
5V 10Hz to 100kHz Output Noise
CREF/BYP = 10nF, CFF = 0
5V 10Hz to 100kHz Output Noise
CREF/BYP = 10nF, CFF = 10nF
RMS Output Noise
vs CREF/BYP VOUT = 0.6V
RMS Output Noise vs Load Current
CREF/BYP = 10nF, CFF = 0
TYPICAL PERFORMANCE CHARACTERISTICS
SHDN Transient Response
CREF/BYP = 10nF
Transient Response, VOUT = 5V
Load Dump, VIN = 12V to 45V
SHDN Transient Response
CREF/BYP = 0
LOAD CURRENT (mA)
0.01
0
OUTPUT NOISE VOLTAGE (µV
RMS)
70
80
90
100
40
50
60
30
20
10
110
0.1 10 100
3061 G31
1
CREF/BYP = 100nF
CREF/BYP = 100pF
CREF/BYP = 10pF
CREF/BYP = 0
CREF/BYP = 10nF
f = 10Hz TO 100kHz
COUT = 10µF
LOAD CURRENT (mA)
0.01
0
OUTPUT NOISE VOLTAGE (µV
RMS)
70
80
90
100
110
120
130
140
150
40
50
60
30
20
10
160
0.1 10 100
3061 G32
1
f = 10Hz TO 100kHz
COUT = 10µF
VOUT = 0.6V
VOUT = 1.2V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 5V
FEEDFORWARD CAPACITOR, CFF (nF)
0.01
0
OUTPUT NOISE VOLTAGE (µV
RMS)
70
80
90
100
110
120
40
50
60
30
20
10
130
0.1 10
3061 G33
1
f = 10Hz TO 100kHz
CREF/BYP = 10nF
COUT = 10µF
IFB-DIVIDER = 5µA
ILOAD = 100mA
VOUT = 5V
VOUT = 0.6V
VOUT = 3.3V
VOUT = 1.2V
VOUT = 2.5V
1ms/DIV 3061 G34
COUT = 10µF
ILOAD = 100mA
VOUT
100µV/DIV
1ms/DIV 3061 G35
COUT = 10µF
ILOAD = 100mA
VOUT
100µV/DIV
1ms/DIV
12V
45V
3061 G36
COUT = 10µF
CREF/BYP = CFF = 10nF
IFB-DIVIDER = 5µA
VOUT
5mV/DIV
VIN
10V/DIV
2ms/DIV 3061 G37
COUT = 10µF
CFF = 0
VOUT
2V/DIV
RL = 500k
REF/BYP
500mV/DIV
SHDN
1V/DIV
2ms/DIV 3061 G38
COUT = 10µF
CFF = 0
VOUT
2V/DIV
RL = 500k
REF/BYP
500mV/DIV
SHDN
1V/DIV
TA = 25°C, unless otherwise noted.
LT3061 Series
10
3061fb
For more information www.linear.com/LT3061
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
Start-Up Time
vs REF/BYP Capacitor Start-up Time vs CFF
REF/BYP CAPACITOR (nF)
0.01
0.01
START-UP TIME (ms)
10
0.1
1
100
10 1000.1
3061 G39
1
CFF = 0
V
OUT
= 1.2V I
FB–DIVIDER
= 5µA
LT3061–3.3
LT3061–5
FEED-FORWARD CAPACITOR, C
FF
(nF)
0.01
0.1
1
100
0.01
0.1
1
100
1000
START-UP TIME (ms)
LT3061 G40
LT3061 Series
11
3061fb
For more information www.linear.com/LT3061
PIN FUNCTIONS
REF/BYP (Pin 1): Reference/ Bypass. Connecting a single
capacitor from this pin to GND bypasses the LT3061’s
reference noise and soft-starts the reference. A 10nF by-
pass capacitor typically reduces output voltage noise to
30μVRMS in a 10Hz to 100kHz bandwidth. Soft-start time
is directly proportional to the REF/BYP capacitor value.
If the LT3061 is placed in shutdown, REF/BYP is actively
pulled low by an internal device to reset soft-start. If low
noise or soft-start performance is not required, this pin
must be left floating (unconnected). Do not drive this pin
with any active circuitry.
ADJ (Pin 2): Adjust. This pin is the error amplifier’s invert-
ing terminal. Its typical bias current of 15nA flows out of
the pin (see curve of ADJ Pin Bias Current vs Temperature
in the Typical performance Characteristics section). The
ADJ pin voltage is 600mV referenced to GND.
OUT (Pins 3, 4): Output. These pins supply power to the
load. A minimum output capacitor of 3.3µF is required
to prevent oscillations. Large load transient applications
require larger output capacitors to limit peak voltage
transients. See the Applications Information section for
more information on reverse output characteristics. The
output voltage range is 600mV to 19V. If the LT3061 is
placed in shutdown, OUT is actively discharged by an
internal NMOS device. Gate drive is controlled to insure
that a 10μF capacitor is discharged 90% in 2ms or less.
If IN is driven low, OUT is actively discharged to ~800mV.
For OUT voltages greater than 6V, current limit foldback is
implemented to protect the NMOS device and discharge
rates increase. See the Applications Information section
for more information.
IN (Pins 5, 6): Input. These pins supply power to the
device. The LT3061 requires a bypass capacitor at IN if
the device is located more than six inches from the main
input filter capacitor. In general, the output impedance of
a battery rises with frequency, so it is advisable to include
a bypass capacitor in battery-powered circuits. A bypass
capacitor in the range of 1µF to 10µF suffices. See Input
Capacitance and Stability in the Application Information
section for more information.
The LT3061 withstands reverse voltages on the IN pin
with respect to the GND and OUT pins. In a reversed input
situation, such as the battery plugged in backwards, the
LT3061 behaves as if a large value resistor is in series with
its input. Limited reverse current flows into the LT3061
and no reverse voltage appears at the load. The device
protects itself and the load.
SHDN (Pin 7): Shutdown. Pulling the SHDN pin low puts
the LT3061 into a low power state and turns the output
off. Drive the SHDN pin with either logic or an open collec-
tor/drain with a pull-up resistor. The resistor supplies the
pull-up current to the open collector/drain logic, normally
several microamperes, and the SHDN pin current, typi-
cally less than 3µA. If unused, connect the SHDN pin to
VIN. The LT3061 does not function if the SHDN pin is not
connected. The SHDN pin cannot be driven below GND
unless tied to the IN pin. If the SHDN pin is driven below
GND while IN is powered, the output will turn on. SHDN
pin logic cannot be referenced to a negative rail.
GND (Pin 8, Exposed Pad Pin 9): Ground. Connect the
bottom of the external resistor divider that sets the output
voltage directly to GND for optimum regulation. Tie the
exposed pad Pin 9 directly to Pin 8 and the PCB ground.
This exposed pad provides enhanced thermal performance
with its connection to the PCB ground. See the Applica-
tions Information section for thermal considerations and
calculating junction temperature.
LT3061 Series
12
3061fb
For more information www.linear.com/LT3061
The LT3061 is a 100mA low dropout regulator with
shutdown that is available in fixed output and adjustable
versions. The device is capable of supplying 100mA at
a typical dropout voltage of 250mV and operates over a
1.6V to 45V input range.
A single external capacitor provides programmable low
noise reference performance and output soft-start func-
tionality. For example, connecting a 10nF capacitor from
the REF/BYP pin to GND lowers output noise to 30µVRMS
over a 10Hz to 100kHz bandwidth. This capacitor also
soft-starts the reference and prevents output voltage
overshoot at turn-on.
The LT3061’s quiescent current is merely 45μA, while
providing fast transient response with a 3.3µF minimum
low ESR ceramic output capacitor. In shutdown, quies-
cent current is less than 3μA and the reference soft-start
capacitor and output are reset.
The LT3061 optimizes stability and transient response
with low ESR, ceramic output capacitors. The LT3061
does not require the addition of ESR as is common with
other regulators. The LT3061 has an adjustable output
and typically provides 0.1% line regulation and 0.1%
load regulation. A curve of load regulation appears in the
Typical Performance Characteristics section.
The LT3061 discharges the output in shutdown. Internal
protection circuitry includes reverse-battery protection,
reverse-current protection, current limit with foldback
and thermal shutdown.
Adjustable Operation
The adjustable LT3061 has an output voltage range of 0.6V
to 19V. Output voltage is set by the ratio of two external
resistors, as shown in Figure 1. The device regulates the
output to maintain the ADJ pin voltage at 0.6V referenced
to ground. The current in R1 equals 0.6V/R1, and R2’s
current is R1’s current minus the ADJ pin bias current.
The ADJ pin bias current, 15nA at 25°C, flows from the
ADJ pin through R1 to GND. Calculate the output voltage
using the formula in Figure 1. R1’s value should not be
greater than 124k to provide a minimum ~5μA load cur-
rent so that output voltage errors, caused by the ADJ pin
APPLICATIONS INFORMATION
Figure 1. Adjustable Operation
bias current, are minimized. Note that in shutdown, the
output is turned off and the divider current is zero. Curves
of ADJ Pin Voltage vs Temperature and ADJ Pin Bias Cur-
rent vs Temperature appear in the Typical Performance
Characteristics section.
3061 F01
IN
SHDN
OUT
ADJ
GND REF/BYP
LT3061
VIN
VOUT
R2
R1
VOUT =0.6V 1+R2
R1
!
"
#$
%
&– IADJ •R2
( )
VADJ =0.6V
IADJ =15nA at 25°C
OUTPUT RANGE =0.6V to 19V
The LT3061 is tested and specified with the ADJ pin tied to
the OUT pin for an output voltage of 0.6V. Specifications
for output voltages greater than 0.6V are proportional to
the ratio of the desired output voltage to 0.6V: VOUT/0.6V.
For example, load regulation for an output current change
of 1mA to 100mA is –0.2mV typical at VOUT = 0.6V. At
VOUT = 12V, load regulation is:
12V
0.6V
•–0.2mV
( )
=–4mV
Table 1 shows 1% resistor divider values for some com-
mon output voltages with a resistor divider current of 5µA.
Table 1. Output Voltage Resistor Divider Values
VOUT
(V)
R1
(kΩ)
R2
(kΩ)
1.2 118 118
1.5 121 182
1.8 124 249
2.5 115 365
3 124 499
3.3 124 562
5 115 845
12 124 2370
15 124 3010
LT3061 Series
13
3061fb
For more information www.linear.com/LT3061
APPLICATIONS INFORMATION
Bypass Capacitance, Output Voltage Noise and
Transient Response
The LT3061 regulator provides low output voltage noise
over the 10Hz to 100kHz bandwidth while operating at full
load with the addition of a bypass capacitor (CREF/BYP)
from the REF/BYP pin to GND. A good quality low leak-
age capacitor is recommended. This capacitor bypasses
the reference of the regulator, providing a low frequency
noise pole for the internal reference. With the use of 10nF
for CREF/BYP, the output voltage noise decreases to as
low as 30µVRMS when the output voltage is set for 0.6V.
For higher output voltages (generated by using a resistor
divider), the output voltage noise gains up accordingly
when using CREF/BYP by itself.
To lower the output voltage noise for higher output volt-
ages, include a feedforward capacitor (CFF) from VOUT
to the ADJ pin. A good quality, low leakage capacitor is
recommended. This capacitor bypasses the error amplifier
of the regulator, providing a low frequency noise pole. With
the use of 10nF for both CFF and CREF/BYP, output voltage
noise decreases to 30µVRMS when the output voltage is
set to 5V by a 5µA feedback resistor divider. If the cur-
rent in the feedback resistor divider is doubled, CFF must
also be doubled to achieve equivalent noise performance.
Higher values of output voltage noise may be measured
if care is not exercised with regard to circuit layout and
testing. Crosstalk from nearby traces can induce unwanted
noise onto the LT3061’s output. Power supply ripple rejec-
tion must also be considered. The LT3061 regulator does
not have unlimited power supply rejection and will pass
a small portion of the input noise through to the output.
Using a feedforward capacitor (CFF) from VOUT to the ADJ
pin has the added benefit of improving transient response
for output voltages greater than 0.6V. With no feedforward
capacitor, the settling time will increase as the output
voltage is raised above 0.6V. Use the equation in Figure 2
to determine the minimum value of CFF to achieve a
transient response that is similar to 0.6V output voltage
performance regardless of the chosen output voltage (see
Figure 3 and Transient Response in the Typical Performance
Characteristics section).
Feedforward capacitance can also be used in fixed-voltage
parts; the feedforward capacitor is connected from OUT
to ADJ in the same manner. In this case, the current in
the internal feedback resistor divider is 5μA.
3061 F02
IN
SHDN
OUT
ADJ
GND REF/BYP
LT3061
VIN
VOUT
CREF/BYP
CFF COUT
R2
R1
C4.7nF
5µA I
IV
R1 R2
FF FB–DIVIDER
FB–DIVIDER OUT
()
≥•
=+
100µs/DIV
VOUT = 5V
COUT = 10µF
IFB-DIVIDER = 5µA
0
1nF
10nF
LOAD CURRENT
100mA/DIV
FEEDFORWARD
CAPACITOR, CFF
100pF
3061 F03
VOUT
50mV/DIV
Figure 2. Feedforward Capacitor for Fast Transient Response
Figure 3. Transient Response vs Feedforward Capacitor
LT3061 Series
14
3061fb
For more information www.linear.com/LT3061
During start-up, the internal reference soft-starts if a refer-
ence bypass capacitor is present. Regulator startup time
is directly proportional to the size of the bypass capacitor,
slowing to 6ms with a 10nF bypass capacitor (See SHDN
Transient Response vs REF/BYP Capacitor in the Typical
Performance Characteristics section). The reference by-
pass capacitor is actively pulled low during shutdown to
reset the internal reference.
Start-up time is also affected by the use of a feedforward
capacitor. Start-up time is directly proportional to the size
of the feedforward capacitor and output voltage, and is
inversely proportional to the feedback resistor divider cur-
rent, slowing to 15ms with a 4.7nF feedforward capacitor
and a 10µF output capacitor for an output voltage set to
5V by a 5µA feedback resistor divider.
Output Capacitance
The LT3061 regulator is stable with a wide range of output
capacitors. The ESR of the output capacitor affects stabil-
ity, most notably with small capacitors. Use a minimum
output capacitor of 3.3µF with an ESR of 3Ω or less to
prevent oscillations. The LT3061 is a micropower device
and output load transient response is a function of output
capacitance. Larger values of output capacitance decrease
the peak deviations and provide improved transient re-
sponse for larger load current changes. Bypass capacitors,
used to decouple individual components powered by the
LT3061, will increase the effective output capacitor value.
For applications with large load current transients, a low
ESR ceramic capacitor in parallel with a bulk tantalum
capacitor often provides an optimally damped response.
Give extra consideration to the use of ceramic capacitors.
Manufacturers make ceramic capacitors with a variety of
dielectrics, each with different behavior across tempera-
ture and applied voltage. The most common dielectrics
are specified with EIA temperature characteristic codes
of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics
provide high C-V products in a small package at low cost,
but exhibit strong voltage and temperature coefficients as
shown in Figures 4 and 5. When used with a 5V regulator,
a 16V 10µF Y5V capacitor can exhibit an effective value
as low as 1µF to 2µF for the DC bias voltage applied and
over the operating temperature range. The X5R and X7R
APPLICATIONS INFORMATION
dielectrics yield much more stable characteristics and are
more suitable for use as the output capacitor. The X7R
type works over a wider temperature range and has better
temperature stability, while the X5R is less expensive and is
available in higher values. Care still must be exercised when
using X5R and X7R capacitors; the X5R and X7R codes
only specify operating temperature range and maximum
capacitance change over temperature. Capacitance change
due to DC bias with X5R and X7R capacitors is better than
Y5V and Z5U capacitors, but can still be significant enough
to drop capacitor values below appropriate levels. Capaci-
tor DC bias characteristics tend to improve as component
case size increases, but expected capacitance at operating
voltage should be verified.
DC BIAS VOLTAGE (V)
CHANGE IN VALUE (%)
3061 F04
20
0
–20
–40
–60
–80
–100 04810
2 6 12 14
X5R
Y5V
16
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
TEMPERATURE (°C)
–50
40
20
0
–20
–40
–60
–80
–100 25 75
3061 F05
–25 0 50 100 125
Y5V
CHANGE IN VALUE (%)
X5R
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10µF
Figure 4. Ceramic Capacitor DC Bias Characteristics
Figure 5. Ceramic Capacitor Temperature Characteristics
LT3061 Series
15
3061fb
For more information www.linear.com/LT3061
APPLICATIONS INFORMATION
Figure 6. Noise Resulting from Tapping on a Ceramic Capacitor
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or micro-
phone works. For a ceramic capacitor, the stress can be
induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
amounts of noise. A ceramic capacitor produced the trace
in Figure 6 in response to light tapping from a pencil.
Similar vibration induced behavior can masquerade as
increased output voltage noise.
Input Capacitance and Stability
Low ESR, ceramic input bypass capacitors are acceptable
for applications without long input leads. However, appli-
cations connecting a power supply to an LT3061 circuit’s
IN and GND pins with long input wires combined with a
low ESR, ceramic input capacitor are prone to voltage
spikes, reliability concerns and application-specific board
oscillations.
The input wire inductance found in many battery-powered
applications, combined with the low ESR ceramic input
capacitor, forms a high Q LC resonant tank circuit. In
some instances this resonant frequency beats against the
output current dependent LDO bandwidth and interferes
with proper operation. Simple circuit modifications/solu-
tions are then required. This behavior is not indicative of
LT3061 instability, but is a common ceramic input bypass
capacitor application issue.
The self-inductance, or isolated inductance, of a wire is
directly proportional to its length. Wire diameter is not a
major factor on its self-inductance. For example, the self-
inductance of a 2-AWG isolated wire (diameter = 0.26") is
about half the self-inductance of a 30-AWG wire (diameter
= 0.01"). One foot of 30-AWG wire has approximately
465nH of self-inductance.
Tw o methods can reduce wire self-inductance. One method
divides the current flowing towards the LT3061 between
two parallel conductors. In this case, the farther apart the
wires are from each other, the more the self-inductance is
reduced; up to a 50% reduction when placed a few inches
apart. Splitting the wires connects two equal inductors in
parallel, but placing them in close proximity creates mutual
inductance adding to the self-inductance. The second and
most effective way to reduce overall inductance is to place
both forward and return current conductors (the input
and GND wires) in very close proximity. Tw o 30-AWG
wires separated by only 0.02”, used as forward and return
current conductors, reduce the overall self-inductance
to approximately one-fifth that of a single isolated wire.
If a battery, mounted in close proximity, powers the LT3061,
a 1µF input capacitor suffices for stability. However, if a
distant supply powers the LT3061, use a larger value input
capacitor. Use a rough guideline of 1µF (in addition to the
1µF minimum) per 8 inches of wire length. The minimum
input capacitance needed to stabilize the application also
varies with power supply output impedance variations.
Placing additional capacitance on the LT3061’s output
also helps. However, this requires an order of magnitude
more capacitance in comparison with additional LT3061
input bypassing. Series resistance between the supply
and the LT3061 input also helps stabilize the applica-
tion; as little as 0.1Ω to 0.5Ω suffices. This impedance
dampens the LC tank circuit at the expense of dropout
voltage. A better alternative is to use higher ESR tantalum
or electrolytic capacitors at the LT3061 input in place of
ceramic capacitors.
4ms/DIV
3061 F06
VOUT
500µV/DIV
VOUT = 0.6V
COUT = 10µF
CREF/BYP = 10nF
ILOAD = 100mA
LT3061 Series
16
3061fb
For more information www.linear.com/LT3061
APPLICATIONS INFORMATION
Overload Recovery
Like many IC power regulators, the LT3061 has safe oper-
ating area protection. The safe area protection decreases
current limit as input-to-output voltage increases and keeps
the power transistor inside a safe operating region for all
values of input-to-output voltage. The protective design
provides some output current at all values of input-to-
output voltage up to the device breakdown.
When power is first applied, as input voltage rises, the
output follows the input, allowing the regulator to start up
into very heavy loads. During start-up, as the input voltage
is rising, the input-to-output voltage differential is small,
allowing the regulator to supply large output currents. With
a high input voltage, a problem can occur wherein removal
of an output short will not allow the output to recover.
The problem occurs with a heavy output load when the
input voltage is high and the output voltage is low. Com-
mon situations include immediately after the removal of a
short-circuit or if the shutdown pin is pulled high after the
input voltage has already been turned on. The load line for
such a load may intersect the output current curve at two
points. If this happens, there are two stable output operat-
ing points for the regulator. With this double intersection,
the input power supply may need to be cycled down to
zero and brought up again to make the output recover.
Thermal Considerations
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C for
LT3061E, LT3061I or 150°C for LT3061MP, LT3061H). Tw o
components comprise the power dissipated by the device:
1. Output current multiplied by the input/output voltage
differential: IOUT • (VIN – VOUT), and
2. GND pin current multiplied by the input voltage:
IGND • VIN
GND pin current is determined using the GND Pin Current
curves in the Typical Performance Characteristics section.
Power dissipation will be equal to the sum of the two
components listed above.
The LT3061 regulator has internal thermal limiting that pro-
tects the device during overload conditions. For continuous
normal conditions, the maximum junction temperature of
125°C (E-grade, I-grade) or 150°C (MP-grade, H-grade)
must not be exceeded. Carefully consider all sources of
thermal resistance from junction to ambient including
other heat sources mounted in proximity to the LT3061.
The undersides of the LT3061 packages have exposed metal
from the lead frame to the die attachment. The package
allows heat to directly transfer from the die junction to the
printed circuit board metal to control maximum operating
junction temperature. The dual-in-line pin arrangement
allows metal to extend beyond the ends of the package
on the topside (component side) of a PCB. Connect this
metal to GND on the PCB. The multiple IN and OUT pins
of the LT3061 also assist in spreading heat to the PCB.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
Tables 2 and 3 list thermal resistance for several different
board sizes and copper areas. All measurements were taken
in still air on a 4 layer FR-4 board with 1oz solid internal
planes and 2oz top/bottom external trace planes with a total
board thickness of 1.6mm. The four layers were electrically
isolated with no thermal vias present. PCB layers, copper
weight, board layout and thermal vias will affect the resul-
tant thermal resistance. For more information on thermal
resistance and high thermal conductivity test boards,
refer to JEDEC standard JESD51, notably JESD51-12 and
JESD51-7. Achieving low thermal resistance necessitates
attention to detail and careful PCB layout.
LT3061 Series
17
3061fb
For more information www.linear.com/LT3061
APPLICATIONS INFORMATION
Table 2. Measured Thermal Resistance for DFN Package
COPPER AREA
BOARD AREA
(mm2)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
TOPSIDE*
(mm2)
BACKSIDE
(mm2)
2500 2500 2500 38°C/W
1000 2500 2500 38°C/W
225 2500 2500 40°C/W
100 2500 2500 45°C/W
*Device is mounted on topside
Table 3. Measured Thermal Resistance for MSOP Package
COPPER AREA
BOARD AREA
(mm2)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
TOPSIDE*
(mm2)
BACKSIDE
(mm2)
2500 2500 2500 29°C/W
1000 2500 2500 30°C/W
225 2500 2500 32°C/W
100 2500 2500 45°C/W
*Device is mounted on topside
Calculating Junction Temperature
Example: Given an output voltage of 2.5V, an input volt-
age range of 12V ±5%, an output current range of 0mA
to 50mA and a maximum ambient temperature of 85°C,
what will the maximum junction temperature be?
The power dissipated by the device equals:
IOUT(MAX) • (VIN(MAX)–VOUT) + IGND • VIN(MAX)
where,
IOUT(MAX) = 50mA
VIN(MAX) = 12.6V
IGND at (IOUT = 50mA, VIN = 12V) = 1mA
So,
P = 50mA • (12.6V – 2.5V) + 1mA • 12.6V = 0.518W
Using a DFN package, the thermal resistance will be in
the range of 38°C/W to 45°C/W depending on the copper
area. So the junction temperature rise above ambient will
be approximately equal to:
0.518W • 45°C/W = 23.3°C
The maximum junction temperature equals the maximum
ambient temperature plus the maximum junction tempera-
ture rise above ambient or:
TJMAX = 85°C + 23.3°C = 108.3°C
Output Discharge
The LT3061 includes a low resistance medium voltage
NMOS device which rapidly discharges the output voltage
if the part is put in shutdown mode. For a 2.9V output
with a 10μF decoupling capacitor, this NMOS discharges
the output to 290mV in 750µs if SHDN is driven low.
Control circuitry drives the gate of the NMOS high if either
the SHDN pin or the IN pin are driven low. In the case
where the IN pin is driven to ground, the NMOS rapidly
discharges the OUT pin to the threshold voltage of the
NMOS, about 800mV. From 800mV, the external load
will continue to discharge the OUT pin at a reduced rate.
The control circuitry implements protection features which
allow the OUT pin to be driven from –1V to 20V without
damaging the LT3061. Current limit foldback for output
voltages greater than 6V protects the NMOS pull-down,
but increases discharge time for higher output voltages.
Figure 7. Discharge Time vs Output Voltage
OUTPUT VOLTAGE (V)
0
0
OUTPUT DISCHARGE TIME (ms)
3.5
3.0
1.0
1.5
2.0
2.5
0.5
4.0
2 4 12 14 16 18 206 8
3061 F07
10
COUT = 10µF
VIN = VOUT +1V
OUTPUT DISCHARGE
FOLDBACK STARTS
LT3061 Series
18
3061fb
For more information www.linear.com/LT3061
APPLICATIONS INFORMATION
Protection Features
The LT3061 incorporates several protection features that
make it ideal for use in battery-powered circuits. In ad-
dition to the normal protection features associated with
monolithic regulators, such as current limiting and thermal
limiting, the device also protects against reverse-input
voltages and reverse output-to-input voltages.
Current limit protection and thermal overload protection
protect the device against current overload conditions at
the output of the device. The typical thermal limit tem-
perature is 165°C. For normal operation, do not exceed
a junction temperature of 125°C (LT3061E, LT3061I) or
150°C (LT3061MP, LT3061H).
The LT3061 IN pin withstands reverse voltages of 50V. The
device limits current flow to less than 1mA (typically less
than 250µA) and no negative voltage appears at OUT. The
device protects both itself and the load against batteries
that are plugged in backwards.
The SHDN pin cannot be driven below GND unless tied to
the IN pin. If the SHDN pin is driven below GND while IN
is powered, the output will turn on. SHDN pin logic cannot
be referenced to a negative rail.
The LT3061 incurs no damage if the ADJ pin is pulled
above or below ground by 50V. If the input is left open
circuit or grounded, the ADJ pin performs like a large
resistor (typically 30k) in series with a diode when pulled
above or below ground.
Several different input/output conditions can occur, some
temporarily until the output capacitor is discharged by the
LT3061. The output voltage may be held up temporarily
or otherwise while the input is pulled to ground, pulled
to some intermediate voltage or left open-circuit. Current
flow back into the OUT pin follows the curve shown in
Figure 8. If the LT3061's IN pin is forced below the OUT
pin or the OUT pin is pulled above the IN pin, regardless
of the state of the SHDN pin, input current typically drops
to less than 3µA.
If IN is pulled near 0V, the output discharge pull-down
NMOS turns on, regardless of the state of the SHDN pin.
The gate drive for the pull-down is supplied by the output
voltage.
Figure 8. Reverse Output Current
VOUT (V)
0
0
OUTPUT CURRENT (µA)
45
40
30
35
20
25
5
10
15
50
2 12 14 16 18 204 6 8
3061 F08
10
VIN = VSHDN = 2.1V
VADJ = VOUT
LT3061 Series
19
3061fb
For more information www.linear.com/LT3061
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3061#packaging for the most recent package drawings.
3.00 ±0.10
(2 SIDES)
2.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
1.35 REF
1
4
85
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DCB8) DFN 0106 REV A
0.23 ±0.05
0.45 BSC
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
0.25 ±0.05
1.35 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.10 ±0.05
0.70 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.45 BSC
1.35 ±0.10
1.35 ±0.05
1.65 ±0.10
1.65 ±0.05
DCB Package
8-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1718 Rev A)
LT3061 Series
20
3061fb
For more information www.linear.com/LT3061
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3061#packaging for the most recent package drawings.
MSOP (MS8E) 0213 REV K
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
1 2 34
4.90 ±0.152
(.193 ±.006)
8
8
1
BOTTOM VIEW OF
EXPOSED PAD OPTION
765
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.52
(.0205)
REF
1.68
(.066)
1.88
(.074)
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
1.68 ±0.102
(.066 ±.004)
1.88 ±0.102
(.074 ±.004) 0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.65
(.0256)
BSC
0.42 ±0.038
(.0165 ±.0015)
TYP
0.1016 ±0.0508
(.004 ±.002)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.05 REF
0.29
REF
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev K)
LT3061 Series
21
3061fb
For more information www.linear.com/LT3061
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/16 Add 3.3V/5V fixed voltage options 1-22
B 11/17 Modified Guaranteed Dropout Voltage curve 5
LT3061 Series
22
3061fb
For more information www.linear.com/LT3061
LT 1117 REV B • PRINTED IN USA
www.linear.com/LT3061
ANALOG DEVICES, INC. 2014
TYPICAL APPLICATION
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LT3062 45V VIN, Micropower, Low Noise,
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with Active Output Discharge
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LT3082 200mA, Parallelable, Single Resistor,
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Outputs May Be Paralleled for Higher Output, Current or Heat Spreading, Wide Input Voltage
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Output Voltage Initial Set Pin Current Accuracy: 1%, Low Output Noise: 40μVRMS (10Hz to 100kHz)
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LT3085 500mA, Parallelable, Low Noise,
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275mV Dropout Voltage (2-Supply Operation), Low Noise: 40µVRMS, VIN: 1.2V to 36V,
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LT3092 200mA 2-Terminal Programmable
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3061 TA02
IN
SHDN
OUT
ADJ
GND BYP
LT3061
VIN
2.2V
VOUT
1.8V
100mA
1µF 10µF
118k
1%
59k
1%
0.01µF
1.8V Low Noise Regulator