UPD444016LLE-A12-A - RENESAS TECHNOLOGY

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MOS INTEGRATED CIRCUIT

PD444016L

4M-BIT CMOS FAST SRAM

256K-WORD BY 16-BIT

DATA SHEET

Document No. M14431EJ5V0DS00 (5th edition)

Date Published September 2006 NS CP(K)

Printed in Japan The mark <R> shows major revised points.

The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.

1999

Description

The

PD444016L is a high speed, low power, 4,194,304 bits (262,144 words by 16 bits) CMOS static RAM.

Operating supply voltage is 3.3 V ± 0.3 V.

The

PD444016L is packaged in 44-pin plastic SOJ and 44-pin plastic TSOP (II).

Features

• 262,144 words by 16 bits organization

• Fast access time : 8, 10, 12 ns (MAX.)

• Byte data control : /LB (I/O1 - I/O8), /UB (I/O9 - I/O16)

• Output Enable input for easy application

• Single +3.3 V power supply

Ordering Information

Part number Package Access time Supply current mA (MAX.)

ns (MAX.) At operating At standby

PD444016LLE-A8 44-pin plastic SOJ 8 210 5

PD444016LLE-A10 (10.16 mm (400)) 10 190

PD444016LLE-A12 12 180

PD444016LG5-A8-7JF 44-pin plastic TSOP (II) 8 210

PD444016LG5-A10-7JF (10.16 mm (400)) 10 190

PD444016LG5-A12-7JF (Normal bent) 12 180

PD444016LLE-A8-A 44-pin plastic SOJ 8 210

PD444016LLE-A10-A (10.16 mm (400)) 10 190

PD444016LLE-A12-A 12 180

PD444016LG5-A8-7JF-A 44-pin plastic TSOP (II) 8 210

PD444016LG5-A10-7JF-A (10.16 mm (400)) 10 190

PD444016LG5-A12-7JF-A (Normal bent) 12 180

Remark Products with -A at the end of the part number are lead-free products.

PD444016L

Data Sheet M14431EJ5V0DS

Pin Configuration (Marking Side)

/××× indicates active low signal.

44-pin plastic SOJ (10.16 mm (400))

[

PD444016LLE ]

[

PD444016LLE-A ]

44-pin plastic TSOP (II) (10.16 mm (400)) (Normal bent)

[

PD444016LG5-×××-7JF ]

[

PD444016LG5-×××-7JF-A ]

/CS

I/O1

I/O2

I/O3

I/O4

GND

I/O5

I/O6

I/O7

I/O8

/WE

A17

A16

A15

/OE

/UB

/LB

I/O16

I/O15

I/O14

I/O13

GND

I/O12

I/O11

I/O10

I/O9

A14

A13

A12

A11

A10

A0 - A17 : Address Inputs

I/O1 - I/O16 : Data Inputs / Outputs

/CS : Chip Select

/WE : Write Enable

/OE : Output Enable

/LB, /UB : Byte data select

CC : Power supply

GND : Ground

NC : No connection

Remark Refer to Package Drawings for the 1-pin index mark.

PD444016L

Data Sheet M14431EJ5V0DS

Block Diagram

GND

/WE

/OE

/CS

Input data

controller

Sense amplifier /

Switching circuit

Column decoder

Address buffer

A17

Address buffer

Row decoder

Memory cell array

4,194,304 bits

Output data

controller

/LB

/UB

I/O9 - I/O16

I/O1 - I/O8

Truth Table

/CS /OE /WE /LB /UB Mode I/O Supply current

I/O1 - I/O8 I/O9 - I/O16

H × × × × Not selected High impedance High impedance ISB

L L H L L Read DOUT DOUT ICC

L H DOUT High impedance

H L High impedance DOUT

L × L L L Write DIN DIN

L H DIN High impedance

H L High impedance DIN

L H H × × Output disable High impedance High impedance

L × × H H High impedance High impedance

Remark × : Don’t care

PD444016L

Data Sheet M14431EJ5V0DS

Electrical Specifications

Absolute Maximum Ratings

Parameter Symbol Condition Rating Unit

Supply voltage VCC –0.5 Note to +4.0 V

Input / Output voltage VT –0.5 Note to +4.0 V

Operating ambient temperature TA 0 to 70 °C

Storage temperature Tstg –55 to +125 °C

Note –2.0 V (MIN.) (pulse width : 2 ns)

Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Parameter Symbol Condition MIN. TYP. MAX. Unit

Supply voltage VCC 3.0 3.3 3.6 V

High level input voltage VIH 2.0 VCC+0.3 V

Low level input voltage VIL –0.3

Note +0.8 V

Operating ambient temperature TA 0 70 °C

Note –2.0 V (MIN.) (pulse width : 2 ns)

PD444016L

Data Sheet M14431EJ5V0DS

DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)

Parameter Symbol Test condition MIN. TYP. MAX. Unit

Input leakage current ILI VIN = 0 V to VCC –2 +2

Output leakage current ILO VI/O = 0 V to VCC, /CS = VIH or /OE = VIH –2 +2

or /WE = VIL or /LB = VIH or /UB = VIH

Operating supply current ICC /CS = VIL, Cycle time : 8 ns 210 mA

II/O = 0 mA, Cycle time : 10 ns 190

Minimum cycle time Cycle time : 12 ns 180

Standby supply current ISB /CS = VIH, VIN = VIH or VIL 40 mA

ISB1 /CS ≥ VCC – 0.2 V, 5

VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V

High level output voltage VOH IOH = –4.0 mA

2.4 V

Low level output voltage VOL IOL = +8.0 mA 0.4 V

Remarks 1. VIN : Input voltage

I/O : Input / Output voltage

2. These DC characteristics are in common regardless of package types.

Capacitance (TA = 25 °C, f = 1 MHz)

Parameter Symbol Test condition MIN. TYP. MAX. Unit

Input capacitance CIN VIN = 0 V 6 pF

Input / Output capacitance CI/O VI/O = 0 V 8 pF

Remarks 1. VIN : Input voltage

I/O : Input / Output voltage

2. These parameters are periodically sampled and not 100% tested.

PD444016L

Data Sheet M14431EJ5V0DS

AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)

AC Test Conditions

Input Waveform (Rise and Fall Time ≤ 3 ns)

Test Points

GND

3.0 V

1.5 V 1.5 V

Output Waveform

Test Points1.5 V 1.5 V

Output Load

AC characteristics directed with the note should be measured with the output load shown in Figure 1 or Figure

Figure 1 Figure 2

(tAA, tACS, tOE, tABD, tOH) (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW)

= +1.5 V

I/O (Output)

50 Ω

= 50 Ω

30 pF

+3.3 V

I/O (Output)

317 Ω

5 pF

351 Ω

Remark CL includes capacitances of the probe and jig, and stray capacitances.

PD444016L

Data Sheet M14431EJ5V0DS

Read Cycle

Parameter Symbol

PD444016L-A8

PD444016L-A10

PD444016L-A12 Unit Notes

MIN. MAX. MIN. MAX. MIN. MAX.

Read cycle time tRC 8 10 12 ns

Address access time tAA 8 10 12 ns 1

/CS access time tACS 8 10 12 ns

/OE access time tOE 4 5 6 ns

/LB, /UB access time tABD 4 5 6 ns

Output hold from address change tOH 3 3 3 ns

/CS to output in low impedance tCLZ 3 3 3 ns 2, 3

/OE to output in low impedance tOLZ 0 0 0 ns

/LB, /UB to output in low impedance tBLZ 0 0 0 ns

/CS to output in high impedance tCHZ 4 5 6 ns

/OE to output hold in high impedance tOHZ 4 5 6 ns

/LB, /UB to output hold in high impedance tBHZ 4 5 6 ns

Notes 1. See the output load shown in Figure 1.

2. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2.

3. These parameters are periodically sampled and not 100% tested.

Remark These AC characteristics are in common regardless of package types.

Read Cycle Timing Chart 1 (Address Access)

Address (Input)

I/O (Output) Previous data out Data out

Remarks 1. In read cycle, /WE should be fixed to high level.

2. /CS = /OE = /LB (or /UB) = VIL

PD444016L

Data Sheet M14431EJ5V0DS

Read Cycle Timing Chart 2 (/CS Access)

Address (Input)

tRC

tAA

tOLZ

/CS (Input)

I/O (Output) Data out

tOHZ

High impedance

tACS

/OE (Input)

tOE

tCLZ tCHZ

High impedance

/LB, /UB (Input)

tBLZ

tABD tBHZ

Caution Address valid prior to or coincident with /CS low level input.

Remark In read cycle, /WE should be fixed to high level.

PD444016L

Data Sheet M14431EJ5V0DS

Write Cycle

Parameter Symbol

PD444016L-A8

PD444016L-A10

PD444016L-A12 Unit Notes

MIN. MAX. MIN. MAX. MIN. MAX.

Write cycle time tWC 8 10 12 ns

/CS to end of write tCW 6 7 8 ns

Address valid to end of write tAW 6 7 8 ns

Write pulse width tWP 6 7 8 ns

/LB, /UB to end of write tBW 6 7 8 ns

Data valid to end of write tDW 4 5 6 ns

Data hold time tDH 0 0 0 ns

Address setup time tAS 0 0 0 ns

Write recovery time tWR 0 0 0 ns

/WE to output in high impedance tWHZ 4 5 6 ns 1, 2

Output active from end of write tOW 3 3 3 ns

Notes 1. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2.

2. These parameters are periodically sampled and not 100% tested.

Remark These AC characteristics are in common regardless of package types.

Write Cycle Timing Chart 1 (/WE Controlled)

tWC

tCW

tWP tWR

Address (Input)

/CS (Input)

/WE (Input)

I/O (Input / Output)

tDHtWHZ

tAW

High

impe-

dance

High

impe-

dance

tOW

Indefinite data out Data in Indefinite data out

tDW

tAS

/LB, /UB (Input)

tBW

Cautions 1. /CS or /WE should be fixed to high level during address transition.

2. Do not input data to the I/O pins while they are in the output state.

Remarks 1. Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB

(or low level /UB).

2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read

operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.

PD444016L

Data Sheet M14431EJ5V0DS

Write Cycle Timing Chart 2 (/CS Controlled)

tWC

tAS tCW

tAW

tWP tWR

tDW tDH

Address (Input)

/CS (Input)

/WE (Input)

/LB, /UB (Input)

High impedance Data in High impedance

tBW

I/O (Input)

Cautions 1. /CS or /WE should be fixed to high level during address transition.

2. Do not input data to the I/O pins while they are in the output state.

Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB

(or low level /UB).

PD444016L

Data Sheet M14431EJ5V0DS

Write Cycle Timing Chart 3 (/LB, /UB Controlled)

tWC

tAS tBW

tWR

tDW tDH

Address (Input)

/LB, /UB (Input)

/WE (Input)

/CS (Input)

High impedance Data in High impedance

tCW

I/O (Input)

tAW

tWP

Cautions 1. /CS or /WE should be fixed to high level during address transition.

2. Do not input data to the I/O pins while they are in the output state.

Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB

(or low level /UB).

PD444016L

Data Sheet M14431EJ5V0DS

Package Drawings

ITEM MILLIMETERS

NOTE

Each lead centerline is located within 0.12 mm of

its true position (T.P.) at maximum material condition.

D 11.18±0.20

10.16

B 28.73+0.20

−0.35

44-PIN PLASTIC SOJ (10.16 mm (400))

3.5±0.2

0.8 MIN.

0.74

E 1.03±0.15

H 2.3±0.2

0.12

1.27 (T.P.)

P44LE-400A-1

M 0.40±0.10

9.4±0.20

J 2.6

0.10Q

TR 0.85

U 0.20+0.10

−0.05

44 23

122

PD444016L

Data Sheet M14431EJ5V0DS

44-PIN PLASTIC TSOP (II) (10.16 mm (400))

NOTE

Each lead centerline is located within 0.13 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

18.63 MAX.

0.93 MAX.

0.1±0.05E

0.8 (T.P.)

1.2 MAX.

G0.97

H 11.76±0.2

I 10.16±0.1

J 0.8±0.2

D 0.32+0.08

−0.07

M0.13

N0.10

L 0.5±0.1

K 0.145+0.025

−0.015

P3°+7°

−3°

S44G5-80-7JF5-1

44 23

122

detail of lead end

PD444016L

Data Sheet M14431EJ5V0DS

Recommended Soldering Conditions

Please consult with our sales offices for soldering conditions of the

PD444016L.

Types of Surface Mount Device

PD444016LLE : 44-pin plastic SOJ (10.16 mm (400))

PD444016LG5-7JF : 44-pin plastic TSOP (II) (10.16 mm (400)) (Normal bent)

PD444016LLE-A : 44-pin plastic SOJ (10.16 mm (400))

PD444016LG5-7JF-A : 44-pin plastic TSOP (II) (10.16 mm (400)) (Normal bent)

Quality Grade

• A quality grade of the products is “Standard”.

• Anti-radioactive design is not implemented in the products.

• Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the

ground and so forth.

<R>

PD444016L

Data Sheet M14431EJ5V0DS

Revision History

Edition/ Page Type of Location Description

Date This Previous revision (Previous edition → This edition)

edition edition

5th edition/ p.14 p.14 Addition Quality Grade Section of Quality Grade has been added.

Sep. 2006

PD444016L

Data Sheet M14431EJ5V0DS

[ MEMO ]

PD444016L

Data Sheet M14431EJ5V0DS

[ MEMO ]

PD444016L

Data Sheet M14431EJ5V0DS

[ MEMO ]

PD444016L

Data Sheet M14431EJ5V0DS

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between VIL (MAX) and

VIH (MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

NOTES FOR CMOS DEVICES

PD444016L

The information in this document is current as of September, 2006. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

•

M8E 02. 11-1