DS028 (v1.2) November 5, 2001 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
•0.22 µm 5-layer epitaxial process
•QML certified
• Radiation hard ened FPGA s for spa ce and satellite
applications
• Guaranteed total ionizing dose to 100K Rad(si)
• Latch-up immune to LET = 125 M eV cm 2/mg
• SEU immunity achievable with recommen ded
redundanc y implementat ion
• Guaranteed over the full m ilit ary tem perat ure range
(–55°C to +125°C)
• Fast, high-density Field-Programm able Gate Arrays
- Densities from 100k to 1M system gates
- System performance up to 200 MHz
- Hot-swappab le for Compact PCI
• Multi-standard SelectI/O™ interfaces
- 16 high-performance interface standards
- Connec ts directly to ZBTRAM devices
• Built-in clock-man agem ent circuitry
- Four dedicated delay-locked loops (DLLs) for
advanced clock con trol
- Four primary low-skew g lobal clock distribution
nets, plu s 24 secondary global nets
• Hierarchical memor y system
- LUTs conf igurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
- Conf igurable synchronous dual-port ed 4k-bit
RAMs
- Fast interfaces to external high-perf ormance RAMs
• Flexible architecture that balances speed and density
- Dedicated carry logic for high-speed arithmetic
- Dedicat ed multiplier support
- Cas cade chain for wide-input functions
- A bundant registers/latches with clock enable, and
dual synchronous/ asynch ronous se t and reset
- Internal 3-state bussing
- IEEE 1 149 .1 boundary-scan logic
- Die-tem perature sensing device
• Supported by FPGA F oundation™ and Alliance
De v e lopment Systems
- Complete support f or Uni fied Libraries, Relationally
Placed Macros, and Design Manager
- Wide selection of PC and workstat ion platfor m s
• S RA M -based in-system configuration
- Unlimited reprogrammability
- Four programming modes
• Av ailable to Standard Microcircuit Drawings. Contact
Defense Su pply Center Columbus (DSCC) for more
inform ation at http://www.d scc. dla.mil
- 5962-99572 f or XQVR300
- 5962-99573 f or XQVR600
- 5962-99574 f or XQVR1000
Description
The QPro™ Virtex™ FPGA family delivers high-perfor-
mance, high-capacity programmable logic solutions. Dra-
matic increases in silicon efficiency result from optimizing
the new architecture for place-and-route efficiency and
explo iting an aggressive 5-layer-metal 0.22 µm CM OS pro-
cess. These advances make QPro Virtex FPGAs powerful
and flexible alternatives to mask-programmed gate arrays.
The Virtex radiation hardened family comprises the three
members shown in Table 1.
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable sy stem f eatures, a rich hierarchy of
fast, flexibl e interconnect resources, and advanced process
technology, the QPro Virtex family delivers a high-speed
and high-capacity programmable logic solution that
enhances design fle xibility while reducing time-to-market.
Refer to the “Virtex™ 2.5V Field Programmable Gate
Arrays” commercial data sheet for more information on
device architecture and timing specifications.
0QPro Virtex 2.5V Radiation
Hardened FPGAs
DS028 (v1.2) November 5, 2001 02Preliminary Product Speci fication
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QPro Virtex 2.5V Radiation Hard ened FPGAs
2www.xilinx.com DS028 (v1.2 ) November 5, 2001
1-800-255-7778 Preliminary Product Specification
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Radia tio n Specif ica tio ns(1)
Table 1: QPro Virtex Radiation Hardened Field-Programmable Gate Array Family Members.
Device System Gates CLB Array Logic Cells Maximum
Avai lable I/O Block RAM Bits Max Sele ct
RAM Bits
XQVR300 322,970 32x48 6,912 316 65,536 98,304
XQVR600 661,111 48x72 15,552 316 98,304 221,184
XQVR1000 1,124,022 64x96 27,648 404 131,072 393,216
Symbol Description Min Max Units
TID Total Ionizing Dose
Method 1019, Dose Rate ~9.0 rad(Si)/sec 100 - krad(Si)
SEL Sin gle Even t Latch-up Immuni ty
H eavy Ion Sa turation Cross Section
LET > 125 MeV cm 2/mg
-0(cm
2/Device)
SEUFH Single Event Upset CLB Flip-flop
H eavy Ion Sa turation Cross Section -6.5E – 8(cm
2/Bit)
SEUCH Single Event Upset Configuration Latch
H eavy Ion Sa turation Cross Section -8.0E – 8(cm
2/Bit)
SEUCP Single Event Upset Configuration Latch
Proton (63 MeV) Satur ation Cross Section -2.2E – 14 (cm2/Bit)
SEUBH Single Event Upset BRAM Bit
H eavy Ion Sa turation Cross Section -1.6E – 7(cm
2/Bit)
Notes:
1. For more inf ormation, refer to "R adiation Test Results of the Vi rte x FPGA for Space Based Reconfigur able Com puting" and "SEU
Miti gation Techniques f or Virtex FPGAs in Space Appl ications" a t http://www.xilinx.com/products/hirel_qml.htm.
QPro Virtex 2.5V Rad iation Hardened FPG As
DS028 (v1.2) November 5, 2001 www.xilinx.com 3
Preliminary Product Specification 1-800-255-7778
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Virtex Electrical Characteristics
Based on preliminary characterization. Further changes are not ex pected.
All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters
included are common to popular desi gns and typical applications. Contact the factory for design considerations requ iring
more detailed information.
Virtex DC Characteristics
Ab solu te Maxim u m Rati ng s
Recommended Operating Conditions
Symbol Description Min/Max Units
VCCINT Supply voltage relat ive to GND –0.5 to 3.0 V
VCCO Suppl y voltage relative to GND –0.5 to 4.0 V
VREF Input reference voltage –0.5 to 3.6 V
VIN(3) Input voltage relativ e to GND Using VREF –0.5 to 3.6 V
Internal thres hold –0.5 to 5.5 V
VTS Voltage applied to 3-state output –0.5 to 5.5 V
VCC Longes t supply voltage rise time from 1V to 2.375V 50 m s
TSTG Storage temperature (ambient) –65 to +150 °C
TJJunction temperature +150 °C
Notes:
1. Stresses beyond those l isted under Abs olute Maximum Rati ngs may cause permanent damage to the device. These are str ess
ratings onl y, and functiona l operation of the device at these or any other c ondition s beyond those li sted under Operating Condi tions
is not imp lied. Exposure to Absolute Maxi m um Ratings condition s for extended pe riods of tim e may affect device rel iability.
2. Power supplies may turn on in any order.
3. F or p rot racted peri ods (e.g., longer than a day), VIN shoul d not exceed VCCO by m ore t hat 3.6V.
Symbol Description Device Min Max Units
VCCINT Supply voltage relat ive to GND 2.5 – 5% 2.5 + 5% V
VCCO Suppl y voltage relative to GND 1.2 3.6 V
TIN Input signal transition time - 250 ns
TIC Initialization temperature range(4) XQVR300 –55 +125 °C
XQVR600 –55 +125 °C
XQVR1000 –40 +125 °C
TOC Operational temperature range(5) XQVR300 –55 +125 °C
XQVR600 –55 +125 °C
XQVR1000 –55 +125 °C
ICCINTQ Quiescent VCCINT suppl y current XQVR300 - 150 mA
XQVR600 - 200 mA
XQVR1000 - 200 mA
ICCCCOQ Quiescent VCCO supply current XQVR300 - 4.0 mA
XQVR600 - 4.0 mA
XQVR1000 - 4.0 mA
Notes:
1. Correct oper ation is guaranteed with a m inimum VCCINT of 2.25 V (Nominal VCCINT – 10%). Below the minimum value st ated above,
all delay pa rameters i ncrease b y 3% for each 50 mV reduction in VCCINT below the specified range.
2. At junct ion temperatures abo ve those listed as Ope rating Conditions, all dela y parameters increa se by 0.35% per °C.
3. Input and output measurement threshold is ~50% of VCC.
4. Init ializa ti on occurs from the moment of VCC ramp-up to the rising transition of the INIT pin.
5. The device is operational after the INI T pin h as tr ansiti oned high.
QPro Virtex 2.5V Radiation Hard ened FPGAs
4www.xilinx.com DS028 (v1.2 ) November 5, 2001
1-800-255-7778 Preliminary Product Specification
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QPro Virte x Pinouts
Device/Package Combinations and Maximum I/O
Pinout Tables
See the Xilinx WebLINX web site (http://www.xil-
inx.com/partinfo/databook.htm) for updates or additional
pinout information. For convenience, Table 2 and Table 3 list
the locations of special-purpose and power-supply pins.
Pins not listed are user I/Os.
Package
Maximum User I/O (excluding dedica ted clock pins)
XQVR300 XQVR600 XQVR1000
CB228 162 162 -
CG560 - - 404
Table 2: Virtex Ceramic Column Grid (CG560) Pinout
Pin Name Device CG560
GCK0 XQVR1000 AL17
GCK1 AJ17
GCK2 D17
GCK3 A17
M0 AJ29
M1 AK30
M2 AN32
CCLK C4
PROGRAM AM1
DONE AJ5
INIT AH5
BUSY/DOUT D4
D0/DIN E4
D1 K3
D2 L4
D3 P3
D4 W4
D5 AB5
D6 AC4
D7 AJ4
WRITE D6
CS A2
TDI D5
TDO XQVR1000 E6
TMS B33
TCK E29
DXN AK29
DXP AJ28
VCCINT
(VCCINT pins are listed
incrementally. Connect
all pins listed for both the
required dev ice and all
small er devices listed in
the same package.)
A21, B12,
B14, B18,
B28, C22,
C24, E9,
E12, F2,
H30, J1,
K32, M3,
N1, N29,
N33, U5,
U30, Y2,
Y31, AB2,
AB32, AD2,
AD32, AG3,
AG31, AJ13,
AK8, AK11,
AK17, AK20,
AL14, AL22,
AL27 , AN25
VCCO, Bank 0 A22, A26,
A30, B19 , B32
VCCO, Bank 1 A10, A16,
B13, C3, E5
VCCO, Bank 2 B2, D1,
H1, M1 , R2
Table 2: Vi rtex Ce ramic Col u m n Gr i d (CG560) Pinout
(Continued)
Pin Name Device CG560
QPro Virtex 2.5V Rad iation Hardened FPG As
DS028 (v1.2) November 5, 2001 www.xilinx.com 5
Preliminary Product Specification 1-800-255-7778
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VCCO, Bank 3 XQVR1000 V 1, AA2,
AD1, AK1 , AL2
VCCO, Bank 4 AM2, AM15,
AN4, AN8,
AN12
VCCO, Bank 5 AL31, AM21,
AN18, AN24,
AN30
VCCO, Bank 6 W32 , AB33,
AF33 , AK33,
AM32
VCCO, Bank 7 C3 2, D33,
K33, N32, T33
VREF
, Bank 0
Within each bank, if input
reference voltage is no t
required, all VREF pins
are general I/O.
A19 , D20,
D26, D29,
E21, E23,
E24, E27,
VREF
, Bank 1
Within each bank, if input
reference voltage is no t
required, all VREF pins
are general I/O.
A6 , D7 ,
D10, D11,
D13, D16,
E7, E15
VREF
, Bank 2
Within each bank, if input
reference voltage is no t
required, all VREF pins
are general I/O.
B3, G5,
H4, K5,
L5, N5,
P4, R1
VREF
, Bank 3
Within each bank, if input
reference voltage is no t
required, all VREF pins
are general I/O.
V4, W5,
AA4, AD3,
AE5, AF1,
AH4, AK2
VREF
, Bank 4
Within each bank, if input
reference voltage is no t
required, all VREF pins
are general I/O.
AK1 3, AL 7 ,
AL9, AL10,
AL16, AM4,
AM14,AN3
VREF
, Bank 5
Within each bank, if input
reference voltage is no t
required, all VREF pins
are general I/O.
AJ1 8, AJ2 5,
AK28, AL20,
AL2 4, AL29,
AM26, AN23
Table 2: Virtex Ceramic Column Grid (CG560) Pinout
(Continued)
Pin Name Device CG560
VREF, Ba nk 6
Within each bank, if input
reference voltage is not
required, all VREF pins
are general I/O.
XQVR1000 V29, Y32,
AA30,AD31,
AE29, AK32,
AE31, AH30
VREF, Ba nk 7
Within each bank, if input
reference voltage is not
required, all VREF pins
are general I/O.
D31, E31,
G31, H32,
K31, P31,
T31, L33
GND A1, A7, A12,
A14, A18, A20,
A24, A29,
A32, A33,
B1, B6,
B9, B15,
B23, B27,
B31, C 2 ,
E1, F32,
G2 , G33,
J32, K1,
L2, M33,
P1, P33,
R32, T1,
V33, W2,
Y1, Y33,
AB1, A C 3 2 ,
AD33 , AE2 ,
AG 1, AG32,
AH2, AJ33,
AL32, AM3,
AM7, AM11,
AM19, AM25,
AM28, AM33,
AN1, AN2,
AN5, AN10,
AN14, AN16,
AN20, AN22,
AN27, AN33
No Connect XQVR1000 C31, AC2, AK4,
AL3
Table 2: Vi rtex Ce ramic Col u m n Gr i d (CG560) Pinout
(Continued)
Pin Name Device CG560
QPro Virtex 2.5V Radiation Hard ened FPGAs
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1-800-255-7778 Preliminary Product Specification
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Table 3: CQFP Package (CB228)
Function Pin # Bank #
GND 1 7
TMS 2
IO 3
IO 4
IO_VREF_7 5
IO 6
IO 7
GND 8
IO 9
IO 10
IO 11
IO_VREF_7 12
IO 13
GND 14
VCCINT 15
IO 16
IO 17
VCCO 18
IO 19
IO 20
IO_VREF_7 21
IO 22
IO 23
IO 24
IO 25
IO_IRDY 26
GND 27
VCCO 28 6
IO_TRDY 29
VCCINT 30
IO 31
IO 32
IO 33
IO_VREF_6 34
IO 35
IO 36
VCCO 37
IO 38
IO 39
IO 40
VCCINT 41
GND 42
IO 43
IO_VREF_6 44
IO 45
IO 46
IO_VREF_6 47
GND 48
IO 49
IO 50
IO_VREF_6 51
IO 52
IO 53
IO 54
M1 55
GND 56
M0 57
Table 3: CQF P Pa ckage (CB228) (Continued)
Func t i on P i n # Bank #
QPro Virtex 2.5V Rad iation Hardened FPG As
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Preliminary Product Specification 1-800-255-7778
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VCCO 58 5
M2 59
IO 60
IO 61
IO 62
IO_VREF_5 63
IO 64
IO 65
GND 66
IO_VREF_5 67
IO 68
IO 69
IO_VREF5 70
IO 71
GND 72
VCCINT 73
IO 74
IO 75
VCCO 76
IO 77
IO 78
IO_VREF_5 79
IO 80
IO 81
IO 82
Table 3: CQFP Packa ge (CB228) (Continued)
Function Pin # Bank #
VCCINT 83 4
GCK1 84
VCCO 85
GND 86
GCKO 87
IO 88
IO 89
IO 90
IO 91
IO_VREF_4 92
IO 93
IO 94
VCCO 95
IO 96
IO 97
IO 98
VCCINT 99
GND 100
IO 101
IO_VREF_4 102
IO 103
IO 104
IO_VREF_4 105
GND 106
IO 107
IO 108
IO_VREF_4 109
IO 110
IO 111
IO 112
GND 113
DONE 114
VCCO 115
Table 3: CQF P Pa ckage (CB228) (Continued)
Func t i on P i n # Bank #
QPro Virtex 2.5V Radiation Hard ened FPGAs
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1-800-255-7778 Preliminary Product Specification
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PROGRAM 116 3
IO_INIT 117
IO_D7 118
IO 119
IO_VREF_3 120
IO 121
IO 122
GND 123
IO_VREF_3 124
IO 125
IO 126
IO_VREF_3 127
IO_D6 128
GND 129
VCCINT 130
IO_D5 131
IO 132
VCCO 133
IO 134
IO 135
IO_VREF_3 136
IO_D4 137
IO 138
IO 139
VCCINT 140
IO_TRDY 141
VCCO 142
Table 3: CQFP Packa ge (CB228) (Continued)
Function Pin # Bank #
GND 143 2
IO_IRDY 144
IO 145
IO 146
IO 147
IO_D3 148
IO_VREF_2 149
IO 150
IO 151
VCCO 152
IO 153
IO 154
IO_D2 155
VCCINT 156
GND 157
IO_D1 158
IO_VREF_2 159
IO 160
IO 161
IO_VREF_2 162
GND 163
IO 164
IO 165
IO_VREF_2 166
IO 167
IO_DIN_D0 168
IO_DOUT_BUSY 169
CCLK 170
VCCO 171
Table 3: CQF P Pa ckage (CB228) (Continued)
Func t i on P i n # Bank #
QPro Virtex 2.5V Rad iation Hardened FPG As
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Preliminary Product Specification 1-800-255-7778
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TDO 172 1
GND 173
TDI 174
IO_CS 175
IO_WRITE 176
IO 177
IO_VREF_1 178
IO 179
GND 180
IO_VREF_1 181
IO 182
IO 183
IO_VREF_1 184
IO 185
GND 186
VCCINT 187
IO 188
IO 189
IO 190
VCCO 191
IO 192
IO 193
IO_VREF_1 194
IO 195
IO 196
IO 197
IO 198
GCK2 199
GND 200
VCCO 201
Table 3: CQFP Packa ge (CB228) (Continued)
Function Pin # Bank #
GCK3 202 0
VCCINT 203
IO 204
IO 205
IO 206
IO_VREF_0 207
IO 208
IO 209
VCCO 210
IO 211
IO 212
IO 213
VCCINT 214
GND 215
IO 216
IO_VREF_0 217
IO 218
IO 219
IO_VREF_0 220
GND 221
IO 222
IO 223
IO_VREF_0 224
IO 225
IO 226
TCK 227
VCCO 228
Table 3: CQF P Pa ckage (CB228) (Continued)
Func t i on P i n # Bank #
QPro Virtex 2.5V Radiation Hard ened FPGAs
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1-800-255-7778 Preliminary Product Specification
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Pinout Diagrams
The following diagrams illustrate the locations of spe-
cial-purpose pins on Virtex FPGAs. Table 4 lists the sym-
bols used in these diagrams. The diagrams also show
I/O-bank boundaries.
GND 1, 8, 14, 27, 42,
48, 56, 66, 72,
86, 100, 106,
113, 123, 129,
143, 157, 163,
173, 180, 186,
200, 215, 221
-
VCCINT 15, 30, 41, 73,
83, 99, 1 30,
140, 156, 187,
203, 214
-
VCCO 18, 28, 37, 58,
76, 85, 95, 115,
133, 142, 152,
171, 191, 201,
210, 228
-
Table 4: Pinout Diagr am Symbol s
Sym bol Pi n Fu nc tion
S General I/O
d Device-dependent general I/O, n/c on
smaller devices
VV
CCINT
Table 3: CQFP Packa ge (CB228) (Continued)
Function Pin # Bank #
v Device-dependent VCCINT, n/c on sma ller
devices
OV
CCO
RV
REF
r Device-dependent VREF
, re ma i n s I/O o n
smaller devices
G Ground
Ø, 1, 2, 3 Global Clocks
❿, ❶, ❷ M0, M1, M2
➉, ➀, ➁, ➂,
➃, ➄, ➅, ➆D0 /DIN, D1, D2, D3, D4, D5, D6, D7
BDOUT/BUSY
DDONE
PPROGRAM
IINIT
K CCLK
WWRITE
SCS
T Boundary-scan test access po rt
+ Temperature diode, anode
–Temperature diode, cathode
n No connect
Table 4: Pinout Diagram Sym bol s (Continued)
Sym bol Pin Function
QPro Virtex 2.5V Rad iation Hardened FPG As
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Preliminary Product Specification 1-800-255-7778
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CG5 60 P i n Fu nc ti on Diag ram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
A
K
T
➆–
I+
Ø
O
1❶
B
➀➁
➃
➄
➅
❿
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
➉Bank 1 Bank 0
Bank 4
Bank 6
Bank 5
Bank 3
Bank 7Bank 2
CG560
(Top View)
W
27
28
29
30
31
32
33
27
28
29
30
31
32
33
AG
AH
AJ
AK
AL
AM
AN
AG
AH
AJ
AK
AL
AM
AN
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✳✳✳ ✳
✳✳
✳ ✳✳✳
✳✳✳
✳✳✳ ✳
✳✳
✳✳✳
✳✳✳✳
✳✳ ✳
✳ ✳✳✳
R
OR
O
G
O
GGRGO
G
PRV
VGR
RVG
G
RR G
R
G
n
OR O
VR
R
V
n
R
O
GO O
GG G
O
G
O
O
V
VG
OV R
OG
G
❷
OG
G
GO
V
GV
GVO
R
G
GG
R
GS RG OGGO3GGR VO G O GO GG
GO G G
v
VOGVOGGVGOT
GO V
n
O
OTRR R2R R RO
GOT
r
VVR R R
V G
GR RG
OR V
V G
GRVO
GR
O G
VOV
G➂RRG
OR G
GRO
VV
OR R G
GR O
GV VRG
D
n
v
v
v
v
v
v
v
rr rr rr
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
QPro Virtex 2.5V Rad iation Hardened FPG As
DS028 (v1.2) November 5, 2001 www.xilinx.com 13
Preliminary Product Specification 1-800-255-7778
R
De vice/Package Combinations and Maximum I/O
Ordering Information
Package
Maximum User I/O (excludi ng dedicated clock pins)
XQVR300 XQVR600 XQVR1000
CB228 162 162 -
CG560 - - 404
XQVR1000 -4 CG 560 V
Example: M anufacturing Grade
Numbe r of Pins
Package Type
De vi ce Type
Speed Grade (1)
Device Ordering Options
Device Type P ackage Grade
XQVR300 CB228 228-pin Ceramic Quad Flat Pac kage MM ilitary Ceramic TC = –55°C to +125°C
XQVR600 CG560 560-col um n Ceramic Column Grid Package VQP ro Plus TC = –55°C to +1 2 5°C
XQVR1000 Q MIL-PRF-38535(2) TC = –55°C to +125°C
Notes:
1. -4 only suppor ted speed grade.
2. Class Q must be ordered with SMD num ber.
Device Ordering Combinations
M Grade V Grade
XQVR300-4CB228M XQVR300-4CB228V
XQVR600-4CB228M XQVR600-4CB228V
XQVR1000-4CG560M XQVR1000-4CG560V
QPro Virtex 2.5V Radiation Hard ened FPGAs
14 www.xilinx.com DS028 (v1.2 ) November 5, 2001
1-800-255-7778 Preliminary Product Specification
R
SMD (Cla ss Q) Oder in g Optio ns
Revision History
The following table shows the revision histor y for this docum ent.
Date Version Revision
04 /25/00 1.0 In it ial X ilin x r ele as e .
02/13 /01 1.1 Updated Te mpe ratureSpecificat ions.
11/05 /01 1.2 Updated Te mp specifications for V60 0, Added Class V option and SMD. Updated for m at .
5962 R 9957201 Q Y C
Lead Finish
Generic S tand ard
Microcircuit Drawing (SMD)
De vi ce Type
Package Type
QML Certified M IL-PRF-3 8535
Valid SMD Combinations
SMD Number Device Pkg Marking s Le ad Finish
5962R9957201QYC XQVR300-4CB228Q Lid Gold Plate
5962R9957201QZC XQ VR300-4CB228Q Base Gold Plate
5962R9957301QYC XQVR600-4CB228Q Lid Gold Plate
5962R9957301QZC XQ VR600-4CB228Q Base Gold Plate
5962R9957401QXC XQVR1000-4CG560Q - Solder Column
Radiation Hardened
