Advanced Analog Technology, Inc.
May 2008
–
台灣類比科技股份有限公司
–
– Advanced Analog Technology, Inc. –
Version 1.00
Page 1 of 22
AAT1168/
1168
A/
1168
B
Product information presented is current as of publication date. Details are subject to change without notice.
TRIPLE-CHANNEL TFT LCD POWER SOLUTION
WITH OPERATIONAL AMPLIFIERS
FEATURES
Built in 3A, 0.2Ω Switching NMOS
Positive LDO Driver Up to 28V/5mA
Negative LDO Driver Down to
14V/5mA
−
1
COM
V
and 4
GAMMA
V
Operational Amplifiers
28V High Voltage Switch for VGH
Internal Soft-Start Function
1.2MHz Fixed Switching Frequency
3 Channels Fault and Thermal Protection
Low Dissipation Current
QFN-32 Package Available
PIN CONFIGURATION
AAT1168/
AAT1168A/
AAT1168B
1
2
3
4
5
6
7
8
EO
24
23
22
21
20
19
18
17
IN1
VOUT3
VREF
GND
GND1
VO1
VI1 -
VI1+
VO2 VO4
VI5+
VI5 -
VO5
SW
VDD
GENERAL DESCRIPTION
The AAT1168/AAT1168A/AAT1168B is a triple-channel
TFT LCD power solution that provides a step-up PWM
controller, two LDO drivers (one for positive high voltage
and one for negative voltage), five operational amplifiers,
and one high voltage switch up to 28V for TFT LCD
display.
The PWM controller consists of an on-chip voltage
reference, oscillator, error amplifier, current sense circuit,
comparator, under-voltage lockout protection and
internal soft-start circuit. The thermal and power fault
protection prevents internal circuit being damaged by
excessive power.
The LDO drivers generate two regulated output voltage
set by external resistor dividers. VGH voltage does not
activate until DLY voltage exceeds 1.25V.
The AAT1168/AAT1168A/AAT1168B contains 4+1
operational amplifiers. VO1, VO2, VO4, and VO5 are for
gamma corrections and VO3 is for
COM
V
. In the short
circuit condition, operational amplifiers are capable of
sourcing
mA100±
current for
GAMMA
V
, and
mA200±
current for
COM
V
.
With the minimal external components, the
AAT1168/A/B offers a simple and economical solution
for TFT LCD power.
Advanced Analog Technology, Inc.
May 2008
–
台灣類比科技股份有限公司
–
–
Advanced Analog Technology, Inc. –
Version 1.00
Page 2 of 22
AAT1168/
1168
A/
1168
B
ORDERING INFORMATION
NOTE: The product is lead free and halogen free.
TYPICAL APPLICATION
DEVICE
TYPE
PART
NUMBER
PACKAGE PACKING
TEMP.
RANGE MARKING
MARKING
DESCRIPTION
AAT1168 AAT1168
-Q5-T
Q5:VQFN32-
5*5
T: Tape
and Reel 40
C°
to
+
85
C°
AAT1168
XXXXX
XXXX
Device Type
Lot no.(6~9digits)
Date Code
(4digits)
AAT1168A
AAT1168A
-Q5-T
Q5:VQFN32-
5*5
T: Tape
and Reel 40
C°
to
+
85
C°
AAT1168A
XXXXX
XXXX
Device Type
Lot no.(6~9digits)
Date Code
(4Digits)
AAT1168B
AAT1168B
-Q5-T
Q5:VQFN32-
5*5
T: Tape
and Reel 40
C°
to
+
85
C°
AAT1168B
XXXXX
XXXX
Device Type
Lot no.(6~9digits)
Date Code
(4Digits)
Advanced Analog Technology, Inc.
May 2008
–
台灣類比科技股份有限公司
–
–
Advanced Analog Technology, Inc. –
Version 1.00
Page 3 of 22
AAT1168/
1168
A/
1168
B
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL VALUE UNIT
VDD
to GND
DD
V
7 V
VDD1
,
SW to GND (for AAT1168/AAT1168B)
H1
V
14.5 V
VDD1
,
SW to GND (for AAT1168A)
H1
V
25 V
VOUT3
,
OUT3, VGH to GND (for AAT1168/AAT1168B)
H2
V
28 V
VOUT3
,
OUT3, VGH to GND (for AAT1168A)
H2
V
40 V
OUT2 to GND
H3
V
14
−
V
Input Voltage 1 (IN1, IN2, IN3, DLY, CTL)
I1
V
DD
V
+0.3 V
Input Voltage 2
(VI1+,
−
VI1
, VI2+,
−
VI2
, VI3+,
−VI3
, VI4+,
−
VI4
, VI5+,
−VI5
)
I2
V
H1
V
+0.3 V
Output Voltage 1 (EO,
REF
V
)
O1
V
DD
V
+0.3 V
Output Voltage 2 (ADJ, VO1, VO2, VO3, VO4, VO5)
O2
V
H1
V
+0.3 V
Operating Free-Air Temperature Range
C
T
–40 C
to +85 C
C
Storage Temperature Range
STORAGE
T
–45 C
to +125 C
C
Maximum Junction Temperature
J
T +125 C
Package Thermal Resistance
A
J 34 C
/W
Package Thermal Resistance
C
J 1.1 C
/W
Power Dissipation
d
P 1,618 mW
NOTE: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the devices.
Exposure to ABSOLUTE MAXIMUM RATINGS conditions for extended periods may affect device reliability.
Advanced Analog Technology, Inc.
May 2008
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Advanced Analog Technology, Inc. –
Version 1.00
Page 4 of 22
AAT1168/
1168
A/
1168
B
ELECTRICAL CHARACTERISTICS
( V
DD
= 2.6V to 5.5V, T
C
= –40 C
°
to 85 C
°
, unless otherwise specified. Typical values are tested at 25 C
°
ambient
temperature, V
DD
= 5V, V
DD1
= 10V.)
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX
UNIT
VDD Input Voltage Range
DD
V 2.6 5.5 V
AAT1168/AAT1168B 8 14 V
VDD1 Input Voltage Range
DD1
V
AAT1168A 8 23 V
Falling 2.1 2.2 2.3 V
VDD Under Voltage Lockout
UVLO
V
Rising 2.3 2.4 2.5 V
IN1
V= 1.5V, Not Switching 0.56 0.80 mA
VDD Operating Current
VDD
I
IN1
V= 1.0V, Switching 5.60 10.0 mA
VDD1 Operating Current
VDD1
I
+VI1
V~
+VI5
V = 4V 7 10 mA
Thermal Shutdown
SHDN
T 160 C
Reference Voltage
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX
UNIT
Reference Voltage
REF
V I
VREF
= 100µA 1.231
1.250
1.269
V
Line Regulation
RI
V I
VREF
= 100µA,
DD
V= 2.6V~5.5V - 2 5 mV
Load Regulation
RO
V I
VREF
= 0~100 A
µ
- 1 5 mV
Oscillator
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX
UNIT
Oscillation Frequency
OSC
f 1.05 1.20 1.35 MHz
Maximum Duty Cycle
MAX
D 84 87 90 %
Advanced Analog Technology, Inc.
May 2008
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Advanced Analog Technology, Inc. –
Version 1.00
Page 5 of 22
AAT1168/
1168
A/
1168
B
ELECTRICAL CHARACTERISTICS
( V
DD
= 2.6V to 5.5V, T
C
= –40 C
°
to 85 C
°
, unless otherwise specified. Typical values are tested at 25 C
°
ambient
temperature, V
DD
= 5V, V
DD1
= 10V.)
Soft Start & Fault Detect
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX
UNIT
Channel 1 Soft Start Time
SS1
t 14 ms
Channel 2 Soft Start Time
SS2
t 14 ms
Channel 3 Soft Start Time
SS3
t 14 ms
Channel 1 to Channel 2 Delay
D12
t AAT1168A Only 7 ms
Channel 2 to Channel 3 Delay
D23
t AAT1168A Only 7 ms
AAT1168/AAT1168B 55 ms
During Fault Protect Trigger Time
FP
t
AAT1168A 165 ms
AAT1168/AAT1168B 1.00 1.05 1.10 V
IN1 Fault Protection Voltage
F1
V
AAT1168A 1.13 1.17 1.20 V
IN2 Fault Protection Voltage
F2
V 0.40 0.45 0.50 V
IN3 Fault Protection Voltage
F3
V 1.00 1.05 1.10 V
Error Amplifier (Channel 1)
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX
UNIT
Feedback Voltage
IN1
V 1.221
1.233
1.245
V
Input Bias Current
B1
I
IN1
V= 1V to 1.5V –40 0 40 nA
Feedback-Voltage Line Regulation
RI1
V
Level to Produce
V
EO
= 1.233V
2.6V <
DD
V< 5.5V
0.05 0.15 %/V
Transconductance
m
G
∆I = 5 A
µ
105
µ
S
Voltage Gain
V
A 1,500
V/V
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May 2008
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Version 1.00
Page 6 of 22
AAT1168/
1168
A/
1168
B
ELECTRICAL CHARACTERISTICS
( V
DD
= 2.6V to 5.5V, T
C
= –40 C
°
to 85 C
°
, unless otherwise specified. Typical values are tested at 25 C
°
ambient
temperature, V
DD
= 5V, V
DD1
= 10V.)
N-MOS Switch (Channel 1)
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX
UNIT
Current Limit
LIM
I 3.0 A
On-Resistance
ON
R
SW
I= 1.0A 0.2
Ω
Leakage Current
SWOFF
I
SW
V= 12V 0.01 20.00
A
µ
Negative Charge Pump (Channel 2)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX
UNIT
IN2 Threshold Voltage
IN2
V
OUT2
I= –100 A
µ
235 250 265 mV
IN2 Input Bias Current
B2
I
IN2
V= –0.25V to 0.25V –40 0 40 nA
OUT2 Leakage Current
OFF2
I
IN2
V= 0V, OUT2 = –12V 20
−
50
−
A
µ
OUT2 Source Current
OUT2
I
IN2
V= 0.35V, OUT2 = –10V
1 4 mA
Positive Charge Pump (Channel 3)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX
UNIT
IN3 Threshold Voltage
IN3
V
OUT3
I= 100 A
µ
1.22
1.25 1.28
V
IN3 Input Bias Current
B3
I
IN3
V= 1V to1.5V –40 0 40 nA
OUT3 Leakage Current
OFF3
I
IN3
V= 1.4V, OUT3 = 28V 40 80 A
µ
OUT3 Sink Current
OUT3
I
IN3
V= 1.1V, OUT3 = 25V 1 4 mA
Advanced Analog Technology, Inc.
May 2008
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–
–
Advanced Analog Technology, Inc. –
Version 1.00
Page 7 of 22
AAT1168/
1168
A/
1168
B
ELECTRICAL CHARACTERISTICS
( V
DD
= 2.6V to 5.5V, T
C
= –40 C
°
to 85 C
°
, unless otherwise specified. Typical values are tested at 25 C
°
ambient
temperature, V
DD
= 5V, V
DD1
= 10V.)
High Voltage Switch Controller
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX
UNIT
DLY Source Current
DLY
I –4 –5 –6 A
µ
DLY Threshold Voltage
DLY
V 1.22
1.25 1.28
V
DLY Discharge R
ON
DLY
R 8
Ω
CTL Input Low Voltage
IL
V 0.5 V
CTL Input High Voltage
IH
V 2 V
CTL Input Bias Current
B4
I
CTL
V= 0 to
DD
V –40 0 40 nA
Propagation Delay CTL to VGH
PP
t OUT3 = 25V 100 ns
VOUT3 to VGH Switch R-on
ONSC
R
DLY
V= 1.5V,
CTL
V= VDD 15 30
Ω
ADJ to VGH Switch R-on
ONDC
R
DLY
V= 1.5V,
CTL
V= GND 30 60
Ω
Advanced Analog Technology, Inc.
May 2008
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–
–
Advanced Analog Technology, Inc. –
Version 1.00
Page 8 of 22
AAT1168/
1168
A/
1168
B
ELECTRICAL CHARACTERISTICS
( V
DD
= 2.6V to 5.5V, T
C
= –40 C
°
to 85 C
°
, unless otherwise specified. Typical values are tested at 25 C
°
ambient
temperature, V
DD
= 5V, V
DD1
= 10V.)
V
COM
and V
GAMMA
Buffer
PARAMETER SYMBOL TEST CONDITIONS MIN
TYP MAX
UNIT
Input Offset Voltage
OS
V
+VI1
V~
+VI5
V= 4V - 2 12 mV
Input Bias Current
B5
I
+VI1
V~
+VI5
V= 4V –40 0 40 nA
VO1
I,
VO2
I,
VO4
I,
VO5
I=
10mA,
VI1
V,
VI2
V,
VI4
V,
VI5
V= 4V
- 4.02 4.05
OL
V
VO3
I= 50mA,
VI3
V= 4V - 4.03 4.06
VO1
I,
VO2
I,
VO4
I,
VO5
I=
–10mA
VI1
V,
VI2
V,
VI4
V,
VI5
V= 4V
3.95
3.98 -
Output Swing (for AAT1168)
OH
V
VO3
I=
mA50−
,
VI3
V= 4V 3.94
3.97 -
V
VO1
I,
VO2
I,
VO4
I,
VO5
I - 100
±
- mA
Short Circuit Current
SHORT
I
VO3
I - 200
±
- mA
Slew Rate SR
+VI1
V,
+VI3
V= 2V to 8V,
+VI3
V~
+VI5
V= 8V to 2V,
20% to 80%
- 12 - V/
s
µ
Settling Time
S
t
+VI1
V~
+VI5
V= 3.5V to
4.5V, 90% - 5 -
s
µ
Advanced Analog Technology, Inc.
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Page 9 of 22
AAT1168/
1168
A/
1168
B
PIN DESCRIPTION
PIN NO.
QFN-32 NAME I/O DESCRIPTION
1 VOUT3
- Channel 3 Output Voltage (gate high voltage input)
2 VREF O Internal Reference Voltage Output
3 GND - Ground
4 GND1 - SW MOS Ground
5 VO1 O Operational Amplifier 1 Output
6 VI1– I Operational Amplifier 1 Negative Input
7 VI1+ I Operational Amplifier 1 Positive Input
8 VO2 O Operational Amplifier 2 Output
9 VI2– I Operational Amplifier 2 Negative Input
10 VI2+ I Operational Amplifier 2 Positive Input
11 GND2 - Ground for Operational Amplifiers
12 VI3+ I V
COM
Operational Amplifier Positive Input
13 VO3 I V
COM
Operational Amplifier Output
14 VDD1 - High Voltage Power Supply Input
15 VI4+ I Operational Amplifier 4 Positive Input
16 VI4– I Operational Amplifier 4 Negative Input
17 VO4 O Operational Amplifier 4 Output
18 VI5+ I Operational Amplifier 5 Positive Input
19 VI5– I Operational Amplifier 5 Negative Input
20 VO5 O Operational Amplifier 5 Output
21 SW - Main PWM Switching Pin
22 VDD - Power Supply Input
23 IN1 I Main PWM Feedback Pin
24 EO O Main PWM Error Amplifier Output
25 IN3 I Positive Charge Pump Feedback Pin
26 OUT3 O Positive Charge Pump Output
27 IN2 I Negative Charge Pump Feedback Pin
Advanced Analog Technology, Inc.
May 2008
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Page 10 of 22
AAT1168/
1168
A/
1168
B
PIN NO.
QFN-32 NAME I/O DESCRIPTION
28 OUT2 O Negative Charge Pump Output
29 DLY I High Voltage Switch Delay Control
30 CTL I High Voltage Switch Control Pin
31 ADJ O Gate High Voltage Fall Time Setting Pin
32 VGH O Switching Gate High Voltage for TFT
FUNCTION BLOCK DIAGRAM
AAT1168
SW
GND1
OUT2
OUT3
VDD1
VOUT3
Reference Voltage
1. 233V
Comparator
Digital Control Block
Current Sense
and Limit
Oscillator
Error Amplifier
IN1
EO
VREF VDD
Fail / Thermal
Fail Control
0. 25V
IN2
1. 25V
IN3
CTL
GND
High Voltage Control
ADJ
VGH
VO1
VI1-
VI1+
VO2
VI2-
VI2+
VO3
VI3+
VO4
VI4+
VI5+
VI4-
VI5- VO5
DLY
GND2
2.5kΩ
-
-
Ω
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19 20
21
22
23
24
25 26
27 28
29
30
31
32
1.233V
1.25V
0.25V
Advanced Analog Technology, Inc.
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Page 11 of 22
AAT1168/
1168
A/
1168
B
TYPICAL APPLICATION CIRCUIT
VDD
22
SW
AAT1168/A/B
23
IN1
7VI1+
10 VI2+
15 VI4+
18 VI5+
12 VI3+
IN3
OUT3
6VI1-
5VO1
1
VOUT3
28
OUT2
27
IN2
30 CTL
31 ADJ
GND1
2
VREF
14
VDD1
32 VGH
VOUT1
13.3V/300mA
Vin
3.3V To 5V C1
10µF C2
0.1µF
C3
47µF
L
6.8µH
R2
97.6k
Ω
R3
10k
Ω
D
DFLS220L
3
GND
R1
10
Ω
21
C5
1µF
C4
0.1µF SW
C6
1µF
R5
200k
Ω
Q1
MMBT4403
SW
C7
1µF
26
R7
6.8k
Ω
C8
1µF
VOUT3
25V/30mA
25
R4
6.8k
Ω
SW
C9
0.1µF C10
0.1µF
Q2
MMBT4401
U1
BAT54S
U2
BAT54S
U3
BAT54S
R6
10k
Ω
C12
0.1µF
R9
10k
Ω
R8
62k
Ω
C11
1µF
VOUT2
-6V/30mA
11
GND2
VADD
9VI2-
8VO2
16 VI4-
17 VO4
19
20 VO5
VI5-
13 VO3
29 DLY
C13
1µF R16
10
Ω
C14
1µF R17
10
Ω
C15
1µF R18
10
Ω
C16
1µF R19
10
Ω
VCOM R20
10
Ω
C17
10µF
CTL
VGH R22
57.6k
Ω
C19
1.8nF
R21
C18
R10
R11
R12
R13
R14
R15
VGAMMA
4
24 EO
Figure 1. Typical Application Circuit
Advanced Analog Technology, Inc
.
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Page 12 of 22
AAT1168/1168A/1168B
TYPICAL OPERATING CHARACTERISTICS
(
IN
V= 5V,
OUT1
V= 12V,
OUT2
V= −7V,
OUT3
V= 27V,
C
T= +25 C
, unless otherwise noted.)
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.
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AAT1168/1168A/1168B
TYPICAL OPERATING CHARACTERISTICS
(
IN
V= 5V,
OUT1
V= 12V,
OUT2
V= −7V,
OUT3
V= 27V,
C
T= +25 C
, unless otherwise noted.)
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.
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Page 14 of 22
AAT1168/1168A/1168B
DESIGN PROCEDURE
Boost Converter Design
Setting the Output Voltage and Selecting
the Lead Compensation Capacitor
The output voltage of boost converter is set by the
resistor divider from the output (V
OUT1
) to GND with the
center tap connected to the IN1. Where
IN1
V, the boost
converter feedback regulation voltage is 1.233V.
Choose R
2
(Figure 2) between 5.1kΩ to 51kΩ and
calculate R
1
to satisfy the following equation.
OUT1
1 2
IN1
V
R R 1
V
= −
R1
R2
AAT1168/A/B
VREF
gm IN1
CP
RC
CC
EO
VOUT1
VIN1
23
24
Figure 2. Feedback Circuit
Inductor Selection
The minimum inductance value is selected to make
sure that the system operates in continuous conduction
mode (CCM) for high efficiency and to prevent EMI.
The equation of inductor used a parameter
κ
, which is
the ratio of the inductor peak to peak ripple current to
the input DC current. The best trade-off between
voltage ripple of transient output current and
permanent output current has a
κ
between 0.4 and
0.5.
2
O
O
V
L D(1 D)
I fs
η
≥ −
κ
,
IN
O
V
D 1
V
= −
,
Lpeak
IN
I
κ=I
η
: Boost converter efficiency
κ
: The ratio of the inductor peak to peak ripple current
to the input DC current
IN
V
: Input voltage
O
V
: Output voltage
O
I
: Output load current
S
f
: Switching frequency
D
: Duty cycle
LPEAK
I
: Inductor peak to peak ripple current
IN
I
: Input DC current
The AAT1168 SW current limit (
LIM
I
) and inductor’
saturation current rating (
LSAT
I
) should exceed
)peak(L
I
,
and the inductor's DC current rating should exceed
IN
I
.
For the best efficiency, choose an inductor with less
DC series resistance (
L
r
).
LIM
I
and
LSAT
I
>
)peak(L
I
LDC
I>
IN
I
s
IN
IN
)peak(
L
Lf2
DV
II +=
,
O
IN
I
I
(1 D)
=η −
,
2
O
DCR L
I
P r
(1 D)
≈
η −
LDC
I
: DC current rating of inductor
DCR
P
: Power loss of inductor series resistance
Table
1.Inductor Data List
C6-K1.8L
L
r
DC CURRENT RATING
3.9
H
µ
41 m
Ω
2.5A
6.8
H
µ
68 m
Ω
2.2A
10
H
µ
81 m
Ω
1.8A
MITSUMI Product-Max Height:
1.9mm
Example 1: In the typical application circuit (Figure 1)
the output load current is 300mA with 13.3V output
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voltage and input voltage of 5V. Choose a
κ
of 0.465
and efficiency of 90%.
≈≥
2
6
)376.0(624.0
1.1*3.0*465.0
3.13*9.0
L
6.8
H
µ
O
IN
I
I
(1 D)
=η −
=
0.89A
s
IN
IN
)peak(
L
Lf2
DV
II += =
1.095A
DCR
P
=
0.043W or 1% power loss
Schottky Diode Selection
Schottky has to be able to dissipate power. The
dissipated power is the forward voltage and input DC
current. To achieve the best efficiency, choose a
Schottky diode with less recovery capacitor (CT) for
fast recovery time and low forward voltage (VF).
For boost converter, the reverse voltage rating (V
R
)
should be higher than the maximum output voltage,
and current rating should exceed the input DC current.
DIODE
P
=
DCOMDSW
PP
+
DSW
P
=
sRF
fQV)D1(
−
TRR
CVQ
=
)D1/(IVP
OFDCOM
−
=
DIODE
P
: Total power loss of diode for boost converter
DSW
P
: Switching loss of diode for boost converter
DCOM
P
: Conduction loss of diode for boost converter
Table 2. Schottky
D
DD
D
ata
L
LL
L
ist
SMA
F
V
R
V
T
C
B220A 0.24V 14V 150pF
B240A 0.24V 28V 150pF
DIODES Product, Max-Height: 2.3mm
For example,
DCOMDSWDIODE
PPP
+
=
=
0.203W or 5.1% power loss.
Input Capacitor Selection
The input capacitors have two important functions in
PWM controller. First, an input capacitor provides the
power for soft start procedure and supply the current
for the gate-driving circuit. A 10
F
µ ceramic capacitor
is used in typical circuit. Second, an input bypass
capacitor reduces the current peaks, the input voltage
drop, and noise injection into the IC. A low ESR
ceramics capacitor 0.1
F
µ is used in typical circuit. To
ensure the low noise supply at
DD
V
,
DD
V
is decoupled
from input capacitor using an RC low pass filter.
Figure 3. Input Bypass Capacitor Affects the
DD
V
Drop
Output Capacitor
The output capacitor maintains the DC output voltage.
A Low ESR (
C
r
) ceramic capacitor can reduce the
output ripple and power loss. There are two
parameters which can affect the output voltage ripple:
1. the voltage drops when the inductor current flows
through the ESR of output capacitor; 2. charging and
discharging of the output capacitor also affect the
output voltage ripple.
)ESR(V)C(VV
RIPPLEOUTRIPPLERIPPLE
+=
OUTS
O
OUTRIPPLE
Cf
DI
)C(V
≈
RIPPLE L(peak) C
V (ESR) I r
≈
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( )
2
ESR Lpeak C
P = I .r
ESR:
Equivalent Series Resistance
Example 2:
OUT
C
= 38µF,
C
r=
20m
Ω
)C(V
OUTRIPPLE
=
4mV
)ESR(V
RIPPLE
=
22mV
RIPPLE
V
=
26mV
ESR
P
=
0.023W or 0.6% power loss
Boost Converter Power loss
The largest portions of power loss in the boost
converter are the internal power MOSFET, the inductor,
the Schottky diode, and the output capacitor. If the
boost converter has 90% efficiency, there is
approximately 3.3% power loss in the internal MOSFET,
1% power loss in the inductor, 5.1% power loss in the
Schottky diode, and 0.6% power loss in the output
capacitor.
Loop Compensation Design
The voltage-loop gain with current loop closed sets the
stability of steady state response and dynamic
performance of transient response. The loop
compensation design is as follows:
β
Figure 4. Closed-current Loop for Boost with PCM
β
−
+
+
−
+
−
Figure 5. Block Diagram of Boost Converter with
Peak Current Mode (PCM)
Power Stage Transfer Functions
The duty to output voltage transfer function
p
T
is
:
O esr z2
p p0
2 2
n n
V (s w )(s w )
T (s) T
ds 2 w s w
+ −
= =
+ ξ +
Where
( )
( )
C
p0 O
L C
r
T V
1 D R r
−
=− + ,
esr
C
1
w
Cr
=
And
(
)
L
rD1R
w
2
L
2z
−−
=,
( )
( )
2
L
nL C
1 D R r
wLC R r
− +
=+
( )
( )
( )
( )
2
L C L c
2
L C L
C[r R r R r 1 D ] L
2 LC R r [r 1 D R ]
+ + − +
ξ =
+ + −
,
FDSL
R)D1(Drrr −++=
L
r
is the inductor equivalent series resistance,
C
r
is
capacitor ESR,
L
R
is the converter load resistance,
C
is output filter capacitor,
DS
r
is
the transistor turn on
resistance, and
F
R
is the diode forward resistance.
The duty to inductor current transfer function
pi
T
is:
2
nn
2
zi
0pi
l
pi
wsw2s
ws
T
d
i
)s(T
+ξ+
+
==
Where
(
)
( )
O L C
pi0 L C
V R 2r
T ,
L R r
+
=+
( )
zi
L C
1
w
C R / 2 r
=+
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Current Sampling Transfer Function
Error voltage to duty transfer function
m
F
is:
(
)
( )
( )
2 2 2
s n n
m
ei pi0 CS zi sh
2f s 2 w s w
d
F (s) v T R s s w s w
+ ξ +
= = + +
Where
α+
α−
π
=1
1
w3
w
s
sh
,
a1
a2
MM
MM
+
−
=α
s s
w 2 f
= π
Therefore,
m
F
depends on duty to inductor current
transfer function
pi
T
, and
s
f
is the clock switching
frequency;
CS
R
is the current-sense amplifier
transresistance.
For the boost converter,
1
M
=
IN
V
/
L
and
2
M
=
(
O
V
−
IN
V
)/
L
.
For AAT1168,
CS
R
= 0.24 V/A,
a
M
is slope
compensation,
a
M
= 0.8×10
6.
The closed-current loop transfer function
icl
T
is
:
(
)
( )
( )
2 2
2n n
s
icl
2 2
CS pi0
zi sh s
s + 2ξw s + w
12f
T (s) = x
R T
s + w s + w s +12f
The Voltage-Loop Gain with Current Loop
Closed
The control to output voltage transfer function
d
T
is
:
O
d icl p
C
V (s)
T (s) = = T (s)T (s)
V (s)
The voltage-loop gain with current loop closed is:
vi C d
L (s) = β
T (s)T (s)
2
s p0
c
m C
CS pi0
12f T
s w
g R s R T
+
= β ×
(
)
(
)
( )
)f12sws(ws
wsws
2
s
h
s
2
zi
2z1z
+++
−+
Where
FB
O
V
β=
V
The compensator transfer function
C c
C m C
fb
V s w
T (s) g R
v s
+
= =
Where
c
C C
1
w
R C
=
Figure 6. Voltage Loop Compensator
Compensator design guide:
1. Crossover frequency
sci
f
2
1
f<
2. Gain margin>10dB
3. Phase margin>45
∘
4. The
1)s(L
vi
=
at crossover frequency, Therefore,
the compensator resistance,
C
R
is determined by:
(
)
( ) ( )
L C
O ci CS
CFB m
L
R 2r
V 2 f CR
RV g k r
1 D R 1 D
+
π
=
− −
−
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AAT1168/1168A/1168B
Table 3 K factor Table
C Best Corner
Frequency K factor
21.533µF 23.740 kHz 4.692
25.079µF 21.842 kHz 5.083
32.587µF 20.095 kHz 6.042
36.312µF 15.649 kHz 5.230
38.469µF 13.247 kHz 4.703
5. The output filter capacitor is chosen so
C
L
R
pole
cancels
C
R
C
C
zero
L
C C C
R
R C C r
2
ε = +
, and
L
C C
C
R
C
C r
R 2
= +
ε
)3~1(=ε
Example 3:
IN
V
= 5V,
O
V
= 13.3V,
O
I
= 300mA,
s
f
= 1,190kHz,
FB
V
= 1.233V,
L
= 6.65µH,
m
G
= 85µS,
L
r
=
76.689
m
Ω
C
r
= 9.13m
Ω
,
F
R
= 0.7667
Ω
,
C
C
= 1.95nF,
C
R
= 7.6k
Ω
,
C
= 38.5µF,
ε
= 3,
CS
R
= 0.23V/A.
10
2
10
3
10
4
10
5
10
6
-270
-225
-180
-135
-90
Phase (deg)
Bode Diagram
Frequency (Hz)
-40
-20
0
20
40
60
Magnitude (dB)
Figure 7. Bode Plot of Loop Gain Using Matlab
®
Simulation
Positive and Negative LDO driver
Output Voltage Selection
The output voltage of positive LDO driver is set by a
resistive divider from the output (Vout3) to GND with
the center tap connected to the IN3, where V
IN3
, the
positive LDO driver feedback regulation voltage, is
1.25V. Choose R
6
(Figure 8) between 10k
Ω
and
51k
Ω
. And calculate R
5
with the following equation.
−= 1
V
3Vout
RR
3
IN
65
The output voltage of negative LDO driver is set by a
resistive divider from the output (VGL) to VREF with
the center tap connected to the IN2, where V
IN2,
the
negative LDO driver feedback regulation voltage, is
0.25V. Choose R
9
(Figure 9) between 10k
Ω
and
51k
Ω
and calculate R
8
with the following equation.
−
−
=
2INREF
GL2IN
98
VV
VV
RR
Figure 8. The Positive LDO Driver
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AAT1168/1168A/1168B
28
OUT2
27
IN 2
2
VREF
R7
6.8k Ω
SW
C9
0.1µF C10
0.1µF
Q2
MMBT4401
U3
BAT 54 S
C12
0.1µF
R9
10k Ω
R8
62kΩ
C11
1µF
VOUT2
-6V/30mA
Figure 9. The Negative LDO Driver
Example 4:
For system design
V
OUT3
= 25V,
5
R
= 200k
Ω
,
6
R
= 10k
Ω
,
V
OUT2
= −6V,
8
R
= 62k
Ω
,
9
R
= 10k
Ω
Flying Capacitors
Increasing the flying capacitor (
5
C
,
7
C
,
9
C
) values
can lower output voltage ripples. The 1µF ceramic
capacitors works well in positive LDO driver. A 0.1µF
ceramic capacitor works well in negative LDO driver.
LDO Driver Diode
To achieve high efficiency, a Schottky diode should be
used. BAT54S (Figure 8 and 9) has fast recovery time
and low forward voltage for best efficiency.
LDO Driver Base-Emitter Resistors
For AAT1168, the minimum drive current for positive
and negative LDO driver are 1mA, thus the minimum
base-emitter resistance can be calculated by the
following equation:
≥
(min)
4
R
)hfe/)II/((V
)
min
(C
(min)
3OUT(max)BE
−
≥
(min)
7
R )hfe/)II/((V
)
min
(C
(min)
2OUT(max)BE
−
Table 4 Pass Transistor Specifications
MMBT4401 MMBT4403
(max)BE
V
0.65V 0.5V
(min)
hfe
130 90
DIODES Product, Case: SOT23
Example 5:
Output current of V
OUT3
and V
OUT2
are 30mA, the
minimum base-emitter resistor can be calculated as
≥
(min)
4
R≥− )90/)mA30mA1/((5.0
750
Ω
≥
(min)
7
R≥− )130/)mA30mA1/((65.0
845
Ω
The minimum value can be used, however, the larger
value has the advantage of reducing quiescent current.
So we choose 6.8k
Ω
to be R
4
.
Charge Pump Output Capacitor
Using low ESR ceramic capacitor to reduce the output
voltage ripple is recommended. With ceramic capacitor,
output voltage ripple is dominated by the capacitance
value. The minimum capacitance value can be
calculated by the following equation:
sripple
load
fV2
I
Cout ≥
Example 6:
The output voltage ripple of V
OUT3
and VGL is under 1%,
the minimum capacitance value can be calculated as
OUT3
30mA
Cout(V )
2 250mV 1.19MHz
≥ ≈
η × ×
0.1µF
≈
××η
≥MHz19.1mV602
mA30
)V(Cout
GL
0.33µF
η
: Efficiency, about 60% at charge pump circuit
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AAT1168/1168A/1168B
Operational Amplifier
The AAT1168 have five amplifiers independent. The
operational amplifiers are usually used to drive V
COM
and the gamma correction divider string for TFT-LCD.
The output resistors and capacitors of amplifiers are as
low pass filter and compensator for unity GAIN stable.
Table 5. Recommended Components
DESIGNATION
DESCRIPTION
L 6.8 µH, 1.8A,
MITSUMI C6-K1.8L 6R8
U1, U2, U3
200mA 30V Schottky barrier
diode (SOT-23),
DIODES BAT54S
D 2A 20V rectifier diode
DIODES DFLS220L
C3 10 µF, 25V X5R ceramic
capacitor
C5, C6, C7 1 µF, 25V X5R ceramic capacitor
C2, C4, C9,
C10, C12
0.1 µF, 50V X5R ceramic
capacitor
S
oft Start Waveform
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AAT1168/1168A/1168B
LAYOUT CONSIDERATION
Layout Guide
The system’s performances including switching noise,
transient response, and PWM feedback loop stability
are greatly affected by the PC board layout and
grounding. There are some general guidelines for
layout:
Inductor
Always try to use a low EMI inductor with a ferrite core.
Filter Capacitors
Place low ESR ceramics filter capacitors (between
0.1µF and 0.22µF) close to VDD and VREF pins. This
will eliminate as much trace inductance effects as
possible and give the internal IC rail a cleaner voltage
supply. The ground connection of the VDD and VREF
bypass capacitor should be connected to the analog
ground pin (GND) with a wide trace.
Output Capacitors
Place output capacitors as close as possible to the IC.
Minimize the length and maximize the width of traces to
get the best transient response and reduce the ripple
noise. We choose 10µF ceramics capacitor to reduce
the ripple voltage, and use 0.1µF ceramics capacitor to
reduce the ripple noise.
Feedback
If external compensation components are needed for
stability, they should also be placed close to the IC.
Take care to avoid the feedback voltage-divider
resistors’ trace near the SW. Minimize feedback track
lengths to avoid the digital signal noise of TFT control
board.
Ground Plane
The grounds of the IC, input capacitors, and output
capacitors should be connected close to a ground
plane. It would be a good design rule to have a ground
plane on the PCB. This will reduce noise and ground
loop errors as well as absorb more of the EMI radiated
by the inductor. For boards with more than two layers,
a ground plane can be used to separate the power
plane and the signal plane for improved performance.
PC Board Layout
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AAT1168/1168A/1168B
PACKAGE DIMENSION
VQFN32
DIMENSIONS IN MILLIMETERS
SYMBOL MIN TYP MAX
A 0.8 0.9 1.0
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
C ------ 0.2 ------
D 4.9 5.0 5.1
D2 3.05 3.10 3.15
E 4.9 5.0 5.1
E2 3.05 3.10 3.15
e ------ 0.5 ------
L 0.35 0.40 0.45
y 0.000 ------ 0.075
PIN 1 INDENT
E
D A
A1
C
E2
D2
L
e
b
PIN 1 INDENT
E
D A
A1
C
E2
D2
L
e
b
PIN 1 INDENT
E
D A
A1
C
E2
D2
L
e
b
