SGLS130B - JULY 2002 - REVISED DECEMBER 2003 D Compatible With TMS320 and SPI Serial features D Controlled Baseline D D D D D D D D D - One Assembly/Test Site, One Fabrication Site Extended Temperature Performance up to -55C to 125C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree Dual 12-Bit Voltage Output DAC Programmable Internal Reference Programmable Settling Time: 1 s in Fast Mode, 3.5 s in Slow Mode Ports Differential Nonlinearity <0.5 LSB Typ Monotonic Over Temperature applications D D D D D Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices D PACKAGE (TOP VIEW) DIN SCLK CS OUTA Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 8 2 7 3 6 4 5 VDD OUTB REF AGND description The TLV5638 is a dual 12-bit voltage output DAC with a flexible 3-wire serial interface. The serial interface allows glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable precision voltage reference, the TLV5638 simplifies overall system design. Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package to reduce board space. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE TA -40C to 125C SOIC - D Tape and reel TLV5638QDREP -55C to 125C SOIC - D Tape and reel TLV5638MDREP TOP-SIDE MARKING 5638QE 5638ME Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. Copyright 2002 - 2003, Texas Instruments Incorporated !"#$%! & '("")% $& ! *(+,'$%! -$%) "!-('%& '!!"# %! &*)''$%!& *)" %.) %)"#& ! )/$& &%"(#)%& &%$-$"- 0$""$%1 "!-('%! *"!')&&2 -!)& !% )')&&$",1 ',(-) %)&%2 ! $,, *$"$#)%)"& POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 functional block diagram REF AGND VDD PGA With Output Enable Voltage Bandgap Power-On Reset Power and Speed Control 2 2 2-Bit Control Latch x2 OUTA x2 OUTB DIN 12-Bit DAC A Latch 12 SCLK Serial Interface and Control CS 12 12 Buffer 12 12-Bit DAC B Latch 12 Terminal Functions TERMINAL NAME NO. I/O/P DESCRIPTION AGND 5 P Ground CS 3 I Chip select. Digital input active low, used to enable/disable inputs DIN 1 I Digital serial data input OUT A 4 O DAC A analog voltage output OUT B 7 O DAC B analog voltage output REF 6 I/O Analog reference voltage input/output SCLK 2 I Digital serial clock input VDD 8 P Positive power supply 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5638Q (see Note 1) . . . . . . . . . . . . . . . . . . . . . -40C to 125C TLV5638M (see Note 1) . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage temperature range, Tstg (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Package thermal impedance, JA: D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131C/W Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See www.ti.com/ep_quality for additional information on enhanced plastic packaging. recommended operating conditions Supply voltage, VDD VDD = 5 V VDD = 3 V Power on reset, POR VDD = 2.7 V VDD = 5.5 V Low-level digital input voltage, VIL VDD = 2.7 V VDD = 5.5 V Reference voltage, Vref to REF terminal NOM MAX 4.5 5 5.5 V 2.7 3 3.3 V 2 V 0.55 High-level digital input voltage, VIH Reference voltage, Vref to REF terminal MIN 2 V 2.4 0.6 0.8 VDD = 5 V (see Note 1) VDD = 3 V (see Note 1) Load resistance, RL AGND 2.048 AGND 1.024 VDD -1.5 VDD -1.5 2 Load capacitance, CL Clock frequency, fCLK Operating free-air temperature, TA UNIT V V V k 100 pF 20 MHz TLV5638Q (see Note 2) -40 125 TLV5638M (see Note 2) -55 125 C NOTES: 1. Due to the x2 output buffer, a reference input voltage (VDD-0.4 V)/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used. 2. Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See www.ti.com/ep_quality for additional information on enhanced plastic packaging. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 electrical characteristics over recommended operating conditions, Vref = 2.048 V, Vref = 1.024 V (unless otherwise noted) power supply PARAMETER IDD TEST CONDITIONS No load, All inputs = AGND or VDD, DAC latch = 0x800 Power supply current MIN Power supply rejection ratio MAX VDD = 5 V, Int. ref. Fast 4.3 7 Slow 2.2 3.6 VDD = 3 V, Int. ref. Fast 3.8 6.3 Slow 1.8 3.0 VDD = 5 V, Ext. ref. Fast 3.9 6.3 Slow 1.8 3.0 VDD = 3 V, Ext. ref. Fast 3.5 5.7 Slow 1.5 2.6 0.01 10 Power-down supply current PSRR TYP Zero scale, See Note 2 -65 Full scale, -65 See Note 3 UNIT mA mA mA mA A dB NOTES: 3. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) - EZS(VDDmin))/VDDmax] 4. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) - EG(VDDmin))/VDDmax] static DAC specifications PARAMETER TEST CONDITIONS Resolution MIN TYP MAX UNIT 12 bits INL Integral nonlinearity, end point adjusted See Note 4 1.7 6 LSB DNL Differential nonlinearity See Note 5 0.4 1 LSB EZS EZS TC Zero-scale error (offset error at zero scale) See Note 6 Zero-scale-error temperature coefficient See Note 7 EG Gain error See Note 8 24 10 mV ppm/C 0.6 % full scale V EG TC Gain error temperature coefficient See Note 9 10 ppm/C NOTES: 5. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 32 to 4095. 6. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 7. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 8. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/Vref x 106/(Tmax - Tmin). 9. Gain error is the deviation from the ideal output (2Vref - 1 LSB) with an output load of 10 k excluding the effects of the zero-error. 10. Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (Tmin)]/Vref x 106/(Tmax - Tmin). 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 electrical characteristics over recommended operating conditions, Vref = 2.048 V, Vref = 1.024 V (unless otherwise noted) (continued) output specifications PARAMETER VO TEST CONDITIONS Output voltage MIN RL = 10 k Output load regulation accuracy TYP 0 VO = 4.096 V, 2.048 V, MAX VDD-0.4 UNIT V % full 0.25 scale V RL = 2 k reference pin configured as output (REF) PARAMETER Vref(OUTL) Vref(OUTH) Low reference voltage Iref(source) Iref(sink) Output source current TEST CONDITIONS High reference voltage VDD > 4.75 V MIN TYP MAX UNIT 1.003 1.024 1.045 V 2.027 2.048 2.069 V 1 Output sink current -1 mA Load capacitance PSRR 100 Power supply rejection ratio mA -65 pF dB reference pin configured as input (REF) PARAMETER VI RI Input voltage CI Input capacitance TEST CONDITIONS MIN TYP 0 MAX VDD-1.5 Input resistance 10 Reference input bandwidth REF = 0.2 Vpp + 1.024 V dc Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) Slow V M 5 Fast UNIT pF 1.3 MHz 525 kHz -80 dB NOTE 11: Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER IIH IIL High-level digital input current Ci Input capacitance TEST CONDITIONS VI = VDD VI = 0 V Low-level digital input current MIN TYP 1 * DALLAS, TEXAS 75265 UNIT A A -1 8 POST OFFICE BOX 655303 MAX pF 5 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 electrical characteristics over recommended operating conditions (unless otherwise noted) (continued) analog output dynamic performance PARAMETER TEST CONDITIONS MIN TYP MAX Fast 1 3 Slow 3.5 7 Fast 0.5 1.5 Slow 1 2 Fast 12 Slow 1.8 ts(FS) Output settling time, full scale RL = 10 k, See Note 11 CL = 100 pF, ts(CC) Output settling time, code to code RL = 10 k, See Note 12 CL = 100 pF, SR Slew rate RL = 10 k, See Note 13 CL = 100 pF, Glitch energy DIN = 0 to 1, CS = VDD FCLK = 100 kHz, Signal-to-noise ratio 69 74 S/(N+D) Signal-to-noise + distortion 58 67 THD Total harmonic distortion fs = 480 kSPS, fout = 1 kHz, RL = 10 kk,, CL = 100 pF Spurious free dynamic range -69 57 ss ss V/ s V/s 5 SNR UNIT nV-s -57 dB 72 NOTES: 12. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design. 13. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. 14. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. digital input timing requirements MIN NOM MAX UNIT tsu(CS-CK) tsu(C16-CS) Setup time, CS low before first negative SCLK edge Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns 10 ns twH twL SCLK pulse width high 25 ns SCLK pulse width low 25 ns tsu(D) th(D) Setup time, data ready before SCLK falling edge 10 ns Hold time, data held valid after SCLK falling edge 5 ns 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 PARAMETER MEASUREMENT INFORMATION twL SCLK X 1 2 tsu(D) DIN X twH 3 4 5 15 X 16 th(D) D15 D14 D13 D12 D1 D0 X tsu(C16-CS) tsu(CS-CK) CS Figure 1. Timing Diagram TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE POWER DOWN SUPPLY CURRENT vs TIME 4.5 2.4 4 2.2 I DD - Supply Current - mA I DD - Power Down Supply Current - mA 2.6 2 1.8 1.6 1.4 1.2 1 0.8 Fast Mode 3.5 3 2.5 2 Slow Mode 1.5 0.6 0.4 1 0.2 0 0 10 20 30 40 50 60 70 80 t - Time - s VDD = 5 V Vref = Int. 2 V Input Code = Full Scale (Both DACs) 0.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TA - Free-Air Temperature - C Figure 2 Figure 3 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT SUPPLY CURRENT vs FREE-AIR TEMPERATURE 2.064 4.5 2.062 3.5 Fast Mode 3 2.5 2 Slow Mode 1.5 2.06 Slow Mode 2.058 2.056 2.054 2.052 1 2.05 0.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 TA - Free-Air Temperature - C 0 0.5 1 1.5 2 2.5 3 3.5 4 3.5 4 Source Current - mA Figure 4 Figure 5 OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 3 4.128 VDD = 5 V Vref = Int. 2 V Input Code = 4095 Fast Mode VDD = 3 V Vref = Int. 1 V Input Code = 0 2.5 VO - Output Voltage - V 4.126 VO - Output Voltage - V VDD = 3 V Vref = Int. 1 V Input Code = 4095 Fast Mode VO - Output Voltage - V I DD - Supply Current - mA 4 VDD = 3 V Vref = Int. 1 V Input Code = Full Scale (Both DACs) 4.124 Slow Mode 4.122 4.12 4.118 Fast Mode 2 1.5 1 0.5 4.116 Slow Mode 0 4.114 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1.5 2 2.5 Sink Current - mA Source Current - mA Figure 6 8 1 Figure 7 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY THD+N - Total Harmonic Distortion and Noise - dB 5 VDD = 5 V Vref = Int. 2 V Input Code = 0 4.5 3.5 Fast Mode 3 2.5 2 1.5 1 0.5 Slow Mode 0 0 0.5 1 1.5 2 2.5 Sink Current - mA 3 3.5 4 VDD = 5 V Vref = 1 V dc + 1 V p/p Sinewave Output Full Scale -10 -20 -30 -40 -50 -60 Slow Mode -70 Fast Mode -80 -90 -100 100 1000 10000 100000 f - Frequency - Hz Figure 8 Figure 9 TOTAL HARMONIC DISTORTION vs FREQUENCY 0 THD - Total Harmonic Distortion - dB VO - Output Voltage - V 4 0 -10 VDD = 5 V Vref = 1 V dc + 1 V p/p Sinewave Output Full Scale -20 -30 -40 -50 -60 -70 Slow Mode -80 Fast Mode -90 -100 100 10000 1000 100000 f - Frequency - Hz Figure 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 INL - Integral Nonlinearity Error - LSB TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY ERROR 4 3 2 1 0 -1 -2 -3 -4 0 1024 2048 3072 4096 Digital Code DNL - Differential Nonlinearily Error - LSB Figure 11 DIFFERENTIAL NONLINEARITY ERROR 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 1024 2048 Digital Code 3072 4096 Figure 12 APPLICATION INFORMATION general function The TLV5638 is a dual 12-bit, single supply DAC, based on a resistor string architecture. It consists of a serial interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by: 2 REF CODE [V] 0x1000 Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power on reset initially puts the internal latches to a defined state (all bits zero). 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 APPLICATION INFORMATION serial interface A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word. Figure 13 shows examples of how to connect the TLV5638 to TMS320, SPI, and Microwire. TMS320 DSP FSX DX CLKX TLV5638 CS DIN SCLK SPI I/O MOSI SCK TLV5638 CS DIN SCLK Microwire I/O SO SK TLV5638 CS DIN SCLK Figure 13. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the pin connected to CS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5638. After the write operation(s), the holding registers or the control register are updated automatically on the 16th positive clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f sclkmax + 1 + 20 MHz t whmin ) t wlmin The maximum update rate is: f updatemax + 1 + 1.25 MHz 16 t whmin ) t wlmin Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5638 has to be considered, too. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 APPLICATION INFORMATION data format The 16-bit data word for the TLV5638 consists of two parts: D Program bits D New data (D15..D12) (D11..D0) D15 D14 D13 D12 R1 SPD PWR R0 SPD: Speed control bit PWR: Power control bit D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 12 Data bits 1 fast mode 1 power down 0 slow mode 0 normal operation The following table lists the possible combination of the register select bits: register select bits R1 R0 REGISTER 0 0 Write data to DAC B and BUFFER 0 1 Write data to BUFFER 1 0 Write data to DAC A and update DAC B with BUFFER content 1 1 Write data to control register The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value: data bits: DAC A, DAC B and BUFFER D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 New DAC Value If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage: data bits: CONTROL D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X REF1 REF0 X: don't care REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage. reference bits REF1 REF0 REFERENCE 0 0 External 0 1 1.024 V 1 0 2.048 V 1 1 External CAUTION: If external reference voltage is applied to the REF pin, external reference MUST be selected. 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 APPLICATION INFORMATION Examples of operation: D Set DAC A output, select fast mode, select internal reference at 2.048 V: 1. Set reference voltage to 2.048 V (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 D6 D5 D4 D3 D2 D1 D0 2. Write new DAC A value and update DAC A output: D15 D14 D13 D12 1 1 0 0 D11 D10 D9 D8 D7 New DAC A output value The DAC A output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. D Set DAC B output, select fast mode, select external reference: 3. Select external reference (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 D4 D3 D2 D1 D0 4. Write new DAC B value to BUFFER and update DAC B output: D15 D14 D13 D12 0 1 0 0 D11 D10 D9 D8 D7 D6 D5 New BUFFER content and DAC B output value The DAC A output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. D Set DAC A value, set DAC B value, update both simultaneously, select slow mode, select internal reference at 1.024 V: 1. Set reference voltage to 1.024 V (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 D8 D7 D6 D5 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 2. Write data for DAC B to BUFFER: D15 D14 D13 D12 0 0 0 1 D11 D10 D9 New DAC B value 3. Write new DAC A value and update DAC A and B simultaneously: D15 D14 D13 D12 1 0 0 0 D11 D10 D9 D8 D7 D6 D5 New DAC A value POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 APPLICATION INFORMATION Examples of operation: (continued) Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. D Set power-down mode: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1 X X X X X X X X X X X X X X = Don't care linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14. Output Voltage 0V DAC Code Negative Offset Figure 14. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS130B - JULY 2002 - REVISED DECEMBER 2003 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG) Gain error is the error in slope of the DAC transfer function. total harmonic distortion (THD) THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. The value for THD is expressed in decibels. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLV5638MDREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5638QDREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/03628-01XE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/03628-02XE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV5638-EP : TLV5638 * Catalog: * Military: TLV5638M NOTE: Qualified Version Definitions: - TI's standard catalog product * Catalog * Military - QML certified for Military and Defense Applications Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jul-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV5638MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV5638QDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jul-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5638MDREP SOIC D 8 2500 346.0 346.0 29.0 TLV5638QDREP SOIC D 8 2500 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP(R) Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps RF/IF and ZigBee(R) Solutions www.ti.com/lprf TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2011, Texas Instruments Incorporated