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features
DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DExtended Temperature Performance up to
−55°C to 125°C
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product Change Notification
DQualification Pedigree†
DDual 12-Bit Voltage Output DAC
DProgrammable Internal Reference
DProgrammable Settling Time:
1 µs in Fast Mode,
3.5 µs in Slow Mode
†Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
DCompatible With TMS320 and SPI Serial
Ports
DDifferential Nonlinearity <0.5 LSB Typ
DMonotonic Over Temperature
applications
DDigital Servo Control Loops
DDigital Offset and Gain Adjustment
DIndustrial Process Control
DMachine and Motion Control Devices
DMass Storage Devices
description
The TLV5638 is a dual 12-bit voltage output DAC with a flexible 3-wire serial interface. The serial interface allows
glueless interface to TMS320 and SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit
serial string containing 4 control and 12 data bits.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class
AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows
the designer to optimize speed vs power dissipation. With its on-chip programmable precision voltage
reference, the TLV5638 simplifies overall system design.
Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented
with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in
an 8-pin SOIC package to reduce board space.
ORDERING INFORMATION
TAPACKAGE‡ORDERABLE
PART NUMBER TOP-SIDE
MARKING
−40°C to 125°CSOIC − D Tape and reel TLV5638QDREP 5638QE
−55°C to 125°CSOIC − D Tape and reel TLV5638MDREP 5638ME
‡Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002 − 2003, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%)
"!-('%& '!!"# %! &*)''$%!& *)" %.) %)"#& ! )/$& &%"(#)%&
&%$-$"- 0$""$%1 "!-('%! *"!')&&2 -!)& !% )')&&$",1 ',(-)
%)&%2 ! $,, *$"$#)%)"&
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
1
2
3
4
8
7
6
5
DIN
SCLK
CS
OUTA
VDD
OUTB
REF
AGND
D PACKAGE
(TOP VIEW)
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functional block diagram
Serial
Interface
and
Control
12-Bit
DAC B
Latch
SCLK
DIN
CS
OUTA
Power-On
Reset
x2
12
2-Bit
Control
Latch
Power
and Speed
Control
2
Voltage
Bandgap
PGA With
Output Enable
12-Bit
DAC A
Latch
12
REF AGND VDD
2
12 12
OUTB
x2
Buffer
12
Terminal Functions
TERMINAL
I/O/P
DESCRIPTION
NAME NO.
I/O/P
DESCRIPTION
AGND 5 P Ground
CS 3 I Chip select. Digital input active low, used to enable/disable inputs
DIN 1 I Digital serial data input
OUT A 4 O DAC A analog voltage output
OUT B 7 O DAC B analog voltage output
REF 6 I/O Analog reference voltage input/output
SCLK 2 I Digital serial clock input
VDD 8 P Positive power supply
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range −0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range −0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLV5638Q (see Note 1) −40°C to 125°C. . . . . . . . . . . . . . . . . . . . .
TLV5638M (see Note 1) −55°C to 125°C. . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg (see Note 1) −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA: D package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction
of overall device life. See www.ti.com/ep_quality for additional information on enhanced plastic packaging.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VDD
VDD = 5 V 4.5 5 5.5 V
Supply voltage, VDD VDD = 3 V 2.7 3 3.3 V
Power on reset, POR 0.55 2 V
High-level digital input voltage, VIH
VDD = 2.7 V 2
V
High-level digital input voltage, VIH VDD = 5.5 V 2.4 V
Low-level digital input voltage, VIL
VDD = 2.7 V 0.6
V
Low-level digital input voltage, VIL VDD = 5.5 V 0.8 V
Reference voltage, Vref to REF terminal VDD = 5 V (see Note 1) AGND 2.048 VDD−1.5 V
Reference voltage, Vref to REF terminal VDD = 3 V (see Note 1) AGND 1.024 VDD−1.5 V
Load resistance, RL2 kΩ
Load capacitance, CL100 pF
Clock frequency, fCLK 20 MHz
Operating free-air temperature, TA
TLV5638Q (see Note 2) −40 125
°C
Operating free-air temperature, T
ATLV5638M (see Note 2) −55 125 °
C
NOTES: 1. Due to the x2 output buffer, a reference input voltage ≥ (VDD−0.4 V)/2 causes clipping of the transfer function. The output buf fer of
the internal reference must be disabled, if an external reference is used.
2. Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction
of overall device life. See www.ti.com/ep_quality for additional information on enhanced plastic packaging.
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electrical characteristics over recommended operating conditions, Vref = 2.048 V, Vref = 1.024 V
(unless otherwise noted)
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
DD
= 5 V, Fast 4.3 7
mA
VDD = 5 V,
Int. ref. Slow 2.2 3.6
mA
No load,
V
DD
= 3 V, Fast 3.8 6.3
mA
IDD
Power supply current
No load,
All inputs = AGND
VDD = 3 V,
Int. ref. Slow 1.8 3.0
mA
IDD Power supply current
All inputs = AGND
or VDD,
DAC latch = 0x800
V
DD
= 5 V, Fast 3.9 6.3
mA
DD
DAC latch = 0x800
VDD = 5 V,
Ext. ref. Slow 1.8 3.0
mA
V
DD
= 3 V, Fast 3.5 5.7
mA
VDD = 3 V,
Ext. ref. Slow 1.5 2.6
mA
Power-down supply current 0.01 10 µA
PSRR
Power supply rejection ratio
Zero scale, See Note 2 −65
dB
PSRR Power supply rejection ratio Full scale, See Note 3 −65 dB
NOTES: 3. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:
PSRR = 20 log [(EZS(VDDmax) − EZS(VDDmin))/VDDmax]
4. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) − EG(VDDmin))/VDDmax]
static DAC specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 12 bits
INL Integral nonlinearity, end point adjusted See Note 4 ±1.7 ±6 LSB
DNL Differential nonlinearity See Note 5 ±0.4 ±1 LSB
EZS Zero-scale error (offset error at zero scale) See Note 6 ±24 mV
EZS TC Zero-scale-error temperature coefficient See Note 7 10 ppm/°C
EGGain error See Note 8 ±0.6 % full
scale V
EG TCGain error temperature coefficient See Note 9 10 ppm/°C
NOTES: 5. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 32 to 4095.
6. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
7. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
8. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) − E ZS (Tmin)]/Vref × 106/(Tmax − Tmin).
9. Gain error is the deviation from the ideal output (2V ref − 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
10. Gain temperature coefficient is given by: EGTC = [EG(Tmax) − EG (Tmin)]/Vref × 106/(Tmax − Tmin).
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electrical characteristics over recommended operating conditions, Vref = 2.048 V, Vref = 1.024 V
(unless otherwise noted) (continued)
output specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOOutput voltage RL = 10 kΩ0 VDD−0.4 V
Output load regulation accuracy VO = 4.096 V, 2.048 V, RL = 2 kΩ ± 0.25 % full
scale V
reference pin configured as output (REF)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vref(OUTL) Low reference voltage 1.003 1.024 1.045 V
Vref(OUTH) High reference voltage VDD > 4.75 V 2.027 2.048 2.069 V
Iref(source) Output source current 1 mA
Iref(sink) Output sink current −1 mA
Load capacitance 100 pF
PSRR Power supply rejection ratio −65 dB
reference pin configured as input (REF)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIInput voltage 0 VDD−1.5 V
RIInput resistance 10 MΩ
CIInput capacitance 5 pF
Reference input bandwidth
REF = 0.2 Vpp + 1.024 V dc
Fast 1.3 MHz
Reference input bandwidth
REF = 0.2 V
pp
+ 1.024 V dc
Slow 525 kHz
Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) −80 dB
NOTE 11: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH High-level digital input current VI = VDD 1µA
IIL Low-level digital input current VI = 0 V −1 µA
CiInput capacitance 8 pF
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electrical characteristics over recommended operating conditions (unless otherwise noted)
(continued)
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ts(FS)
Output settling time, full scale
RL = 10 k
Ω
,C
L = 100 pF,
Fast 1 3
s
ts(FS) Output settling time, full scale
RL = 10 kΩ,C
L = 100 pF,
See Note 11 Slow 3.5 7 µs
ts(CC)
Output settling time, code to code
RL = 10 k
Ω
,C
L = 100 pF,
Fast 0.5 1.5
s
ts(CC) Output settling time, code to code
RL = 10 kΩ,C
L = 100 pF,
See Note 12 Slow 1 2 µs
SR
Slew rate
RL = 10 k
Ω
,C
L = 100 pF,
Fast 12
V/ s
SR Slew rate
RL = 10 kΩ,C
L = 100 pF,
See Note 13 Slow 1.8 V/µs
Glitch energy DIN = 0 to 1, FCLK = 100 kHz,
CS = VDD 5 nV−s
SNR Signal-to-noise ratio 69 74
S/(N+D) Signal-to-noise + distortion
fs = 480 kSPS, fout = 1 kHz,
58 67
dB
THD Total harmonic distortion
fs = 480 kSPS, fout = 1 kHz,
RL = 10 kΩ,C
L = 100 pF −69 −57 dB
Spurious free dynamic range
RL = 10 k ,C
L = 100 pF
57 72
NOTES: 12. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.
13. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.
14. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
digital input timing requirements
MIN NOM MAX UNIT
tsu(CS−CK) Setup time, CS low before first negative SCLK edge 10 ns
tsu(C16-CS) Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns
twH SCLK pulse width high 25 ns
twL SCLK pulse width low 25 ns
tsu(D) Setup time, data ready before SCLK falling edge 10 ns
th(D) Hold time, data held valid after SCLK falling edge 5 ns
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PARAMETER MEASUREMENT INFORMATION
twL
SCLK
CS
DIN D15 D14 D13 D12 D1 D0 XX
1
X2 3 4 5 15 16 X
twH
tsu(D) th(D)
tsu(CS-CK)
tsu(C16-CS)
Figure 1. Timing Diagram
TYPICAL CHARACTERISTICS
Figure 2
1.4
1
0.4
0010203040
− Power Down Supply Current − mA
2.2
2.4
POWER DOWN SUPPLY CURRENT
vs
TIME
2.6
50 60 70 80
2
1.8
1.6
1.2
0.8
0.6
0.2
t − Time − µs
IDD
Figure 3
2.5
2
1.5
0.5
−40 −30−20 −10 0 10 20
3.5
4
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
4.5
30 50 60 90
3
1
40 70 80
Fast Mode
Slow Mode
VDD = 5 V
Vref = Int. 2 V
Input Code = Full Scale (Both DACs)
− Supply Current − mAIDD
TA − Free-Air Temperature − °C
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TYPICAL CHARACTERISTICS
Figure 4
2.5
2
1.5
0.5
−40 −30−20 −10 0 10 20
3.5
4
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
4.5
30 50 60 90
3
1
40 70 80
Fast Mode
Slow Mode
VDD = 3 V
Vref = Int. 1 V
Input Code = Full Scale (Both DACs)
− Supply Current − mAIDD
TA − Free-Air Temperature − °C
Figure 5
2.058
2.054
2.052
2.05 0 0.5 1 1.5 2 2.5 3
− Output Voltage − V
2.06
2.062
Source Current − mA
OUTPUT VOLTAGE
vs
LOAD CURRENT
2.064
3.5 4
2.056
VO
Fast Mode
Slow Mode
VDD = 3 V
Vref = Int. 1 V
Input Code = 4095
Figure 6
4.122
4.12
4.116
4.114 0 0.5 1 1.5 2 2.5 3
4.124
4.126
4.128
3.5 4
4.118
− Output Voltage − V
Source Current − mA
OUTPUT VOLTAGE
vs
LOAD CURRENT
VO
Fast Mode
Slow Mode
VDD = 5 V
Vref = Int. 2 V
Input Code = 4095
Figure 7
1.5
1
0.5
00 0.5 1 1.5 2 2.5 3
2
2.5
3
3.5 4
− Output Voltage − V
Sink Current − mA
OUTPUT VOLTAGE
vs
LOAD CURRENT
VO
Fast Mode
Slow Mode
VDD = 3 V
Vref = Int. 1 V
Input Code = 0
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TYPICAL CHARACTERISTICS
Figure 8
3.5
2
1
00 0.5 1 1.5 2 2.5 3
4
4.5
5
3.5 4
3
2.5
1.5
0.5
− Output Voltage − V
Sink Current − mA
OUTPUT VOLTAGE
vs
LOAD CURRENT
VO
Fast Mode
Slow Mode
VDD = 5 V
Vref = Int. 2 V
Input Code = 0
Figure 9
−40
−50
−80
−100
100 1000
THD+N − Total Harmonic Distortion and Noise − dB
−20
−10
f − Frequency − Hz
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
10000 100000
−30
−60
−70
−90
Fast Mode
Slow Mode
VDD = 5 V
Vref = 1 V dc + 1 V p/p Sinewave
Output Full Scale
−40
−50
−80
−100
100 1000
THD − Total Harmonic Distortion − dB
−20
−10
f − Frequency − Hz
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
10000 100000
−30
−60
−70
−90 Fast Mode
Slow Mode
VDD = 5 V
Vref = 1 V dc + 1 V p/p Sinewave
Output Full Scale
Figure 10
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TYPICAL CHARACTERISTICS
−1
−4 0 1024 2048
2
3
INTEGRAL NONLINEARITY ERROR
4
3072 4096
INL − Integral Nonlinearity Error − LSB
Digital Code
1
0
−2
−3
Figure 11
−0.4
−10 1024 2048
0.6
0.8
DIFFERENTIAL NONLINEARITY ERROR
1
3072 4096
0.4
0.2
0
−0.2
−0.6
−0.8
DNL − Differential Nonlinearily Error − LSB
Digital Code
Figure 12
APPLICATION INFORMATION
general function
The TLV5638 is a dual 12-bit, single supply DAC, based on a resistor string architecture. It consists of a serial
interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a
rail-to-rail output buffer.
The output voltage (full scale determined by reference) is given by:
2REF CODE
0x1000 [V]
Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power
on reset initially puts the internal latches to a defined state (all bits zero).
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APPLICATION INFORMATION
serial interface
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling
edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the
target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 13 shows examples of how to connect the TLV5638 to TMS320, SPI, and Microwire.
TMS320
DSP FSX
CLKX
DX
TLV5638
SCLK
DIN
CS SPI I/O
SCK
MOSI
TLV5638
SCLK
DIN
CS Microwire
I/O
SK
SO
TLV5638
SCLK
DIN
CS
Figure 13. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a
falling edge on the pin connected to CS. If the word width is 8 bits (SPI and Microwire), two write operations
must be performed to program the TLV5638. After the write operation(s), the holding registers or the control
register are updated automatically on the 16th positive clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
fsclkmax +1
twhmin )twlmin +20 MHz
The maximum update rate is:
fupdatemax +1
16 ǒtwhmin )twlminǓ+1.25 MHz
Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5638 has to be considered, too.
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APPLICATION INFORMATION
data format
The 16-bit data word for the TLV5638 consists of two parts:
DProgram bits (D15..D12)
DNew data (D11..D0)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R1 SPD PWR R0 12 Data bits
SPD: Speed control bit 1 → fast mode 0 →slow mode
PWR: Power control bit 1 → power down 0 → normal operation
The following table lists the possible combination of the register select bits:
register select bits
R1 R0 REGISTER
0 0 Write data to DAC B and BUFFER
0 1 Write data to BUFFER
1 0 Write data to DAC A and update DAC B with BUFFER content
1 1 Write data to control register
The meaning of the 12 data bits depends on the register . If one of the DAC registers or the BUFFER is selected,
then the 12 data bits determine the new DAC value:
data bits: DAC A, DAC B and BUFFER
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
New DAC Value
If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:
data bits: CONTROL
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X X X X X X X X X X REF1 REF0
X: don’t care
REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage.
reference bits
REF1 REF0 REFERENCE
0 0 External
0 1 1.024 V
1 0 2.048 V
1 1 External
CAUTION:
If external reference voltage is applied to the REF pin, external reference MUST be selected.
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APPLICATION INFORMATION
Examples of operation:
DSet DAC A output, select fast mode, select internal reference at 2.048 V:
1. Set reference voltage to 2.048 V (CONTROL register):
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1101000000000010
2. Write new DAC A value and update DAC A output:
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1100 New DAC A output value
The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL
register again.
DSet DAC B output, select fast mode, select external reference:
3. Select external reference (CONTROL register):
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1101000000000000
4. Write new DAC B value to BUFFER and update DAC B output:
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0100 New BUFFER content and DAC B output value
The DAC A output is updated on the rising clock edge after D0 is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL
register again.
DSet DAC A value, set DAC B value, update both simultaneously, select slow mode, select internal reference
at 1.024 V:
1. Set reference voltage to 1.024 V (CONTROL register):
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1001000000000001
2. Write data for DAC B to BUFFER:
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0001 New DAC B value
3. Write new DAC A value and update DAC A and B simultaneously:
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1000 New DAC A value
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APPLICATION INFORMATION
Examples of operation: (continued)
Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.
To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL
register again.
DSet power-down mode:
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
XX1XXXXXXXXXXXXX
X = Don’t care
linearity, offset, and gain error using single ended supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage
may not change with the first code, depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14.
DAC Code
Output
Voltage
0 V
Negative
Offset
Figure 14. Effect of Negative Offset (Single Supply)
This offset error , not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage.
SGLS130B − JULY 2002 − REVISED DECEMBER 2003
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
definitions of specifications and terminology
integral nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the ef fects of zero code and full-scale
errors.
differential nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.
zero-scale error (EZS)
Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.
gain error (EG)
Gain error is the error in slope of the DAC transfer function.
total harmonic distortion (THD)
THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal.
The value for THD is expressed in decibels.
signal-to-noise ratio + distortion (S/N+D)
S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
spurious free dynamic range (SFDR)
Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of
the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV5638MDREP ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV5638QDREP ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/03628-01XE ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V62/03628-02XE ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV5638-EP :
•Catalog: TLV5638
•Military: TLV5638M
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV5638MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV5638QDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jul-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV5638MDREP SOIC D 8 2500 346.0 346.0 29.0
TLV5638QDREP SOIC D 8 2500 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jul-2008
Pack Materials-Page 2
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