LV8400VMPBE - ON SEMICONDUCTOR

1.35V DDR3L SDRAM UDIMM

MT4KTF25664AZ – 2GB

Features

• DDR3L functionality and operations supported as

defined in the component data sheet

• 240-pin, unbuffered dual in-line memory module

(UDIMM)

• Fast data transfer rates: PC3-14900 or PC3-12800

• 2GB (256 Meg x 64)

• VDD = VDDQ = 1.35V (1.238–1.45V)

• VDD = VDDQ = 1.5V (1.425–1.575V)

• Backward-compatible to VDD = VDDQ = 1.5V ±0.075V

• VDDSPD = 3.0–3.6V

• Reset pin for improved system stability

• Nominal and dynamic on-die termination (ODT) for

data, strobe, and mask signals

• Single-rank

• Fixed burst chop (BC) of 4 and burst length (BL) of 8

via the mode register set (MRS)

• Adjustable data-output drive strength

• Serial presence-detect (SPD) EEPROM

• Gold edge contacts

• Halogen-free

• Fly-by topology

• Terminated control, command, and address bus

Figure 1: 240-Pin UDIMM (MO-269 R/C C1)

Module height: 30.0mm (1.181in)

Options Marking

• Operating temperature

– Commercial (0°C ≤ TA ≤ +70°C) None

• Package

– 240-pin DIMM (halogen-free) Z

• Frequency/CAS latency

– 1.07ns @ CL = 13 (DDR3-1866) -1G9

– 1.25ns @ CL = 11 (DDR3-1600) -1G6

Table 1: Key Timing Parameters

Speed

Grade

Industry

Nomenclature

Data Rate (MT/s)

tRCD

(ns)

tRP

(ns)

tRC

(ns)

CL =

10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5

-1G9 PC3-14900 1866 1600 1333 1333 1066 1066 800 667 13.125 13.125 47.125

-1G6 PC3-12800 – 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125

-1G4 PC3-10600 – – 1333 1333 1066 1066 800 667 13.125 13.125 49.125

-1G1 PC3-8500 – – – – 1066 1066 800 667 13.125 13.125 50.625

-1G0 PC3-8500 – – – – 1066 – 800 667 15 15 52.5

-80B PC3-6400 – – – – – – 800 667 15 15 52.5

2GB (x64, SR) 240-Pin DDR3L UDIMM

Features

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Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing

Parameter 2GB

Refresh count 8K

Row address 32K A[14:0]

Device bank address 8 BA[2:0]

Device configuration 4Gb (256 Meg x 16)

Column address 1K A[9:0]

Module rank address 1 S0#

Table 3: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT41K256M16,1 4Gb 1.35V DDR3L SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

MT4KTF25664AZ-1G9__ 2GB 256 Meg x 64 14.9 GB/s 1.07ns/1866 MT/s 13-13-13

MT4KTF25664AZ-1G6__ 2GB 256 Meg x 64 12.8 GB/s 1.25ns/1600 MT/s 11-11-11

Notes: 1. Data sheets for the base device parts can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.

Consult factory for current revision codes. Example: MT4KTF25664AZ-1G9P1.

2GB (x64, SR) 240-Pin DDR3L UDIMM

Features

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Pin Assignments

Table 4: Pin Assignments

240-Pin DDR3 UDIMM Front 240-Pin DDR3 UDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

1 VREFDQ 31 DQ25 61 A2 91 DQ41 121 VSS 151 VSS 181 A1 211 VSS

2 VSS 32 VSS 62 VDD 92 VSS 122 DQ4 152 DM3 182 VDD 212 DM5

3 DQ0 33 DQS3# 63 CK1 93 DQS5# 123 DQ5 153 NC 183 VDD 213 NC

4 DQ1 34 DQS3 64 CK1# 94 DQS5 124 VSS 154 VSS 184 CK0 214 VSS

5 VSS 35 VSS 65 VDD 95 VSS 125 DM0 155 DQ30 185 CK0# 215 DQ46

6 DQS0# 36 DQ26 66 VDD 96 DQ42 126 NC 156 DQ31 186 VDD 216 DQ47

7 DQS0 37 DQ27 67 VREFCA 97 DQ43 127 VSS 157 VSS 187 NC 217 VSS

8 VSS 38 VSS 68 NC 98 VSS 128 DQ6 158 NF 188 A0 218 DQ52

9 DQ2 39 NF 69 VDD 99 DQ48 129 DQ7 159 NF 189 VDD 219 DQ53

10 DQ3 40 NF 70 A10 100 DQ49 130 VSS 160 VSS 190 BA1 220 VSS

11 VSS 41 VSS 71 BA0 101 VSS 131 DQ12 161 NF 191 VDD 221 DM6

12 DQ8 42 NF 72 VDD 102 DQS6# 132 DQ13 162 NF 192 RAS# 222 NC

13 DQ9 43 NF 73 WE# 103 DQS6 133 VSS 163 VSS 193 S0# 223 VSS

14 VSS 44 VSS 74 CAS# 104 VSS 134 DM1 164 NF 194 VDD 224 DQ54

15 DQS1# 45 NF 75 VDD 105 DQ50 135 NC 165 NF 195 ODT0 225 DQ55

16 DQS1 46 NF 76 NF 106 DQ51 136 VSS 166 VSS 196 A13 226 VSS

17 VSS 47 VSS 77 NF 107 VSS 137 DQ14 167 NC 197 VDD 227 DQ60

18 DQ10 48 NC 78 VDD 108 DQ56 138 DQ15 168 RESET# 198 NC 228 DQ61

19 DQ11 49 NC 79 NC 109 DQ57 139 VSS 169 NF 199 VSS 229 VSS

20 VSS 50 CKE0 80 VSS 110 VSS 140 DQ20 170 VDD 200 DQ36 230 DM7

21 DQ16 51 VDD 81 DQ32 111 DQS7# 141 DQ21 171 NF 201 DQ37 231 NC

22 DQ17 52 BA2 82 DQ33 112 DQS7 142 VSS 172 A14 202 VSS 232 VSS

23 VSS 53 NC 83 VSS 113 VSS 143 DM2 173 VDD 203 DM4 233 DQ62

24 DQS2# 54 VDD 84 DQS4# 114 DQ58 144 NC 174 A12 204 NC 234 DQ63

25 DQS2 55 A11 85 DQS4 115 DQ59 145 VSS 175 A9 205 VSS 235 VSS

26 VSS 56 A7 86 VSS 116 VSS 146 DQ22 176 VDD 206 DQ38 236 VDDSPD

27 DQ18 57 VDD 87 DQ34 117 SA0 147 DQ23 177 A8 207 DQ39 237 SA1

28 DQ19 58 A5 88 DQ35 118 SCL 148 VSS 178 A6 208 VSS 238 SDA

29 VSS 59 A4 89 VSS 119 SA2 149 DQ28 179 VDD 209 DQ44 239 VSS

30 DQ24 60 VDD 90 DQ40 120 VTT 150 DQ29 180 A3 210 DQ45 240 VTT

2GB (x64, SR) 240-Pin DDR3L UDIMM

Pin Assignments

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Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for all DDR3

modules. All pins listed may not be supported on this module. See Pin Assignments for

information specific to this module.

Table 5: Pin Descriptions

Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location

out of the memory array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one bank (A10 LOW, bank

selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code

during a LOAD MODE command. See the Pin Assignments Table for density-specific

addressing information.

BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied. BA define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command.

CKx,

CKx#

Input Clock: Differential clock inputs. All control, command, and address input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#.

CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-

try and clocks on the DRAM.

DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data

is masked when DM is sampled HIGH, along with that input data, during a write ac-

cess. Although DM pins are input-only, DM loading is designed to match that of the

DQ and DQS pins.

ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-

nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input

will be ignored if disabled via the LOAD MODE command.

Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being

entered.

RESET# Input

(LVCMOS)

Reset: RESET# is an active LOW asychronous input that is connected to each DRAM

and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial-

ized as though a normal power-up was executed.

Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command

decoder.

SAx Input Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-

dress range on the I2C bus.

SCL Input Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-

cation to and from the temperature sensor/SPD EEPROM on the I2C bus.

CBx I/O Check bits: Used for system error detection and correction.

DQx I/O Data input/output: Bidirectional data bus.

DQSx,

DQSx#

I/O Data strobe: Differential data strobes. Output with read data; edge-aligned with

read data; input with write data; center-aligned with write data.

2GB (x64, SR) 240-Pin DDR3L UDIMM

Pin Descriptions

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Table 5: Pin Descriptions (Continued)

Symbol Type Description

SDA I/O Serial data: Used to transfer addresses and data into and out of the temperature sen-

sor/SPD EEPROM on the I2C bus.

TDQSx,

TDQSx#

Output Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD

MODE command to the extended mode register (EMR). When TDQS is enabled, DM is

disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are

no function.

Err_Out# Output

(open drain)

Parity error output: Parity error found on the command and address bus.

EVENT# Output

(open drain)

Temperature event: The EVENT# pin is asserted by the temperature sensor when crit-

ical temperature thresholds have been exceeded.

VDD Supply Power supply: 1.5V ±0.075V. The component VDD and VDDQ are connected to the

module VDD.

VDDSPD Supply Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.

VREFCA Supply Reference voltage: Control, command, and address VDD/2.

VREFDQ Supply Reference voltage: DQ, DM VDD/2.

VSS Supply Ground.

VTT Supply Termination voltage: Used for control, command, and address VDD/2.

NC – No connect: These pins are not connected on the module.

NF – No function: These pins are connected within the module, but provide no functional-

ity.

2GB (x64, SR) 240-Pin DDR3L UDIMM

Pin Descriptions

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DQ Map

Table 6: Component-to-Module DQ Map

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

U1 0 2 9 U2 0 18 27

1 1 4 1 17 22

2 3 10 2 19 28

3 5 123 3 21 141

4 6 128 4 22 146

5 4 122 5 20 140

6 7 129 6 23 147

7 0 3 7 16 21

8 8 12 8 24 30

9 15 138 9 31 156

10 9 13 10 25 31

11 11 19 11 27 37

12 12 131 12 28 149

13 14 137 13 30 155

14 13 132 14 29 150

15 10 18 15 26 36

U3 0 34 87 U4 0 50 105

1 33 82 1 49 100

2 35 88 2 51 106

3 37 201 3 53 219

4 38 206 4 54 224

5 36 200 5 52 218

6 39 207 6 55 225

7 32 81 7 48 99

8 40 90 8 56 108

9 47 216 9 63 234

10 41 91 10 57 109

11 43 97 11 59 115

12 44 209 12 60 227

13 46 215 13 62 233

14 45 210 14 61 228

15 42 96 15 58 114

2GB (x64, SR) 240-Pin DDR3L UDIMM

DQ Map

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Functional Block Diagram

Figure 2: Functional Block Diagram

DQS

DQS#

DQS

DQS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQS1

DQS1#

DM1

DQS2

DQS2#

DM2

DQS3

DQS3#

DM3

DQS4

DQS4#

DM4

DQS5

DQS5#

DM5

DQS6

DQS6#

DM6

DQS7

DQS7#

DM7

CS#

CS# CS#

CS#

S0#

BA[2:0]

A[14:0]

RAS#

CAS#

WE#

CKE0

ODT0

RESET#

BA[2:0]: DDR3 SDRAM

A[13/12:0]: DDR3 SDRAM

RAS#: DDR3 SDRAM

CAS#: DDR3 SDRAM

WE#: DDR3 SDRAM

CKE0: DDR3 SDRAM

ODT0: DDR3 SDRAM

RESET#: DDR3 SDRAM

DDR3 SDRAM X 4

CK0

CK0#

CK1

CK1#

SPD EEPROM

A1 A2

SA0 SA1

SCL

VREFCA

VSS

DDR3 SDRAM

VDD

DDR3 SDRAM

VDDSPD SPD EEPROM

VTT

DDR3 SDRAM

VREFDQ

VSS

Command, address and clock line terminations

CKE0 A[14:0],

RAS#, CAS#, WE#,

ODT, BA[2:0]

DQS0

DQS0#

DM0

CK0

CK0#

SDA

DQS

DQS#

DQS

DQS#

DQS

DQS#

DQS

DQS#

DQS

DQS#

DQS

DQS#

DDR3

SDRAM

VTT

DDR3

SDRAM

VDD

SA2

Note: 1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor

that is tied to ground. It is used for the calibration of the component’s ODT and output

driver.

2GB (x64, SR) 240-Pin DDR3L UDIMM

Functional Block Diagram

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General Description

DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-

ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-

ules use DDR architecture to achieve high-speed operation. DDR3 architecture is essen-

tially an 8n-prefetch architecture with an interface designed to transfer two data words

per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM mod-

ule effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-

nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers

at the I/O pins.

DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK

and CK# to capture commands, addresses, and control signals. Differential clocks and

data strobes ensure exceptional noise immunity for these signals and provide precise

crossing points to capture input signals.

Fly-By Topology

DDR3 modules use faster clock speeds than earlier DDR technologies, making signal

quality more important than ever. For improved signal quality, the clock, control, com-

mand, and address buses have been routed in a fly-by topology, where each clock, con-

trol, command, and address pin on each DRAM is connected to a single trace and ter-

minated (rather than a tree structure, where the termination is off the module near the

connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-

nals can be easily accounted for by using the write-leveling feature of DDR3.

Serial Presence-Detect EEPROM Operation

DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a

256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with

JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM

Modules." These bytes identify module-specific timing parameters, configuration infor-

mation, and physical attributes. The remaining 128 bytes of storage are available for use

by the customer. System READ/WRITE operations between the master (system logic)

and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL

(clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, per-

manently disabling hardware write protection. For further information refer to Micron

technical note TN-04-42, "Memory Module Serial Presence-Detect."

2GB (x64, SR) 240-Pin DDR3L UDIMM

General Description

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Electrical Specifications

Stresses greater than those listed may cause permanent damage to the module. This is a

stress rating only, and functional operation of the module at these or any other condi-

tions outside those indicated in each device's data sheet is not implied. Exposure to ab-

solute maximum rating conditions for extended periods may adversely affect reliability.

Table 7: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD VDD supply voltage relative to VSS –0.4 1.975 V

VIN, VOUT Voltage on any pin relative to VSS –0.4 1.975 V

Table 8: Operating Conditions

Symbol Parameter Min Nom Max Units Notes

VDD VDD supply voltage 1.283 1.35 1.45 V

1.425 1.5 1.575 V 1

IVTT Termination reference current from VTT –600 – 600 mA

VTT Termination reference voltage (DC)

– command/address bus

0.49 × VDD - 20mV 0.5 × VDD 0.51 × VDD + 20mV V 2

IIInput leakage current;

Any input 0V ≤ VIN ≤ VDD;

VREF input 0V ≤ VIN ≤ 0.95V

(All other pins not under test

= 0V)

Address in-

puts, RAS#,

CAS#, WE#,

BA, S#, CKE,

ODT, CK,

CK#

–8 0 8 µA

DM –2 0 2

IOZ Output leakage current;

0V ≤ VOUT ≤ VDDQ; DQ and

ODT are disabled; ODT is HIGH

DQ, DQS,

DQS#

–5 0 5 µA

IVREF VREF supply leakage current; VREFDQ = VDD/2

or VREFCA = VDD/2 (All other pins not under

test = 0V.)

–4 0 4 µA

TAModule ambient operating

temperature

Commercial 0 – 70 °C 3, 4

TCDDR3 SDRAM component case

operating temperature

Commercial 0 – 95 °C 3, 4, 5

Notes: 1. Module is backward-compatible with 1.5V operation. Refer to device specification for

details and operation guidance.

2. VTT termination voltage in excess of the stated limit will adversely affect the command

and address signals’ voltage margin and will reduce timing margins.

3. TA and TC are simultaneous requirements.

4. For further information, refer to technical note TN-00-08: ”Thermal Applications,” avail-

able on Micron’s Web site.

5. The refresh rate is required to double when 85°C < TC ≤ 95°C.

2GB (x64, SR) 240-Pin DDR3L UDIMM

Electrical Specifications

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DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR3 component data sheets.

Component specifications are available at micron.com. Module speed grades correlate

with component speed grades, as shown below.

Table 9: Module and Component Speed Grades

DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades

Module Speed Grade Component Speed Grade

-2G1 -093

-1G9 -107

-1G6 -125

-1G4 -15E

-1G1 -187E

-1G0 -187

-80C -25E

-80B -25

Design Considerations

Simulations

Micron memory modules are designed to optimize signal integrity through carefully de-

signed terminations, controlled board impedances, routing topologies, trace length

matching, and decoupling. However, good signal integrity starts at the system level.

Micron encourages designers to simulate the signal characteristics of the system's

memory bus to ensure adequate signal integrity of the entire memory system.

Power

Operating voltages are specified at the DRAM, not at the edge connector of the module.

Designers must account for any system voltage drops at anticipated power levels to en-

sure the required supply voltage is maintained.

2GB (x64, SR) 240-Pin DDR3L UDIMM

DRAM Operating Conditions

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IDD Specifications

Table 10: DDR3 IDD Specifications and Conditions – 2GB (Die Revision P)

Values are for the MT41K256M16 DDR3L SDRAM only and are computed from values specified in the 1.35V 4Gb (256 Meg

x 16) component data sheet

Parameter Symbol 1866 1600 Units

Operating current 0: One bank ACTIVATE-to-PRECHARGE IDD0 128 128 mA

Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE IDD1 184 180 mA

Precharge power-down current: Slow exit IDD2P0 48 48 mA

Precharge power-down current: Fast exit IDD2P1 48 48 mA

Precharge quiet standby current IDD2Q 60 60 mA

Precharge standby current IDD2N 68 68 mA

Precharge standby ODT current IDD2NT 92 92 mA

Active power-down current IDD3P 68 68 mA

Active standby current IDD3N 92 88 mA

Burst read operating current IDD4R 416 368 mA

Burst write operating current IDD4W 468 424 mA

Refresh current IDD5B 624 624 mA

Self refresh temperature current: MAX TC = 85°C IDD6 60 60 mA

Self refresh temperature current (SRT-enabled): MAX TC = 95°C IDD6ET 92 92 mA

All banks interleaved read current IDD7 588 528 mA

Reset current IDD8 56 56 mA

2GB (x64, SR) 240-Pin DDR3L UDIMM

IDD Specifications

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Serial Presence-Detect EEPROM

For the latest SPD data, refer to Micron's SPD page: micron.com/spd.

Table 11: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to VDDSPD

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD 3.0 3.6 V

Input low voltage: Logic 0; All inputs VIL –0.45 VDDSPD x 0.3 V

Input high voltage: Logic 1; All inputs VIH VDDSPD x 0.7 VDDSPD + 1.0 V

Output low voltage: IOUT = 3mA VOL – 0.4 V

Input leakage current: VIN = GND to VDD ILI 0.1 2.0 µA

Output leakage current: VOUT = GND to VDD ILO 0.05 2.0 µA

Table 12: Serial Presence-Detect EEPROM AC Operating Conditions

Parameter/Condition Symbol Min Max Units Notes

Clock frequency tSCL 10 400 kHz

Clock pulse width HIGH time tHIGH 0.6 – µs

Clock pulse width LOW time tLOW 1.3 – µs

SDA rise time tR – 300 µs 1

SDA fall time tF 20 300 ns 1

Data-in setup time tSU:DAT 100 – ns

Data-in hold time tHD:DI 0 – µs

Data-out hold time tHD:DAT 200 900 ns

Data out access time from SCL LOW tAA:DAT 0.2 0.9 µs 2

Start condition setup time tSU:STA 0.6 – µs 3

Start condition hold time tHD:STA 0.6 – µs

Stop condition setup time tSU:STO 0.6 – µs

Time the bus must be free before a new transition can

start

tBUF 1.3 – µs

WRITE time tW – 10 ms

Notes: 1. Guaranteed by design and characterization, not necessarily tested.

2. To avoid spurious start and stop conditions, a minimum delay is placed between the fall-

ing edge of SCL and the falling or rising edge of SDA.

3. For a restart condition, or following a WRITE cycle.

2GB (x64, SR) 240-Pin DDR3L UDIMM

Serial Presence-Detect EEPROM

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Module Dimensions

Figure 3: 240-Pin DDR3 UDIMM

30.50 (1.20)

29.85 (1.175)

Pin 1

17.3 (0.68)

TYP

2.50 (0.098) D

(2X)

2.30 (0.091) TYP

5.0 (0.197) TYP

123.0 (4.84)

TYP

1.0 (0.039)

TYP

0.80 (0.031)

TYP

0.75 (0.03) R

(8X)

0.76 (0.030) R

Pin 120

Front view

133.50 (5.256)

133.20 (5.244)

47.0 (1.85)

TYP

71.0 (2.79)

TYP

9.5 (0.374)

TYP

Back view

Pin 240 Pin 121

1.37 (0.054)

1.17 (0.046)

2.70 (0.106)

MAX

2.20 (0.087) TYP

1.45 (0.057) TYP

3.05 (0.12) TYP

54.68 (2.15)

TYP

3.0 (0.118) x4 TYP

No components this side of module

45° (4X)

U1 U2 U3 U4

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only.

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This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

2GB (x64, SR) 240-Pin DDR3L UDIMM

Module Dimensions

PDF: 09005aef84cae8ad

ktf4c256x64az.pdf - Rev. E 12/15 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.